root / target-ppc / op_mem.h @ 173d6cfe
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1 | 9a64fbe4 | bellard | /* External helpers */
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2 | 9a64fbe4 | bellard | void glue(do_lsw, MEMSUFFIX) (int dst); |
3 | 9a64fbe4 | bellard | void glue(do_stsw, MEMSUFFIX) (int src); |
4 | 9a64fbe4 | bellard | |
5 | 0fa85d43 | bellard | static inline uint16_t glue(ld16r, MEMSUFFIX) (target_ulong EA) |
6 | 9a64fbe4 | bellard | { |
7 | ac9eb073 | bellard | uint16_t tmp = glue(lduw, MEMSUFFIX)(EA); |
8 | 9a64fbe4 | bellard | return ((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8); |
9 | 9a64fbe4 | bellard | } |
10 | 9a64fbe4 | bellard | |
11 | 111bfab3 | bellard | static inline int32_t glue(ld16rs, MEMSUFFIX) (target_ulong EA) |
12 | 111bfab3 | bellard | { |
13 | 111bfab3 | bellard | int16_t tmp = glue(lduw, MEMSUFFIX)(EA); |
14 | 111bfab3 | bellard | return ((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8); |
15 | 111bfab3 | bellard | } |
16 | 111bfab3 | bellard | |
17 | 0fa85d43 | bellard | static inline uint32_t glue(ld32r, MEMSUFFIX) (target_ulong EA) |
18 | 9a64fbe4 | bellard | { |
19 | ac9eb073 | bellard | uint32_t tmp = glue(ldl, MEMSUFFIX)(EA); |
20 | 9a64fbe4 | bellard | return ((tmp & 0xFF000000) >> 24) | ((tmp & 0x00FF0000) >> 8) | |
21 | 9a64fbe4 | bellard | ((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24); |
22 | 9a64fbe4 | bellard | } |
23 | 9a64fbe4 | bellard | |
24 | 0fa85d43 | bellard | static inline void glue(st16r, MEMSUFFIX) (target_ulong EA, uint16_t data) |
25 | 9a64fbe4 | bellard | { |
26 | 9a64fbe4 | bellard | uint16_t tmp = ((data & 0xFF00) >> 8) | ((data & 0x00FF) << 8); |
27 | ac9eb073 | bellard | glue(stw, MEMSUFFIX)(EA, tmp); |
28 | 9a64fbe4 | bellard | } |
29 | 9a64fbe4 | bellard | |
30 | 0fa85d43 | bellard | static inline void glue(st32r, MEMSUFFIX) (target_ulong EA, uint32_t data) |
31 | 9a64fbe4 | bellard | { |
32 | 9a64fbe4 | bellard | uint32_t tmp = ((data & 0xFF000000) >> 24) | ((data & 0x00FF0000) >> 8) | |
33 | 9a64fbe4 | bellard | ((data & 0x0000FF00) << 8) | ((data & 0x000000FF) << 24); |
34 | ac9eb073 | bellard | glue(stl, MEMSUFFIX)(EA, tmp); |
35 | 9a64fbe4 | bellard | } |
36 | 9a64fbe4 | bellard | |
37 | 9a64fbe4 | bellard | /*** Integer load ***/
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38 | 9a64fbe4 | bellard | #define PPC_LD_OP(name, op) \
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39 | 9a64fbe4 | bellard | PPC_OP(glue(glue(l, name), MEMSUFFIX)) \ |
40 | 9a64fbe4 | bellard | { \ |
41 | 0fa85d43 | bellard | T1 = glue(op, MEMSUFFIX)(T0); \ |
42 | 9a64fbe4 | bellard | RETURN(); \ |
43 | 9a64fbe4 | bellard | } |
44 | 9a64fbe4 | bellard | |
45 | 9a64fbe4 | bellard | #define PPC_ST_OP(name, op) \
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46 | 9a64fbe4 | bellard | PPC_OP(glue(glue(st, name), MEMSUFFIX)) \ |
47 | 9a64fbe4 | bellard | { \ |
48 | 0fa85d43 | bellard | glue(op, MEMSUFFIX)(T0, T1); \ |
49 | 9a64fbe4 | bellard | RETURN(); \ |
50 | 9a64fbe4 | bellard | } |
51 | 9a64fbe4 | bellard | |
52 | ac9eb073 | bellard | PPC_LD_OP(bz, ldub); |
53 | ac9eb073 | bellard | PPC_LD_OP(ha, ldsw); |
54 | ac9eb073 | bellard | PPC_LD_OP(hz, lduw); |
55 | ac9eb073 | bellard | PPC_LD_OP(wz, ldl); |
56 | 9a64fbe4 | bellard | |
57 | 111bfab3 | bellard | PPC_LD_OP(ha_le, ld16rs); |
58 | 111bfab3 | bellard | PPC_LD_OP(hz_le, ld16r); |
59 | 111bfab3 | bellard | PPC_LD_OP(wz_le, ld32r); |
60 | 111bfab3 | bellard | |
61 | 9a64fbe4 | bellard | /*** Integer store ***/
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62 | ac9eb073 | bellard | PPC_ST_OP(b, stb); |
63 | ac9eb073 | bellard | PPC_ST_OP(h, stw); |
64 | ac9eb073 | bellard | PPC_ST_OP(w, stl); |
65 | 9a64fbe4 | bellard | |
66 | 111bfab3 | bellard | PPC_ST_OP(h_le, st16r); |
67 | 111bfab3 | bellard | PPC_ST_OP(w_le, st32r); |
68 | 111bfab3 | bellard | |
69 | 9a64fbe4 | bellard | /*** Integer load and store with byte reverse ***/
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70 | ac9eb073 | bellard | PPC_LD_OP(hbr, ld16r); |
71 | ac9eb073 | bellard | PPC_LD_OP(wbr, ld32r); |
72 | ac9eb073 | bellard | PPC_ST_OP(hbr, st16r); |
73 | ac9eb073 | bellard | PPC_ST_OP(wbr, st32r); |
74 | 9a64fbe4 | bellard | |
75 | 111bfab3 | bellard | PPC_LD_OP(hbr_le, lduw); |
76 | 111bfab3 | bellard | PPC_LD_OP(wbr_le, ldl); |
77 | 111bfab3 | bellard | PPC_ST_OP(hbr_le, stw); |
78 | 111bfab3 | bellard | PPC_ST_OP(wbr_le, stl); |
79 | 111bfab3 | bellard | |
80 | 9a64fbe4 | bellard | /*** Integer load and store multiple ***/
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81 | 9a64fbe4 | bellard | PPC_OP(glue(lmw, MEMSUFFIX)) |
82 | 9a64fbe4 | bellard | { |
83 | 9a64fbe4 | bellard | int dst = PARAM(1); |
84 | 9a64fbe4 | bellard | |
85 | 9a64fbe4 | bellard | for (; dst < 32; dst++, T0 += 4) { |
86 | 0fa85d43 | bellard | ugpr(dst) = glue(ldl, MEMSUFFIX)(T0); |
87 | 9a64fbe4 | bellard | } |
88 | 9a64fbe4 | bellard | RETURN(); |
89 | 9a64fbe4 | bellard | } |
90 | 9a64fbe4 | bellard | |
91 | 9a64fbe4 | bellard | PPC_OP(glue(stmw, MEMSUFFIX)) |
92 | 9a64fbe4 | bellard | { |
93 | 9a64fbe4 | bellard | int src = PARAM(1); |
94 | 9a64fbe4 | bellard | |
95 | 9a64fbe4 | bellard | for (; src < 32; src++, T0 += 4) { |
96 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0, ugpr(src)); |
97 | 9a64fbe4 | bellard | } |
98 | 9a64fbe4 | bellard | RETURN(); |
99 | 9a64fbe4 | bellard | } |
100 | 9a64fbe4 | bellard | |
101 | 111bfab3 | bellard | PPC_OP(glue(lmw_le, MEMSUFFIX)) |
102 | 111bfab3 | bellard | { |
103 | 111bfab3 | bellard | int dst = PARAM(1); |
104 | 111bfab3 | bellard | |
105 | 111bfab3 | bellard | for (; dst < 32; dst++, T0 += 4) { |
106 | 111bfab3 | bellard | ugpr(dst) = glue(ld32r, MEMSUFFIX)(T0); |
107 | 111bfab3 | bellard | } |
108 | 111bfab3 | bellard | RETURN(); |
109 | 111bfab3 | bellard | } |
110 | 111bfab3 | bellard | |
111 | 111bfab3 | bellard | PPC_OP(glue(stmw_le, MEMSUFFIX)) |
112 | 111bfab3 | bellard | { |
113 | 111bfab3 | bellard | int src = PARAM(1); |
114 | 111bfab3 | bellard | |
115 | 111bfab3 | bellard | for (; src < 32; src++, T0 += 4) { |
116 | 111bfab3 | bellard | glue(st32r, MEMSUFFIX)(T0, ugpr(src)); |
117 | 111bfab3 | bellard | } |
118 | 111bfab3 | bellard | RETURN(); |
119 | 111bfab3 | bellard | } |
120 | 111bfab3 | bellard | |
121 | 9a64fbe4 | bellard | /*** Integer load and store strings ***/
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122 | 9a64fbe4 | bellard | PPC_OP(glue(lswi, MEMSUFFIX)) |
123 | 9a64fbe4 | bellard | { |
124 | 9a64fbe4 | bellard | glue(do_lsw, MEMSUFFIX)(PARAM(1));
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125 | 9a64fbe4 | bellard | RETURN(); |
126 | 9a64fbe4 | bellard | } |
127 | 9a64fbe4 | bellard | |
128 | 111bfab3 | bellard | void glue(do_lsw_le, MEMSUFFIX) (int dst); |
129 | 111bfab3 | bellard | PPC_OP(glue(lswi_le, MEMSUFFIX)) |
130 | 111bfab3 | bellard | { |
131 | 111bfab3 | bellard | glue(do_lsw_le, MEMSUFFIX)(PARAM(1));
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132 | 111bfab3 | bellard | RETURN(); |
133 | 111bfab3 | bellard | } |
134 | 111bfab3 | bellard | |
135 | 9a64fbe4 | bellard | /* PPC32 specification says we must generate an exception if
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136 | 9a64fbe4 | bellard | * rA is in the range of registers to be loaded.
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137 | 9a64fbe4 | bellard | * In an other hand, IBM says this is valid, but rA won't be loaded.
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138 | 9a64fbe4 | bellard | * For now, I'll follow the spec...
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139 | 9a64fbe4 | bellard | */
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140 | 9a64fbe4 | bellard | PPC_OP(glue(lswx, MEMSUFFIX)) |
141 | 9a64fbe4 | bellard | { |
142 | 9a64fbe4 | bellard | if (T1 > 0) { |
143 | 9a64fbe4 | bellard | if ((PARAM(1) < PARAM(2) && (PARAM(1) + T1) > PARAM(2)) || |
144 | 9a64fbe4 | bellard | (PARAM(1) < PARAM(3) && (PARAM(1) + T1) > PARAM(3))) { |
145 | 9fddaa0c | bellard | do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
146 | 9a64fbe4 | bellard | } else {
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147 | 9a64fbe4 | bellard | glue(do_lsw, MEMSUFFIX)(PARAM(1));
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148 | 9a64fbe4 | bellard | } |
149 | 9a64fbe4 | bellard | } |
150 | 9a64fbe4 | bellard | RETURN(); |
151 | 9a64fbe4 | bellard | } |
152 | 9a64fbe4 | bellard | |
153 | 111bfab3 | bellard | PPC_OP(glue(lswx_le, MEMSUFFIX)) |
154 | 111bfab3 | bellard | { |
155 | 111bfab3 | bellard | if (T1 > 0) { |
156 | 111bfab3 | bellard | if ((PARAM(1) < PARAM(2) && (PARAM(1) + T1) > PARAM(2)) || |
157 | 111bfab3 | bellard | (PARAM(1) < PARAM(3) && (PARAM(1) + T1) > PARAM(3))) { |
158 | 111bfab3 | bellard | do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
159 | 111bfab3 | bellard | } else {
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160 | 111bfab3 | bellard | glue(do_lsw_le, MEMSUFFIX)(PARAM(1));
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161 | 111bfab3 | bellard | } |
162 | 111bfab3 | bellard | } |
163 | 111bfab3 | bellard | RETURN(); |
164 | 111bfab3 | bellard | } |
165 | 111bfab3 | bellard | |
166 | 9a64fbe4 | bellard | PPC_OP(glue(stsw, MEMSUFFIX)) |
167 | 9a64fbe4 | bellard | { |
168 | 9a64fbe4 | bellard | glue(do_stsw, MEMSUFFIX)(PARAM(1));
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169 | 9a64fbe4 | bellard | RETURN(); |
170 | 9a64fbe4 | bellard | } |
171 | 9a64fbe4 | bellard | |
172 | 111bfab3 | bellard | void glue(do_stsw_le, MEMSUFFIX) (int src); |
173 | 111bfab3 | bellard | PPC_OP(glue(stsw_le, MEMSUFFIX)) |
174 | 111bfab3 | bellard | { |
175 | 111bfab3 | bellard | glue(do_stsw_le, MEMSUFFIX)(PARAM(1));
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176 | 111bfab3 | bellard | RETURN(); |
177 | 111bfab3 | bellard | } |
178 | 111bfab3 | bellard | |
179 | 9a64fbe4 | bellard | /*** Floating-point store ***/
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180 | 9a64fbe4 | bellard | #define PPC_STF_OP(name, op) \
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181 | 9a64fbe4 | bellard | PPC_OP(glue(glue(st, name), MEMSUFFIX)) \ |
182 | 9a64fbe4 | bellard | { \ |
183 | 0fa85d43 | bellard | glue(op, MEMSUFFIX)(T0, FT1); \ |
184 | 9a64fbe4 | bellard | RETURN(); \ |
185 | 9a64fbe4 | bellard | } |
186 | 9a64fbe4 | bellard | |
187 | 9a64fbe4 | bellard | PPC_STF_OP(fd, stfq); |
188 | 9a64fbe4 | bellard | PPC_STF_OP(fs, stfl); |
189 | 9a64fbe4 | bellard | |
190 | 111bfab3 | bellard | static inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d) |
191 | 111bfab3 | bellard | { |
192 | 111bfab3 | bellard | union {
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193 | 111bfab3 | bellard | double d;
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194 | 111bfab3 | bellard | uint64_t u; |
195 | 111bfab3 | bellard | } u; |
196 | 111bfab3 | bellard | |
197 | 111bfab3 | bellard | u.d = d; |
198 | 111bfab3 | bellard | u.u = ((u.u & 0xFF00000000000000ULL) >> 56) | |
199 | 111bfab3 | bellard | ((u.u & 0x00FF000000000000ULL) >> 40) | |
200 | 111bfab3 | bellard | ((u.u & 0x0000FF0000000000ULL) >> 24) | |
201 | 111bfab3 | bellard | ((u.u & 0x000000FF00000000ULL) >> 8) | |
202 | 111bfab3 | bellard | ((u.u & 0x00000000FF000000ULL) << 8) | |
203 | 111bfab3 | bellard | ((u.u & 0x0000000000FF0000ULL) << 24) | |
204 | 111bfab3 | bellard | ((u.u & 0x000000000000FF00ULL) << 40) | |
205 | 111bfab3 | bellard | ((u.u & 0x00000000000000FFULL) << 56); |
206 | 111bfab3 | bellard | glue(stfq, MEMSUFFIX)(EA, u.d); |
207 | 111bfab3 | bellard | } |
208 | 111bfab3 | bellard | |
209 | 111bfab3 | bellard | static inline void glue(stflr, MEMSUFFIX) (target_ulong EA, float f) |
210 | 111bfab3 | bellard | { |
211 | 111bfab3 | bellard | union {
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212 | 111bfab3 | bellard | float f;
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213 | 111bfab3 | bellard | uint32_t u; |
214 | 111bfab3 | bellard | } u; |
215 | 111bfab3 | bellard | |
216 | 111bfab3 | bellard | u.f = f; |
217 | 111bfab3 | bellard | u.u = ((u.u & 0xFF000000UL) >> 24) | |
218 | 111bfab3 | bellard | ((u.u & 0x00FF0000ULL) >> 8) | |
219 | 111bfab3 | bellard | ((u.u & 0x0000FF00UL) << 8) | |
220 | 111bfab3 | bellard | ((u.u & 0x000000FFULL) << 24); |
221 | 111bfab3 | bellard | glue(stfl, MEMSUFFIX)(EA, u.f); |
222 | 111bfab3 | bellard | } |
223 | 111bfab3 | bellard | |
224 | 111bfab3 | bellard | PPC_STF_OP(fd_le, stfqr); |
225 | 111bfab3 | bellard | PPC_STF_OP(fs_le, stflr); |
226 | 111bfab3 | bellard | |
227 | 9a64fbe4 | bellard | /*** Floating-point load ***/
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228 | 9a64fbe4 | bellard | #define PPC_LDF_OP(name, op) \
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229 | 9a64fbe4 | bellard | PPC_OP(glue(glue(l, name), MEMSUFFIX)) \ |
230 | 9a64fbe4 | bellard | { \ |
231 | 0fa85d43 | bellard | FT1 = glue(op, MEMSUFFIX)(T0); \ |
232 | 9a64fbe4 | bellard | RETURN(); \ |
233 | 9a64fbe4 | bellard | } |
234 | 9a64fbe4 | bellard | |
235 | 9a64fbe4 | bellard | PPC_LDF_OP(fd, ldfq); |
236 | 9a64fbe4 | bellard | PPC_LDF_OP(fs, ldfl); |
237 | 9a64fbe4 | bellard | |
238 | 111bfab3 | bellard | static inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA) |
239 | 111bfab3 | bellard | { |
240 | 111bfab3 | bellard | union {
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241 | 111bfab3 | bellard | double d;
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242 | 111bfab3 | bellard | uint64_t u; |
243 | 111bfab3 | bellard | } u; |
244 | 111bfab3 | bellard | |
245 | 111bfab3 | bellard | u.d = glue(ldfq, MEMSUFFIX)(EA); |
246 | 111bfab3 | bellard | u.u = ((u.u & 0xFF00000000000000ULL) >> 56) | |
247 | 111bfab3 | bellard | ((u.u & 0x00FF000000000000ULL) >> 40) | |
248 | 111bfab3 | bellard | ((u.u & 0x0000FF0000000000ULL) >> 24) | |
249 | 111bfab3 | bellard | ((u.u & 0x000000FF00000000ULL) >> 8) | |
250 | 111bfab3 | bellard | ((u.u & 0x00000000FF000000ULL) << 8) | |
251 | 111bfab3 | bellard | ((u.u & 0x0000000000FF0000ULL) << 24) | |
252 | 111bfab3 | bellard | ((u.u & 0x000000000000FF00ULL) << 40) | |
253 | 111bfab3 | bellard | ((u.u & 0x00000000000000FFULL) << 56); |
254 | 111bfab3 | bellard | |
255 | 111bfab3 | bellard | return u.d;
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256 | 111bfab3 | bellard | } |
257 | 111bfab3 | bellard | |
258 | 111bfab3 | bellard | static inline float glue(ldflr, MEMSUFFIX) (target_ulong EA) |
259 | 111bfab3 | bellard | { |
260 | 111bfab3 | bellard | union {
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261 | 111bfab3 | bellard | float f;
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262 | 111bfab3 | bellard | uint32_t u; |
263 | 111bfab3 | bellard | } u; |
264 | 111bfab3 | bellard | |
265 | 111bfab3 | bellard | u.f = glue(ldfl, MEMSUFFIX)(EA); |
266 | 111bfab3 | bellard | u.u = ((u.u & 0xFF000000UL) >> 24) | |
267 | 111bfab3 | bellard | ((u.u & 0x00FF0000ULL) >> 8) | |
268 | 111bfab3 | bellard | ((u.u & 0x0000FF00UL) << 8) | |
269 | 111bfab3 | bellard | ((u.u & 0x000000FFULL) << 24); |
270 | 111bfab3 | bellard | |
271 | 111bfab3 | bellard | return u.f;
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272 | 111bfab3 | bellard | } |
273 | 111bfab3 | bellard | |
274 | 111bfab3 | bellard | PPC_LDF_OP(fd_le, ldfqr); |
275 | 111bfab3 | bellard | PPC_LDF_OP(fs_le, ldflr); |
276 | 111bfab3 | bellard | |
277 | 985a19d6 | bellard | /* Load and set reservation */
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278 | 985a19d6 | bellard | PPC_OP(glue(lwarx, MEMSUFFIX)) |
279 | 985a19d6 | bellard | { |
280 | 985a19d6 | bellard | if (T0 & 0x03) { |
281 | 9fddaa0c | bellard | do_raise_exception(EXCP_ALIGN); |
282 | 985a19d6 | bellard | } else {
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283 | 0fa85d43 | bellard | T1 = glue(ldl, MEMSUFFIX)(T0); |
284 | 28fbe299 | bellard | regs->reserve = T0; |
285 | 985a19d6 | bellard | } |
286 | 985a19d6 | bellard | RETURN(); |
287 | 985a19d6 | bellard | } |
288 | 985a19d6 | bellard | |
289 | 111bfab3 | bellard | PPC_OP(glue(lwarx_le, MEMSUFFIX)) |
290 | 111bfab3 | bellard | { |
291 | 111bfab3 | bellard | if (T0 & 0x03) { |
292 | 111bfab3 | bellard | do_raise_exception(EXCP_ALIGN); |
293 | 111bfab3 | bellard | } else {
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294 | 111bfab3 | bellard | T1 = glue(ld32r, MEMSUFFIX)(T0); |
295 | 111bfab3 | bellard | regs->reserve = T0; |
296 | 111bfab3 | bellard | } |
297 | 111bfab3 | bellard | RETURN(); |
298 | 111bfab3 | bellard | } |
299 | 111bfab3 | bellard | |
300 | 9a64fbe4 | bellard | /* Store with reservation */
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301 | 9a64fbe4 | bellard | PPC_OP(glue(stwcx, MEMSUFFIX)) |
302 | 9a64fbe4 | bellard | { |
303 | 9a64fbe4 | bellard | if (T0 & 0x03) { |
304 | 9fddaa0c | bellard | do_raise_exception(EXCP_ALIGN); |
305 | 9a64fbe4 | bellard | } else {
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306 | 9a64fbe4 | bellard | if (regs->reserve != T0) {
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307 | 9a64fbe4 | bellard | env->crf[0] = xer_ov;
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308 | 9a64fbe4 | bellard | } else {
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309 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0, T1); |
310 | 9a64fbe4 | bellard | env->crf[0] = xer_ov | 0x02; |
311 | 9a64fbe4 | bellard | } |
312 | 9a64fbe4 | bellard | } |
313 | 9a64fbe4 | bellard | regs->reserve = 0;
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314 | 9a64fbe4 | bellard | RETURN(); |
315 | 9a64fbe4 | bellard | } |
316 | 9a64fbe4 | bellard | |
317 | 111bfab3 | bellard | PPC_OP(glue(stwcx_le, MEMSUFFIX)) |
318 | 111bfab3 | bellard | { |
319 | 111bfab3 | bellard | if (T0 & 0x03) { |
320 | 111bfab3 | bellard | do_raise_exception(EXCP_ALIGN); |
321 | 111bfab3 | bellard | } else {
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322 | 111bfab3 | bellard | if (regs->reserve != T0) {
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323 | 111bfab3 | bellard | env->crf[0] = xer_ov;
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324 | 111bfab3 | bellard | } else {
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325 | 111bfab3 | bellard | glue(st32r, MEMSUFFIX)(T0, T1); |
326 | 111bfab3 | bellard | env->crf[0] = xer_ov | 0x02; |
327 | 111bfab3 | bellard | } |
328 | 111bfab3 | bellard | } |
329 | 111bfab3 | bellard | regs->reserve = 0;
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330 | 111bfab3 | bellard | RETURN(); |
331 | 111bfab3 | bellard | } |
332 | 111bfab3 | bellard | |
333 | 9a64fbe4 | bellard | PPC_OP(glue(dcbz, MEMSUFFIX)) |
334 | 9a64fbe4 | bellard | { |
335 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x00, 0); |
336 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x04, 0); |
337 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x08, 0); |
338 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x0C, 0); |
339 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x10, 0); |
340 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x14, 0); |
341 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x18, 0); |
342 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x1C, 0); |
343 | 9a64fbe4 | bellard | RETURN(); |
344 | 9a64fbe4 | bellard | } |
345 | 9a64fbe4 | bellard | |
346 | 9a64fbe4 | bellard | /* External access */
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347 | 9a64fbe4 | bellard | PPC_OP(glue(eciwx, MEMSUFFIX)) |
348 | 9a64fbe4 | bellard | { |
349 | 0fa85d43 | bellard | T1 = glue(ldl, MEMSUFFIX)(T0); |
350 | 9a64fbe4 | bellard | RETURN(); |
351 | 9a64fbe4 | bellard | } |
352 | 9a64fbe4 | bellard | |
353 | 9a64fbe4 | bellard | PPC_OP(glue(ecowx, MEMSUFFIX)) |
354 | 9a64fbe4 | bellard | { |
355 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0, T1); |
356 | 9a64fbe4 | bellard | RETURN(); |
357 | 9a64fbe4 | bellard | } |
358 | 9a64fbe4 | bellard | |
359 | 111bfab3 | bellard | PPC_OP(glue(eciwx_le, MEMSUFFIX)) |
360 | 111bfab3 | bellard | { |
361 | 111bfab3 | bellard | T1 = glue(ld32r, MEMSUFFIX)(T0); |
362 | 111bfab3 | bellard | RETURN(); |
363 | 111bfab3 | bellard | } |
364 | 111bfab3 | bellard | |
365 | 111bfab3 | bellard | PPC_OP(glue(ecowx_le, MEMSUFFIX)) |
366 | 111bfab3 | bellard | { |
367 | 111bfab3 | bellard | glue(st32r, MEMSUFFIX)(T0, T1); |
368 | 111bfab3 | bellard | RETURN(); |
369 | 111bfab3 | bellard | } |
370 | 111bfab3 | bellard | |
371 | 9a64fbe4 | bellard | #undef MEMSUFFIX |