root / hw / hpet.c @ 177539e0
History | View | Annotate | Download (18.5 kB)
1 | 16b29ae1 | aliguori | /*
|
---|---|---|---|
2 | 16b29ae1 | aliguori | * High Precisition Event Timer emulation
|
3 | 16b29ae1 | aliguori | *
|
4 | 16b29ae1 | aliguori | * Copyright (c) 2007 Alexander Graf
|
5 | 16b29ae1 | aliguori | * Copyright (c) 2008 IBM Corporation
|
6 | 16b29ae1 | aliguori | *
|
7 | 16b29ae1 | aliguori | * Authors: Beth Kon <bkon@us.ibm.com>
|
8 | 16b29ae1 | aliguori | *
|
9 | 16b29ae1 | aliguori | * This library is free software; you can redistribute it and/or
|
10 | 16b29ae1 | aliguori | * modify it under the terms of the GNU Lesser General Public
|
11 | 16b29ae1 | aliguori | * License as published by the Free Software Foundation; either
|
12 | 16b29ae1 | aliguori | * version 2 of the License, or (at your option) any later version.
|
13 | 16b29ae1 | aliguori | *
|
14 | 16b29ae1 | aliguori | * This library is distributed in the hope that it will be useful,
|
15 | 16b29ae1 | aliguori | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
16 | 16b29ae1 | aliguori | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
17 | 16b29ae1 | aliguori | * Lesser General Public License for more details.
|
18 | 16b29ae1 | aliguori | *
|
19 | 16b29ae1 | aliguori | * You should have received a copy of the GNU Lesser General Public
|
20 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
21 | 16b29ae1 | aliguori | *
|
22 | 16b29ae1 | aliguori | * *****************************************************************
|
23 | 16b29ae1 | aliguori | *
|
24 | 16b29ae1 | aliguori | * This driver attempts to emulate an HPET device in software.
|
25 | 16b29ae1 | aliguori | */
|
26 | 16b29ae1 | aliguori | |
27 | 16b29ae1 | aliguori | #include "hw.h" |
28 | bf4f74c0 | aurel32 | #include "pc.h" |
29 | 16b29ae1 | aliguori | #include "console.h" |
30 | 16b29ae1 | aliguori | #include "qemu-timer.h" |
31 | 16b29ae1 | aliguori | #include "hpet_emul.h" |
32 | 16b29ae1 | aliguori | |
33 | 16b29ae1 | aliguori | //#define HPET_DEBUG
|
34 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
35 | 16b29ae1 | aliguori | #define dprintf printf
|
36 | 16b29ae1 | aliguori | #else
|
37 | 16b29ae1 | aliguori | #define dprintf(...)
|
38 | 16b29ae1 | aliguori | #endif
|
39 | 16b29ae1 | aliguori | |
40 | 16b29ae1 | aliguori | static HPETState *hpet_statep;
|
41 | 16b29ae1 | aliguori | |
42 | 16b29ae1 | aliguori | uint32_t hpet_in_legacy_mode(void)
|
43 | 16b29ae1 | aliguori | { |
44 | 16b29ae1 | aliguori | if (hpet_statep)
|
45 | 16b29ae1 | aliguori | return hpet_statep->config & HPET_CFG_LEGACY;
|
46 | 16b29ae1 | aliguori | else
|
47 | 16b29ae1 | aliguori | return 0; |
48 | 16b29ae1 | aliguori | } |
49 | 16b29ae1 | aliguori | |
50 | c50c2d68 | aurel32 | static uint32_t timer_int_route(struct HPETTimer *timer) |
51 | 16b29ae1 | aliguori | { |
52 | 16b29ae1 | aliguori | uint32_t route; |
53 | 16b29ae1 | aliguori | route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; |
54 | 16b29ae1 | aliguori | return route;
|
55 | 16b29ae1 | aliguori | } |
56 | 16b29ae1 | aliguori | |
57 | 16b29ae1 | aliguori | static uint32_t hpet_enabled(void) |
58 | 16b29ae1 | aliguori | { |
59 | 16b29ae1 | aliguori | return hpet_statep->config & HPET_CFG_ENABLE;
|
60 | 16b29ae1 | aliguori | } |
61 | 16b29ae1 | aliguori | |
62 | 16b29ae1 | aliguori | static uint32_t timer_is_periodic(HPETTimer *t)
|
63 | 16b29ae1 | aliguori | { |
64 | 16b29ae1 | aliguori | return t->config & HPET_TN_PERIODIC;
|
65 | 16b29ae1 | aliguori | } |
66 | 16b29ae1 | aliguori | |
67 | 16b29ae1 | aliguori | static uint32_t timer_enabled(HPETTimer *t)
|
68 | 16b29ae1 | aliguori | { |
69 | 16b29ae1 | aliguori | return t->config & HPET_TN_ENABLE;
|
70 | 16b29ae1 | aliguori | } |
71 | 16b29ae1 | aliguori | |
72 | 16b29ae1 | aliguori | static uint32_t hpet_time_after(uint64_t a, uint64_t b)
|
73 | 16b29ae1 | aliguori | { |
74 | 16b29ae1 | aliguori | return ((int32_t)(b) - (int32_t)(a) < 0); |
75 | 16b29ae1 | aliguori | } |
76 | 16b29ae1 | aliguori | |
77 | 16b29ae1 | aliguori | static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
|
78 | 16b29ae1 | aliguori | { |
79 | 16b29ae1 | aliguori | return ((int64_t)(b) - (int64_t)(a) < 0); |
80 | 16b29ae1 | aliguori | } |
81 | 16b29ae1 | aliguori | |
82 | c50c2d68 | aurel32 | static uint64_t ticks_to_ns(uint64_t value)
|
83 | 16b29ae1 | aliguori | { |
84 | 16b29ae1 | aliguori | return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
|
85 | 16b29ae1 | aliguori | } |
86 | 16b29ae1 | aliguori | |
87 | c50c2d68 | aurel32 | static uint64_t ns_to_ticks(uint64_t value)
|
88 | 16b29ae1 | aliguori | { |
89 | 16b29ae1 | aliguori | return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
|
90 | 16b29ae1 | aliguori | } |
91 | 16b29ae1 | aliguori | |
92 | 16b29ae1 | aliguori | static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
|
93 | 16b29ae1 | aliguori | { |
94 | 16b29ae1 | aliguori | new &= mask; |
95 | 16b29ae1 | aliguori | new |= old & ~mask; |
96 | 16b29ae1 | aliguori | return new;
|
97 | 16b29ae1 | aliguori | } |
98 | 16b29ae1 | aliguori | |
99 | 16b29ae1 | aliguori | static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) |
100 | 16b29ae1 | aliguori | { |
101 | c50c2d68 | aurel32 | return (!(old & mask) && (new & mask));
|
102 | 16b29ae1 | aliguori | } |
103 | 16b29ae1 | aliguori | |
104 | 16b29ae1 | aliguori | static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) |
105 | 16b29ae1 | aliguori | { |
106 | c50c2d68 | aurel32 | return ((old & mask) && !(new & mask));
|
107 | 16b29ae1 | aliguori | } |
108 | 16b29ae1 | aliguori | |
109 | c50c2d68 | aurel32 | static uint64_t hpet_get_ticks(void) |
110 | 16b29ae1 | aliguori | { |
111 | 16b29ae1 | aliguori | uint64_t ticks; |
112 | 16b29ae1 | aliguori | ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset); |
113 | 16b29ae1 | aliguori | return ticks;
|
114 | 16b29ae1 | aliguori | } |
115 | 16b29ae1 | aliguori | |
116 | c50c2d68 | aurel32 | /*
|
117 | c50c2d68 | aurel32 | * calculate diff between comparator value and current ticks
|
118 | 16b29ae1 | aliguori | */
|
119 | 16b29ae1 | aliguori | static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) |
120 | 16b29ae1 | aliguori | { |
121 | c50c2d68 | aurel32 | |
122 | 16b29ae1 | aliguori | if (t->config & HPET_TN_32BIT) {
|
123 | 16b29ae1 | aliguori | uint32_t diff, cmp; |
124 | 16b29ae1 | aliguori | cmp = (uint32_t)t->cmp; |
125 | 16b29ae1 | aliguori | diff = cmp - (uint32_t)current; |
126 | 16b29ae1 | aliguori | diff = (int32_t)diff > 0 ? diff : (uint32_t)0; |
127 | 16b29ae1 | aliguori | return (uint64_t)diff;
|
128 | 16b29ae1 | aliguori | } else {
|
129 | 16b29ae1 | aliguori | uint64_t diff, cmp; |
130 | 16b29ae1 | aliguori | cmp = t->cmp; |
131 | 16b29ae1 | aliguori | diff = cmp - current; |
132 | 16b29ae1 | aliguori | diff = (int64_t)diff > 0 ? diff : (uint64_t)0; |
133 | 16b29ae1 | aliguori | return diff;
|
134 | 16b29ae1 | aliguori | } |
135 | 16b29ae1 | aliguori | } |
136 | 16b29ae1 | aliguori | |
137 | 16b29ae1 | aliguori | static void update_irq(struct HPETTimer *timer) |
138 | 16b29ae1 | aliguori | { |
139 | 16b29ae1 | aliguori | qemu_irq irq; |
140 | 16b29ae1 | aliguori | int route;
|
141 | 16b29ae1 | aliguori | |
142 | 16b29ae1 | aliguori | if (timer->tn <= 1 && hpet_in_legacy_mode()) { |
143 | 16b29ae1 | aliguori | /* if LegacyReplacementRoute bit is set, HPET specification requires
|
144 | 16b29ae1 | aliguori | * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
|
145 | c50c2d68 | aurel32 | * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
|
146 | 16b29ae1 | aliguori | */
|
147 | 16b29ae1 | aliguori | if (timer->tn == 0) { |
148 | 16b29ae1 | aliguori | irq=timer->state->irqs[0];
|
149 | 16b29ae1 | aliguori | } else
|
150 | 16b29ae1 | aliguori | irq=timer->state->irqs[8];
|
151 | 16b29ae1 | aliguori | } else {
|
152 | 16b29ae1 | aliguori | route=timer_int_route(timer); |
153 | 16b29ae1 | aliguori | irq=timer->state->irqs[route]; |
154 | 16b29ae1 | aliguori | } |
155 | 16b29ae1 | aliguori | if (timer_enabled(timer) && hpet_enabled()) {
|
156 | 16b29ae1 | aliguori | qemu_irq_pulse(irq); |
157 | 16b29ae1 | aliguori | } |
158 | 16b29ae1 | aliguori | } |
159 | 16b29ae1 | aliguori | |
160 | 16b29ae1 | aliguori | static void hpet_save(QEMUFile *f, void *opaque) |
161 | 16b29ae1 | aliguori | { |
162 | 16b29ae1 | aliguori | HPETState *s = opaque; |
163 | 16b29ae1 | aliguori | int i;
|
164 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->config); |
165 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->isr); |
166 | 16b29ae1 | aliguori | /* save current counter value */
|
167 | c50c2d68 | aurel32 | s->hpet_counter = hpet_get_ticks(); |
168 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->hpet_counter); |
169 | 16b29ae1 | aliguori | |
170 | 16b29ae1 | aliguori | for (i = 0; i < HPET_NUM_TIMERS; i++) { |
171 | 16b29ae1 | aliguori | qemu_put_8s(f, &s->timer[i].tn); |
172 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->timer[i].config); |
173 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->timer[i].cmp); |
174 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->timer[i].fsb); |
175 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->timer[i].period); |
176 | 16b29ae1 | aliguori | qemu_put_8s(f, &s->timer[i].wrap_flag); |
177 | 16b29ae1 | aliguori | if (s->timer[i].qemu_timer) {
|
178 | 16b29ae1 | aliguori | qemu_put_timer(f, s->timer[i].qemu_timer); |
179 | 16b29ae1 | aliguori | } |
180 | 16b29ae1 | aliguori | } |
181 | 16b29ae1 | aliguori | } |
182 | 16b29ae1 | aliguori | |
183 | 16b29ae1 | aliguori | static int hpet_load(QEMUFile *f, void *opaque, int version_id) |
184 | 16b29ae1 | aliguori | { |
185 | 16b29ae1 | aliguori | HPETState *s = opaque; |
186 | 16b29ae1 | aliguori | int i;
|
187 | c50c2d68 | aurel32 | |
188 | 16b29ae1 | aliguori | if (version_id != 1) |
189 | 16b29ae1 | aliguori | return -EINVAL;
|
190 | 16b29ae1 | aliguori | |
191 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->config); |
192 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->isr); |
193 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->hpet_counter); |
194 | 16b29ae1 | aliguori | /* Recalculate the offset between the main counter and guest time */
|
195 | 16b29ae1 | aliguori | s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); |
196 | 16b29ae1 | aliguori | |
197 | 16b29ae1 | aliguori | for (i = 0; i < HPET_NUM_TIMERS; i++) { |
198 | 16b29ae1 | aliguori | qemu_get_8s(f, &s->timer[i].tn); |
199 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->timer[i].config); |
200 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->timer[i].cmp); |
201 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->timer[i].fsb); |
202 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->timer[i].period); |
203 | 16b29ae1 | aliguori | qemu_get_8s(f, &s->timer[i].wrap_flag); |
204 | 16b29ae1 | aliguori | if (s->timer[i].qemu_timer) {
|
205 | 16b29ae1 | aliguori | qemu_get_timer(f, s->timer[i].qemu_timer); |
206 | 16b29ae1 | aliguori | } |
207 | 16b29ae1 | aliguori | } |
208 | 16b29ae1 | aliguori | return 0; |
209 | 16b29ae1 | aliguori | } |
210 | 16b29ae1 | aliguori | |
211 | c50c2d68 | aurel32 | /*
|
212 | 16b29ae1 | aliguori | * timer expiration callback
|
213 | 16b29ae1 | aliguori | */
|
214 | 16b29ae1 | aliguori | static void hpet_timer(void *opaque) |
215 | 16b29ae1 | aliguori | { |
216 | 16b29ae1 | aliguori | HPETTimer *t = (HPETTimer*)opaque; |
217 | 16b29ae1 | aliguori | uint64_t diff; |
218 | 16b29ae1 | aliguori | |
219 | 16b29ae1 | aliguori | uint64_t period = t->period; |
220 | 16b29ae1 | aliguori | uint64_t cur_tick = hpet_get_ticks(); |
221 | 16b29ae1 | aliguori | |
222 | 16b29ae1 | aliguori | if (timer_is_periodic(t) && period != 0) { |
223 | 16b29ae1 | aliguori | if (t->config & HPET_TN_32BIT) {
|
224 | 16b29ae1 | aliguori | while (hpet_time_after(cur_tick, t->cmp))
|
225 | 16b29ae1 | aliguori | t->cmp = (uint32_t)(t->cmp + t->period); |
226 | 16b29ae1 | aliguori | } else
|
227 | 16b29ae1 | aliguori | while (hpet_time_after64(cur_tick, t->cmp))
|
228 | 16b29ae1 | aliguori | t->cmp += period; |
229 | 16b29ae1 | aliguori | |
230 | 16b29ae1 | aliguori | diff = hpet_calculate_diff(t, cur_tick); |
231 | c50c2d68 | aurel32 | qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
232 | 16b29ae1 | aliguori | + (int64_t)ticks_to_ns(diff)); |
233 | 16b29ae1 | aliguori | } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
234 | 16b29ae1 | aliguori | if (t->wrap_flag) {
|
235 | 16b29ae1 | aliguori | diff = hpet_calculate_diff(t, cur_tick); |
236 | c50c2d68 | aurel32 | qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
237 | 16b29ae1 | aliguori | + (int64_t)ticks_to_ns(diff)); |
238 | 16b29ae1 | aliguori | t->wrap_flag = 0;
|
239 | 16b29ae1 | aliguori | } |
240 | 16b29ae1 | aliguori | } |
241 | 16b29ae1 | aliguori | update_irq(t); |
242 | 16b29ae1 | aliguori | } |
243 | 16b29ae1 | aliguori | |
244 | 16b29ae1 | aliguori | static void hpet_set_timer(HPETTimer *t) |
245 | 16b29ae1 | aliguori | { |
246 | 16b29ae1 | aliguori | uint64_t diff; |
247 | 16b29ae1 | aliguori | uint32_t wrap_diff; /* how many ticks until we wrap? */
|
248 | 16b29ae1 | aliguori | uint64_t cur_tick = hpet_get_ticks(); |
249 | c50c2d68 | aurel32 | |
250 | 16b29ae1 | aliguori | /* whenever new timer is being set up, make sure wrap_flag is 0 */
|
251 | 16b29ae1 | aliguori | t->wrap_flag = 0;
|
252 | 16b29ae1 | aliguori | diff = hpet_calculate_diff(t, cur_tick); |
253 | 16b29ae1 | aliguori | |
254 | c50c2d68 | aurel32 | /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
|
255 | 16b29ae1 | aliguori | * counter wraps in addition to an interrupt with comparator match.
|
256 | c50c2d68 | aurel32 | */
|
257 | 16b29ae1 | aliguori | if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
|
258 | 16b29ae1 | aliguori | wrap_diff = 0xffffffff - (uint32_t)cur_tick;
|
259 | 16b29ae1 | aliguori | if (wrap_diff < (uint32_t)diff) {
|
260 | 16b29ae1 | aliguori | diff = wrap_diff; |
261 | c50c2d68 | aurel32 | t->wrap_flag = 1;
|
262 | 16b29ae1 | aliguori | } |
263 | 16b29ae1 | aliguori | } |
264 | c50c2d68 | aurel32 | qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
265 | 16b29ae1 | aliguori | + (int64_t)ticks_to_ns(diff)); |
266 | 16b29ae1 | aliguori | } |
267 | 16b29ae1 | aliguori | |
268 | 16b29ae1 | aliguori | static void hpet_del_timer(HPETTimer *t) |
269 | 16b29ae1 | aliguori | { |
270 | 16b29ae1 | aliguori | qemu_del_timer(t->qemu_timer); |
271 | 16b29ae1 | aliguori | } |
272 | 16b29ae1 | aliguori | |
273 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
274 | 16b29ae1 | aliguori | static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr) |
275 | 16b29ae1 | aliguori | { |
276 | 16b29ae1 | aliguori | printf("qemu: hpet_read b at %" PRIx64 "\n", addr); |
277 | 16b29ae1 | aliguori | return 0; |
278 | 16b29ae1 | aliguori | } |
279 | 16b29ae1 | aliguori | |
280 | 16b29ae1 | aliguori | static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr) |
281 | 16b29ae1 | aliguori | { |
282 | 16b29ae1 | aliguori | printf("qemu: hpet_read w at %" PRIx64 "\n", addr); |
283 | 16b29ae1 | aliguori | return 0; |
284 | 16b29ae1 | aliguori | } |
285 | 16b29ae1 | aliguori | #endif
|
286 | 16b29ae1 | aliguori | |
287 | 16b29ae1 | aliguori | static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr) |
288 | 16b29ae1 | aliguori | { |
289 | 16b29ae1 | aliguori | HPETState *s = (HPETState *)opaque; |
290 | 16b29ae1 | aliguori | uint64_t cur_tick, index; |
291 | 16b29ae1 | aliguori | |
292 | 16b29ae1 | aliguori | dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); |
293 | 16b29ae1 | aliguori | index = addr; |
294 | 16b29ae1 | aliguori | /*address range of all TN regs*/
|
295 | 16b29ae1 | aliguori | if (index >= 0x100 && index <= 0x3ff) { |
296 | 16b29ae1 | aliguori | uint8_t timer_id = (addr - 0x100) / 0x20; |
297 | 16b29ae1 | aliguori | if (timer_id > HPET_NUM_TIMERS - 1) { |
298 | 16b29ae1 | aliguori | printf("qemu: timer id out of range\n");
|
299 | 16b29ae1 | aliguori | return 0; |
300 | 16b29ae1 | aliguori | } |
301 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[timer_id]; |
302 | 16b29ae1 | aliguori | |
303 | 16b29ae1 | aliguori | switch ((addr - 0x100) % 0x20) { |
304 | 16b29ae1 | aliguori | case HPET_TN_CFG:
|
305 | 16b29ae1 | aliguori | return timer->config;
|
306 | 16b29ae1 | aliguori | case HPET_TN_CFG + 4: // Interrupt capabilities |
307 | 16b29ae1 | aliguori | return timer->config >> 32; |
308 | 16b29ae1 | aliguori | case HPET_TN_CMP: // comparator register |
309 | 16b29ae1 | aliguori | return timer->cmp;
|
310 | 16b29ae1 | aliguori | case HPET_TN_CMP + 4: |
311 | 16b29ae1 | aliguori | return timer->cmp >> 32; |
312 | 16b29ae1 | aliguori | case HPET_TN_ROUTE:
|
313 | 16b29ae1 | aliguori | return timer->fsb >> 32; |
314 | 16b29ae1 | aliguori | default:
|
315 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_readl\n");
|
316 | 16b29ae1 | aliguori | break;
|
317 | 16b29ae1 | aliguori | } |
318 | 16b29ae1 | aliguori | } else {
|
319 | 16b29ae1 | aliguori | switch (index) {
|
320 | 16b29ae1 | aliguori | case HPET_ID:
|
321 | 16b29ae1 | aliguori | return s->capability;
|
322 | 16b29ae1 | aliguori | case HPET_PERIOD:
|
323 | c50c2d68 | aurel32 | return s->capability >> 32; |
324 | 16b29ae1 | aliguori | case HPET_CFG:
|
325 | 16b29ae1 | aliguori | return s->config;
|
326 | 16b29ae1 | aliguori | case HPET_CFG + 4: |
327 | 16b29ae1 | aliguori | dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
|
328 | 16b29ae1 | aliguori | return 0; |
329 | c50c2d68 | aurel32 | case HPET_COUNTER:
|
330 | 16b29ae1 | aliguori | if (hpet_enabled())
|
331 | 16b29ae1 | aliguori | cur_tick = hpet_get_ticks(); |
332 | c50c2d68 | aurel32 | else
|
333 | 16b29ae1 | aliguori | cur_tick = s->hpet_counter; |
334 | 16b29ae1 | aliguori | dprintf("qemu: reading counter = %" PRIx64 "\n", cur_tick); |
335 | 16b29ae1 | aliguori | return cur_tick;
|
336 | 16b29ae1 | aliguori | case HPET_COUNTER + 4: |
337 | 16b29ae1 | aliguori | if (hpet_enabled())
|
338 | 16b29ae1 | aliguori | cur_tick = hpet_get_ticks(); |
339 | c50c2d68 | aurel32 | else
|
340 | 16b29ae1 | aliguori | cur_tick = s->hpet_counter; |
341 | 16b29ae1 | aliguori | dprintf("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); |
342 | 16b29ae1 | aliguori | return cur_tick >> 32; |
343 | 16b29ae1 | aliguori | case HPET_STATUS:
|
344 | 16b29ae1 | aliguori | return s->isr;
|
345 | 16b29ae1 | aliguori | default:
|
346 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_readl\n");
|
347 | 16b29ae1 | aliguori | break;
|
348 | 16b29ae1 | aliguori | } |
349 | 16b29ae1 | aliguori | } |
350 | 16b29ae1 | aliguori | return 0; |
351 | 16b29ae1 | aliguori | } |
352 | 16b29ae1 | aliguori | |
353 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
354 | c50c2d68 | aurel32 | static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr, |
355 | 16b29ae1 | aliguori | uint32_t value) |
356 | 16b29ae1 | aliguori | { |
357 | c50c2d68 | aurel32 | printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n", |
358 | 16b29ae1 | aliguori | addr, value); |
359 | 16b29ae1 | aliguori | } |
360 | 16b29ae1 | aliguori | |
361 | c50c2d68 | aurel32 | static void hpet_ram_writew(void *opaque, target_phys_addr_t addr, |
362 | 16b29ae1 | aliguori | uint32_t value) |
363 | 16b29ae1 | aliguori | { |
364 | c50c2d68 | aurel32 | printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n", |
365 | 16b29ae1 | aliguori | addr, value); |
366 | 16b29ae1 | aliguori | } |
367 | 16b29ae1 | aliguori | #endif
|
368 | 16b29ae1 | aliguori | |
369 | 16b29ae1 | aliguori | static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, |
370 | 16b29ae1 | aliguori | uint32_t value) |
371 | 16b29ae1 | aliguori | { |
372 | 16b29ae1 | aliguori | int i;
|
373 | 16b29ae1 | aliguori | HPETState *s = (HPETState *)opaque; |
374 | ce536cfd | Beth Kon | uint64_t old_val, new_val, val, index; |
375 | 16b29ae1 | aliguori | |
376 | 16b29ae1 | aliguori | dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); |
377 | 16b29ae1 | aliguori | index = addr; |
378 | 16b29ae1 | aliguori | old_val = hpet_ram_readl(opaque, addr); |
379 | 16b29ae1 | aliguori | new_val = value; |
380 | 16b29ae1 | aliguori | |
381 | 16b29ae1 | aliguori | /*address range of all TN regs*/
|
382 | 16b29ae1 | aliguori | if (index >= 0x100 && index <= 0x3ff) { |
383 | 16b29ae1 | aliguori | uint8_t timer_id = (addr - 0x100) / 0x20; |
384 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
|
385 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[timer_id]; |
386 | c50c2d68 | aurel32 | |
387 | 16b29ae1 | aliguori | switch ((addr - 0x100) % 0x20) { |
388 | 16b29ae1 | aliguori | case HPET_TN_CFG:
|
389 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
|
390 | ce536cfd | Beth Kon | val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); |
391 | ce536cfd | Beth Kon | timer->config = (timer->config & 0xffffffff00000000ULL) | val;
|
392 | 16b29ae1 | aliguori | if (new_val & HPET_TN_32BIT) {
|
393 | 16b29ae1 | aliguori | timer->cmp = (uint32_t)timer->cmp; |
394 | 16b29ae1 | aliguori | timer->period = (uint32_t)timer->period; |
395 | 16b29ae1 | aliguori | } |
396 | 16b29ae1 | aliguori | if (new_val & HPET_TIMER_TYPE_LEVEL) {
|
397 | 16b29ae1 | aliguori | printf("qemu: level-triggered hpet not supported\n");
|
398 | 16b29ae1 | aliguori | exit (-1);
|
399 | 16b29ae1 | aliguori | } |
400 | 16b29ae1 | aliguori | |
401 | 16b29ae1 | aliguori | break;
|
402 | 16b29ae1 | aliguori | case HPET_TN_CFG + 4: // Interrupt capabilities |
403 | 16b29ae1 | aliguori | dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
|
404 | 16b29ae1 | aliguori | break;
|
405 | 16b29ae1 | aliguori | case HPET_TN_CMP: // comparator register |
406 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
|
407 | 16b29ae1 | aliguori | if (timer->config & HPET_TN_32BIT)
|
408 | 16b29ae1 | aliguori | new_val = (uint32_t)new_val; |
409 | 16b29ae1 | aliguori | if (!timer_is_periodic(timer) ||
|
410 | 16b29ae1 | aliguori | (timer->config & HPET_TN_SETVAL)) |
411 | 16b29ae1 | aliguori | timer->cmp = (timer->cmp & 0xffffffff00000000ULL)
|
412 | 16b29ae1 | aliguori | | new_val; |
413 | 37873241 | aliguori | if (timer_is_periodic(timer)) {
|
414 | 16b29ae1 | aliguori | /*
|
415 | 16b29ae1 | aliguori | * FIXME: Clamp period to reasonable min value?
|
416 | 16b29ae1 | aliguori | * Clamp period to reasonable max value
|
417 | 16b29ae1 | aliguori | */
|
418 | 16b29ae1 | aliguori | new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
419 | 16b29ae1 | aliguori | timer->period = (timer->period & 0xffffffff00000000ULL)
|
420 | 16b29ae1 | aliguori | | new_val; |
421 | 16b29ae1 | aliguori | } |
422 | 16b29ae1 | aliguori | timer->config &= ~HPET_TN_SETVAL; |
423 | 16b29ae1 | aliguori | if (hpet_enabled())
|
424 | 16b29ae1 | aliguori | hpet_set_timer(timer); |
425 | 16b29ae1 | aliguori | break;
|
426 | 16b29ae1 | aliguori | case HPET_TN_CMP + 4: // comparator register high order |
427 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
|
428 | 16b29ae1 | aliguori | if (!timer_is_periodic(timer) ||
|
429 | 16b29ae1 | aliguori | (timer->config & HPET_TN_SETVAL)) |
430 | 16b29ae1 | aliguori | timer->cmp = (timer->cmp & 0xffffffffULL)
|
431 | 16b29ae1 | aliguori | | new_val << 32;
|
432 | 16b29ae1 | aliguori | else {
|
433 | 16b29ae1 | aliguori | /*
|
434 | 16b29ae1 | aliguori | * FIXME: Clamp period to reasonable min value?
|
435 | 16b29ae1 | aliguori | * Clamp period to reasonable max value
|
436 | 16b29ae1 | aliguori | */
|
437 | c50c2d68 | aurel32 | new_val &= (timer->config |
438 | 16b29ae1 | aliguori | & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
439 | 16b29ae1 | aliguori | timer->period = (timer->period & 0xffffffffULL)
|
440 | 16b29ae1 | aliguori | | new_val << 32;
|
441 | 16b29ae1 | aliguori | } |
442 | 16b29ae1 | aliguori | timer->config &= ~HPET_TN_SETVAL; |
443 | 16b29ae1 | aliguori | if (hpet_enabled())
|
444 | 16b29ae1 | aliguori | hpet_set_timer(timer); |
445 | 16b29ae1 | aliguori | break;
|
446 | 16b29ae1 | aliguori | case HPET_TN_ROUTE + 4: |
447 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
|
448 | 16b29ae1 | aliguori | break;
|
449 | 16b29ae1 | aliguori | default:
|
450 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_writel\n");
|
451 | 16b29ae1 | aliguori | break;
|
452 | 16b29ae1 | aliguori | } |
453 | 16b29ae1 | aliguori | return;
|
454 | 16b29ae1 | aliguori | } else {
|
455 | 16b29ae1 | aliguori | switch (index) {
|
456 | 16b29ae1 | aliguori | case HPET_ID:
|
457 | 16b29ae1 | aliguori | return;
|
458 | 16b29ae1 | aliguori | case HPET_CFG:
|
459 | ce536cfd | Beth Kon | val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); |
460 | ce536cfd | Beth Kon | s->config = (s->config & 0xffffffff00000000ULL) | val;
|
461 | 16b29ae1 | aliguori | if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
462 | 16b29ae1 | aliguori | /* Enable main counter and interrupt generation. */
|
463 | 16b29ae1 | aliguori | s->hpet_offset = ticks_to_ns(s->hpet_counter) |
464 | 16b29ae1 | aliguori | - qemu_get_clock(vm_clock); |
465 | 16b29ae1 | aliguori | for (i = 0; i < HPET_NUM_TIMERS; i++) |
466 | 16b29ae1 | aliguori | if ((&s->timer[i])->cmp != ~0ULL) |
467 | 16b29ae1 | aliguori | hpet_set_timer(&s->timer[i]); |
468 | 16b29ae1 | aliguori | } |
469 | 16b29ae1 | aliguori | else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { |
470 | 16b29ae1 | aliguori | /* Halt main counter and disable interrupt generation. */
|
471 | c50c2d68 | aurel32 | s->hpet_counter = hpet_get_ticks(); |
472 | 16b29ae1 | aliguori | for (i = 0; i < HPET_NUM_TIMERS; i++) |
473 | 16b29ae1 | aliguori | hpet_del_timer(&s->timer[i]); |
474 | 16b29ae1 | aliguori | } |
475 | 16b29ae1 | aliguori | /* i8254 and RTC are disabled when HPET is in legacy mode */
|
476 | 16b29ae1 | aliguori | if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
477 | 16b29ae1 | aliguori | hpet_pit_disable(); |
478 | 16b29ae1 | aliguori | } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { |
479 | 16b29ae1 | aliguori | hpet_pit_enable(); |
480 | 16b29ae1 | aliguori | } |
481 | 16b29ae1 | aliguori | break;
|
482 | c50c2d68 | aurel32 | case HPET_CFG + 4: |
483 | 16b29ae1 | aliguori | dprintf("qemu: invalid HPET_CFG+4 write \n");
|
484 | 16b29ae1 | aliguori | break;
|
485 | 16b29ae1 | aliguori | case HPET_STATUS:
|
486 | 16b29ae1 | aliguori | /* FIXME: need to handle level-triggered interrupts */
|
487 | 16b29ae1 | aliguori | break;
|
488 | 16b29ae1 | aliguori | case HPET_COUNTER:
|
489 | c50c2d68 | aurel32 | if (hpet_enabled())
|
490 | c50c2d68 | aurel32 | printf("qemu: Writing counter while HPET enabled!\n");
|
491 | c50c2d68 | aurel32 | s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
|
492 | 16b29ae1 | aliguori | | value; |
493 | 16b29ae1 | aliguori | dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", |
494 | 16b29ae1 | aliguori | value, s->hpet_counter); |
495 | 16b29ae1 | aliguori | break;
|
496 | 16b29ae1 | aliguori | case HPET_COUNTER + 4: |
497 | c50c2d68 | aurel32 | if (hpet_enabled())
|
498 | c50c2d68 | aurel32 | printf("qemu: Writing counter while HPET enabled!\n");
|
499 | c50c2d68 | aurel32 | s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
|
500 | 16b29ae1 | aliguori | | (((uint64_t)value) << 32);
|
501 | 16b29ae1 | aliguori | dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", |
502 | 16b29ae1 | aliguori | value, s->hpet_counter); |
503 | 16b29ae1 | aliguori | break;
|
504 | 16b29ae1 | aliguori | default:
|
505 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_writel\n");
|
506 | 16b29ae1 | aliguori | break;
|
507 | 16b29ae1 | aliguori | } |
508 | 16b29ae1 | aliguori | } |
509 | 16b29ae1 | aliguori | } |
510 | 16b29ae1 | aliguori | |
511 | 16b29ae1 | aliguori | static CPUReadMemoryFunc *hpet_ram_read[] = {
|
512 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
513 | 16b29ae1 | aliguori | hpet_ram_readb, |
514 | 16b29ae1 | aliguori | hpet_ram_readw, |
515 | 16b29ae1 | aliguori | #else
|
516 | 16b29ae1 | aliguori | NULL,
|
517 | 16b29ae1 | aliguori | NULL,
|
518 | 16b29ae1 | aliguori | #endif
|
519 | 16b29ae1 | aliguori | hpet_ram_readl, |
520 | 16b29ae1 | aliguori | }; |
521 | 16b29ae1 | aliguori | |
522 | 16b29ae1 | aliguori | static CPUWriteMemoryFunc *hpet_ram_write[] = {
|
523 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
524 | 16b29ae1 | aliguori | hpet_ram_writeb, |
525 | 16b29ae1 | aliguori | hpet_ram_writew, |
526 | 16b29ae1 | aliguori | #else
|
527 | 16b29ae1 | aliguori | NULL,
|
528 | 16b29ae1 | aliguori | NULL,
|
529 | 16b29ae1 | aliguori | #endif
|
530 | 16b29ae1 | aliguori | hpet_ram_writel, |
531 | 16b29ae1 | aliguori | }; |
532 | 16b29ae1 | aliguori | |
533 | 16b29ae1 | aliguori | static void hpet_reset(void *opaque) { |
534 | 16b29ae1 | aliguori | HPETState *s = opaque; |
535 | 16b29ae1 | aliguori | int i;
|
536 | 16b29ae1 | aliguori | static int count = 0; |
537 | 16b29ae1 | aliguori | |
538 | 16b29ae1 | aliguori | for (i=0; i<HPET_NUM_TIMERS; i++) { |
539 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[i]; |
540 | 16b29ae1 | aliguori | hpet_del_timer(timer); |
541 | 16b29ae1 | aliguori | timer->tn = i; |
542 | 16b29ae1 | aliguori | timer->cmp = ~0ULL;
|
543 | 16b29ae1 | aliguori | timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; |
544 | ce536cfd | Beth Kon | /* advertise availability of ioapic inti2 */
|
545 | ce536cfd | Beth Kon | timer->config |= 0x00000004ULL << 32; |
546 | 16b29ae1 | aliguori | timer->state = s; |
547 | 16b29ae1 | aliguori | timer->period = 0ULL;
|
548 | 16b29ae1 | aliguori | timer->wrap_flag = 0;
|
549 | 16b29ae1 | aliguori | } |
550 | 16b29ae1 | aliguori | |
551 | 16b29ae1 | aliguori | s->hpet_counter = 0ULL;
|
552 | 16b29ae1 | aliguori | s->hpet_offset = 0ULL;
|
553 | 16b29ae1 | aliguori | /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
|
554 | 16b29ae1 | aliguori | s->capability = 0x8086a201ULL;
|
555 | 16b29ae1 | aliguori | s->capability |= ((HPET_CLK_PERIOD) << 32);
|
556 | 7d93b1fa | Beth Kon | s->config = 0ULL;
|
557 | 16b29ae1 | aliguori | if (count > 0) |
558 | c50c2d68 | aurel32 | /* we don't enable pit when hpet_reset is first called (by hpet_init)
|
559 | 16b29ae1 | aliguori | * because hpet is taking over for pit here. On subsequent invocations,
|
560 | 16b29ae1 | aliguori | * hpet_reset is called due to system reset. At this point control must
|
561 | c50c2d68 | aurel32 | * be returned to pit until SW reenables hpet.
|
562 | 16b29ae1 | aliguori | */
|
563 | 16b29ae1 | aliguori | hpet_pit_enable(); |
564 | 16b29ae1 | aliguori | count = 1;
|
565 | 16b29ae1 | aliguori | } |
566 | 16b29ae1 | aliguori | |
567 | 16b29ae1 | aliguori | |
568 | 16b29ae1 | aliguori | void hpet_init(qemu_irq *irq) {
|
569 | 16b29ae1 | aliguori | int i, iomemtype;
|
570 | 16b29ae1 | aliguori | HPETState *s; |
571 | c50c2d68 | aurel32 | |
572 | 16b29ae1 | aliguori | dprintf ("hpet_init\n");
|
573 | 16b29ae1 | aliguori | |
574 | 16b29ae1 | aliguori | s = qemu_mallocz(sizeof(HPETState));
|
575 | 16b29ae1 | aliguori | hpet_statep = s; |
576 | 16b29ae1 | aliguori | s->irqs = irq; |
577 | 16b29ae1 | aliguori | for (i=0; i<HPET_NUM_TIMERS; i++) { |
578 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[i]; |
579 | 16b29ae1 | aliguori | timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer); |
580 | 16b29ae1 | aliguori | } |
581 | 16b29ae1 | aliguori | hpet_reset(s); |
582 | 16b29ae1 | aliguori | register_savevm("hpet", -1, 1, hpet_save, hpet_load, s); |
583 | a08d4367 | Jan Kiszka | qemu_register_reset(hpet_reset, s); |
584 | 16b29ae1 | aliguori | /* HPET Area */
|
585 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(hpet_ram_read, |
586 | 16b29ae1 | aliguori | hpet_ram_write, s); |
587 | 16b29ae1 | aliguori | cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
|
588 | 16b29ae1 | aliguori | } |