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/*
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 *  MIPS emulation micro-operations for qemu.
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 * 
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 *  Copyright (c) 2004-2005 Jocelyn Mayer
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 *  Copyright (c) 2006 Marius Groeger (FPU operations)
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "config.h"
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#include "exec.h"
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#ifndef CALL_FROM_TB0
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#define CALL_FROM_TB0(func) func();
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#endif
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#ifndef CALL_FROM_TB1
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#define CALL_FROM_TB1(func, arg0) func(arg0);
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#endif
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#ifndef CALL_FROM_TB1_CONST16
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#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0);
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#endif
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#ifndef CALL_FROM_TB2
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#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1);
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#endif
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#ifndef CALL_FROM_TB2_CONST16
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#define CALL_FROM_TB2_CONST16(func, arg0, arg1)     \
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CALL_FROM_TB2(func, arg0, arg1);
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#endif
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#ifndef CALL_FROM_TB3
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#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2);
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#endif
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#ifndef CALL_FROM_TB4
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#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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        func(arg0, arg1, arg2, arg3);
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#endif
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#define REG 1
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#include "op_template.c"
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#undef REG
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#define REG 2
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#include "op_template.c"
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#undef REG
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#define REG 3
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#include "op_template.c"
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#undef REG
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#define REG 4
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#include "op_template.c"
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#undef REG
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#define REG 5
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#include "op_template.c"
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#undef REG
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#define REG 6
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#include "op_template.c"
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#undef REG
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#define REG 7
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#include "op_template.c"
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#undef REG
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#define REG 8
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#include "op_template.c"
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#undef REG
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#define REG 9
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#include "op_template.c"
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#undef REG
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#define REG 10
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#include "op_template.c"
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#undef REG
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#define REG 11
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#include "op_template.c"
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#undef REG
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#define REG 12
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#include "op_template.c"
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#undef REG
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#define REG 13
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#include "op_template.c"
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#undef REG
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#define REG 14
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#include "op_template.c"
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#undef REG
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#define REG 15
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#include "op_template.c"
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#undef REG
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#define REG 16
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#include "op_template.c"
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#undef REG
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#define REG 17
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#include "op_template.c"
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#undef REG
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#define REG 18
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#include "op_template.c"
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#undef REG
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#define REG 19
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#include "op_template.c"
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#undef REG
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#define REG 20
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#include "op_template.c"
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#undef REG
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#define REG 21
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#include "op_template.c"
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#undef REG
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#define REG 22
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#include "op_template.c"
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#undef REG
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#define REG 23
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#include "op_template.c"
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#undef REG
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#define REG 24
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#include "op_template.c"
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#undef REG
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#define REG 25
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#include "op_template.c"
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#undef REG
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#define REG 26
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#include "op_template.c"
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#undef REG
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#define REG 27
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#include "op_template.c"
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#undef REG
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#define REG 28
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#include "op_template.c"
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#undef REG
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#define REG 29
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#include "op_template.c"
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#undef REG
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#define REG 30
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#include "op_template.c"
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#undef REG
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#define REG 31
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#include "op_template.c"
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#undef REG
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#define TN T0
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#include "op_template.c"
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#undef TN
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#define TN T1
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#include "op_template.c"
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#undef TN
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#define TN T2
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#include "op_template.c"
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#undef TN
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#ifdef MIPS_USES_FPU
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#define SFREG 0
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#define DFREG 0
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 1
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 2
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#define DFREG 2
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 3
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 4
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#define DFREG 4
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 5
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 6
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#define DFREG 6
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 7
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 8
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#define DFREG 8
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 9
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 10
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#define DFREG 10
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 11
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 12
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#define DFREG 12
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 13
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 14
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#define DFREG 14
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 15
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 16
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#define DFREG 16
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 17
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 18
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#define DFREG 18
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 19
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 20
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#define DFREG 20
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 21
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 22
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#define DFREG 22
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 23
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 24
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#define DFREG 24
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 25
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 26
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#define DFREG 26
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 27
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 28
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#define DFREG 28
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 29
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 30
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#define DFREG 30
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 31
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#include "fop_template.c"
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#undef SFREG
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#define FTN
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#include "fop_template.c"
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#undef FTN
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#endif
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void op_dup_T0 (void)
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{
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    T2 = T0;
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    RETURN();
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}
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void op_load_HI (void)
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{
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    T0 = env->HI;
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    RETURN();
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}
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void op_store_HI (void)
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{
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    env->HI = T0;
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    RETURN();
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}
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void op_load_LO (void)
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{
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    T0 = env->LO;
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    RETURN();
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}
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void op_store_LO (void)
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{
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    env->LO = T0;
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    RETURN();
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}
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/* Load and store */
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#define MEMSUFFIX _raw
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#include "op_mem.c"
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_mem.c"
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_mem.c"
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#undef MEMSUFFIX
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#endif
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/* Arithmetic */
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void op_add (void)
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{
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    T0 += T1;
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    RETURN();
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}
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void op_addo (void)
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{
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    target_ulong tmp;
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    tmp = T0;
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    T0 += T1;
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    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
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       /* operands of same sign, result different sign */
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        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
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    }
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    RETURN();
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}
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void op_sub (void)
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{
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    T0 -= T1;
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    RETURN();
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}
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void op_subo (void)
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{
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    target_ulong tmp;
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    tmp = T0;
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    T0 = (int32_t)T0 - (int32_t)T1;
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    if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
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       /* operands of different sign, first operand and result different sign */
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        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
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    }
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    RETURN();
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}
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void op_mul (void)
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{
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    T0 = (int32_t)T0 * (int32_t)T1;
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    RETURN();
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}
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void op_div (void)
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{
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    if (T1 != 0) {
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        env->LO = (int32_t)T0 / (int32_t)T1;
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        env->HI = (int32_t)T0 % (int32_t)T1;
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    }
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    RETURN();
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}
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void op_divu (void)
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{
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    if (T1 != 0) {
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        env->LO = T0 / T1;
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        env->HI = T0 % T1;
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    }
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    RETURN();
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}
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/* Logical */
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void op_and (void)
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{
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    T0 &= T1;
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    RETURN();
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}
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void op_nor (void)
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{
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    T0 = ~(T0 | T1);
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    RETURN();
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}
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void op_or (void)
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{
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    T0 |= T1;
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    RETURN();
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}
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void op_xor (void)
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{
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    T0 ^= T1;
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    RETURN();
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}
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void op_sll (void)
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{
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    T0 = T0 << T1;
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    RETURN();
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}
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void op_sra (void)
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{
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    T0 = (int32_t)T0 >> T1;
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    RETURN();
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}
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void op_srl (void)
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{
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    T0 = T0 >> T1;
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    RETURN();
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}
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void op_rotr (void)
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{
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    target_ulong tmp;
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    if (T1) {
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       tmp = T0 << (0x20 - T1);
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       T0 = (T0 >> T1) | tmp;
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    } else
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       T0 = T1;
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    RETURN();
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}
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void op_sllv (void)
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{
454 6af0bf9c bellard
    T0 = T1 << (T0 & 0x1F);
455 6af0bf9c bellard
    RETURN();
456 6af0bf9c bellard
}
457 6af0bf9c bellard
458 6af0bf9c bellard
void op_srav (void)
459 6af0bf9c bellard
{
460 6af0bf9c bellard
    T0 = (int32_t)T1 >> (T0 & 0x1F);
461 6af0bf9c bellard
    RETURN();
462 6af0bf9c bellard
}
463 6af0bf9c bellard
464 6af0bf9c bellard
void op_srlv (void)
465 6af0bf9c bellard
{
466 6af0bf9c bellard
    T0 = T1 >> (T0 & 0x1F);
467 6af0bf9c bellard
    RETURN();
468 6af0bf9c bellard
}
469 6af0bf9c bellard
470 7a387fff ths
void op_rotrv (void)
471 7a387fff ths
{
472 7a387fff ths
    target_ulong tmp;
473 7a387fff ths
474 7a387fff ths
    T0 &= 0x1F;
475 7a387fff ths
    if (T0) {
476 7a387fff ths
       tmp = T1 << (0x20 - T0);
477 7a387fff ths
       T0 = (T1 >> T0) | tmp;
478 7a387fff ths
    } else
479 7a387fff ths
       T0 = T1;
480 7a387fff ths
    RETURN();
481 7a387fff ths
}
482 7a387fff ths
483 6af0bf9c bellard
void op_clo (void)
484 6af0bf9c bellard
{
485 6af0bf9c bellard
    int n;
486 6af0bf9c bellard
487 6af0bf9c bellard
    if (T0 == (target_ulong)-1) {
488 6af0bf9c bellard
        T0 = 32;
489 6af0bf9c bellard
    } else {
490 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
491 6af0bf9c bellard
            if (!(T0 & (1 << 31)))
492 6af0bf9c bellard
                break;
493 6af0bf9c bellard
            T0 = T0 << 1;
494 6af0bf9c bellard
        }
495 6af0bf9c bellard
        T0 = n;
496 6af0bf9c bellard
    }
497 6af0bf9c bellard
    RETURN();
498 6af0bf9c bellard
}
499 6af0bf9c bellard
500 6af0bf9c bellard
void op_clz (void)
501 6af0bf9c bellard
{
502 6af0bf9c bellard
    int n;
503 6af0bf9c bellard
504 6af0bf9c bellard
    if (T0 == 0) {
505 6af0bf9c bellard
        T0 = 32;
506 6af0bf9c bellard
    } else {
507 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
508 6af0bf9c bellard
            if (T0 & (1 << 31))
509 6af0bf9c bellard
                break;
510 6af0bf9c bellard
            T0 = T0 << 1;
511 6af0bf9c bellard
        }
512 6af0bf9c bellard
        T0 = n;
513 6af0bf9c bellard
    }
514 6af0bf9c bellard
    RETURN();
515 6af0bf9c bellard
}
516 6af0bf9c bellard
517 6af0bf9c bellard
/* 64 bits arithmetic */
518 6af0bf9c bellard
#if (HOST_LONG_BITS == 64)
519 6af0bf9c bellard
static inline uint64_t get_HILO (void)
520 6af0bf9c bellard
{
521 6af0bf9c bellard
    return ((uint64_t)env->HI << 32) | (uint64_t)env->LO;
522 6af0bf9c bellard
}
523 6af0bf9c bellard
524 6af0bf9c bellard
static inline void set_HILO (uint64_t HILO)
525 6af0bf9c bellard
{
526 6af0bf9c bellard
    env->LO = HILO & 0xFFFFFFFF;
527 6af0bf9c bellard
    env->HI = HILO >> 32;
528 6af0bf9c bellard
}
529 6af0bf9c bellard
530 6af0bf9c bellard
void op_mult (void)
531 6af0bf9c bellard
{
532 4ad40f36 bellard
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
533 6af0bf9c bellard
    RETURN();
534 6af0bf9c bellard
}
535 6af0bf9c bellard
536 6af0bf9c bellard
void op_multu (void)
537 6af0bf9c bellard
{
538 6af0bf9c bellard
    set_HILO((uint64_t)T0 * (uint64_t)T1);
539 6af0bf9c bellard
    RETURN();
540 6af0bf9c bellard
}
541 6af0bf9c bellard
542 6af0bf9c bellard
void op_madd (void)
543 6af0bf9c bellard
{
544 6af0bf9c bellard
    int64_t tmp;
545 6af0bf9c bellard
546 4ad40f36 bellard
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
547 6af0bf9c bellard
    set_HILO((int64_t)get_HILO() + tmp);
548 6af0bf9c bellard
    RETURN();
549 6af0bf9c bellard
}
550 6af0bf9c bellard
551 6af0bf9c bellard
void op_maddu (void)
552 6af0bf9c bellard
{
553 6af0bf9c bellard
    uint64_t tmp;
554 6af0bf9c bellard
555 6af0bf9c bellard
    tmp = ((uint64_t)T0 * (uint64_t)T1);
556 6af0bf9c bellard
    set_HILO(get_HILO() + tmp);
557 6af0bf9c bellard
    RETURN();
558 6af0bf9c bellard
}
559 6af0bf9c bellard
560 6af0bf9c bellard
void op_msub (void)
561 6af0bf9c bellard
{
562 6af0bf9c bellard
    int64_t tmp;
563 6af0bf9c bellard
564 4ad40f36 bellard
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
565 6af0bf9c bellard
    set_HILO((int64_t)get_HILO() - tmp);
566 6af0bf9c bellard
    RETURN();
567 6af0bf9c bellard
}
568 6af0bf9c bellard
569 6af0bf9c bellard
void op_msubu (void)
570 6af0bf9c bellard
{
571 6af0bf9c bellard
    uint64_t tmp;
572 6af0bf9c bellard
573 6af0bf9c bellard
    tmp = ((uint64_t)T0 * (uint64_t)T1);
574 6af0bf9c bellard
    set_HILO(get_HILO() - tmp);
575 6af0bf9c bellard
    RETURN();
576 6af0bf9c bellard
}
577 6af0bf9c bellard
#else
578 6af0bf9c bellard
void op_mult (void)
579 6af0bf9c bellard
{
580 6af0bf9c bellard
    CALL_FROM_TB0(do_mult);
581 6af0bf9c bellard
    RETURN();
582 6af0bf9c bellard
}
583 6af0bf9c bellard
584 6af0bf9c bellard
void op_multu (void)
585 6af0bf9c bellard
{
586 6af0bf9c bellard
    CALL_FROM_TB0(do_multu);
587 6af0bf9c bellard
    RETURN();
588 6af0bf9c bellard
}
589 6af0bf9c bellard
590 6af0bf9c bellard
void op_madd (void)
591 6af0bf9c bellard
{
592 6af0bf9c bellard
    CALL_FROM_TB0(do_madd);
593 6af0bf9c bellard
    RETURN();
594 6af0bf9c bellard
}
595 6af0bf9c bellard
596 6af0bf9c bellard
void op_maddu (void)
597 6af0bf9c bellard
{
598 6af0bf9c bellard
    CALL_FROM_TB0(do_maddu);
599 6af0bf9c bellard
    RETURN();
600 6af0bf9c bellard
}
601 6af0bf9c bellard
602 6af0bf9c bellard
void op_msub (void)
603 6af0bf9c bellard
{
604 6af0bf9c bellard
    CALL_FROM_TB0(do_msub);
605 6af0bf9c bellard
    RETURN();
606 6af0bf9c bellard
}
607 6af0bf9c bellard
608 6af0bf9c bellard
void op_msubu (void)
609 6af0bf9c bellard
{
610 6af0bf9c bellard
    CALL_FROM_TB0(do_msubu);
611 6af0bf9c bellard
    RETURN();
612 6af0bf9c bellard
}
613 6af0bf9c bellard
#endif
614 6af0bf9c bellard
615 6af0bf9c bellard
/* Conditional moves */
616 6af0bf9c bellard
void op_movn (void)
617 6af0bf9c bellard
{
618 6af0bf9c bellard
    if (T1 != 0)
619 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
620 6af0bf9c bellard
    RETURN();
621 6af0bf9c bellard
}
622 6af0bf9c bellard
623 6af0bf9c bellard
void op_movz (void)
624 6af0bf9c bellard
{
625 6af0bf9c bellard
    if (T1 == 0)
626 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
627 6af0bf9c bellard
    RETURN();
628 6af0bf9c bellard
}
629 6af0bf9c bellard
630 71fb7241 ths
#ifdef MIPS_USES_FPU
631 7a387fff ths
void op_movf (void)
632 7a387fff ths
{
633 7a387fff ths
    if (!(env->fcr31 & PARAM1))
634 7a387fff ths
        env->gpr[PARAM2] = env->gpr[PARAM3];
635 7a387fff ths
    RETURN();
636 7a387fff ths
}
637 7a387fff ths
638 7a387fff ths
void op_movt (void)
639 7a387fff ths
{
640 7a387fff ths
    if (env->fcr31 & PARAM1)
641 7a387fff ths
        env->gpr[PARAM2] = env->gpr[PARAM3];
642 7a387fff ths
    RETURN();
643 7a387fff ths
}
644 71fb7241 ths
#endif
645 7a387fff ths
646 6af0bf9c bellard
/* Tests */
647 6af0bf9c bellard
#define OP_COND(name, cond) \
648 6af0bf9c bellard
void glue(op_, name) (void) \
649 6af0bf9c bellard
{                           \
650 6af0bf9c bellard
    if (cond) {             \
651 6af0bf9c bellard
        T0 = 1;             \
652 6af0bf9c bellard
    } else {                \
653 6af0bf9c bellard
        T0 = 0;             \
654 6af0bf9c bellard
    }                       \
655 6af0bf9c bellard
    RETURN();               \
656 6af0bf9c bellard
}
657 6af0bf9c bellard
658 6af0bf9c bellard
OP_COND(eq, T0 == T1);
659 6af0bf9c bellard
OP_COND(ne, T0 != T1);
660 6af0bf9c bellard
OP_COND(ge, (int32_t)T0 >= (int32_t)T1);
661 6af0bf9c bellard
OP_COND(geu, T0 >= T1);
662 6af0bf9c bellard
OP_COND(lt, (int32_t)T0 < (int32_t)T1);
663 6af0bf9c bellard
OP_COND(ltu, T0 < T1);
664 6af0bf9c bellard
OP_COND(gez, (int32_t)T0 >= 0);
665 6af0bf9c bellard
OP_COND(gtz, (int32_t)T0 > 0);
666 6af0bf9c bellard
OP_COND(lez, (int32_t)T0 <= 0);
667 6af0bf9c bellard
OP_COND(ltz, (int32_t)T0 < 0);
668 6af0bf9c bellard
669 7a387fff ths
/* Branches */
670 6af0bf9c bellard
//#undef USE_DIRECT_JUMP
671 c53be334 bellard
672 c53be334 bellard
void OPPROTO op_goto_tb0(void)
673 c53be334 bellard
{
674 c53be334 bellard
    GOTO_TB(op_goto_tb0, PARAM1, 0);
675 7a387fff ths
    RETURN();
676 c53be334 bellard
}
677 c53be334 bellard
678 c53be334 bellard
void OPPROTO op_goto_tb1(void)
679 c53be334 bellard
{
680 c53be334 bellard
    GOTO_TB(op_goto_tb1, PARAM1, 1);
681 7a387fff ths
    RETURN();
682 c53be334 bellard
}
683 6af0bf9c bellard
684 6af0bf9c bellard
/* Branch to register */
685 6af0bf9c bellard
void op_save_breg_target (void)
686 6af0bf9c bellard
{
687 6af0bf9c bellard
    env->btarget = T2;
688 7a387fff ths
    RETURN();
689 6af0bf9c bellard
}
690 6af0bf9c bellard
691 6af0bf9c bellard
void op_restore_breg_target (void)
692 6af0bf9c bellard
{
693 6af0bf9c bellard
    T2 = env->btarget;
694 7a387fff ths
    RETURN();
695 6af0bf9c bellard
}
696 6af0bf9c bellard
697 6af0bf9c bellard
void op_breg (void)
698 6af0bf9c bellard
{
699 6af0bf9c bellard
    env->PC = T2;
700 6af0bf9c bellard
    RETURN();
701 6af0bf9c bellard
}
702 6af0bf9c bellard
703 6af0bf9c bellard
void op_save_btarget (void)
704 6af0bf9c bellard
{
705 6af0bf9c bellard
    env->btarget = PARAM1;
706 6af0bf9c bellard
    RETURN();
707 6af0bf9c bellard
}
708 6af0bf9c bellard
709 6af0bf9c bellard
/* Conditional branch */
710 6af0bf9c bellard
void op_set_bcond (void)
711 6af0bf9c bellard
{
712 6af0bf9c bellard
    T2 = T0;
713 6af0bf9c bellard
    RETURN();
714 6af0bf9c bellard
}
715 6af0bf9c bellard
716 6af0bf9c bellard
void op_save_bcond (void)
717 6af0bf9c bellard
{
718 6af0bf9c bellard
    env->bcond = T2;
719 6af0bf9c bellard
    RETURN();
720 6af0bf9c bellard
}
721 6af0bf9c bellard
722 6af0bf9c bellard
void op_restore_bcond (void)
723 6af0bf9c bellard
{
724 6af0bf9c bellard
    T2 = env->bcond;
725 6af0bf9c bellard
    RETURN();
726 6af0bf9c bellard
}
727 6af0bf9c bellard
728 c53be334 bellard
void op_jnz_T2 (void)
729 6af0bf9c bellard
{
730 c53be334 bellard
    if (T2)
731 c53be334 bellard
        GOTO_LABEL_PARAM(1);
732 6af0bf9c bellard
    RETURN();
733 6af0bf9c bellard
}
734 6af0bf9c bellard
735 6af0bf9c bellard
/* CP0 functions */
736 873eb012 ths
void op_mfc0_index (void)
737 6af0bf9c bellard
{
738 873eb012 ths
    T0 = env->CP0_index;
739 873eb012 ths
    RETURN();
740 873eb012 ths
}
741 873eb012 ths
742 873eb012 ths
void op_mfc0_random (void)
743 873eb012 ths
{
744 873eb012 ths
    CALL_FROM_TB0(do_mfc0_random);
745 873eb012 ths
    RETURN();
746 873eb012 ths
}
747 873eb012 ths
748 873eb012 ths
void op_mfc0_entrylo0 (void)
749 873eb012 ths
{
750 873eb012 ths
    T0 = env->CP0_EntryLo0;
751 873eb012 ths
    RETURN();
752 873eb012 ths
}
753 873eb012 ths
754 873eb012 ths
void op_mfc0_entrylo1 (void)
755 873eb012 ths
{
756 873eb012 ths
    T0 = env->CP0_EntryLo1;
757 873eb012 ths
    RETURN();
758 873eb012 ths
}
759 873eb012 ths
760 873eb012 ths
void op_mfc0_context (void)
761 873eb012 ths
{
762 873eb012 ths
    T0 = env->CP0_Context;
763 873eb012 ths
    RETURN();
764 873eb012 ths
}
765 873eb012 ths
766 873eb012 ths
void op_mfc0_pagemask (void)
767 873eb012 ths
{
768 873eb012 ths
    T0 = env->CP0_PageMask;
769 873eb012 ths
    RETURN();
770 873eb012 ths
}
771 873eb012 ths
772 7a387fff ths
void op_mfc0_pagegrain (void)
773 7a387fff ths
{
774 7a387fff ths
    T0 = env->CP0_PageGrain;
775 7a387fff ths
    RETURN();
776 7a387fff ths
}
777 7a387fff ths
778 873eb012 ths
void op_mfc0_wired (void)
779 873eb012 ths
{
780 873eb012 ths
    T0 = env->CP0_Wired;
781 873eb012 ths
    RETURN();
782 873eb012 ths
}
783 873eb012 ths
784 7a387fff ths
void op_mfc0_hwrena (void)
785 7a387fff ths
{
786 7a387fff ths
    T0 = env->CP0_HWREna;
787 7a387fff ths
    RETURN();
788 7a387fff ths
}
789 7a387fff ths
790 873eb012 ths
void op_mfc0_badvaddr (void)
791 873eb012 ths
{
792 873eb012 ths
    T0 = env->CP0_BadVAddr;
793 873eb012 ths
    RETURN();
794 873eb012 ths
}
795 873eb012 ths
796 873eb012 ths
void op_mfc0_count (void)
797 873eb012 ths
{
798 873eb012 ths
    CALL_FROM_TB0(do_mfc0_count);
799 873eb012 ths
    RETURN();
800 873eb012 ths
}
801 873eb012 ths
802 873eb012 ths
void op_mfc0_entryhi (void)
803 873eb012 ths
{
804 873eb012 ths
    T0 = env->CP0_EntryHi;
805 873eb012 ths
    RETURN();
806 873eb012 ths
}
807 873eb012 ths
808 873eb012 ths
void op_mfc0_compare (void)
809 873eb012 ths
{
810 873eb012 ths
    T0 = env->CP0_Compare;
811 873eb012 ths
    RETURN();
812 873eb012 ths
}
813 873eb012 ths
814 873eb012 ths
void op_mfc0_status (void)
815 873eb012 ths
{
816 873eb012 ths
    T0 = env->CP0_Status;
817 873eb012 ths
    if (env->hflags & MIPS_HFLAG_UM)
818 873eb012 ths
        T0 |= (1 << CP0St_UM);
819 873eb012 ths
    if (env->hflags & MIPS_HFLAG_ERL)
820 873eb012 ths
        T0 |= (1 << CP0St_ERL);
821 873eb012 ths
    if (env->hflags & MIPS_HFLAG_EXL)
822 873eb012 ths
        T0 |= (1 << CP0St_EXL);
823 873eb012 ths
    RETURN();
824 873eb012 ths
}
825 873eb012 ths
826 7a387fff ths
void op_mfc0_intctl (void)
827 7a387fff ths
{
828 7a387fff ths
    T0 = env->CP0_IntCtl;
829 7a387fff ths
    RETURN();
830 7a387fff ths
}
831 7a387fff ths
832 7a387fff ths
void op_mfc0_srsctl (void)
833 7a387fff ths
{
834 7a387fff ths
    T0 = env->CP0_SRSCtl;
835 7a387fff ths
    RETURN();
836 7a387fff ths
}
837 7a387fff ths
838 873eb012 ths
void op_mfc0_cause (void)
839 873eb012 ths
{
840 873eb012 ths
    T0 = env->CP0_Cause;
841 873eb012 ths
    RETURN();
842 873eb012 ths
}
843 873eb012 ths
844 873eb012 ths
void op_mfc0_epc (void)
845 873eb012 ths
{
846 873eb012 ths
    T0 = env->CP0_EPC;
847 873eb012 ths
    RETURN();
848 873eb012 ths
}
849 873eb012 ths
850 873eb012 ths
void op_mfc0_prid (void)
851 873eb012 ths
{
852 873eb012 ths
    T0 = env->CP0_PRid;
853 873eb012 ths
    RETURN();
854 873eb012 ths
}
855 873eb012 ths
856 7a387fff ths
void op_mfc0_ebase (void)
857 7a387fff ths
{
858 7a387fff ths
    T0 = env->CP0_EBase;
859 7a387fff ths
    RETURN();
860 7a387fff ths
}
861 7a387fff ths
862 873eb012 ths
void op_mfc0_config0 (void)
863 873eb012 ths
{
864 873eb012 ths
    T0 = env->CP0_Config0;
865 873eb012 ths
    RETURN();
866 873eb012 ths
}
867 873eb012 ths
868 873eb012 ths
void op_mfc0_config1 (void)
869 873eb012 ths
{
870 873eb012 ths
    T0 = env->CP0_Config1;
871 873eb012 ths
    RETURN();
872 873eb012 ths
}
873 873eb012 ths
874 7a387fff ths
void op_mfc0_config2 (void)
875 7a387fff ths
{
876 7a387fff ths
    T0 = env->CP0_Config2;
877 7a387fff ths
    RETURN();
878 7a387fff ths
}
879 7a387fff ths
880 7a387fff ths
void op_mfc0_config3 (void)
881 7a387fff ths
{
882 7a387fff ths
    T0 = env->CP0_Config3;
883 7a387fff ths
    RETURN();
884 7a387fff ths
}
885 7a387fff ths
886 873eb012 ths
void op_mfc0_lladdr (void)
887 873eb012 ths
{
888 873eb012 ths
    T0 = env->CP0_LLAddr >> 4;
889 873eb012 ths
    RETURN();
890 873eb012 ths
}
891 873eb012 ths
892 7a387fff ths
void op_mfc0_watchlo0 (void)
893 873eb012 ths
{
894 873eb012 ths
    T0 = env->CP0_WatchLo;
895 873eb012 ths
    RETURN();
896 873eb012 ths
}
897 873eb012 ths
898 7a387fff ths
void op_mfc0_watchhi0 (void)
899 873eb012 ths
{
900 873eb012 ths
    T0 = env->CP0_WatchHi;
901 873eb012 ths
    RETURN();
902 873eb012 ths
}
903 873eb012 ths
904 7a387fff ths
void op_mfc0_xcontext (void)
905 7a387fff ths
{
906 7a387fff ths
    T0 = env->CP0_XContext;
907 7a387fff ths
    RETURN();
908 7a387fff ths
}
909 7a387fff ths
910 7a387fff ths
void op_mfc0_framemask (void)
911 7a387fff ths
{
912 7a387fff ths
    T0 = env->CP0_Framemask;
913 7a387fff ths
    RETURN();
914 7a387fff ths
}
915 7a387fff ths
916 873eb012 ths
void op_mfc0_debug (void)
917 873eb012 ths
{
918 873eb012 ths
    T0 = env->CP0_Debug;
919 873eb012 ths
    if (env->hflags & MIPS_HFLAG_DM)
920 873eb012 ths
        T0 |= 1 << CP0DB_DM;
921 873eb012 ths
    RETURN();
922 873eb012 ths
}
923 873eb012 ths
924 873eb012 ths
void op_mfc0_depc (void)
925 873eb012 ths
{
926 873eb012 ths
    T0 = env->CP0_DEPC;
927 873eb012 ths
    RETURN();
928 873eb012 ths
}
929 873eb012 ths
930 7a387fff ths
void op_mfc0_performance0 (void)
931 7a387fff ths
{
932 7a387fff ths
    T0 = env->CP0_Performance0;
933 7a387fff ths
    RETURN();
934 7a387fff ths
}
935 7a387fff ths
936 873eb012 ths
void op_mfc0_taglo (void)
937 873eb012 ths
{
938 873eb012 ths
    T0 = env->CP0_TagLo;
939 873eb012 ths
    RETURN();
940 873eb012 ths
}
941 873eb012 ths
942 873eb012 ths
void op_mfc0_datalo (void)
943 873eb012 ths
{
944 873eb012 ths
    T0 = env->CP0_DataLo;
945 873eb012 ths
    RETURN();
946 873eb012 ths
}
947 873eb012 ths
948 7a387fff ths
void op_mfc0_taghi (void)
949 7a387fff ths
{
950 7a387fff ths
    T0 = env->CP0_TagHi;
951 7a387fff ths
    RETURN();
952 7a387fff ths
}
953 7a387fff ths
954 7a387fff ths
void op_mfc0_datahi (void)
955 7a387fff ths
{
956 7a387fff ths
    T0 = env->CP0_DataHi;
957 7a387fff ths
    RETURN();
958 7a387fff ths
}
959 7a387fff ths
960 873eb012 ths
void op_mfc0_errorepc (void)
961 873eb012 ths
{
962 873eb012 ths
    T0 = env->CP0_ErrorEPC;
963 873eb012 ths
    RETURN();
964 873eb012 ths
}
965 873eb012 ths
966 873eb012 ths
void op_mfc0_desave (void)
967 873eb012 ths
{
968 873eb012 ths
    T0 = env->CP0_DESAVE;
969 6af0bf9c bellard
    RETURN();
970 6af0bf9c bellard
}
971 6af0bf9c bellard
972 8c0fdd85 ths
void op_mtc0_index (void)
973 6af0bf9c bellard
{
974 7a387fff ths
    env->CP0_index = (env->CP0_index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
975 8c0fdd85 ths
    RETURN();
976 8c0fdd85 ths
}
977 8c0fdd85 ths
978 8c0fdd85 ths
void op_mtc0_entrylo0 (void)
979 8c0fdd85 ths
{
980 7a387fff ths
    /* Large physaddr not implemented */
981 7a387fff ths
    /* 1k pages not implemented */
982 7a387fff ths
    env->CP0_EntryLo0 = T0 & 0x3FFFFFFFUL;
983 8c0fdd85 ths
    RETURN();
984 8c0fdd85 ths
}
985 8c0fdd85 ths
986 8c0fdd85 ths
void op_mtc0_entrylo1 (void)
987 8c0fdd85 ths
{
988 7a387fff ths
    /* Large physaddr not implemented */
989 7a387fff ths
    /* 1k pages not implemented */
990 7a387fff ths
    env->CP0_EntryLo1 = T0 & 0x3FFFFFFFUL;
991 8c0fdd85 ths
    RETURN();
992 8c0fdd85 ths
}
993 8c0fdd85 ths
994 8c0fdd85 ths
void op_mtc0_context (void)
995 8c0fdd85 ths
{
996 7a387fff ths
    env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
997 8c0fdd85 ths
    RETURN();
998 8c0fdd85 ths
}
999 8c0fdd85 ths
1000 8c0fdd85 ths
void op_mtc0_pagemask (void)
1001 8c0fdd85 ths
{
1002 7a387fff ths
    /* 1k pages not implemented */
1003 7a387fff ths
    env->CP0_PageMask = T0 & 0x1FFFE000;
1004 7a387fff ths
    RETURN();
1005 7a387fff ths
}
1006 7a387fff ths
1007 7a387fff ths
void op_mtc0_pagegrain (void)
1008 7a387fff ths
{
1009 7a387fff ths
    /* SmartMIPS not implemented */
1010 7a387fff ths
    /* Large physaddr not implemented */
1011 7a387fff ths
    /* 1k pages not implemented */
1012 7a387fff ths
    env->CP0_PageGrain = 0;
1013 8c0fdd85 ths
    RETURN();
1014 8c0fdd85 ths
}
1015 8c0fdd85 ths
1016 8c0fdd85 ths
void op_mtc0_wired (void)
1017 8c0fdd85 ths
{
1018 7a387fff ths
    env->CP0_Wired = T0 & (MIPS_TLB_NB - 1);
1019 7a387fff ths
    RETURN();
1020 7a387fff ths
}
1021 7a387fff ths
1022 7a387fff ths
void op_mtc0_hwrena (void)
1023 7a387fff ths
{
1024 7a387fff ths
    env->CP0_HWREna = T0 & 0x0000000F;
1025 8c0fdd85 ths
    RETURN();
1026 8c0fdd85 ths
}
1027 8c0fdd85 ths
1028 8c0fdd85 ths
void op_mtc0_count (void)
1029 8c0fdd85 ths
{
1030 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1031 8c0fdd85 ths
    RETURN();
1032 8c0fdd85 ths
}
1033 8c0fdd85 ths
1034 8c0fdd85 ths
void op_mtc0_entryhi (void)
1035 8c0fdd85 ths
{
1036 8c0fdd85 ths
    uint32_t old, val;
1037 8c0fdd85 ths
1038 7a387fff ths
    /* 1k pages not implemented */
1039 7a387fff ths
    /* Ignore MIPS64 TLB for now */
1040 8c0fdd85 ths
    val = T0 & 0xFFFFE0FF;
1041 8c0fdd85 ths
    old = env->CP0_EntryHi;
1042 8c0fdd85 ths
    env->CP0_EntryHi = val;
1043 8c0fdd85 ths
    /* If the ASID changes, flush qemu's TLB.  */
1044 8c0fdd85 ths
    if ((old & 0xFF) != (val & 0xFF))
1045 8c0fdd85 ths
        CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1046 8c0fdd85 ths
    RETURN();
1047 8c0fdd85 ths
}
1048 8c0fdd85 ths
1049 8c0fdd85 ths
void op_mtc0_compare (void)
1050 8c0fdd85 ths
{
1051 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1052 8c0fdd85 ths
    RETURN();
1053 8c0fdd85 ths
}
1054 8c0fdd85 ths
1055 8c0fdd85 ths
void op_mtc0_status (void)
1056 8c0fdd85 ths
{
1057 8c0fdd85 ths
    uint32_t val, old, mask;
1058 8c0fdd85 ths
1059 8c0fdd85 ths
    val = T0 & 0xFA78FF01;
1060 8c0fdd85 ths
    old = env->CP0_Status;
1061 8c0fdd85 ths
    if (T0 & (1 << CP0St_UM))
1062 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_UM;
1063 8c0fdd85 ths
    else
1064 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_UM;
1065 8c0fdd85 ths
    if (T0 & (1 << CP0St_ERL))
1066 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_ERL;
1067 8c0fdd85 ths
    else
1068 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_ERL;
1069 8c0fdd85 ths
    if (T0 & (1 << CP0St_EXL))
1070 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_EXL;
1071 8c0fdd85 ths
    else
1072 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_EXL;
1073 8c0fdd85 ths
    env->CP0_Status = val;
1074 8c0fdd85 ths
    /* If we unmasked an asserted IRQ, raise it */
1075 8c0fdd85 ths
    mask = 0x0000FF00;
1076 8c0fdd85 ths
    if (loglevel & CPU_LOG_TB_IN_ASM)
1077 8c0fdd85 ths
       CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1078 8c0fdd85 ths
    if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) &&
1079 8c0fdd85 ths
        !(env->hflags & MIPS_HFLAG_EXL) &&
1080 8c0fdd85 ths
        !(env->hflags & MIPS_HFLAG_ERL) &&
1081 8c0fdd85 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
1082 8c0fdd85 ths
        (env->CP0_Status & env->CP0_Cause & mask)) {
1083 8c0fdd85 ths
        env->interrupt_request |= CPU_INTERRUPT_HARD;
1084 8c0fdd85 ths
       if (logfile)
1085 8c0fdd85 ths
           CALL_FROM_TB0(do_mtc0_status_irqraise_debug);
1086 8c0fdd85 ths
    } else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) {
1087 8c0fdd85 ths
        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1088 8c0fdd85 ths
    }
1089 8c0fdd85 ths
    RETURN();
1090 8c0fdd85 ths
}
1091 8c0fdd85 ths
1092 7a387fff ths
void op_mtc0_intctl (void)
1093 7a387fff ths
{
1094 7a387fff ths
    /* vectored interrupts not implemented */
1095 7a387fff ths
    env->CP0_IntCtl = 0;
1096 7a387fff ths
    RETURN();
1097 7a387fff ths
}
1098 7a387fff ths
1099 7a387fff ths
void op_mtc0_srsctl (void)
1100 7a387fff ths
{
1101 7a387fff ths
    /* shadow registers not implemented */
1102 7a387fff ths
    env->CP0_SRSCtl = 0;
1103 7a387fff ths
    RETURN();
1104 7a387fff ths
}
1105 7a387fff ths
1106 8c0fdd85 ths
void op_mtc0_cause (void)
1107 8c0fdd85 ths
{
1108 8c0fdd85 ths
    uint32_t val, old;
1109 8c0fdd85 ths
1110 8c0fdd85 ths
    val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300);
1111 8c0fdd85 ths
    old = env->CP0_Cause;
1112 8c0fdd85 ths
    env->CP0_Cause = val;
1113 8c0fdd85 ths
#if 0
1114 8c0fdd85 ths
    {
1115 8c0fdd85 ths
        int i, mask;
1116 8c0fdd85 ths
       /* Check if we ever asserted a software IRQ */
1117 8c0fdd85 ths
        for (i = 0; i < 2; i++) {
1118 8c0fdd85 ths
            mask = 0x100 << i;
1119 8c0fdd85 ths
            if ((val & mask) & !(old & mask))
1120 8c0fdd85 ths
                CALL_FROM_TB1(mips_set_irq, i);
1121 8c0fdd85 ths
        }
1122 8c0fdd85 ths
    }
1123 8c0fdd85 ths
#endif
1124 8c0fdd85 ths
    RETURN();
1125 8c0fdd85 ths
}
1126 8c0fdd85 ths
1127 8c0fdd85 ths
void op_mtc0_epc (void)
1128 8c0fdd85 ths
{
1129 8c0fdd85 ths
    env->CP0_EPC = T0;
1130 8c0fdd85 ths
    RETURN();
1131 8c0fdd85 ths
}
1132 8c0fdd85 ths
1133 7a387fff ths
void op_mtc0_ebase (void)
1134 7a387fff ths
{
1135 7a387fff ths
    /* vectored interrupts not implemented */
1136 7a387fff ths
    /* Multi-CPU not implemented */
1137 7a387fff ths
    env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1138 7a387fff ths
    RETURN();
1139 7a387fff ths
}
1140 7a387fff ths
1141 8c0fdd85 ths
void op_mtc0_config0 (void)
1142 8c0fdd85 ths
{
1143 8c0fdd85 ths
#if defined(MIPS_USES_R4K_TLB)
1144 7a387fff ths
     /* Fixed mapping MMU not implemented */
1145 7a387fff ths
    env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001);
1146 8c0fdd85 ths
#else
1147 7a387fff ths
    env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001);
1148 8c0fdd85 ths
#endif
1149 8c0fdd85 ths
    RETURN();
1150 8c0fdd85 ths
}
1151 8c0fdd85 ths
1152 7a387fff ths
void op_mtc0_config2 (void)
1153 7a387fff ths
{
1154 7a387fff ths
    /* tertiary/secondary caches not implemented */
1155 7a387fff ths
    env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1156 7a387fff ths
    RETURN();
1157 7a387fff ths
}
1158 7a387fff ths
1159 7a387fff ths
void op_mtc0_watchlo0 (void)
1160 8c0fdd85 ths
{
1161 8c0fdd85 ths
    env->CP0_WatchLo = T0;
1162 8c0fdd85 ths
    RETURN();
1163 8c0fdd85 ths
}
1164 8c0fdd85 ths
1165 7a387fff ths
void op_mtc0_watchhi0 (void)
1166 8c0fdd85 ths
{
1167 8c0fdd85 ths
    env->CP0_WatchHi = T0 & 0x40FF0FF8;
1168 8c0fdd85 ths
    RETURN();
1169 8c0fdd85 ths
}
1170 8c0fdd85 ths
1171 7a387fff ths
void op_mtc0_xcontext (void)
1172 7a387fff ths
{
1173 7a387fff ths
    env->CP0_XContext = T0; /* XXX */
1174 7a387fff ths
    RETURN();
1175 7a387fff ths
}
1176 7a387fff ths
1177 7a387fff ths
void op_mtc0_framemask (void)
1178 7a387fff ths
{
1179 7a387fff ths
    env->CP0_Framemask = T0; /* XXX */
1180 7a387fff ths
    RETURN();
1181 7a387fff ths
}
1182 7a387fff ths
1183 8c0fdd85 ths
void op_mtc0_debug (void)
1184 8c0fdd85 ths
{
1185 8c0fdd85 ths
    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1186 8c0fdd85 ths
    if (T0 & (1 << CP0DB_DM))
1187 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_DM;
1188 8c0fdd85 ths
    else
1189 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_DM;
1190 8c0fdd85 ths
    RETURN();
1191 8c0fdd85 ths
}
1192 8c0fdd85 ths
1193 8c0fdd85 ths
void op_mtc0_depc (void)
1194 8c0fdd85 ths
{
1195 8c0fdd85 ths
    env->CP0_DEPC = T0;
1196 8c0fdd85 ths
    RETURN();
1197 8c0fdd85 ths
}
1198 8c0fdd85 ths
1199 7a387fff ths
void op_mtc0_performance0 (void)
1200 7a387fff ths
{
1201 7a387fff ths
    env->CP0_Performance0 = T0; /* XXX */
1202 7a387fff ths
    RETURN();
1203 7a387fff ths
}
1204 7a387fff ths
1205 8c0fdd85 ths
void op_mtc0_taglo (void)
1206 8c0fdd85 ths
{
1207 8c0fdd85 ths
    env->CP0_TagLo = T0 & 0xFFFFFCF6;
1208 8c0fdd85 ths
    RETURN();
1209 8c0fdd85 ths
}
1210 8c0fdd85 ths
1211 7a387fff ths
void op_mtc0_datalo (void)
1212 7a387fff ths
{
1213 7a387fff ths
    env->CP0_DataLo = T0; /* XXX */
1214 7a387fff ths
    RETURN();
1215 7a387fff ths
}
1216 7a387fff ths
1217 7a387fff ths
void op_mtc0_taghi (void)
1218 7a387fff ths
{
1219 7a387fff ths
    env->CP0_TagHi = T0; /* XXX */
1220 7a387fff ths
    RETURN();
1221 7a387fff ths
}
1222 7a387fff ths
1223 7a387fff ths
void op_mtc0_datahi (void)
1224 7a387fff ths
{
1225 7a387fff ths
    env->CP0_DataHi = T0; /* XXX */
1226 7a387fff ths
    RETURN();
1227 7a387fff ths
}
1228 7a387fff ths
1229 8c0fdd85 ths
void op_mtc0_errorepc (void)
1230 8c0fdd85 ths
{
1231 8c0fdd85 ths
    env->CP0_ErrorEPC = T0;
1232 8c0fdd85 ths
    RETURN();
1233 8c0fdd85 ths
}
1234 8c0fdd85 ths
1235 8c0fdd85 ths
void op_mtc0_desave (void)
1236 8c0fdd85 ths
{
1237 8c0fdd85 ths
    env->CP0_DESAVE = T0;
1238 6af0bf9c bellard
    RETURN();
1239 6af0bf9c bellard
}
1240 6af0bf9c bellard
1241 6ea83fed bellard
#ifdef MIPS_USES_FPU
1242 6ea83fed bellard
1243 6ea83fed bellard
#if 0
1244 6ea83fed bellard
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1245 6ea83fed bellard
#else
1246 6ea83fed bellard
# define DEBUG_FPU_STATE() do { } while(0)
1247 6ea83fed bellard
#endif
1248 6ea83fed bellard
1249 6ea83fed bellard
void op_cp1_enabled(void)
1250 6ea83fed bellard
{
1251 6ea83fed bellard
    if (!(env->CP0_Status & (1 << CP0St_CU1))) {
1252 6ea83fed bellard
        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
1253 6ea83fed bellard
    }
1254 6ea83fed bellard
    RETURN();
1255 6ea83fed bellard
}
1256 6ea83fed bellard
1257 6ea83fed bellard
/* CP1 functions */
1258 6ea83fed bellard
void op_cfc1 (void)
1259 6ea83fed bellard
{
1260 6ea83fed bellard
    if (T1 == 0) {
1261 6ea83fed bellard
        T0 = env->fcr0;
1262 6ea83fed bellard
    }
1263 6ea83fed bellard
    else {
1264 6ea83fed bellard
        /* fetch fcr31, masking unused bits */
1265 6ea83fed bellard
        T0 = env->fcr31 & 0x0183FFFF;
1266 6ea83fed bellard
    }
1267 6ea83fed bellard
    DEBUG_FPU_STATE();
1268 6ea83fed bellard
    RETURN();
1269 6ea83fed bellard
}
1270 6ea83fed bellard
1271 6ea83fed bellard
/* convert MIPS rounding mode in FCR31 to IEEE library */
1272 6ea83fed bellard
unsigned int ieee_rm[] = { 
1273 6ea83fed bellard
    float_round_nearest_even,
1274 6ea83fed bellard
    float_round_to_zero,
1275 6ea83fed bellard
    float_round_up,
1276 6ea83fed bellard
    float_round_down
1277 6ea83fed bellard
};
1278 6ea83fed bellard
1279 6ea83fed bellard
#define RESTORE_ROUNDING_MODE \
1280 6ea83fed bellard
    set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
1281 6ea83fed bellard
1282 6ea83fed bellard
void op_ctc1 (void)
1283 6ea83fed bellard
{
1284 6ea83fed bellard
    if (T1 == 0) {
1285 6ea83fed bellard
        /* XXX should this throw an exception?
1286 6ea83fed bellard
         * don't write to FCR0.
1287 6ea83fed bellard
         * env->fcr0 = T0; 
1288 6ea83fed bellard
         */
1289 6ea83fed bellard
    }
1290 6ea83fed bellard
    else {
1291 6ea83fed bellard
        /* store new fcr31, masking unused bits */  
1292 6ea83fed bellard
        env->fcr31 = T0 & 0x0183FFFF;
1293 6ea83fed bellard
1294 6ea83fed bellard
        /* set rounding mode */
1295 6ea83fed bellard
        RESTORE_ROUNDING_MODE;
1296 6ea83fed bellard
1297 6ea83fed bellard
#ifndef CONFIG_SOFTFLOAT
1298 6ea83fed bellard
        /* no floating point exception for native float */
1299 6ea83fed bellard
        SET_FP_ENABLE(env->fcr31, 0);
1300 6ea83fed bellard
#endif
1301 6ea83fed bellard
    }
1302 6ea83fed bellard
    DEBUG_FPU_STATE();
1303 6ea83fed bellard
    RETURN();
1304 6ea83fed bellard
}
1305 6ea83fed bellard
1306 6ea83fed bellard
void op_mfc1 (void)
1307 6ea83fed bellard
{
1308 6ea83fed bellard
    T0 = WT0;
1309 6ea83fed bellard
    DEBUG_FPU_STATE();
1310 6ea83fed bellard
    RETURN();
1311 6ea83fed bellard
}
1312 6ea83fed bellard
1313 6ea83fed bellard
void op_mtc1 (void)
1314 6ea83fed bellard
{
1315 6ea83fed bellard
    WT0 = T0;
1316 6ea83fed bellard
    DEBUG_FPU_STATE();
1317 6ea83fed bellard
    RETURN();
1318 6ea83fed bellard
}
1319 6ea83fed bellard
1320 6ea83fed bellard
/* Float support.
1321 6ea83fed bellard
   Single precition routines have a "s" suffix, double precision a
1322 6ea83fed bellard
   "d" suffix.  */
1323 6ea83fed bellard
1324 6ea83fed bellard
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1325 6ea83fed bellard
1326 dd016883 bellard
FLOAT_OP(cvtd, s)
1327 dd016883 bellard
{
1328 dd016883 bellard
    FDT2 = float32_to_float64(WT0, &env->fp_status);
1329 dd016883 bellard
    DEBUG_FPU_STATE();
1330 dd016883 bellard
    RETURN();
1331 dd016883 bellard
}
1332 6ea83fed bellard
FLOAT_OP(cvtd, w)
1333 6ea83fed bellard
{
1334 6ea83fed bellard
    FDT2 = int32_to_float64(WT0, &env->fp_status);
1335 6ea83fed bellard
    DEBUG_FPU_STATE();
1336 6ea83fed bellard
    RETURN();
1337 6ea83fed bellard
}
1338 dd016883 bellard
FLOAT_OP(cvts, d)
1339 dd016883 bellard
{
1340 417f38f0 pbrook
    FST2 = float64_to_float32(FDT0, &env->fp_status);
1341 dd016883 bellard
    DEBUG_FPU_STATE();
1342 dd016883 bellard
    RETURN();
1343 dd016883 bellard
}
1344 6ea83fed bellard
FLOAT_OP(cvts, w)
1345 6ea83fed bellard
{
1346 6ea83fed bellard
    FST2 = int32_to_float32(WT0, &env->fp_status);
1347 6ea83fed bellard
    DEBUG_FPU_STATE();
1348 6ea83fed bellard
    RETURN();
1349 6ea83fed bellard
}
1350 6ea83fed bellard
FLOAT_OP(cvtw, s)
1351 6ea83fed bellard
{
1352 6ea83fed bellard
    WT2 = float32_to_int32(FST0, &env->fp_status);
1353 6ea83fed bellard
    DEBUG_FPU_STATE();
1354 6ea83fed bellard
    RETURN();
1355 6ea83fed bellard
}
1356 6ea83fed bellard
FLOAT_OP(cvtw, d)
1357 6ea83fed bellard
{
1358 6ea83fed bellard
    WT2 = float64_to_int32(FDT0, &env->fp_status);
1359 6ea83fed bellard
    DEBUG_FPU_STATE();
1360 6ea83fed bellard
    RETURN();
1361 6ea83fed bellard
}
1362 6ea83fed bellard
1363 6ea83fed bellard
FLOAT_OP(roundw, d)
1364 6ea83fed bellard
{
1365 6ea83fed bellard
    set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1366 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1367 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1368 6ea83fed bellard
1369 6ea83fed bellard
    DEBUG_FPU_STATE();
1370 6ea83fed bellard
    RETURN();
1371 6ea83fed bellard
}
1372 6ea83fed bellard
FLOAT_OP(roundw, s)
1373 6ea83fed bellard
{
1374 6ea83fed bellard
    set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1375 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1376 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1377 6ea83fed bellard
    DEBUG_FPU_STATE();
1378 6ea83fed bellard
    RETURN();
1379 6ea83fed bellard
}
1380 6ea83fed bellard
1381 6ea83fed bellard
FLOAT_OP(truncw, d)
1382 6ea83fed bellard
{
1383 6ea83fed bellard
    WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status);
1384 6ea83fed bellard
    DEBUG_FPU_STATE();
1385 6ea83fed bellard
    RETURN();
1386 6ea83fed bellard
}
1387 6ea83fed bellard
FLOAT_OP(truncw, s)
1388 6ea83fed bellard
{
1389 6ea83fed bellard
    WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status);
1390 6ea83fed bellard
    DEBUG_FPU_STATE();
1391 6ea83fed bellard
    RETURN();
1392 6ea83fed bellard
}
1393 6ea83fed bellard
1394 6ea83fed bellard
FLOAT_OP(ceilw, d)
1395 6ea83fed bellard
{
1396 6ea83fed bellard
    set_float_rounding_mode(float_round_up, &env->fp_status);
1397 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1398 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1399 6ea83fed bellard
1400 6ea83fed bellard
    DEBUG_FPU_STATE();
1401 6ea83fed bellard
    RETURN();
1402 6ea83fed bellard
}
1403 6ea83fed bellard
FLOAT_OP(ceilw, s)
1404 6ea83fed bellard
{
1405 6ea83fed bellard
    set_float_rounding_mode(float_round_up, &env->fp_status);
1406 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1407 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1408 6ea83fed bellard
    DEBUG_FPU_STATE();
1409 6ea83fed bellard
    RETURN();
1410 6ea83fed bellard
}
1411 6ea83fed bellard
1412 6ea83fed bellard
FLOAT_OP(floorw, d)
1413 6ea83fed bellard
{
1414 6ea83fed bellard
    set_float_rounding_mode(float_round_down, &env->fp_status);
1415 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1416 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1417 6ea83fed bellard
1418 6ea83fed bellard
    DEBUG_FPU_STATE();
1419 6ea83fed bellard
    RETURN();
1420 6ea83fed bellard
}
1421 6ea83fed bellard
FLOAT_OP(floorw, s)
1422 6ea83fed bellard
{
1423 6ea83fed bellard
    set_float_rounding_mode(float_round_down, &env->fp_status);
1424 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1425 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1426 6ea83fed bellard
    DEBUG_FPU_STATE();
1427 6ea83fed bellard
    RETURN();
1428 6ea83fed bellard
}
1429 6ea83fed bellard
1430 6ea83fed bellard
/* binary operations */
1431 6ea83fed bellard
#define FLOAT_BINOP(name) \
1432 6ea83fed bellard
FLOAT_OP(name, d)         \
1433 6ea83fed bellard
{                         \
1434 6ea83fed bellard
    FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status);    \
1435 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1436 6ea83fed bellard
}                         \
1437 6ea83fed bellard
FLOAT_OP(name, s)         \
1438 6ea83fed bellard
{                         \
1439 6ea83fed bellard
    FST2 = float32_ ## name (FST0, FST1, &env->fp_status);    \
1440 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1441 6ea83fed bellard
}
1442 6ea83fed bellard
FLOAT_BINOP(add)
1443 6ea83fed bellard
FLOAT_BINOP(sub)
1444 6ea83fed bellard
FLOAT_BINOP(mul)
1445 6ea83fed bellard
FLOAT_BINOP(div)
1446 6ea83fed bellard
#undef FLOAT_BINOP
1447 6ea83fed bellard
1448 6ea83fed bellard
/* unary operations, modifying fp status  */
1449 6ea83fed bellard
#define FLOAT_UNOP(name)  \
1450 6ea83fed bellard
FLOAT_OP(name, d)         \
1451 6ea83fed bellard
{                         \
1452 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0, &env->fp_status);   \
1453 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1454 6ea83fed bellard
}                         \
1455 6ea83fed bellard
FLOAT_OP(name, s)         \
1456 6ea83fed bellard
{                         \
1457 6ea83fed bellard
    FST2 = float32_ ## name(FST0, &env->fp_status);   \
1458 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1459 6ea83fed bellard
}
1460 6ea83fed bellard
FLOAT_UNOP(sqrt)
1461 6ea83fed bellard
#undef FLOAT_UNOP
1462 6ea83fed bellard
1463 6ea83fed bellard
/* unary operations, not modifying fp status  */
1464 6ea83fed bellard
#define FLOAT_UNOP(name)  \
1465 6ea83fed bellard
FLOAT_OP(name, d)         \
1466 6ea83fed bellard
{                         \
1467 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0);   \
1468 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1469 6ea83fed bellard
}                         \
1470 6ea83fed bellard
FLOAT_OP(name, s)         \
1471 6ea83fed bellard
{                         \
1472 6ea83fed bellard
    FST2 = float32_ ## name(FST0);   \
1473 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1474 6ea83fed bellard
}
1475 6ea83fed bellard
FLOAT_UNOP(abs)
1476 6ea83fed bellard
FLOAT_UNOP(chs)
1477 6ea83fed bellard
#undef FLOAT_UNOP
1478 6ea83fed bellard
1479 6ea83fed bellard
FLOAT_OP(mov, d)
1480 6ea83fed bellard
{
1481 6ea83fed bellard
    FDT2 = FDT0;
1482 6ea83fed bellard
    DEBUG_FPU_STATE();
1483 6ea83fed bellard
    RETURN();
1484 6ea83fed bellard
}
1485 6ea83fed bellard
FLOAT_OP(mov, s)
1486 6ea83fed bellard
{
1487 6ea83fed bellard
    FST2 = FST0;
1488 6ea83fed bellard
    DEBUG_FPU_STATE();
1489 6ea83fed bellard
    RETURN();
1490 6ea83fed bellard
}
1491 6ea83fed bellard
1492 6ea83fed bellard
#ifdef CONFIG_SOFTFLOAT
1493 6ea83fed bellard
#define clear_invalid() do {                                \
1494 6ea83fed bellard
    int flags = get_float_exception_flags(&env->fp_status); \
1495 6ea83fed bellard
    flags &= ~float_flag_invalid;                           \
1496 6ea83fed bellard
    set_float_exception_flags(flags, &env->fp_status);      \
1497 6ea83fed bellard
} while(0)
1498 6ea83fed bellard
#else
1499 6ea83fed bellard
#define clear_invalid() do { } while(0)
1500 6ea83fed bellard
#endif
1501 6ea83fed bellard
1502 6ea83fed bellard
extern void dump_fpu_s(CPUState *env);
1503 6ea83fed bellard
1504 6ea83fed bellard
#define FOP_COND(fmt, op, sig, cond)           \
1505 6ea83fed bellard
void op_cmp_ ## fmt ## _ ## op (void)          \
1506 6ea83fed bellard
{                                              \
1507 6ea83fed bellard
    if (cond)                                  \
1508 6ea83fed bellard
        SET_FP_COND(env->fcr31);               \
1509 6ea83fed bellard
    else                                       \
1510 6ea83fed bellard
        CLEAR_FP_COND(env->fcr31);             \
1511 6ea83fed bellard
    if (!sig)                                  \
1512 6ea83fed bellard
        clear_invalid();                       \
1513 6ea83fed bellard
    /*CALL_FROM_TB1(dump_fpu_s, env);*/ \
1514 6ea83fed bellard
    DEBUG_FPU_STATE();                         \
1515 6ea83fed bellard
    RETURN();                                  \
1516 6ea83fed bellard
}
1517 6ea83fed bellard
1518 569f5d66 bellard
int float64_is_unordered(float64 a, float64 b STATUS_PARAM)
1519 6ea83fed bellard
{
1520 6ea83fed bellard
    if (float64_is_nan(a) || float64_is_nan(b)) {
1521 6ea83fed bellard
        float_raise(float_flag_invalid, status);
1522 6ea83fed bellard
        return 1;
1523 6ea83fed bellard
    }
1524 6ea83fed bellard
    else {
1525 6ea83fed bellard
        return 0;
1526 6ea83fed bellard
    }
1527 6ea83fed bellard
}
1528 6ea83fed bellard
1529 6ea83fed bellard
FOP_COND(d, f,   0,                                                      0) 
1530 6ea83fed bellard
FOP_COND(d, un,  0, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1531 6ea83fed bellard
FOP_COND(d, eq,  0,                                                      float64_eq(FDT0, FDT1, &env->fp_status))
1532 6ea83fed bellard
FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1533 6ea83fed bellard
FOP_COND(d, olt, 0,                                                      float64_lt(FDT0, FDT1, &env->fp_status))
1534 6ea83fed bellard
FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1535 6ea83fed bellard
FOP_COND(d, ole, 0,                                                      float64_le(FDT0, FDT1, &env->fp_status))
1536 6ea83fed bellard
FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1537 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1538 6ea83fed bellard
 * but float*_is_unordered() is still called
1539 6ea83fed bellard
 */
1540 6ea83fed bellard
FOP_COND(d, sf,  1,                                                      (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0))
1541 6ea83fed bellard
FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1542 6ea83fed bellard
FOP_COND(d, seq, 1,                                                      float64_eq(FDT0, FDT1, &env->fp_status))
1543 6ea83fed bellard
FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1544 6ea83fed bellard
FOP_COND(d, lt,  1,                                                      float64_lt(FDT0, FDT1, &env->fp_status))
1545 6ea83fed bellard
FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1546 6ea83fed bellard
FOP_COND(d, le,  1,                                                      float64_le(FDT0, FDT1, &env->fp_status))
1547 6ea83fed bellard
FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1548 6ea83fed bellard
1549 6ea83fed bellard
flag float32_is_unordered(float32 a, float32 b STATUS_PARAM)
1550 6ea83fed bellard
{
1551 6ea83fed bellard
    extern flag float32_is_nan( float32 a );
1552 6ea83fed bellard
    if (float32_is_nan(a) || float32_is_nan(b)) {
1553 6ea83fed bellard
        float_raise(float_flag_invalid, status);
1554 6ea83fed bellard
        return 1;
1555 6ea83fed bellard
    }
1556 6ea83fed bellard
    else {
1557 6ea83fed bellard
        return 0;
1558 6ea83fed bellard
    }
1559 6ea83fed bellard
}
1560 6ea83fed bellard
1561 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1562 6ea83fed bellard
 * but float*_is_unordered() is still called
1563 6ea83fed bellard
 */
1564 6ea83fed bellard
FOP_COND(s, f,   0,                                                      0) 
1565 6ea83fed bellard
FOP_COND(s, un,  0, float32_is_unordered(FST1, FST0, &env->fp_status))
1566 6ea83fed bellard
FOP_COND(s, eq,  0,                                                      float32_eq(FST0, FST1, &env->fp_status))
1567 6ea83fed bellard
FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1568 6ea83fed bellard
FOP_COND(s, olt, 0,                                                      float32_lt(FST0, FST1, &env->fp_status))
1569 6ea83fed bellard
FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1570 6ea83fed bellard
FOP_COND(s, ole, 0,                                                      float32_le(FST0, FST1, &env->fp_status))
1571 6ea83fed bellard
FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1572 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1573 6ea83fed bellard
 * but float*_is_unordered() is still called
1574 6ea83fed bellard
 */
1575 6ea83fed bellard
FOP_COND(s, sf,  1,                                                      (float32_is_unordered(FST0, FST1, &env->fp_status), 0))
1576 6ea83fed bellard
FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status))
1577 6ea83fed bellard
FOP_COND(s, seq, 1,                                                      float32_eq(FST0, FST1, &env->fp_status))
1578 6ea83fed bellard
FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1579 6ea83fed bellard
FOP_COND(s, lt,  1,                                                      float32_lt(FST0, FST1, &env->fp_status))
1580 6ea83fed bellard
FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1581 6ea83fed bellard
FOP_COND(s, le,  1,                                                      float32_le(FST0, FST1, &env->fp_status))
1582 6ea83fed bellard
FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1583 6ea83fed bellard
1584 6ea83fed bellard
void op_bc1f (void)
1585 6ea83fed bellard
{
1586 6ea83fed bellard
    T0 = ! IS_FP_COND_SET(env->fcr31);
1587 6ea83fed bellard
    DEBUG_FPU_STATE();
1588 6ea83fed bellard
    RETURN();
1589 6ea83fed bellard
}
1590 6ea83fed bellard
1591 6ea83fed bellard
void op_bc1t (void)
1592 6ea83fed bellard
{
1593 6ea83fed bellard
    T0 = IS_FP_COND_SET(env->fcr31);
1594 6ea83fed bellard
    DEBUG_FPU_STATE();
1595 6ea83fed bellard
    RETURN();
1596 6ea83fed bellard
}
1597 6ea83fed bellard
#endif /* MIPS_USES_FPU */
1598 6ea83fed bellard
1599 6af0bf9c bellard
#if defined(MIPS_USES_R4K_TLB)
1600 6af0bf9c bellard
void op_tlbwi (void)
1601 6af0bf9c bellard
{
1602 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbwi);
1603 6af0bf9c bellard
    RETURN();
1604 6af0bf9c bellard
}
1605 6af0bf9c bellard
1606 6af0bf9c bellard
void op_tlbwr (void)
1607 6af0bf9c bellard
{
1608 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbwr);
1609 6af0bf9c bellard
    RETURN();
1610 6af0bf9c bellard
}
1611 6af0bf9c bellard
1612 6af0bf9c bellard
void op_tlbp (void)
1613 6af0bf9c bellard
{
1614 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbp);
1615 6af0bf9c bellard
    RETURN();
1616 6af0bf9c bellard
}
1617 6af0bf9c bellard
1618 6af0bf9c bellard
void op_tlbr (void)
1619 6af0bf9c bellard
{
1620 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbr);
1621 6af0bf9c bellard
    RETURN();
1622 6af0bf9c bellard
}
1623 6af0bf9c bellard
#endif
1624 6af0bf9c bellard
1625 6af0bf9c bellard
/* Specials */
1626 6af0bf9c bellard
void op_pmon (void)
1627 6af0bf9c bellard
{
1628 6af0bf9c bellard
    CALL_FROM_TB1(do_pmon, PARAM1);
1629 7a387fff ths
    RETURN();
1630 7a387fff ths
}
1631 7a387fff ths
1632 7a387fff ths
void op_di (void)
1633 7a387fff ths
{
1634 7a387fff ths
    uint32_t val;
1635 7a387fff ths
1636 7a387fff ths
    T0 = env->CP0_Status;
1637 7a387fff ths
    val = T0 & ~(1 << CP0St_IE);
1638 7a387fff ths
    if (val != T0) {
1639 7a387fff ths
        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1640 7a387fff ths
        env->CP0_Status = val;
1641 7a387fff ths
    }
1642 7a387fff ths
    RETURN();
1643 7a387fff ths
}
1644 7a387fff ths
1645 7a387fff ths
void op_ei (void)
1646 7a387fff ths
{
1647 7a387fff ths
    uint32_t val;
1648 7a387fff ths
1649 7a387fff ths
    T0 = env->CP0_Status;
1650 7a387fff ths
    val = T0 | (1 << CP0St_IE);
1651 7a387fff ths
    if (val != T0) {
1652 7a387fff ths
       const uint32_t mask = 0x0000FF00;
1653 7a387fff ths
1654 7a387fff ths
       env->CP0_Status = val;
1655 7a387fff ths
       if (!(env->hflags & MIPS_HFLAG_EXL) &&
1656 7a387fff ths
           !(env->hflags & MIPS_HFLAG_ERL) &&
1657 7a387fff ths
           !(env->hflags & MIPS_HFLAG_DM) &&
1658 7a387fff ths
           (env->CP0_Status & env->CP0_Cause & mask)) {
1659 7a387fff ths
               env->interrupt_request |= CPU_INTERRUPT_HARD;
1660 7a387fff ths
               if (logfile)
1661 7a387fff ths
                   CALL_FROM_TB0(do_mtc0_status_irqraise_debug);
1662 7a387fff ths
       }
1663 7a387fff ths
    }
1664 7a387fff ths
    RETURN();
1665 6af0bf9c bellard
}
1666 6af0bf9c bellard
1667 6af0bf9c bellard
void op_trap (void)
1668 6af0bf9c bellard
{
1669 6af0bf9c bellard
    if (T0) {
1670 4ad40f36 bellard
        CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP);
1671 6af0bf9c bellard
    }
1672 6af0bf9c bellard
    RETURN();
1673 6af0bf9c bellard
}
1674 6af0bf9c bellard
1675 4ad40f36 bellard
void op_debug (void)
1676 4ad40f36 bellard
{
1677 7a387fff ths
    CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
1678 7a387fff ths
    RETURN();
1679 4ad40f36 bellard
}
1680 4ad40f36 bellard
1681 6af0bf9c bellard
void op_set_lladdr (void)
1682 6af0bf9c bellard
{
1683 6af0bf9c bellard
    env->CP0_LLAddr = T2;
1684 7a387fff ths
    RETURN();
1685 6af0bf9c bellard
}
1686 6af0bf9c bellard
1687 6af0bf9c bellard
void debug_eret (void);
1688 6af0bf9c bellard
void op_eret (void)
1689 6af0bf9c bellard
{
1690 6af0bf9c bellard
    CALL_FROM_TB0(debug_eret);
1691 51e11d9e bellard
    if (env->hflags & MIPS_HFLAG_ERL) {
1692 6af0bf9c bellard
        env->PC = env->CP0_ErrorEPC;
1693 51e11d9e bellard
        env->hflags &= ~MIPS_HFLAG_ERL;
1694 3e382bc8 bellard
        env->CP0_Status &= ~(1 << CP0St_ERL);
1695 51e11d9e bellard
    } else {
1696 6af0bf9c bellard
        env->PC = env->CP0_EPC;
1697 51e11d9e bellard
        env->hflags &= ~MIPS_HFLAG_EXL;
1698 3e382bc8 bellard
        env->CP0_Status &= ~(1 << CP0St_EXL);
1699 51e11d9e bellard
    }
1700 6af0bf9c bellard
    env->CP0_LLAddr = 1;
1701 7a387fff ths
    RETURN();
1702 6af0bf9c bellard
}
1703 6af0bf9c bellard
1704 6af0bf9c bellard
void op_deret (void)
1705 6af0bf9c bellard
{
1706 6af0bf9c bellard
    CALL_FROM_TB0(debug_eret);
1707 6af0bf9c bellard
    env->PC = env->CP0_DEPC;
1708 7a387fff ths
    RETURN();
1709 7a387fff ths
}
1710 7a387fff ths
1711 7a387fff ths
void op_rdhwr_cpunum(void)
1712 7a387fff ths
{
1713 7a387fff ths
    if (env->CP0_HWREna & (1 << 0))
1714 7a387fff ths
       T0 = env->CP0_EBase & 0x2ff;
1715 7a387fff ths
    else
1716 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
1717 7a387fff ths
    RETURN();
1718 7a387fff ths
}
1719 7a387fff ths
1720 7a387fff ths
void op_rdhwr_synci_step(void)
1721 7a387fff ths
{
1722 7a387fff ths
    if (env->CP0_HWREna & (1 << 1))
1723 7a387fff ths
       T0 = env->SYNCI_Step;
1724 7a387fff ths
    else
1725 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
1726 7a387fff ths
    RETURN();
1727 7a387fff ths
}
1728 7a387fff ths
1729 7a387fff ths
void op_rdhwr_cc(void)
1730 7a387fff ths
{
1731 7a387fff ths
    if (env->CP0_HWREna & (1 << 2))
1732 7a387fff ths
       T0 = env->CP0_Count;
1733 7a387fff ths
    else
1734 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
1735 7a387fff ths
    RETURN();
1736 7a387fff ths
}
1737 7a387fff ths
1738 7a387fff ths
void op_rdhwr_ccres(void)
1739 7a387fff ths
{
1740 7a387fff ths
    if (env->CP0_HWREna & (1 << 3))
1741 7a387fff ths
       T0 = env->CCRes;
1742 7a387fff ths
    else
1743 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
1744 7a387fff ths
    RETURN();
1745 6af0bf9c bellard
}
1746 6af0bf9c bellard
1747 6af0bf9c bellard
void op_save_state (void)
1748 6af0bf9c bellard
{
1749 6af0bf9c bellard
    env->hflags = PARAM1;
1750 6af0bf9c bellard
    RETURN();
1751 6af0bf9c bellard
}
1752 6af0bf9c bellard
1753 6af0bf9c bellard
void op_save_pc (void)
1754 6af0bf9c bellard
{
1755 6af0bf9c bellard
    env->PC = PARAM1;
1756 6af0bf9c bellard
    RETURN();
1757 6af0bf9c bellard
}
1758 6af0bf9c bellard
1759 6af0bf9c bellard
void op_raise_exception (void)
1760 6af0bf9c bellard
{
1761 6af0bf9c bellard
    CALL_FROM_TB1(do_raise_exception, PARAM1);
1762 6af0bf9c bellard
    RETURN();
1763 6af0bf9c bellard
}
1764 6af0bf9c bellard
1765 6af0bf9c bellard
void op_raise_exception_err (void)
1766 6af0bf9c bellard
{
1767 6af0bf9c bellard
    CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
1768 6af0bf9c bellard
    RETURN();
1769 6af0bf9c bellard
}
1770 6af0bf9c bellard
1771 6af0bf9c bellard
void op_exit_tb (void)
1772 6af0bf9c bellard
{
1773 6af0bf9c bellard
    EXIT_TB();
1774 7a387fff ths
    RETURN();
1775 6af0bf9c bellard
}
1776 6af0bf9c bellard
1777 4ad40f36 bellard
void op_wait (void)
1778 4ad40f36 bellard
{
1779 4ad40f36 bellard
    env->halted = 1;
1780 4ad40f36 bellard
    CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
1781 7a387fff ths
    RETURN();
1782 7a387fff ths
}
1783 7a387fff ths
1784 7a387fff ths
/* Bitfield operations. */
1785 7a387fff ths
void op_ext(void)
1786 7a387fff ths
{
1787 7a387fff ths
    unsigned int pos = PARAM1;
1788 7a387fff ths
    unsigned int size = PARAM2;
1789 7a387fff ths
1790 7a387fff ths
    T0 = (T1 >> pos) & ((1 << size) - 1);
1791 7a387fff ths
    RETURN();
1792 7a387fff ths
}
1793 7a387fff ths
1794 7a387fff ths
void op_ins(void)
1795 7a387fff ths
{
1796 7a387fff ths
    unsigned int pos = PARAM1;
1797 7a387fff ths
    unsigned int size = PARAM2;
1798 7a387fff ths
    target_ulong mask = ((1 << size) - 1) << pos;
1799 7a387fff ths
1800 7a387fff ths
    T0 = (T2 & ~mask) | ((T1 << pos) & mask);
1801 7a387fff ths
    RETURN();
1802 7a387fff ths
}
1803 7a387fff ths
1804 7a387fff ths
void op_wsbh(void)
1805 7a387fff ths
{
1806 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
1807 7a387fff ths
    RETURN();
1808 7a387fff ths
}
1809 7a387fff ths
1810 7a387fff ths
void op_dsbh(void)
1811 7a387fff ths
{
1812 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
1813 7a387fff ths
    RETURN();
1814 7a387fff ths
}
1815 7a387fff ths
1816 7a387fff ths
void op_dshd(void)
1817 7a387fff ths
{
1818 7a387fff ths
    T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
1819 7a387fff ths
    RETURN();
1820 7a387fff ths
}
1821 7a387fff ths
1822 7a387fff ths
void op_seb(void)
1823 7a387fff ths
{
1824 7a387fff ths
    T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
1825 7a387fff ths
    RETURN();
1826 7a387fff ths
}
1827 7a387fff ths
1828 7a387fff ths
void op_seh(void)
1829 7a387fff ths
{
1830 7a387fff ths
    T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
1831 7a387fff ths
    RETURN();
1832 4ad40f36 bellard
}