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1 | 4c9649a9 | j_mayer | /*
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2 | 4c9649a9 | j_mayer | * Alpha emulation cpu translation for qemu.
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3 | 5fafdf24 | ths | *
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4 | 4c9649a9 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 4c9649a9 | j_mayer | *
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6 | 4c9649a9 | j_mayer | * This library is free software; you can redistribute it and/or
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7 | 4c9649a9 | j_mayer | * modify it under the terms of the GNU Lesser General Public
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8 | 4c9649a9 | j_mayer | * License as published by the Free Software Foundation; either
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9 | 4c9649a9 | j_mayer | * version 2 of the License, or (at your option) any later version.
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10 | 4c9649a9 | j_mayer | *
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11 | 4c9649a9 | j_mayer | * This library is distributed in the hope that it will be useful,
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12 | 4c9649a9 | j_mayer | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 4c9649a9 | j_mayer | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 4c9649a9 | j_mayer | * Lesser General Public License for more details.
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15 | 4c9649a9 | j_mayer | *
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16 | 4c9649a9 | j_mayer | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 4c9649a9 | j_mayer | */
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19 | 4c9649a9 | j_mayer | |
20 | 4c9649a9 | j_mayer | #include "cpu.h" |
21 | 4c9649a9 | j_mayer | #include "disas.h" |
22 | ae8ecd42 | aurel32 | #include "host-utils.h" |
23 | 57fec1fe | bellard | #include "tcg-op.h" |
24 | 4c9649a9 | j_mayer | |
25 | a7812ae4 | pbrook | #include "helper.h" |
26 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
27 | a7812ae4 | pbrook | #include "helper.h" |
28 | a7812ae4 | pbrook | |
29 | 19188121 | Richard Henderson | #undef ALPHA_DEBUG_DISAS
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30 | f24518b5 | Richard Henderson | #define CONFIG_SOFTFLOAT_INLINE
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31 | d12d51d5 | aliguori | |
32 | d12d51d5 | aliguori | #ifdef ALPHA_DEBUG_DISAS
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33 | 806991da | Richard Henderson | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
34 | d12d51d5 | aliguori | #else
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35 | d12d51d5 | aliguori | # define LOG_DISAS(...) do { } while (0) |
36 | d12d51d5 | aliguori | #endif
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37 | d12d51d5 | aliguori | |
38 | 4c9649a9 | j_mayer | typedef struct DisasContext DisasContext; |
39 | 4c9649a9 | j_mayer | struct DisasContext {
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40 | 4af70374 | Richard Henderson | struct TranslationBlock *tb;
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41 | 4af70374 | Richard Henderson | CPUAlphaState *env; |
42 | 4c9649a9 | j_mayer | uint64_t pc; |
43 | 4c9649a9 | j_mayer | int mem_idx;
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44 | f24518b5 | Richard Henderson | |
45 | f24518b5 | Richard Henderson | /* Current rounding mode for this TB. */
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46 | f24518b5 | Richard Henderson | int tb_rm;
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47 | f24518b5 | Richard Henderson | /* Current flush-to-zero setting for this TB. */
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48 | f24518b5 | Richard Henderson | int tb_ftz;
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49 | 4c9649a9 | j_mayer | }; |
50 | 4c9649a9 | j_mayer | |
51 | 4af70374 | Richard Henderson | /* Return values from translate_one, indicating the state of the TB.
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52 | 4af70374 | Richard Henderson | Note that zero indicates that we are not exiting the TB. */
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53 | 4af70374 | Richard Henderson | |
54 | 4af70374 | Richard Henderson | typedef enum { |
55 | 4af70374 | Richard Henderson | NO_EXIT, |
56 | 4af70374 | Richard Henderson | |
57 | 4af70374 | Richard Henderson | /* We have emitted one or more goto_tb. No fixup required. */
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58 | 4af70374 | Richard Henderson | EXIT_GOTO_TB, |
59 | 4af70374 | Richard Henderson | |
60 | 4af70374 | Richard Henderson | /* We are not using a goto_tb (for whatever reason), but have updated
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61 | 4af70374 | Richard Henderson | the PC (for whatever reason), so there's no need to do it again on
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62 | 4af70374 | Richard Henderson | exiting the TB. */
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63 | 4af70374 | Richard Henderson | EXIT_PC_UPDATED, |
64 | 4af70374 | Richard Henderson | |
65 | 4af70374 | Richard Henderson | /* We are exiting the TB, but have neither emitted a goto_tb, nor
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66 | 4af70374 | Richard Henderson | updated the PC for the next instruction to be executed. */
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67 | 8aa3fa20 | Richard Henderson | EXIT_PC_STALE, |
68 | 8aa3fa20 | Richard Henderson | |
69 | 8aa3fa20 | Richard Henderson | /* We are ending the TB with a noreturn function call, e.g. longjmp.
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70 | 8aa3fa20 | Richard Henderson | No following code will be executed. */
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71 | 8aa3fa20 | Richard Henderson | EXIT_NORETURN, |
72 | 4af70374 | Richard Henderson | } ExitStatus; |
73 | 4af70374 | Richard Henderson | |
74 | 3761035f | aurel32 | /* global register indexes */
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75 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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76 | 496cb5b9 | aurel32 | static TCGv cpu_ir[31]; |
77 | f18cd223 | aurel32 | static TCGv cpu_fir[31]; |
78 | 496cb5b9 | aurel32 | static TCGv cpu_pc;
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79 | 6910b8f6 | Richard Henderson | static TCGv cpu_lock_addr;
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80 | 6910b8f6 | Richard Henderson | static TCGv cpu_lock_st_addr;
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81 | 6910b8f6 | Richard Henderson | static TCGv cpu_lock_value;
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82 | 2ace7e55 | Richard Henderson | static TCGv cpu_unique;
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83 | 2ace7e55 | Richard Henderson | #ifndef CONFIG_USER_ONLY
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84 | 2ace7e55 | Richard Henderson | static TCGv cpu_sysval;
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85 | 2ace7e55 | Richard Henderson | static TCGv cpu_usp;
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86 | ab471ade | Richard Henderson | #endif
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87 | 496cb5b9 | aurel32 | |
88 | 3761035f | aurel32 | /* register names */
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89 | f18cd223 | aurel32 | static char cpu_reg_names[10*4+21*5 + 10*5+21*6]; |
90 | 2e70f6ef | pbrook | |
91 | 2e70f6ef | pbrook | #include "gen-icount.h" |
92 | 2e70f6ef | pbrook | |
93 | a5f1b965 | blueswir1 | static void alpha_translate_init(void) |
94 | 2e70f6ef | pbrook | { |
95 | 496cb5b9 | aurel32 | int i;
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96 | 496cb5b9 | aurel32 | char *p;
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97 | 2e70f6ef | pbrook | static int done_init = 0; |
98 | 496cb5b9 | aurel32 | |
99 | 2e70f6ef | pbrook | if (done_init)
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100 | 2e70f6ef | pbrook | return;
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101 | 496cb5b9 | aurel32 | |
102 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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103 | 496cb5b9 | aurel32 | |
104 | 496cb5b9 | aurel32 | p = cpu_reg_names; |
105 | 496cb5b9 | aurel32 | for (i = 0; i < 31; i++) { |
106 | 496cb5b9 | aurel32 | sprintf(p, "ir%d", i);
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107 | a7812ae4 | pbrook | cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0, |
108 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, ir[i]), p); |
109 | 6ba8dcd7 | aurel32 | p += (i < 10) ? 4 : 5; |
110 | f18cd223 | aurel32 | |
111 | f18cd223 | aurel32 | sprintf(p, "fir%d", i);
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112 | a7812ae4 | pbrook | cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0, |
113 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, fir[i]), p); |
114 | f18cd223 | aurel32 | p += (i < 10) ? 5 : 6; |
115 | 496cb5b9 | aurel32 | } |
116 | 496cb5b9 | aurel32 | |
117 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, |
118 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, pc), "pc");
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119 | 496cb5b9 | aurel32 | |
120 | 6910b8f6 | Richard Henderson | cpu_lock_addr = tcg_global_mem_new_i64(TCG_AREG0, |
121 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, lock_addr), |
122 | 6910b8f6 | Richard Henderson | "lock_addr");
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123 | 6910b8f6 | Richard Henderson | cpu_lock_st_addr = tcg_global_mem_new_i64(TCG_AREG0, |
124 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, lock_st_addr), |
125 | 6910b8f6 | Richard Henderson | "lock_st_addr");
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126 | 6910b8f6 | Richard Henderson | cpu_lock_value = tcg_global_mem_new_i64(TCG_AREG0, |
127 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, lock_value), |
128 | 6910b8f6 | Richard Henderson | "lock_value");
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129 | f4ed8679 | aurel32 | |
130 | 2ace7e55 | Richard Henderson | cpu_unique = tcg_global_mem_new_i64(TCG_AREG0, |
131 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, unique), "unique");
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132 | 2ace7e55 | Richard Henderson | #ifndef CONFIG_USER_ONLY
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133 | 2ace7e55 | Richard Henderson | cpu_sysval = tcg_global_mem_new_i64(TCG_AREG0, |
134 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, sysval), "sysval");
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135 | 2ace7e55 | Richard Henderson | cpu_usp = tcg_global_mem_new_i64(TCG_AREG0, |
136 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, usp), "usp");
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137 | ab471ade | Richard Henderson | #endif
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138 | ab471ade | Richard Henderson | |
139 | 496cb5b9 | aurel32 | /* register helpers */
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140 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
141 | 496cb5b9 | aurel32 | #include "helper.h" |
142 | 496cb5b9 | aurel32 | |
143 | 2e70f6ef | pbrook | done_init = 1;
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144 | 2e70f6ef | pbrook | } |
145 | 2e70f6ef | pbrook | |
146 | bf1b03fe | Richard Henderson | static void gen_excp_1(int exception, int error_code) |
147 | 4c9649a9 | j_mayer | { |
148 | a7812ae4 | pbrook | TCGv_i32 tmp1, tmp2; |
149 | 6ad02592 | aurel32 | |
150 | 6ad02592 | aurel32 | tmp1 = tcg_const_i32(exception); |
151 | 6ad02592 | aurel32 | tmp2 = tcg_const_i32(error_code); |
152 | b9f0923e | Richard Henderson | gen_helper_excp(cpu_env, tmp1, tmp2); |
153 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp2); |
154 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp1); |
155 | bf1b03fe | Richard Henderson | } |
156 | 8aa3fa20 | Richard Henderson | |
157 | bf1b03fe | Richard Henderson | static ExitStatus gen_excp(DisasContext *ctx, int exception, int error_code) |
158 | bf1b03fe | Richard Henderson | { |
159 | bf1b03fe | Richard Henderson | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
160 | bf1b03fe | Richard Henderson | gen_excp_1(exception, error_code); |
161 | 8aa3fa20 | Richard Henderson | return EXIT_NORETURN;
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162 | 4c9649a9 | j_mayer | } |
163 | 4c9649a9 | j_mayer | |
164 | 8aa3fa20 | Richard Henderson | static inline ExitStatus gen_invalid(DisasContext *ctx) |
165 | 4c9649a9 | j_mayer | { |
166 | 8aa3fa20 | Richard Henderson | return gen_excp(ctx, EXCP_OPCDEC, 0); |
167 | 4c9649a9 | j_mayer | } |
168 | 4c9649a9 | j_mayer | |
169 | 636aa200 | Blue Swirl | static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags) |
170 | f18cd223 | aurel32 | { |
171 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
172 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
173 | f18cd223 | aurel32 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
174 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(tmp32, tmp); |
175 | a7812ae4 | pbrook | gen_helper_memory_to_f(t0, tmp32); |
176 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
177 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
178 | f18cd223 | aurel32 | } |
179 | f18cd223 | aurel32 | |
180 | 636aa200 | Blue Swirl | static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags) |
181 | f18cd223 | aurel32 | { |
182 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
183 | f18cd223 | aurel32 | tcg_gen_qemu_ld64(tmp, t1, flags); |
184 | a7812ae4 | pbrook | gen_helper_memory_to_g(t0, tmp); |
185 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
186 | f18cd223 | aurel32 | } |
187 | f18cd223 | aurel32 | |
188 | 636aa200 | Blue Swirl | static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags) |
189 | f18cd223 | aurel32 | { |
190 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
191 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
192 | f18cd223 | aurel32 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
193 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(tmp32, tmp); |
194 | a7812ae4 | pbrook | gen_helper_memory_to_s(t0, tmp32); |
195 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
196 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
197 | f18cd223 | aurel32 | } |
198 | f18cd223 | aurel32 | |
199 | 636aa200 | Blue Swirl | static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags) |
200 | f4ed8679 | aurel32 | { |
201 | f4ed8679 | aurel32 | tcg_gen_qemu_ld32s(t0, t1, flags); |
202 | 6910b8f6 | Richard Henderson | tcg_gen_mov_i64(cpu_lock_addr, t1); |
203 | 6910b8f6 | Richard Henderson | tcg_gen_mov_i64(cpu_lock_value, t0); |
204 | f4ed8679 | aurel32 | } |
205 | f4ed8679 | aurel32 | |
206 | 636aa200 | Blue Swirl | static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags) |
207 | f4ed8679 | aurel32 | { |
208 | f4ed8679 | aurel32 | tcg_gen_qemu_ld64(t0, t1, flags); |
209 | 6910b8f6 | Richard Henderson | tcg_gen_mov_i64(cpu_lock_addr, t1); |
210 | 6910b8f6 | Richard Henderson | tcg_gen_mov_i64(cpu_lock_value, t0); |
211 | f4ed8679 | aurel32 | } |
212 | f4ed8679 | aurel32 | |
213 | 636aa200 | Blue Swirl | static inline void gen_load_mem(DisasContext *ctx, |
214 | 636aa200 | Blue Swirl | void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,
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215 | 636aa200 | Blue Swirl | int flags),
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216 | 636aa200 | Blue Swirl | int ra, int rb, int32_t disp16, int fp, |
217 | 636aa200 | Blue Swirl | int clear)
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218 | 023d8ca2 | aurel32 | { |
219 | 6910b8f6 | Richard Henderson | TCGv addr, va; |
220 | 023d8ca2 | aurel32 | |
221 | 6910b8f6 | Richard Henderson | /* LDQ_U with ra $31 is UNOP. Other various loads are forms of
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222 | 6910b8f6 | Richard Henderson | prefetches, which we can treat as nops. No worries about
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223 | 6910b8f6 | Richard Henderson | missed exceptions here. */
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224 | 6910b8f6 | Richard Henderson | if (unlikely(ra == 31)) { |
225 | 023d8ca2 | aurel32 | return;
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226 | 6910b8f6 | Richard Henderson | } |
227 | 023d8ca2 | aurel32 | |
228 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
229 | 023d8ca2 | aurel32 | if (rb != 31) { |
230 | 023d8ca2 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
231 | 6910b8f6 | Richard Henderson | if (clear) {
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232 | 023d8ca2 | aurel32 | tcg_gen_andi_i64(addr, addr, ~0x7);
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233 | 6910b8f6 | Richard Henderson | } |
234 | 023d8ca2 | aurel32 | } else {
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235 | 6910b8f6 | Richard Henderson | if (clear) {
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236 | 023d8ca2 | aurel32 | disp16 &= ~0x7;
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237 | 6910b8f6 | Richard Henderson | } |
238 | 023d8ca2 | aurel32 | tcg_gen_movi_i64(addr, disp16); |
239 | 023d8ca2 | aurel32 | } |
240 | 6910b8f6 | Richard Henderson | |
241 | 6910b8f6 | Richard Henderson | va = (fp ? cpu_fir[ra] : cpu_ir[ra]); |
242 | 6910b8f6 | Richard Henderson | tcg_gen_qemu_load(va, addr, ctx->mem_idx); |
243 | 6910b8f6 | Richard Henderson | |
244 | 023d8ca2 | aurel32 | tcg_temp_free(addr); |
245 | 023d8ca2 | aurel32 | } |
246 | 023d8ca2 | aurel32 | |
247 | 636aa200 | Blue Swirl | static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags) |
248 | f18cd223 | aurel32 | { |
249 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
250 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
251 | a7812ae4 | pbrook | gen_helper_f_to_memory(tmp32, t0); |
252 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(tmp, tmp32); |
253 | f18cd223 | aurel32 | tcg_gen_qemu_st32(tmp, t1, flags); |
254 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
255 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
256 | f18cd223 | aurel32 | } |
257 | f18cd223 | aurel32 | |
258 | 636aa200 | Blue Swirl | static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags) |
259 | f18cd223 | aurel32 | { |
260 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
261 | a7812ae4 | pbrook | gen_helper_g_to_memory(tmp, t0); |
262 | f18cd223 | aurel32 | tcg_gen_qemu_st64(tmp, t1, flags); |
263 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
264 | f18cd223 | aurel32 | } |
265 | f18cd223 | aurel32 | |
266 | 636aa200 | Blue Swirl | static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags) |
267 | f18cd223 | aurel32 | { |
268 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
269 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
270 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp32, t0); |
271 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(tmp, tmp32); |
272 | f18cd223 | aurel32 | tcg_gen_qemu_st32(tmp, t1, flags); |
273 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
274 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
275 | f18cd223 | aurel32 | } |
276 | f18cd223 | aurel32 | |
277 | 636aa200 | Blue Swirl | static inline void gen_store_mem(DisasContext *ctx, |
278 | 636aa200 | Blue Swirl | void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
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279 | 636aa200 | Blue Swirl | int flags),
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280 | 636aa200 | Blue Swirl | int ra, int rb, int32_t disp16, int fp, |
281 | 6910b8f6 | Richard Henderson | int clear)
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282 | 023d8ca2 | aurel32 | { |
283 | 6910b8f6 | Richard Henderson | TCGv addr, va; |
284 | 6910b8f6 | Richard Henderson | |
285 | 6910b8f6 | Richard Henderson | addr = tcg_temp_new(); |
286 | 023d8ca2 | aurel32 | if (rb != 31) { |
287 | 023d8ca2 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
288 | 6910b8f6 | Richard Henderson | if (clear) {
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289 | 023d8ca2 | aurel32 | tcg_gen_andi_i64(addr, addr, ~0x7);
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290 | 6910b8f6 | Richard Henderson | } |
291 | 023d8ca2 | aurel32 | } else {
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292 | 6910b8f6 | Richard Henderson | if (clear) {
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293 | 023d8ca2 | aurel32 | disp16 &= ~0x7;
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294 | 6910b8f6 | Richard Henderson | } |
295 | 023d8ca2 | aurel32 | tcg_gen_movi_i64(addr, disp16); |
296 | 023d8ca2 | aurel32 | } |
297 | 6910b8f6 | Richard Henderson | |
298 | 6910b8f6 | Richard Henderson | if (ra == 31) { |
299 | 6910b8f6 | Richard Henderson | va = tcg_const_i64(0);
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300 | f18cd223 | aurel32 | } else {
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301 | 6910b8f6 | Richard Henderson | va = (fp ? cpu_fir[ra] : cpu_ir[ra]); |
302 | 023d8ca2 | aurel32 | } |
303 | 6910b8f6 | Richard Henderson | tcg_gen_qemu_store(va, addr, ctx->mem_idx); |
304 | 6910b8f6 | Richard Henderson | |
305 | 023d8ca2 | aurel32 | tcg_temp_free(addr); |
306 | 6910b8f6 | Richard Henderson | if (ra == 31) { |
307 | 6910b8f6 | Richard Henderson | tcg_temp_free(va); |
308 | 6910b8f6 | Richard Henderson | } |
309 | 6910b8f6 | Richard Henderson | } |
310 | 6910b8f6 | Richard Henderson | |
311 | 6910b8f6 | Richard Henderson | static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb, |
312 | 6910b8f6 | Richard Henderson | int32_t disp16, int quad)
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313 | 6910b8f6 | Richard Henderson | { |
314 | 6910b8f6 | Richard Henderson | TCGv addr; |
315 | 6910b8f6 | Richard Henderson | |
316 | 6910b8f6 | Richard Henderson | if (ra == 31) { |
317 | 6910b8f6 | Richard Henderson | /* ??? Don't bother storing anything. The user can't tell
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318 | 6910b8f6 | Richard Henderson | the difference, since the zero register always reads zero. */
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319 | 6910b8f6 | Richard Henderson | return NO_EXIT;
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320 | 6910b8f6 | Richard Henderson | } |
321 | 6910b8f6 | Richard Henderson | |
322 | 6910b8f6 | Richard Henderson | #if defined(CONFIG_USER_ONLY)
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323 | 6910b8f6 | Richard Henderson | addr = cpu_lock_st_addr; |
324 | 6910b8f6 | Richard Henderson | #else
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325 | e52458fe | Richard Henderson | addr = tcg_temp_local_new(); |
326 | 6910b8f6 | Richard Henderson | #endif
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327 | 6910b8f6 | Richard Henderson | |
328 | 6910b8f6 | Richard Henderson | if (rb != 31) { |
329 | 6910b8f6 | Richard Henderson | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
330 | 6910b8f6 | Richard Henderson | } else {
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331 | 6910b8f6 | Richard Henderson | tcg_gen_movi_i64(addr, disp16); |
332 | 6910b8f6 | Richard Henderson | } |
333 | 6910b8f6 | Richard Henderson | |
334 | 6910b8f6 | Richard Henderson | #if defined(CONFIG_USER_ONLY)
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335 | 6910b8f6 | Richard Henderson | /* ??? This is handled via a complicated version of compare-and-swap
|
336 | 6910b8f6 | Richard Henderson | in the cpu_loop. Hopefully one day we'll have a real CAS opcode
|
337 | 6910b8f6 | Richard Henderson | in TCG so that this isn't necessary. */
|
338 | 6910b8f6 | Richard Henderson | return gen_excp(ctx, quad ? EXCP_STQ_C : EXCP_STL_C, ra);
|
339 | 6910b8f6 | Richard Henderson | #else
|
340 | 6910b8f6 | Richard Henderson | /* ??? In system mode we are never multi-threaded, so CAS can be
|
341 | 6910b8f6 | Richard Henderson | implemented via a non-atomic load-compare-store sequence. */
|
342 | 6910b8f6 | Richard Henderson | { |
343 | 6910b8f6 | Richard Henderson | int lab_fail, lab_done;
|
344 | 6910b8f6 | Richard Henderson | TCGv val; |
345 | 6910b8f6 | Richard Henderson | |
346 | 6910b8f6 | Richard Henderson | lab_fail = gen_new_label(); |
347 | 6910b8f6 | Richard Henderson | lab_done = gen_new_label(); |
348 | e52458fe | Richard Henderson | tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_lock_addr, lab_fail); |
349 | 6910b8f6 | Richard Henderson | |
350 | 6910b8f6 | Richard Henderson | val = tcg_temp_new(); |
351 | 6910b8f6 | Richard Henderson | if (quad) {
|
352 | 6910b8f6 | Richard Henderson | tcg_gen_qemu_ld64(val, addr, ctx->mem_idx); |
353 | 6910b8f6 | Richard Henderson | } else {
|
354 | 6910b8f6 | Richard Henderson | tcg_gen_qemu_ld32s(val, addr, ctx->mem_idx); |
355 | 6910b8f6 | Richard Henderson | } |
356 | e52458fe | Richard Henderson | tcg_gen_brcond_i64(TCG_COND_NE, val, cpu_lock_value, lab_fail); |
357 | 6910b8f6 | Richard Henderson | |
358 | 6910b8f6 | Richard Henderson | if (quad) {
|
359 | 6910b8f6 | Richard Henderson | tcg_gen_qemu_st64(cpu_ir[ra], addr, ctx->mem_idx); |
360 | 6910b8f6 | Richard Henderson | } else {
|
361 | 6910b8f6 | Richard Henderson | tcg_gen_qemu_st32(cpu_ir[ra], addr, ctx->mem_idx); |
362 | 6910b8f6 | Richard Henderson | } |
363 | 6910b8f6 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[ra], 1);
|
364 | 6910b8f6 | Richard Henderson | tcg_gen_br(lab_done); |
365 | 6910b8f6 | Richard Henderson | |
366 | 6910b8f6 | Richard Henderson | gen_set_label(lab_fail); |
367 | 6910b8f6 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[ra], 0);
|
368 | 6910b8f6 | Richard Henderson | |
369 | 6910b8f6 | Richard Henderson | gen_set_label(lab_done); |
370 | 6910b8f6 | Richard Henderson | tcg_gen_movi_i64(cpu_lock_addr, -1);
|
371 | 6910b8f6 | Richard Henderson | |
372 | 6910b8f6 | Richard Henderson | tcg_temp_free(addr); |
373 | 6910b8f6 | Richard Henderson | return NO_EXIT;
|
374 | 6910b8f6 | Richard Henderson | } |
375 | 6910b8f6 | Richard Henderson | #endif
|
376 | 023d8ca2 | aurel32 | } |
377 | 023d8ca2 | aurel32 | |
378 | 4af70374 | Richard Henderson | static int use_goto_tb(DisasContext *ctx, uint64_t dest) |
379 | 4c9649a9 | j_mayer | { |
380 | 4af70374 | Richard Henderson | /* Check for the dest on the same page as the start of the TB. We
|
381 | 4af70374 | Richard Henderson | also want to suppress goto_tb in the case of single-steping and IO. */
|
382 | 4af70374 | Richard Henderson | return (((ctx->tb->pc ^ dest) & TARGET_PAGE_MASK) == 0 |
383 | 4af70374 | Richard Henderson | && !ctx->env->singlestep_enabled |
384 | 4af70374 | Richard Henderson | && !(ctx->tb->cflags & CF_LAST_IO)); |
385 | 4af70374 | Richard Henderson | } |
386 | dbb30fe6 | Richard Henderson | |
387 | 4af70374 | Richard Henderson | static ExitStatus gen_bdirect(DisasContext *ctx, int ra, int32_t disp) |
388 | 4af70374 | Richard Henderson | { |
389 | 4af70374 | Richard Henderson | uint64_t dest = ctx->pc + (disp << 2);
|
390 | 4af70374 | Richard Henderson | |
391 | 4af70374 | Richard Henderson | if (ra != 31) { |
392 | 4af70374 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
393 | 4af70374 | Richard Henderson | } |
394 | 4af70374 | Richard Henderson | |
395 | 4af70374 | Richard Henderson | /* Notice branch-to-next; used to initialize RA with the PC. */
|
396 | 4af70374 | Richard Henderson | if (disp == 0) { |
397 | 4af70374 | Richard Henderson | return 0; |
398 | 4af70374 | Richard Henderson | } else if (use_goto_tb(ctx, dest)) { |
399 | 4af70374 | Richard Henderson | tcg_gen_goto_tb(0);
|
400 | 4af70374 | Richard Henderson | tcg_gen_movi_i64(cpu_pc, dest); |
401 | 4b4a72e5 | Stefan Weil | tcg_gen_exit_tb((tcg_target_long)ctx->tb); |
402 | 4af70374 | Richard Henderson | return EXIT_GOTO_TB;
|
403 | 4af70374 | Richard Henderson | } else {
|
404 | 4af70374 | Richard Henderson | tcg_gen_movi_i64(cpu_pc, dest); |
405 | 4af70374 | Richard Henderson | return EXIT_PC_UPDATED;
|
406 | 4af70374 | Richard Henderson | } |
407 | dbb30fe6 | Richard Henderson | } |
408 | dbb30fe6 | Richard Henderson | |
409 | 4af70374 | Richard Henderson | static ExitStatus gen_bcond_internal(DisasContext *ctx, TCGCond cond,
|
410 | 4af70374 | Richard Henderson | TCGv cmp, int32_t disp) |
411 | dbb30fe6 | Richard Henderson | { |
412 | 4af70374 | Richard Henderson | uint64_t dest = ctx->pc + (disp << 2);
|
413 | dbb30fe6 | Richard Henderson | int lab_true = gen_new_label();
|
414 | 9c29504e | aurel32 | |
415 | 4af70374 | Richard Henderson | if (use_goto_tb(ctx, dest)) {
|
416 | 4af70374 | Richard Henderson | tcg_gen_brcondi_i64(cond, cmp, 0, lab_true);
|
417 | 4af70374 | Richard Henderson | |
418 | 4af70374 | Richard Henderson | tcg_gen_goto_tb(0);
|
419 | 4af70374 | Richard Henderson | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
420 | 4b4a72e5 | Stefan Weil | tcg_gen_exit_tb((tcg_target_long)ctx->tb); |
421 | 4af70374 | Richard Henderson | |
422 | 4af70374 | Richard Henderson | gen_set_label(lab_true); |
423 | 4af70374 | Richard Henderson | tcg_gen_goto_tb(1);
|
424 | 4af70374 | Richard Henderson | tcg_gen_movi_i64(cpu_pc, dest); |
425 | 4b4a72e5 | Stefan Weil | tcg_gen_exit_tb((tcg_target_long)ctx->tb + 1);
|
426 | 4af70374 | Richard Henderson | |
427 | 4af70374 | Richard Henderson | return EXIT_GOTO_TB;
|
428 | 4af70374 | Richard Henderson | } else {
|
429 | 57e289de | Richard Henderson | TCGv_i64 z = tcg_const_i64(0);
|
430 | 57e289de | Richard Henderson | TCGv_i64 d = tcg_const_i64(dest); |
431 | 57e289de | Richard Henderson | TCGv_i64 p = tcg_const_i64(ctx->pc); |
432 | 4af70374 | Richard Henderson | |
433 | 57e289de | Richard Henderson | tcg_gen_movcond_i64(cond, cpu_pc, cmp, z, d, p); |
434 | 4af70374 | Richard Henderson | |
435 | 57e289de | Richard Henderson | tcg_temp_free_i64(z); |
436 | 57e289de | Richard Henderson | tcg_temp_free_i64(d); |
437 | 57e289de | Richard Henderson | tcg_temp_free_i64(p); |
438 | 4af70374 | Richard Henderson | return EXIT_PC_UPDATED;
|
439 | 4af70374 | Richard Henderson | } |
440 | 4af70374 | Richard Henderson | } |
441 | 4af70374 | Richard Henderson | |
442 | 4af70374 | Richard Henderson | static ExitStatus gen_bcond(DisasContext *ctx, TCGCond cond, int ra, |
443 | 4af70374 | Richard Henderson | int32_t disp, int mask)
|
444 | 4af70374 | Richard Henderson | { |
445 | 4af70374 | Richard Henderson | TCGv cmp_tmp; |
446 | 4af70374 | Richard Henderson | |
447 | 4af70374 | Richard Henderson | if (unlikely(ra == 31)) { |
448 | 4af70374 | Richard Henderson | cmp_tmp = tcg_const_i64(0);
|
449 | 4af70374 | Richard Henderson | } else {
|
450 | 4af70374 | Richard Henderson | cmp_tmp = tcg_temp_new(); |
451 | 9c29504e | aurel32 | if (mask) {
|
452 | 4af70374 | Richard Henderson | tcg_gen_andi_i64(cmp_tmp, cpu_ir[ra], 1);
|
453 | dbb30fe6 | Richard Henderson | } else {
|
454 | 4af70374 | Richard Henderson | tcg_gen_mov_i64(cmp_tmp, cpu_ir[ra]); |
455 | dbb30fe6 | Richard Henderson | } |
456 | 9c29504e | aurel32 | } |
457 | 4af70374 | Richard Henderson | |
458 | 4af70374 | Richard Henderson | return gen_bcond_internal(ctx, cond, cmp_tmp, disp);
|
459 | 4c9649a9 | j_mayer | } |
460 | 4c9649a9 | j_mayer | |
461 | 4af70374 | Richard Henderson | /* Fold -0.0 for comparison with COND. */
|
462 | dbb30fe6 | Richard Henderson | |
463 | 4af70374 | Richard Henderson | static void gen_fold_mzero(TCGCond cond, TCGv dest, TCGv src) |
464 | 4c9649a9 | j_mayer | { |
465 | dbb30fe6 | Richard Henderson | uint64_t mzero = 1ull << 63; |
466 | f18cd223 | aurel32 | |
467 | dbb30fe6 | Richard Henderson | switch (cond) {
|
468 | dbb30fe6 | Richard Henderson | case TCG_COND_LE:
|
469 | dbb30fe6 | Richard Henderson | case TCG_COND_GT:
|
470 | dbb30fe6 | Richard Henderson | /* For <= or >, the -0.0 value directly compares the way we want. */
|
471 | 4af70374 | Richard Henderson | tcg_gen_mov_i64(dest, src); |
472 | a7812ae4 | pbrook | break;
|
473 | dbb30fe6 | Richard Henderson | |
474 | dbb30fe6 | Richard Henderson | case TCG_COND_EQ:
|
475 | dbb30fe6 | Richard Henderson | case TCG_COND_NE:
|
476 | dbb30fe6 | Richard Henderson | /* For == or !=, we can simply mask off the sign bit and compare. */
|
477 | 4af70374 | Richard Henderson | tcg_gen_andi_i64(dest, src, mzero - 1);
|
478 | a7812ae4 | pbrook | break;
|
479 | dbb30fe6 | Richard Henderson | |
480 | dbb30fe6 | Richard Henderson | case TCG_COND_GE:
|
481 | dbb30fe6 | Richard Henderson | case TCG_COND_LT:
|
482 | 4af70374 | Richard Henderson | /* For >= or <, map -0.0 to +0.0 via comparison and mask. */
|
483 | 4af70374 | Richard Henderson | tcg_gen_setcondi_i64(TCG_COND_NE, dest, src, mzero); |
484 | 4af70374 | Richard Henderson | tcg_gen_neg_i64(dest, dest); |
485 | 4af70374 | Richard Henderson | tcg_gen_and_i64(dest, dest, src); |
486 | a7812ae4 | pbrook | break;
|
487 | dbb30fe6 | Richard Henderson | |
488 | a7812ae4 | pbrook | default:
|
489 | a7812ae4 | pbrook | abort(); |
490 | f18cd223 | aurel32 | } |
491 | dbb30fe6 | Richard Henderson | } |
492 | dbb30fe6 | Richard Henderson | |
493 | 4af70374 | Richard Henderson | static ExitStatus gen_fbcond(DisasContext *ctx, TCGCond cond, int ra, |
494 | 4af70374 | Richard Henderson | int32_t disp) |
495 | dbb30fe6 | Richard Henderson | { |
496 | 4af70374 | Richard Henderson | TCGv cmp_tmp; |
497 | dbb30fe6 | Richard Henderson | |
498 | dbb30fe6 | Richard Henderson | if (unlikely(ra == 31)) { |
499 | dbb30fe6 | Richard Henderson | /* Very uncommon case, but easier to optimize it to an integer
|
500 | dbb30fe6 | Richard Henderson | comparison than continuing with the floating point comparison. */
|
501 | 4af70374 | Richard Henderson | return gen_bcond(ctx, cond, ra, disp, 0); |
502 | dbb30fe6 | Richard Henderson | } |
503 | dbb30fe6 | Richard Henderson | |
504 | 4af70374 | Richard Henderson | cmp_tmp = tcg_temp_new(); |
505 | 4af70374 | Richard Henderson | gen_fold_mzero(cond, cmp_tmp, cpu_fir[ra]); |
506 | 4af70374 | Richard Henderson | return gen_bcond_internal(ctx, cond, cmp_tmp, disp);
|
507 | 4c9649a9 | j_mayer | } |
508 | 4c9649a9 | j_mayer | |
509 | bbe1dab4 | Richard Henderson | static void gen_cmov(TCGCond cond, int ra, int rb, int rc, |
510 | 4af70374 | Richard Henderson | int islit, uint8_t lit, int mask) |
511 | 4c9649a9 | j_mayer | { |
512 | 57e289de | Richard Henderson | TCGv_i64 c1, z, v1; |
513 | 9c29504e | aurel32 | |
514 | 57e289de | Richard Henderson | if (unlikely(rc == 31)) { |
515 | 9c29504e | aurel32 | return;
|
516 | 57e289de | Richard Henderson | } |
517 | 9c29504e | aurel32 | |
518 | 57e289de | Richard Henderson | if (ra == 31) { |
519 | 9c29504e | aurel32 | /* Very uncommon case - Do not bother to optimize. */
|
520 | 57e289de | Richard Henderson | c1 = tcg_const_i64(0);
|
521 | 57e289de | Richard Henderson | } else if (mask) { |
522 | 57e289de | Richard Henderson | c1 = tcg_const_i64(1);
|
523 | 57e289de | Richard Henderson | tcg_gen_and_i64(c1, c1, cpu_ir[ra]); |
524 | 57e289de | Richard Henderson | } else {
|
525 | 57e289de | Richard Henderson | c1 = cpu_ir[ra]; |
526 | 57e289de | Richard Henderson | } |
527 | 57e289de | Richard Henderson | if (islit) {
|
528 | 57e289de | Richard Henderson | v1 = tcg_const_i64(lit); |
529 | 57e289de | Richard Henderson | } else {
|
530 | 57e289de | Richard Henderson | v1 = cpu_ir[rb]; |
531 | 9c29504e | aurel32 | } |
532 | 57e289de | Richard Henderson | z = tcg_const_i64(0);
|
533 | 9c29504e | aurel32 | |
534 | 57e289de | Richard Henderson | tcg_gen_movcond_i64(cond, cpu_ir[rc], c1, z, v1, cpu_ir[rc]); |
535 | 57e289de | Richard Henderson | |
536 | 57e289de | Richard Henderson | tcg_temp_free_i64(z); |
537 | 57e289de | Richard Henderson | if (ra == 31 || mask) { |
538 | 57e289de | Richard Henderson | tcg_temp_free_i64(c1); |
539 | 57e289de | Richard Henderson | } |
540 | 57e289de | Richard Henderson | if (islit) {
|
541 | 57e289de | Richard Henderson | tcg_temp_free_i64(v1); |
542 | 57e289de | Richard Henderson | } |
543 | 4c9649a9 | j_mayer | } |
544 | 4c9649a9 | j_mayer | |
545 | bbe1dab4 | Richard Henderson | static void gen_fcmov(TCGCond cond, int ra, int rb, int rc) |
546 | dbb30fe6 | Richard Henderson | { |
547 | 57e289de | Richard Henderson | TCGv_i64 c1, z, v1; |
548 | dbb30fe6 | Richard Henderson | |
549 | 4af70374 | Richard Henderson | if (unlikely(rc == 31)) { |
550 | dbb30fe6 | Richard Henderson | return;
|
551 | 4af70374 | Richard Henderson | } |
552 | 4af70374 | Richard Henderson | |
553 | 57e289de | Richard Henderson | c1 = tcg_temp_new_i64(); |
554 | dbb30fe6 | Richard Henderson | if (unlikely(ra == 31)) { |
555 | 57e289de | Richard Henderson | tcg_gen_movi_i64(c1, 0);
|
556 | 4af70374 | Richard Henderson | } else {
|
557 | 57e289de | Richard Henderson | gen_fold_mzero(cond, c1, cpu_fir[ra]); |
558 | dbb30fe6 | Richard Henderson | } |
559 | 57e289de | Richard Henderson | if (rb == 31) { |
560 | 57e289de | Richard Henderson | v1 = tcg_const_i64(0);
|
561 | 57e289de | Richard Henderson | } else {
|
562 | 57e289de | Richard Henderson | v1 = cpu_fir[rb]; |
563 | 57e289de | Richard Henderson | } |
564 | 57e289de | Richard Henderson | z = tcg_const_i64(0);
|
565 | dbb30fe6 | Richard Henderson | |
566 | 57e289de | Richard Henderson | tcg_gen_movcond_i64(cond, cpu_fir[rc], c1, z, v1, cpu_fir[rc]); |
567 | dbb30fe6 | Richard Henderson | |
568 | 57e289de | Richard Henderson | tcg_temp_free_i64(z); |
569 | 57e289de | Richard Henderson | tcg_temp_free_i64(c1); |
570 | 57e289de | Richard Henderson | if (rb == 31) { |
571 | 57e289de | Richard Henderson | tcg_temp_free_i64(v1); |
572 | 57e289de | Richard Henderson | } |
573 | dbb30fe6 | Richard Henderson | } |
574 | dbb30fe6 | Richard Henderson | |
575 | f24518b5 | Richard Henderson | #define QUAL_RM_N 0x080 /* Round mode nearest even */ |
576 | f24518b5 | Richard Henderson | #define QUAL_RM_C 0x000 /* Round mode chopped */ |
577 | f24518b5 | Richard Henderson | #define QUAL_RM_M 0x040 /* Round mode minus infinity */ |
578 | f24518b5 | Richard Henderson | #define QUAL_RM_D 0x0c0 /* Round mode dynamic */ |
579 | f24518b5 | Richard Henderson | #define QUAL_RM_MASK 0x0c0 |
580 | f24518b5 | Richard Henderson | |
581 | f24518b5 | Richard Henderson | #define QUAL_U 0x100 /* Underflow enable (fp output) */ |
582 | f24518b5 | Richard Henderson | #define QUAL_V 0x100 /* Overflow enable (int output) */ |
583 | f24518b5 | Richard Henderson | #define QUAL_S 0x400 /* Software completion enable */ |
584 | f24518b5 | Richard Henderson | #define QUAL_I 0x200 /* Inexact detection enable */ |
585 | f24518b5 | Richard Henderson | |
586 | f24518b5 | Richard Henderson | static void gen_qual_roundmode(DisasContext *ctx, int fn11) |
587 | f24518b5 | Richard Henderson | { |
588 | f24518b5 | Richard Henderson | TCGv_i32 tmp; |
589 | f24518b5 | Richard Henderson | |
590 | f24518b5 | Richard Henderson | fn11 &= QUAL_RM_MASK; |
591 | f24518b5 | Richard Henderson | if (fn11 == ctx->tb_rm) {
|
592 | f24518b5 | Richard Henderson | return;
|
593 | f24518b5 | Richard Henderson | } |
594 | f24518b5 | Richard Henderson | ctx->tb_rm = fn11; |
595 | f24518b5 | Richard Henderson | |
596 | f24518b5 | Richard Henderson | tmp = tcg_temp_new_i32(); |
597 | f24518b5 | Richard Henderson | switch (fn11) {
|
598 | f24518b5 | Richard Henderson | case QUAL_RM_N:
|
599 | f24518b5 | Richard Henderson | tcg_gen_movi_i32(tmp, float_round_nearest_even); |
600 | f24518b5 | Richard Henderson | break;
|
601 | f24518b5 | Richard Henderson | case QUAL_RM_C:
|
602 | f24518b5 | Richard Henderson | tcg_gen_movi_i32(tmp, float_round_to_zero); |
603 | f24518b5 | Richard Henderson | break;
|
604 | f24518b5 | Richard Henderson | case QUAL_RM_M:
|
605 | f24518b5 | Richard Henderson | tcg_gen_movi_i32(tmp, float_round_down); |
606 | f24518b5 | Richard Henderson | break;
|
607 | f24518b5 | Richard Henderson | case QUAL_RM_D:
|
608 | 4a58aedf | Richard Henderson | tcg_gen_ld8u_i32(tmp, cpu_env, |
609 | 4a58aedf | Richard Henderson | offsetof(CPUAlphaState, fpcr_dyn_round)); |
610 | f24518b5 | Richard Henderson | break;
|
611 | f24518b5 | Richard Henderson | } |
612 | f24518b5 | Richard Henderson | |
613 | f24518b5 | Richard Henderson | #if defined(CONFIG_SOFTFLOAT_INLINE)
|
614 | f24518b5 | Richard Henderson | /* ??? The "softfloat.h" interface is to call set_float_rounding_mode.
|
615 | f24518b5 | Richard Henderson | With CONFIG_SOFTFLOAT that expands to an out-of-line call that just
|
616 | f24518b5 | Richard Henderson | sets the one field. */
|
617 | f24518b5 | Richard Henderson | tcg_gen_st8_i32(tmp, cpu_env, |
618 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, fp_status.float_rounding_mode)); |
619 | f24518b5 | Richard Henderson | #else
|
620 | f24518b5 | Richard Henderson | gen_helper_setroundmode(tmp); |
621 | f24518b5 | Richard Henderson | #endif
|
622 | f24518b5 | Richard Henderson | |
623 | f24518b5 | Richard Henderson | tcg_temp_free_i32(tmp); |
624 | f24518b5 | Richard Henderson | } |
625 | f24518b5 | Richard Henderson | |
626 | f24518b5 | Richard Henderson | static void gen_qual_flushzero(DisasContext *ctx, int fn11) |
627 | f24518b5 | Richard Henderson | { |
628 | f24518b5 | Richard Henderson | TCGv_i32 tmp; |
629 | f24518b5 | Richard Henderson | |
630 | f24518b5 | Richard Henderson | fn11 &= QUAL_U; |
631 | f24518b5 | Richard Henderson | if (fn11 == ctx->tb_ftz) {
|
632 | f24518b5 | Richard Henderson | return;
|
633 | f24518b5 | Richard Henderson | } |
634 | f24518b5 | Richard Henderson | ctx->tb_ftz = fn11; |
635 | f24518b5 | Richard Henderson | |
636 | f24518b5 | Richard Henderson | tmp = tcg_temp_new_i32(); |
637 | f24518b5 | Richard Henderson | if (fn11) {
|
638 | f24518b5 | Richard Henderson | /* Underflow is enabled, use the FPCR setting. */
|
639 | 4a58aedf | Richard Henderson | tcg_gen_ld8u_i32(tmp, cpu_env, |
640 | 4a58aedf | Richard Henderson | offsetof(CPUAlphaState, fpcr_flush_to_zero)); |
641 | f24518b5 | Richard Henderson | } else {
|
642 | f24518b5 | Richard Henderson | /* Underflow is disabled, force flush-to-zero. */
|
643 | f24518b5 | Richard Henderson | tcg_gen_movi_i32(tmp, 1);
|
644 | f24518b5 | Richard Henderson | } |
645 | f24518b5 | Richard Henderson | |
646 | f24518b5 | Richard Henderson | #if defined(CONFIG_SOFTFLOAT_INLINE)
|
647 | f24518b5 | Richard Henderson | tcg_gen_st8_i32(tmp, cpu_env, |
648 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, fp_status.flush_to_zero)); |
649 | f24518b5 | Richard Henderson | #else
|
650 | f24518b5 | Richard Henderson | gen_helper_setflushzero(tmp); |
651 | f24518b5 | Richard Henderson | #endif
|
652 | f24518b5 | Richard Henderson | |
653 | f24518b5 | Richard Henderson | tcg_temp_free_i32(tmp); |
654 | f24518b5 | Richard Henderson | } |
655 | f24518b5 | Richard Henderson | |
656 | f24518b5 | Richard Henderson | static TCGv gen_ieee_input(int reg, int fn11, int is_cmp) |
657 | f24518b5 | Richard Henderson | { |
658 | 74343409 | Richard Henderson | TCGv val; |
659 | f24518b5 | Richard Henderson | if (reg == 31) { |
660 | 74343409 | Richard Henderson | val = tcg_const_i64(0);
|
661 | f24518b5 | Richard Henderson | } else {
|
662 | 74343409 | Richard Henderson | if ((fn11 & QUAL_S) == 0) { |
663 | 74343409 | Richard Henderson | if (is_cmp) {
|
664 | 74343409 | Richard Henderson | gen_helper_ieee_input_cmp(cpu_env, cpu_fir[reg]); |
665 | 74343409 | Richard Henderson | } else {
|
666 | 74343409 | Richard Henderson | gen_helper_ieee_input(cpu_env, cpu_fir[reg]); |
667 | 74343409 | Richard Henderson | } |
668 | 74343409 | Richard Henderson | } |
669 | 74343409 | Richard Henderson | val = tcg_temp_new(); |
670 | 74343409 | Richard Henderson | tcg_gen_mov_i64(val, cpu_fir[reg]); |
671 | f24518b5 | Richard Henderson | } |
672 | f24518b5 | Richard Henderson | return val;
|
673 | f24518b5 | Richard Henderson | } |
674 | f24518b5 | Richard Henderson | |
675 | f24518b5 | Richard Henderson | static void gen_fp_exc_clear(void) |
676 | f24518b5 | Richard Henderson | { |
677 | f24518b5 | Richard Henderson | #if defined(CONFIG_SOFTFLOAT_INLINE)
|
678 | f24518b5 | Richard Henderson | TCGv_i32 zero = tcg_const_i32(0);
|
679 | f24518b5 | Richard Henderson | tcg_gen_st8_i32(zero, cpu_env, |
680 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, fp_status.float_exception_flags)); |
681 | f24518b5 | Richard Henderson | tcg_temp_free_i32(zero); |
682 | f24518b5 | Richard Henderson | #else
|
683 | 4a58aedf | Richard Henderson | gen_helper_fp_exc_clear(cpu_env); |
684 | f24518b5 | Richard Henderson | #endif
|
685 | f24518b5 | Richard Henderson | } |
686 | f24518b5 | Richard Henderson | |
687 | f24518b5 | Richard Henderson | static void gen_fp_exc_raise_ignore(int rc, int fn11, int ignore) |
688 | f24518b5 | Richard Henderson | { |
689 | f24518b5 | Richard Henderson | /* ??? We ought to be able to do something with imprecise exceptions.
|
690 | f24518b5 | Richard Henderson | E.g. notice we're still in the trap shadow of something within the
|
691 | f24518b5 | Richard Henderson | TB and do not generate the code to signal the exception; end the TB
|
692 | f24518b5 | Richard Henderson | when an exception is forced to arrive, either by consumption of a
|
693 | f24518b5 | Richard Henderson | register value or TRAPB or EXCB. */
|
694 | f24518b5 | Richard Henderson | TCGv_i32 exc = tcg_temp_new_i32(); |
695 | f24518b5 | Richard Henderson | TCGv_i32 reg; |
696 | f24518b5 | Richard Henderson | |
697 | f24518b5 | Richard Henderson | #if defined(CONFIG_SOFTFLOAT_INLINE)
|
698 | f24518b5 | Richard Henderson | tcg_gen_ld8u_i32(exc, cpu_env, |
699 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, fp_status.float_exception_flags)); |
700 | f24518b5 | Richard Henderson | #else
|
701 | 4a58aedf | Richard Henderson | gen_helper_fp_exc_get(exc, cpu_env); |
702 | f24518b5 | Richard Henderson | #endif
|
703 | f24518b5 | Richard Henderson | |
704 | f24518b5 | Richard Henderson | if (ignore) {
|
705 | f24518b5 | Richard Henderson | tcg_gen_andi_i32(exc, exc, ~ignore); |
706 | f24518b5 | Richard Henderson | } |
707 | f24518b5 | Richard Henderson | |
708 | f24518b5 | Richard Henderson | /* ??? Pass in the regno of the destination so that the helper can
|
709 | f24518b5 | Richard Henderson | set EXC_MASK, which contains a bitmask of destination registers
|
710 | f24518b5 | Richard Henderson | that have caused arithmetic traps. A simple userspace emulation
|
711 | f24518b5 | Richard Henderson | does not require this. We do need it for a guest kernel's entArith,
|
712 | f24518b5 | Richard Henderson | or if we were to do something clever with imprecise exceptions. */
|
713 | f24518b5 | Richard Henderson | reg = tcg_const_i32(rc + 32);
|
714 | f24518b5 | Richard Henderson | |
715 | f24518b5 | Richard Henderson | if (fn11 & QUAL_S) {
|
716 | 4a58aedf | Richard Henderson | gen_helper_fp_exc_raise_s(cpu_env, exc, reg); |
717 | f24518b5 | Richard Henderson | } else {
|
718 | 4a58aedf | Richard Henderson | gen_helper_fp_exc_raise(cpu_env, exc, reg); |
719 | f24518b5 | Richard Henderson | } |
720 | f24518b5 | Richard Henderson | |
721 | f24518b5 | Richard Henderson | tcg_temp_free_i32(reg); |
722 | f24518b5 | Richard Henderson | tcg_temp_free_i32(exc); |
723 | f24518b5 | Richard Henderson | } |
724 | f24518b5 | Richard Henderson | |
725 | f24518b5 | Richard Henderson | static inline void gen_fp_exc_raise(int rc, int fn11) |
726 | f24518b5 | Richard Henderson | { |
727 | f24518b5 | Richard Henderson | gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact);
|
728 | 4c9649a9 | j_mayer | } |
729 | f24518b5 | Richard Henderson | |
730 | 593f17e5 | Richard Henderson | static void gen_fcvtlq(int rb, int rc) |
731 | 593f17e5 | Richard Henderson | { |
732 | 593f17e5 | Richard Henderson | if (unlikely(rc == 31)) { |
733 | 593f17e5 | Richard Henderson | return;
|
734 | 593f17e5 | Richard Henderson | } |
735 | 593f17e5 | Richard Henderson | if (unlikely(rb == 31)) { |
736 | 593f17e5 | Richard Henderson | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
737 | 593f17e5 | Richard Henderson | } else {
|
738 | 593f17e5 | Richard Henderson | TCGv tmp = tcg_temp_new(); |
739 | 593f17e5 | Richard Henderson | |
740 | 593f17e5 | Richard Henderson | /* The arithmetic right shift here, plus the sign-extended mask below
|
741 | 593f17e5 | Richard Henderson | yields a sign-extended result without an explicit ext32s_i64. */
|
742 | 593f17e5 | Richard Henderson | tcg_gen_sari_i64(tmp, cpu_fir[rb], 32);
|
743 | 593f17e5 | Richard Henderson | tcg_gen_shri_i64(cpu_fir[rc], cpu_fir[rb], 29);
|
744 | 593f17e5 | Richard Henderson | tcg_gen_andi_i64(tmp, tmp, (int32_t)0xc0000000);
|
745 | 593f17e5 | Richard Henderson | tcg_gen_andi_i64(cpu_fir[rc], cpu_fir[rc], 0x3fffffff);
|
746 | 593f17e5 | Richard Henderson | tcg_gen_or_i64(cpu_fir[rc], cpu_fir[rc], tmp); |
747 | 593f17e5 | Richard Henderson | |
748 | 593f17e5 | Richard Henderson | tcg_temp_free(tmp); |
749 | 593f17e5 | Richard Henderson | } |
750 | 593f17e5 | Richard Henderson | } |
751 | 593f17e5 | Richard Henderson | |
752 | 735cf45f | Richard Henderson | static void gen_fcvtql(int rb, int rc) |
753 | 735cf45f | Richard Henderson | { |
754 | 735cf45f | Richard Henderson | if (unlikely(rc == 31)) { |
755 | 735cf45f | Richard Henderson | return;
|
756 | 735cf45f | Richard Henderson | } |
757 | 735cf45f | Richard Henderson | if (unlikely(rb == 31)) { |
758 | 735cf45f | Richard Henderson | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
759 | 735cf45f | Richard Henderson | } else {
|
760 | 735cf45f | Richard Henderson | TCGv tmp = tcg_temp_new(); |
761 | 735cf45f | Richard Henderson | |
762 | 735cf45f | Richard Henderson | tcg_gen_andi_i64(tmp, cpu_fir[rb], 0xC0000000);
|
763 | 735cf45f | Richard Henderson | tcg_gen_andi_i64(cpu_fir[rc], cpu_fir[rb], 0x3FFFFFFF);
|
764 | 735cf45f | Richard Henderson | tcg_gen_shli_i64(tmp, tmp, 32);
|
765 | 735cf45f | Richard Henderson | tcg_gen_shli_i64(cpu_fir[rc], cpu_fir[rc], 29);
|
766 | 735cf45f | Richard Henderson | tcg_gen_or_i64(cpu_fir[rc], cpu_fir[rc], tmp); |
767 | 735cf45f | Richard Henderson | |
768 | 735cf45f | Richard Henderson | tcg_temp_free(tmp); |
769 | 735cf45f | Richard Henderson | } |
770 | 735cf45f | Richard Henderson | } |
771 | 735cf45f | Richard Henderson | |
772 | 735cf45f | Richard Henderson | static void gen_fcvtql_v(DisasContext *ctx, int rb, int rc) |
773 | 735cf45f | Richard Henderson | { |
774 | 735cf45f | Richard Henderson | if (rb != 31) { |
775 | 735cf45f | Richard Henderson | int lab = gen_new_label();
|
776 | 735cf45f | Richard Henderson | TCGv tmp = tcg_temp_new(); |
777 | 735cf45f | Richard Henderson | |
778 | 735cf45f | Richard Henderson | tcg_gen_ext32s_i64(tmp, cpu_fir[rb]); |
779 | 735cf45f | Richard Henderson | tcg_gen_brcond_i64(TCG_COND_EQ, tmp, cpu_fir[rb], lab); |
780 | 735cf45f | Richard Henderson | gen_excp(ctx, EXCP_ARITH, EXC_M_IOV); |
781 | 735cf45f | Richard Henderson | |
782 | 735cf45f | Richard Henderson | gen_set_label(lab); |
783 | 735cf45f | Richard Henderson | } |
784 | 735cf45f | Richard Henderson | gen_fcvtql(rb, rc); |
785 | 735cf45f | Richard Henderson | } |
786 | 735cf45f | Richard Henderson | |
787 | 4a58aedf | Richard Henderson | #define FARITH2(name) \
|
788 | 4a58aedf | Richard Henderson | static inline void glue(gen_f, name)(int rb, int rc) \ |
789 | 4a58aedf | Richard Henderson | { \ |
790 | 4a58aedf | Richard Henderson | if (unlikely(rc == 31)) { \ |
791 | 4a58aedf | Richard Henderson | return; \
|
792 | 4a58aedf | Richard Henderson | } \ |
793 | 4a58aedf | Richard Henderson | if (rb != 31) { \ |
794 | 4a58aedf | Richard Henderson | gen_helper_ ## name(cpu_fir[rc], cpu_env, cpu_fir[rb]); \ |
795 | 4a58aedf | Richard Henderson | } else { \
|
796 | 4a58aedf | Richard Henderson | TCGv tmp = tcg_const_i64(0); \
|
797 | 4a58aedf | Richard Henderson | gen_helper_ ## name(cpu_fir[rc], cpu_env, tmp); \ |
798 | 4a58aedf | Richard Henderson | tcg_temp_free(tmp); \ |
799 | 4a58aedf | Richard Henderson | } \ |
800 | 4a58aedf | Richard Henderson | } |
801 | f24518b5 | Richard Henderson | |
802 | f24518b5 | Richard Henderson | /* ??? VAX instruction qualifiers ignored. */
|
803 | a7812ae4 | pbrook | FARITH2(sqrtf) |
804 | a7812ae4 | pbrook | FARITH2(sqrtg) |
805 | a7812ae4 | pbrook | FARITH2(cvtgf) |
806 | a7812ae4 | pbrook | FARITH2(cvtgq) |
807 | a7812ae4 | pbrook | FARITH2(cvtqf) |
808 | a7812ae4 | pbrook | FARITH2(cvtqg) |
809 | f24518b5 | Richard Henderson | |
810 | 4a58aedf | Richard Henderson | static void gen_ieee_arith2(DisasContext *ctx, |
811 | 4a58aedf | Richard Henderson | void (*helper)(TCGv, TCGv_ptr, TCGv),
|
812 | f24518b5 | Richard Henderson | int rb, int rc, int fn11) |
813 | f24518b5 | Richard Henderson | { |
814 | f24518b5 | Richard Henderson | TCGv vb; |
815 | f24518b5 | Richard Henderson | |
816 | f24518b5 | Richard Henderson | /* ??? This is wrong: the instruction is not a nop, it still may
|
817 | f24518b5 | Richard Henderson | raise exceptions. */
|
818 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { |
819 | f24518b5 | Richard Henderson | return;
|
820 | f24518b5 | Richard Henderson | } |
821 | f24518b5 | Richard Henderson | |
822 | f24518b5 | Richard Henderson | gen_qual_roundmode(ctx, fn11); |
823 | f24518b5 | Richard Henderson | gen_qual_flushzero(ctx, fn11); |
824 | f24518b5 | Richard Henderson | gen_fp_exc_clear(); |
825 | f24518b5 | Richard Henderson | |
826 | f24518b5 | Richard Henderson | vb = gen_ieee_input(rb, fn11, 0);
|
827 | 4a58aedf | Richard Henderson | helper(cpu_fir[rc], cpu_env, vb); |
828 | f24518b5 | Richard Henderson | tcg_temp_free(vb); |
829 | f24518b5 | Richard Henderson | |
830 | f24518b5 | Richard Henderson | gen_fp_exc_raise(rc, fn11); |
831 | f24518b5 | Richard Henderson | } |
832 | f24518b5 | Richard Henderson | |
833 | f24518b5 | Richard Henderson | #define IEEE_ARITH2(name) \
|
834 | f24518b5 | Richard Henderson | static inline void glue(gen_f, name)(DisasContext *ctx, \ |
835 | f24518b5 | Richard Henderson | int rb, int rc, int fn11) \ |
836 | f24518b5 | Richard Henderson | { \ |
837 | f24518b5 | Richard Henderson | gen_ieee_arith2(ctx, gen_helper_##name, rb, rc, fn11); \ |
838 | f24518b5 | Richard Henderson | } |
839 | f24518b5 | Richard Henderson | IEEE_ARITH2(sqrts) |
840 | f24518b5 | Richard Henderson | IEEE_ARITH2(sqrtt) |
841 | f24518b5 | Richard Henderson | IEEE_ARITH2(cvtst) |
842 | f24518b5 | Richard Henderson | IEEE_ARITH2(cvtts) |
843 | f24518b5 | Richard Henderson | |
844 | f24518b5 | Richard Henderson | static void gen_fcvttq(DisasContext *ctx, int rb, int rc, int fn11) |
845 | f24518b5 | Richard Henderson | { |
846 | f24518b5 | Richard Henderson | TCGv vb; |
847 | f24518b5 | Richard Henderson | int ignore = 0; |
848 | f24518b5 | Richard Henderson | |
849 | f24518b5 | Richard Henderson | /* ??? This is wrong: the instruction is not a nop, it still may
|
850 | f24518b5 | Richard Henderson | raise exceptions. */
|
851 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { |
852 | f24518b5 | Richard Henderson | return;
|
853 | f24518b5 | Richard Henderson | } |
854 | f24518b5 | Richard Henderson | |
855 | f24518b5 | Richard Henderson | /* No need to set flushzero, since we have an integer output. */
|
856 | f24518b5 | Richard Henderson | gen_fp_exc_clear(); |
857 | f24518b5 | Richard Henderson | vb = gen_ieee_input(rb, fn11, 0);
|
858 | f24518b5 | Richard Henderson | |
859 | f24518b5 | Richard Henderson | /* Almost all integer conversions use cropped rounding, and most
|
860 | f24518b5 | Richard Henderson | also do not have integer overflow enabled. Special case that. */
|
861 | f24518b5 | Richard Henderson | switch (fn11) {
|
862 | f24518b5 | Richard Henderson | case QUAL_RM_C:
|
863 | 4a58aedf | Richard Henderson | gen_helper_cvttq_c(cpu_fir[rc], cpu_env, vb); |
864 | f24518b5 | Richard Henderson | break;
|
865 | f24518b5 | Richard Henderson | case QUAL_V | QUAL_RM_C:
|
866 | f24518b5 | Richard Henderson | case QUAL_S | QUAL_V | QUAL_RM_C:
|
867 | f24518b5 | Richard Henderson | ignore = float_flag_inexact; |
868 | f24518b5 | Richard Henderson | /* FALLTHRU */
|
869 | f24518b5 | Richard Henderson | case QUAL_S | QUAL_V | QUAL_I | QUAL_RM_C:
|
870 | 4a58aedf | Richard Henderson | gen_helper_cvttq_svic(cpu_fir[rc], cpu_env, vb); |
871 | f24518b5 | Richard Henderson | break;
|
872 | f24518b5 | Richard Henderson | default:
|
873 | f24518b5 | Richard Henderson | gen_qual_roundmode(ctx, fn11); |
874 | 4a58aedf | Richard Henderson | gen_helper_cvttq(cpu_fir[rc], cpu_env, vb); |
875 | f24518b5 | Richard Henderson | ignore |= (fn11 & QUAL_V ? 0 : float_flag_overflow);
|
876 | f24518b5 | Richard Henderson | ignore |= (fn11 & QUAL_I ? 0 : float_flag_inexact);
|
877 | f24518b5 | Richard Henderson | break;
|
878 | f24518b5 | Richard Henderson | } |
879 | f24518b5 | Richard Henderson | tcg_temp_free(vb); |
880 | f24518b5 | Richard Henderson | |
881 | f24518b5 | Richard Henderson | gen_fp_exc_raise_ignore(rc, fn11, ignore); |
882 | 4c9649a9 | j_mayer | } |
883 | 4c9649a9 | j_mayer | |
884 | 4a58aedf | Richard Henderson | static void gen_ieee_intcvt(DisasContext *ctx, |
885 | 4a58aedf | Richard Henderson | void (*helper)(TCGv, TCGv_ptr, TCGv),
|
886 | f24518b5 | Richard Henderson | int rb, int rc, int fn11) |
887 | f24518b5 | Richard Henderson | { |
888 | f24518b5 | Richard Henderson | TCGv vb; |
889 | f24518b5 | Richard Henderson | |
890 | f24518b5 | Richard Henderson | /* ??? This is wrong: the instruction is not a nop, it still may
|
891 | f24518b5 | Richard Henderson | raise exceptions. */
|
892 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { |
893 | f24518b5 | Richard Henderson | return;
|
894 | f24518b5 | Richard Henderson | } |
895 | f24518b5 | Richard Henderson | |
896 | f24518b5 | Richard Henderson | gen_qual_roundmode(ctx, fn11); |
897 | f24518b5 | Richard Henderson | |
898 | f24518b5 | Richard Henderson | if (rb == 31) { |
899 | f24518b5 | Richard Henderson | vb = tcg_const_i64(0);
|
900 | f24518b5 | Richard Henderson | } else {
|
901 | f24518b5 | Richard Henderson | vb = cpu_fir[rb]; |
902 | f24518b5 | Richard Henderson | } |
903 | f24518b5 | Richard Henderson | |
904 | f24518b5 | Richard Henderson | /* The only exception that can be raised by integer conversion
|
905 | f24518b5 | Richard Henderson | is inexact. Thus we only need to worry about exceptions when
|
906 | f24518b5 | Richard Henderson | inexact handling is requested. */
|
907 | f24518b5 | Richard Henderson | if (fn11 & QUAL_I) {
|
908 | f24518b5 | Richard Henderson | gen_fp_exc_clear(); |
909 | 4a58aedf | Richard Henderson | helper(cpu_fir[rc], cpu_env, vb); |
910 | f24518b5 | Richard Henderson | gen_fp_exc_raise(rc, fn11); |
911 | f24518b5 | Richard Henderson | } else {
|
912 | 4a58aedf | Richard Henderson | helper(cpu_fir[rc], cpu_env, vb); |
913 | f24518b5 | Richard Henderson | } |
914 | f24518b5 | Richard Henderson | |
915 | f24518b5 | Richard Henderson | if (rb == 31) { |
916 | f24518b5 | Richard Henderson | tcg_temp_free(vb); |
917 | f24518b5 | Richard Henderson | } |
918 | f24518b5 | Richard Henderson | } |
919 | f24518b5 | Richard Henderson | |
920 | f24518b5 | Richard Henderson | #define IEEE_INTCVT(name) \
|
921 | f24518b5 | Richard Henderson | static inline void glue(gen_f, name)(DisasContext *ctx, \ |
922 | f24518b5 | Richard Henderson | int rb, int rc, int fn11) \ |
923 | f24518b5 | Richard Henderson | { \ |
924 | f24518b5 | Richard Henderson | gen_ieee_intcvt(ctx, gen_helper_##name, rb, rc, fn11); \ |
925 | f24518b5 | Richard Henderson | } |
926 | f24518b5 | Richard Henderson | IEEE_INTCVT(cvtqs) |
927 | f24518b5 | Richard Henderson | IEEE_INTCVT(cvtqt) |
928 | f24518b5 | Richard Henderson | |
929 | dc96be4b | Richard Henderson | static void gen_cpys_internal(int ra, int rb, int rc, int inv_a, uint64_t mask) |
930 | dc96be4b | Richard Henderson | { |
931 | dc96be4b | Richard Henderson | TCGv va, vb, vmask; |
932 | dc96be4b | Richard Henderson | int za = 0, zb = 0; |
933 | dc96be4b | Richard Henderson | |
934 | dc96be4b | Richard Henderson | if (unlikely(rc == 31)) { |
935 | dc96be4b | Richard Henderson | return;
|
936 | dc96be4b | Richard Henderson | } |
937 | dc96be4b | Richard Henderson | |
938 | dc96be4b | Richard Henderson | vmask = tcg_const_i64(mask); |
939 | dc96be4b | Richard Henderson | |
940 | dc96be4b | Richard Henderson | TCGV_UNUSED_I64(va); |
941 | dc96be4b | Richard Henderson | if (ra == 31) { |
942 | dc96be4b | Richard Henderson | if (inv_a) {
|
943 | dc96be4b | Richard Henderson | va = vmask; |
944 | dc96be4b | Richard Henderson | } else {
|
945 | dc96be4b | Richard Henderson | za = 1;
|
946 | dc96be4b | Richard Henderson | } |
947 | dc96be4b | Richard Henderson | } else {
|
948 | dc96be4b | Richard Henderson | va = tcg_temp_new_i64(); |
949 | dc96be4b | Richard Henderson | tcg_gen_mov_i64(va, cpu_fir[ra]); |
950 | dc96be4b | Richard Henderson | if (inv_a) {
|
951 | dc96be4b | Richard Henderson | tcg_gen_andc_i64(va, vmask, va); |
952 | dc96be4b | Richard Henderson | } else {
|
953 | dc96be4b | Richard Henderson | tcg_gen_and_i64(va, va, vmask); |
954 | dc96be4b | Richard Henderson | } |
955 | dc96be4b | Richard Henderson | } |
956 | dc96be4b | Richard Henderson | |
957 | dc96be4b | Richard Henderson | TCGV_UNUSED_I64(vb); |
958 | dc96be4b | Richard Henderson | if (rb == 31) { |
959 | dc96be4b | Richard Henderson | zb = 1;
|
960 | dc96be4b | Richard Henderson | } else {
|
961 | dc96be4b | Richard Henderson | vb = tcg_temp_new_i64(); |
962 | dc96be4b | Richard Henderson | tcg_gen_andc_i64(vb, cpu_fir[rb], vmask); |
963 | dc96be4b | Richard Henderson | } |
964 | dc96be4b | Richard Henderson | |
965 | dc96be4b | Richard Henderson | switch (za << 1 | zb) { |
966 | dc96be4b | Richard Henderson | case 0 | 0: |
967 | dc96be4b | Richard Henderson | tcg_gen_or_i64(cpu_fir[rc], va, vb); |
968 | dc96be4b | Richard Henderson | break;
|
969 | dc96be4b | Richard Henderson | case 0 | 1: |
970 | dc96be4b | Richard Henderson | tcg_gen_mov_i64(cpu_fir[rc], va); |
971 | dc96be4b | Richard Henderson | break;
|
972 | dc96be4b | Richard Henderson | case 2 | 0: |
973 | dc96be4b | Richard Henderson | tcg_gen_mov_i64(cpu_fir[rc], vb); |
974 | dc96be4b | Richard Henderson | break;
|
975 | dc96be4b | Richard Henderson | case 2 | 1: |
976 | dc96be4b | Richard Henderson | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
977 | dc96be4b | Richard Henderson | break;
|
978 | dc96be4b | Richard Henderson | } |
979 | dc96be4b | Richard Henderson | |
980 | dc96be4b | Richard Henderson | tcg_temp_free(vmask); |
981 | dc96be4b | Richard Henderson | if (ra != 31) { |
982 | dc96be4b | Richard Henderson | tcg_temp_free(va); |
983 | dc96be4b | Richard Henderson | } |
984 | dc96be4b | Richard Henderson | if (rb != 31) { |
985 | dc96be4b | Richard Henderson | tcg_temp_free(vb); |
986 | dc96be4b | Richard Henderson | } |
987 | dc96be4b | Richard Henderson | } |
988 | dc96be4b | Richard Henderson | |
989 | dc96be4b | Richard Henderson | static inline void gen_fcpys(int ra, int rb, int rc) |
990 | dc96be4b | Richard Henderson | { |
991 | dc96be4b | Richard Henderson | gen_cpys_internal(ra, rb, rc, 0, 0x8000000000000000ULL); |
992 | dc96be4b | Richard Henderson | } |
993 | dc96be4b | Richard Henderson | |
994 | dc96be4b | Richard Henderson | static inline void gen_fcpysn(int ra, int rb, int rc) |
995 | dc96be4b | Richard Henderson | { |
996 | dc96be4b | Richard Henderson | gen_cpys_internal(ra, rb, rc, 1, 0x8000000000000000ULL); |
997 | dc96be4b | Richard Henderson | } |
998 | dc96be4b | Richard Henderson | |
999 | dc96be4b | Richard Henderson | static inline void gen_fcpyse(int ra, int rb, int rc) |
1000 | dc96be4b | Richard Henderson | { |
1001 | dc96be4b | Richard Henderson | gen_cpys_internal(ra, rb, rc, 0, 0xFFF0000000000000ULL); |
1002 | dc96be4b | Richard Henderson | } |
1003 | dc96be4b | Richard Henderson | |
1004 | 4a58aedf | Richard Henderson | #define FARITH3(name) \
|
1005 | 4a58aedf | Richard Henderson | static inline void glue(gen_f, name)(int ra, int rb, int rc) \ |
1006 | 4a58aedf | Richard Henderson | { \ |
1007 | 4a58aedf | Richard Henderson | TCGv va, vb; \ |
1008 | 4a58aedf | Richard Henderson | \ |
1009 | 4a58aedf | Richard Henderson | if (unlikely(rc == 31)) { \ |
1010 | 4a58aedf | Richard Henderson | return; \
|
1011 | 4a58aedf | Richard Henderson | } \ |
1012 | 4a58aedf | Richard Henderson | if (ra == 31) { \ |
1013 | 4a58aedf | Richard Henderson | va = tcg_const_i64(0); \
|
1014 | 4a58aedf | Richard Henderson | } else { \
|
1015 | 4a58aedf | Richard Henderson | va = cpu_fir[ra]; \ |
1016 | 4a58aedf | Richard Henderson | } \ |
1017 | 4a58aedf | Richard Henderson | if (rb == 31) { \ |
1018 | 4a58aedf | Richard Henderson | vb = tcg_const_i64(0); \
|
1019 | 4a58aedf | Richard Henderson | } else { \
|
1020 | 4a58aedf | Richard Henderson | vb = cpu_fir[rb]; \ |
1021 | 4a58aedf | Richard Henderson | } \ |
1022 | 4a58aedf | Richard Henderson | \ |
1023 | 4a58aedf | Richard Henderson | gen_helper_ ## name(cpu_fir[rc], cpu_env, va, vb); \ |
1024 | 4a58aedf | Richard Henderson | \ |
1025 | 4a58aedf | Richard Henderson | if (ra == 31) { \ |
1026 | 4a58aedf | Richard Henderson | tcg_temp_free(va); \ |
1027 | 4a58aedf | Richard Henderson | } \ |
1028 | 4a58aedf | Richard Henderson | if (rb == 31) { \ |
1029 | 4a58aedf | Richard Henderson | tcg_temp_free(vb); \ |
1030 | 4a58aedf | Richard Henderson | } \ |
1031 | 4a58aedf | Richard Henderson | } |
1032 | f24518b5 | Richard Henderson | |
1033 | f24518b5 | Richard Henderson | /* ??? VAX instruction qualifiers ignored. */
|
1034 | a7812ae4 | pbrook | FARITH3(addf) |
1035 | a7812ae4 | pbrook | FARITH3(subf) |
1036 | a7812ae4 | pbrook | FARITH3(mulf) |
1037 | a7812ae4 | pbrook | FARITH3(divf) |
1038 | a7812ae4 | pbrook | FARITH3(addg) |
1039 | a7812ae4 | pbrook | FARITH3(subg) |
1040 | a7812ae4 | pbrook | FARITH3(mulg) |
1041 | a7812ae4 | pbrook | FARITH3(divg) |
1042 | a7812ae4 | pbrook | FARITH3(cmpgeq) |
1043 | a7812ae4 | pbrook | FARITH3(cmpglt) |
1044 | a7812ae4 | pbrook | FARITH3(cmpgle) |
1045 | f24518b5 | Richard Henderson | |
1046 | f24518b5 | Richard Henderson | static void gen_ieee_arith3(DisasContext *ctx, |
1047 | 4a58aedf | Richard Henderson | void (*helper)(TCGv, TCGv_ptr, TCGv, TCGv),
|
1048 | f24518b5 | Richard Henderson | int ra, int rb, int rc, int fn11) |
1049 | f24518b5 | Richard Henderson | { |
1050 | f24518b5 | Richard Henderson | TCGv va, vb; |
1051 | f24518b5 | Richard Henderson | |
1052 | f24518b5 | Richard Henderson | /* ??? This is wrong: the instruction is not a nop, it still may
|
1053 | f24518b5 | Richard Henderson | raise exceptions. */
|
1054 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { |
1055 | f24518b5 | Richard Henderson | return;
|
1056 | f24518b5 | Richard Henderson | } |
1057 | f24518b5 | Richard Henderson | |
1058 | f24518b5 | Richard Henderson | gen_qual_roundmode(ctx, fn11); |
1059 | f24518b5 | Richard Henderson | gen_qual_flushzero(ctx, fn11); |
1060 | f24518b5 | Richard Henderson | gen_fp_exc_clear(); |
1061 | f24518b5 | Richard Henderson | |
1062 | f24518b5 | Richard Henderson | va = gen_ieee_input(ra, fn11, 0);
|
1063 | f24518b5 | Richard Henderson | vb = gen_ieee_input(rb, fn11, 0);
|
1064 | 4a58aedf | Richard Henderson | helper(cpu_fir[rc], cpu_env, va, vb); |
1065 | f24518b5 | Richard Henderson | tcg_temp_free(va); |
1066 | f24518b5 | Richard Henderson | tcg_temp_free(vb); |
1067 | f24518b5 | Richard Henderson | |
1068 | f24518b5 | Richard Henderson | gen_fp_exc_raise(rc, fn11); |
1069 | f24518b5 | Richard Henderson | } |
1070 | f24518b5 | Richard Henderson | |
1071 | f24518b5 | Richard Henderson | #define IEEE_ARITH3(name) \
|
1072 | f24518b5 | Richard Henderson | static inline void glue(gen_f, name)(DisasContext *ctx, \ |
1073 | f24518b5 | Richard Henderson | int ra, int rb, int rc, int fn11) \ |
1074 | f24518b5 | Richard Henderson | { \ |
1075 | f24518b5 | Richard Henderson | gen_ieee_arith3(ctx, gen_helper_##name, ra, rb, rc, fn11); \ |
1076 | f24518b5 | Richard Henderson | } |
1077 | f24518b5 | Richard Henderson | IEEE_ARITH3(adds) |
1078 | f24518b5 | Richard Henderson | IEEE_ARITH3(subs) |
1079 | f24518b5 | Richard Henderson | IEEE_ARITH3(muls) |
1080 | f24518b5 | Richard Henderson | IEEE_ARITH3(divs) |
1081 | f24518b5 | Richard Henderson | IEEE_ARITH3(addt) |
1082 | f24518b5 | Richard Henderson | IEEE_ARITH3(subt) |
1083 | f24518b5 | Richard Henderson | IEEE_ARITH3(mult) |
1084 | f24518b5 | Richard Henderson | IEEE_ARITH3(divt) |
1085 | f24518b5 | Richard Henderson | |
1086 | f24518b5 | Richard Henderson | static void gen_ieee_compare(DisasContext *ctx, |
1087 | 4a58aedf | Richard Henderson | void (*helper)(TCGv, TCGv_ptr, TCGv, TCGv),
|
1088 | f24518b5 | Richard Henderson | int ra, int rb, int rc, int fn11) |
1089 | f24518b5 | Richard Henderson | { |
1090 | f24518b5 | Richard Henderson | TCGv va, vb; |
1091 | f24518b5 | Richard Henderson | |
1092 | f24518b5 | Richard Henderson | /* ??? This is wrong: the instruction is not a nop, it still may
|
1093 | f24518b5 | Richard Henderson | raise exceptions. */
|
1094 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { |
1095 | f24518b5 | Richard Henderson | return;
|
1096 | f24518b5 | Richard Henderson | } |
1097 | f24518b5 | Richard Henderson | |
1098 | f24518b5 | Richard Henderson | gen_fp_exc_clear(); |
1099 | f24518b5 | Richard Henderson | |
1100 | f24518b5 | Richard Henderson | va = gen_ieee_input(ra, fn11, 1);
|
1101 | f24518b5 | Richard Henderson | vb = gen_ieee_input(rb, fn11, 1);
|
1102 | 4a58aedf | Richard Henderson | helper(cpu_fir[rc], cpu_env, va, vb); |
1103 | f24518b5 | Richard Henderson | tcg_temp_free(va); |
1104 | f24518b5 | Richard Henderson | tcg_temp_free(vb); |
1105 | f24518b5 | Richard Henderson | |
1106 | f24518b5 | Richard Henderson | gen_fp_exc_raise(rc, fn11); |
1107 | f24518b5 | Richard Henderson | } |
1108 | f24518b5 | Richard Henderson | |
1109 | f24518b5 | Richard Henderson | #define IEEE_CMP3(name) \
|
1110 | f24518b5 | Richard Henderson | static inline void glue(gen_f, name)(DisasContext *ctx, \ |
1111 | f24518b5 | Richard Henderson | int ra, int rb, int rc, int fn11) \ |
1112 | f24518b5 | Richard Henderson | { \ |
1113 | f24518b5 | Richard Henderson | gen_ieee_compare(ctx, gen_helper_##name, ra, rb, rc, fn11); \ |
1114 | f24518b5 | Richard Henderson | } |
1115 | f24518b5 | Richard Henderson | IEEE_CMP3(cmptun) |
1116 | f24518b5 | Richard Henderson | IEEE_CMP3(cmpteq) |
1117 | f24518b5 | Richard Henderson | IEEE_CMP3(cmptlt) |
1118 | f24518b5 | Richard Henderson | IEEE_CMP3(cmptle) |
1119 | a7812ae4 | pbrook | |
1120 | 248c42f3 | Richard Henderson | static inline uint64_t zapnot_mask(uint8_t lit) |
1121 | 248c42f3 | Richard Henderson | { |
1122 | 248c42f3 | Richard Henderson | uint64_t mask = 0;
|
1123 | 248c42f3 | Richard Henderson | int i;
|
1124 | 248c42f3 | Richard Henderson | |
1125 | 248c42f3 | Richard Henderson | for (i = 0; i < 8; ++i) { |
1126 | 248c42f3 | Richard Henderson | if ((lit >> i) & 1) |
1127 | 248c42f3 | Richard Henderson | mask |= 0xffull << (i * 8); |
1128 | 248c42f3 | Richard Henderson | } |
1129 | 248c42f3 | Richard Henderson | return mask;
|
1130 | 248c42f3 | Richard Henderson | } |
1131 | 248c42f3 | Richard Henderson | |
1132 | 87d98f95 | Richard Henderson | /* Implement zapnot with an immediate operand, which expands to some
|
1133 | 87d98f95 | Richard Henderson | form of immediate AND. This is a basic building block in the
|
1134 | 87d98f95 | Richard Henderson | definition of many of the other byte manipulation instructions. */
|
1135 | 248c42f3 | Richard Henderson | static void gen_zapnoti(TCGv dest, TCGv src, uint8_t lit) |
1136 | 87d98f95 | Richard Henderson | { |
1137 | 87d98f95 | Richard Henderson | switch (lit) {
|
1138 | 87d98f95 | Richard Henderson | case 0x00: |
1139 | 248c42f3 | Richard Henderson | tcg_gen_movi_i64(dest, 0);
|
1140 | 87d98f95 | Richard Henderson | break;
|
1141 | 87d98f95 | Richard Henderson | case 0x01: |
1142 | 248c42f3 | Richard Henderson | tcg_gen_ext8u_i64(dest, src); |
1143 | 87d98f95 | Richard Henderson | break;
|
1144 | 87d98f95 | Richard Henderson | case 0x03: |
1145 | 248c42f3 | Richard Henderson | tcg_gen_ext16u_i64(dest, src); |
1146 | 87d98f95 | Richard Henderson | break;
|
1147 | 87d98f95 | Richard Henderson | case 0x0f: |
1148 | 248c42f3 | Richard Henderson | tcg_gen_ext32u_i64(dest, src); |
1149 | 87d98f95 | Richard Henderson | break;
|
1150 | 87d98f95 | Richard Henderson | case 0xff: |
1151 | 248c42f3 | Richard Henderson | tcg_gen_mov_i64(dest, src); |
1152 | 87d98f95 | Richard Henderson | break;
|
1153 | 87d98f95 | Richard Henderson | default:
|
1154 | 248c42f3 | Richard Henderson | tcg_gen_andi_i64 (dest, src, zapnot_mask (lit)); |
1155 | 87d98f95 | Richard Henderson | break;
|
1156 | 87d98f95 | Richard Henderson | } |
1157 | 87d98f95 | Richard Henderson | } |
1158 | 87d98f95 | Richard Henderson | |
1159 | 87d98f95 | Richard Henderson | static inline void gen_zapnot(int ra, int rb, int rc, int islit, uint8_t lit) |
1160 | 87d98f95 | Richard Henderson | { |
1161 | 87d98f95 | Richard Henderson | if (unlikely(rc == 31)) |
1162 | 87d98f95 | Richard Henderson | return;
|
1163 | 87d98f95 | Richard Henderson | else if (unlikely(ra == 31)) |
1164 | 87d98f95 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1165 | 87d98f95 | Richard Henderson | else if (islit) |
1166 | 248c42f3 | Richard Henderson | gen_zapnoti(cpu_ir[rc], cpu_ir[ra], lit); |
1167 | 87d98f95 | Richard Henderson | else
|
1168 | 87d98f95 | Richard Henderson | gen_helper_zapnot (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1169 | 87d98f95 | Richard Henderson | } |
1170 | 87d98f95 | Richard Henderson | |
1171 | 87d98f95 | Richard Henderson | static inline void gen_zap(int ra, int rb, int rc, int islit, uint8_t lit) |
1172 | 87d98f95 | Richard Henderson | { |
1173 | 87d98f95 | Richard Henderson | if (unlikely(rc == 31)) |
1174 | 87d98f95 | Richard Henderson | return;
|
1175 | 87d98f95 | Richard Henderson | else if (unlikely(ra == 31)) |
1176 | 87d98f95 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1177 | 87d98f95 | Richard Henderson | else if (islit) |
1178 | 248c42f3 | Richard Henderson | gen_zapnoti(cpu_ir[rc], cpu_ir[ra], ~lit); |
1179 | 87d98f95 | Richard Henderson | else
|
1180 | 87d98f95 | Richard Henderson | gen_helper_zap (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1181 | 87d98f95 | Richard Henderson | } |
1182 | 87d98f95 | Richard Henderson | |
1183 | 87d98f95 | Richard Henderson | |
1184 | 248c42f3 | Richard Henderson | /* EXTWH, EXTLH, EXTQH */
|
1185 | ffec44f1 | Richard Henderson | static void gen_ext_h(int ra, int rb, int rc, int islit, |
1186 | ffec44f1 | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
1187 | b3249f63 | aurel32 | { |
1188 | b3249f63 | aurel32 | if (unlikely(rc == 31)) |
1189 | b3249f63 | aurel32 | return;
|
1190 | 377a43b6 | Richard Henderson | else if (unlikely(ra == 31)) |
1191 | 377a43b6 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1192 | 377a43b6 | Richard Henderson | else {
|
1193 | dfaa8583 | aurel32 | if (islit) {
|
1194 | 377a43b6 | Richard Henderson | lit = (64 - (lit & 7) * 8) & 0x3f; |
1195 | 377a43b6 | Richard Henderson | tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1196 | fe2b269a | aurel32 | } else {
|
1197 | 377a43b6 | Richard Henderson | TCGv tmp1 = tcg_temp_new(); |
1198 | b3249f63 | aurel32 | tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
|
1199 | b3249f63 | aurel32 | tcg_gen_shli_i64(tmp1, tmp1, 3);
|
1200 | dbf95805 | Vince Weaver | tcg_gen_neg_i64(tmp1, tmp1); |
1201 | dbf95805 | Vince Weaver | tcg_gen_andi_i64(tmp1, tmp1, 0x3f);
|
1202 | dfaa8583 | aurel32 | tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1); |
1203 | b3249f63 | aurel32 | tcg_temp_free(tmp1); |
1204 | dfaa8583 | aurel32 | } |
1205 | 248c42f3 | Richard Henderson | gen_zapnoti(cpu_ir[rc], cpu_ir[rc], byte_mask); |
1206 | 377a43b6 | Richard Henderson | } |
1207 | b3249f63 | aurel32 | } |
1208 | b3249f63 | aurel32 | |
1209 | 248c42f3 | Richard Henderson | /* EXTBL, EXTWL, EXTLL, EXTQL */
|
1210 | ffec44f1 | Richard Henderson | static void gen_ext_l(int ra, int rb, int rc, int islit, |
1211 | ffec44f1 | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
1212 | b3249f63 | aurel32 | { |
1213 | b3249f63 | aurel32 | if (unlikely(rc == 31)) |
1214 | b3249f63 | aurel32 | return;
|
1215 | 377a43b6 | Richard Henderson | else if (unlikely(ra == 31)) |
1216 | 377a43b6 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1217 | 377a43b6 | Richard Henderson | else {
|
1218 | dfaa8583 | aurel32 | if (islit) {
|
1219 | 377a43b6 | Richard Henderson | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8); |
1220 | dfaa8583 | aurel32 | } else {
|
1221 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1222 | b3249f63 | aurel32 | tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
|
1223 | b3249f63 | aurel32 | tcg_gen_shli_i64(tmp, tmp, 3);
|
1224 | dfaa8583 | aurel32 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp); |
1225 | b3249f63 | aurel32 | tcg_temp_free(tmp); |
1226 | fe2b269a | aurel32 | } |
1227 | 248c42f3 | Richard Henderson | gen_zapnoti(cpu_ir[rc], cpu_ir[rc], byte_mask); |
1228 | 248c42f3 | Richard Henderson | } |
1229 | 248c42f3 | Richard Henderson | } |
1230 | 248c42f3 | Richard Henderson | |
1231 | 50eb6e5c | Richard Henderson | /* INSWH, INSLH, INSQH */
|
1232 | 50eb6e5c | Richard Henderson | static void gen_ins_h(int ra, int rb, int rc, int islit, |
1233 | 50eb6e5c | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
1234 | 50eb6e5c | Richard Henderson | { |
1235 | 50eb6e5c | Richard Henderson | if (unlikely(rc == 31)) |
1236 | 50eb6e5c | Richard Henderson | return;
|
1237 | 50eb6e5c | Richard Henderson | else if (unlikely(ra == 31) || (islit && (lit & 7) == 0)) |
1238 | 50eb6e5c | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1239 | 50eb6e5c | Richard Henderson | else {
|
1240 | 50eb6e5c | Richard Henderson | TCGv tmp = tcg_temp_new(); |
1241 | 50eb6e5c | Richard Henderson | |
1242 | 50eb6e5c | Richard Henderson | /* The instruction description has us left-shift the byte mask
|
1243 | 50eb6e5c | Richard Henderson | and extract bits <15:8> and apply that zap at the end. This
|
1244 | 50eb6e5c | Richard Henderson | is equivalent to simply performing the zap first and shifting
|
1245 | 50eb6e5c | Richard Henderson | afterward. */
|
1246 | 50eb6e5c | Richard Henderson | gen_zapnoti (tmp, cpu_ir[ra], byte_mask); |
1247 | 50eb6e5c | Richard Henderson | |
1248 | 50eb6e5c | Richard Henderson | if (islit) {
|
1249 | 50eb6e5c | Richard Henderson | /* Note that we have handled the lit==0 case above. */
|
1250 | 50eb6e5c | Richard Henderson | tcg_gen_shri_i64 (cpu_ir[rc], tmp, 64 - (lit & 7) * 8); |
1251 | 50eb6e5c | Richard Henderson | } else {
|
1252 | 50eb6e5c | Richard Henderson | TCGv shift = tcg_temp_new(); |
1253 | 50eb6e5c | Richard Henderson | |
1254 | 50eb6e5c | Richard Henderson | /* If (B & 7) == 0, we need to shift by 64 and leave a zero.
|
1255 | 50eb6e5c | Richard Henderson | Do this portably by splitting the shift into two parts:
|
1256 | 50eb6e5c | Richard Henderson | shift_count-1 and 1. Arrange for the -1 by using
|
1257 | 50eb6e5c | Richard Henderson | ones-complement instead of twos-complement in the negation:
|
1258 | 50eb6e5c | Richard Henderson | ~((B & 7) * 8) & 63. */
|
1259 | 50eb6e5c | Richard Henderson | |
1260 | 50eb6e5c | Richard Henderson | tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
|
1261 | 50eb6e5c | Richard Henderson | tcg_gen_shli_i64(shift, shift, 3);
|
1262 | 50eb6e5c | Richard Henderson | tcg_gen_not_i64(shift, shift); |
1263 | 50eb6e5c | Richard Henderson | tcg_gen_andi_i64(shift, shift, 0x3f);
|
1264 | 50eb6e5c | Richard Henderson | |
1265 | 50eb6e5c | Richard Henderson | tcg_gen_shr_i64(cpu_ir[rc], tmp, shift); |
1266 | 50eb6e5c | Richard Henderson | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[rc], 1);
|
1267 | 50eb6e5c | Richard Henderson | tcg_temp_free(shift); |
1268 | 50eb6e5c | Richard Henderson | } |
1269 | 50eb6e5c | Richard Henderson | tcg_temp_free(tmp); |
1270 | 50eb6e5c | Richard Henderson | } |
1271 | 50eb6e5c | Richard Henderson | } |
1272 | 50eb6e5c | Richard Henderson | |
1273 | 248c42f3 | Richard Henderson | /* INSBL, INSWL, INSLL, INSQL */
|
1274 | ffec44f1 | Richard Henderson | static void gen_ins_l(int ra, int rb, int rc, int islit, |
1275 | ffec44f1 | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
1276 | 248c42f3 | Richard Henderson | { |
1277 | 248c42f3 | Richard Henderson | if (unlikely(rc == 31)) |
1278 | 248c42f3 | Richard Henderson | return;
|
1279 | 248c42f3 | Richard Henderson | else if (unlikely(ra == 31)) |
1280 | 248c42f3 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1281 | 248c42f3 | Richard Henderson | else {
|
1282 | 248c42f3 | Richard Henderson | TCGv tmp = tcg_temp_new(); |
1283 | 248c42f3 | Richard Henderson | |
1284 | 248c42f3 | Richard Henderson | /* The instruction description has us left-shift the byte mask
|
1285 | 248c42f3 | Richard Henderson | the same number of byte slots as the data and apply the zap
|
1286 | 248c42f3 | Richard Henderson | at the end. This is equivalent to simply performing the zap
|
1287 | 248c42f3 | Richard Henderson | first and shifting afterward. */
|
1288 | 248c42f3 | Richard Henderson | gen_zapnoti (tmp, cpu_ir[ra], byte_mask); |
1289 | 248c42f3 | Richard Henderson | |
1290 | 248c42f3 | Richard Henderson | if (islit) {
|
1291 | 248c42f3 | Richard Henderson | tcg_gen_shli_i64(cpu_ir[rc], tmp, (lit & 7) * 8); |
1292 | 248c42f3 | Richard Henderson | } else {
|
1293 | 248c42f3 | Richard Henderson | TCGv shift = tcg_temp_new(); |
1294 | 248c42f3 | Richard Henderson | tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
|
1295 | 248c42f3 | Richard Henderson | tcg_gen_shli_i64(shift, shift, 3);
|
1296 | 248c42f3 | Richard Henderson | tcg_gen_shl_i64(cpu_ir[rc], tmp, shift); |
1297 | 248c42f3 | Richard Henderson | tcg_temp_free(shift); |
1298 | 248c42f3 | Richard Henderson | } |
1299 | 248c42f3 | Richard Henderson | tcg_temp_free(tmp); |
1300 | 377a43b6 | Richard Henderson | } |
1301 | b3249f63 | aurel32 | } |
1302 | b3249f63 | aurel32 | |
1303 | ffec44f1 | Richard Henderson | /* MSKWH, MSKLH, MSKQH */
|
1304 | ffec44f1 | Richard Henderson | static void gen_msk_h(int ra, int rb, int rc, int islit, |
1305 | ffec44f1 | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
1306 | ffec44f1 | Richard Henderson | { |
1307 | ffec44f1 | Richard Henderson | if (unlikely(rc == 31)) |
1308 | ffec44f1 | Richard Henderson | return;
|
1309 | ffec44f1 | Richard Henderson | else if (unlikely(ra == 31)) |
1310 | ffec44f1 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1311 | ffec44f1 | Richard Henderson | else if (islit) { |
1312 | ffec44f1 | Richard Henderson | gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~((byte_mask << (lit & 7)) >> 8)); |
1313 | ffec44f1 | Richard Henderson | } else {
|
1314 | ffec44f1 | Richard Henderson | TCGv shift = tcg_temp_new(); |
1315 | ffec44f1 | Richard Henderson | TCGv mask = tcg_temp_new(); |
1316 | ffec44f1 | Richard Henderson | |
1317 | ffec44f1 | Richard Henderson | /* The instruction description is as above, where the byte_mask
|
1318 | ffec44f1 | Richard Henderson | is shifted left, and then we extract bits <15:8>. This can be
|
1319 | ffec44f1 | Richard Henderson | emulated with a right-shift on the expanded byte mask. This
|
1320 | ffec44f1 | Richard Henderson | requires extra care because for an input <2:0> == 0 we need a
|
1321 | ffec44f1 | Richard Henderson | shift of 64 bits in order to generate a zero. This is done by
|
1322 | ffec44f1 | Richard Henderson | splitting the shift into two parts, the variable shift - 1
|
1323 | ffec44f1 | Richard Henderson | followed by a constant 1 shift. The code we expand below is
|
1324 | ffec44f1 | Richard Henderson | equivalent to ~((B & 7) * 8) & 63. */
|
1325 | ffec44f1 | Richard Henderson | |
1326 | ffec44f1 | Richard Henderson | tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
|
1327 | ffec44f1 | Richard Henderson | tcg_gen_shli_i64(shift, shift, 3);
|
1328 | ffec44f1 | Richard Henderson | tcg_gen_not_i64(shift, shift); |
1329 | ffec44f1 | Richard Henderson | tcg_gen_andi_i64(shift, shift, 0x3f);
|
1330 | ffec44f1 | Richard Henderson | tcg_gen_movi_i64(mask, zapnot_mask (byte_mask)); |
1331 | ffec44f1 | Richard Henderson | tcg_gen_shr_i64(mask, mask, shift); |
1332 | ffec44f1 | Richard Henderson | tcg_gen_shri_i64(mask, mask, 1);
|
1333 | ffec44f1 | Richard Henderson | |
1334 | ffec44f1 | Richard Henderson | tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask); |
1335 | ffec44f1 | Richard Henderson | |
1336 | ffec44f1 | Richard Henderson | tcg_temp_free(mask); |
1337 | ffec44f1 | Richard Henderson | tcg_temp_free(shift); |
1338 | ffec44f1 | Richard Henderson | } |
1339 | ffec44f1 | Richard Henderson | } |
1340 | ffec44f1 | Richard Henderson | |
1341 | 14ab1634 | Richard Henderson | /* MSKBL, MSKWL, MSKLL, MSKQL */
|
1342 | ffec44f1 | Richard Henderson | static void gen_msk_l(int ra, int rb, int rc, int islit, |
1343 | ffec44f1 | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
1344 | 14ab1634 | Richard Henderson | { |
1345 | 14ab1634 | Richard Henderson | if (unlikely(rc == 31)) |
1346 | 14ab1634 | Richard Henderson | return;
|
1347 | 14ab1634 | Richard Henderson | else if (unlikely(ra == 31)) |
1348 | 14ab1634 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1349 | 14ab1634 | Richard Henderson | else if (islit) { |
1350 | 14ab1634 | Richard Henderson | gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~(byte_mask << (lit & 7)));
|
1351 | 14ab1634 | Richard Henderson | } else {
|
1352 | 14ab1634 | Richard Henderson | TCGv shift = tcg_temp_new(); |
1353 | 14ab1634 | Richard Henderson | TCGv mask = tcg_temp_new(); |
1354 | 14ab1634 | Richard Henderson | |
1355 | 14ab1634 | Richard Henderson | tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
|
1356 | 14ab1634 | Richard Henderson | tcg_gen_shli_i64(shift, shift, 3);
|
1357 | 14ab1634 | Richard Henderson | tcg_gen_movi_i64(mask, zapnot_mask (byte_mask)); |
1358 | 14ab1634 | Richard Henderson | tcg_gen_shl_i64(mask, mask, shift); |
1359 | 14ab1634 | Richard Henderson | |
1360 | 14ab1634 | Richard Henderson | tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask); |
1361 | 14ab1634 | Richard Henderson | |
1362 | 14ab1634 | Richard Henderson | tcg_temp_free(mask); |
1363 | 14ab1634 | Richard Henderson | tcg_temp_free(shift); |
1364 | 14ab1634 | Richard Henderson | } |
1365 | 14ab1634 | Richard Henderson | } |
1366 | 14ab1634 | Richard Henderson | |
1367 | 04acd307 | aurel32 | /* Code to call arith3 helpers */
|
1368 | a7812ae4 | pbrook | #define ARITH3(name) \
|
1369 | 636aa200 | Blue Swirl | static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\ |
1370 | 636aa200 | Blue Swirl | uint8_t lit) \ |
1371 | a7812ae4 | pbrook | { \ |
1372 | a7812ae4 | pbrook | if (unlikely(rc == 31)) \ |
1373 | a7812ae4 | pbrook | return; \
|
1374 | a7812ae4 | pbrook | \ |
1375 | a7812ae4 | pbrook | if (ra != 31) { \ |
1376 | a7812ae4 | pbrook | if (islit) { \
|
1377 | a7812ae4 | pbrook | TCGv tmp = tcg_const_i64(lit); \ |
1378 | a7812ae4 | pbrook | gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp); \ |
1379 | a7812ae4 | pbrook | tcg_temp_free(tmp); \ |
1380 | a7812ae4 | pbrook | } else \
|
1381 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \ |
1382 | a7812ae4 | pbrook | } else { \
|
1383 | a7812ae4 | pbrook | TCGv tmp1 = tcg_const_i64(0); \
|
1384 | a7812ae4 | pbrook | if (islit) { \
|
1385 | a7812ae4 | pbrook | TCGv tmp2 = tcg_const_i64(lit); \ |
1386 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2); \ |
1387 | a7812ae4 | pbrook | tcg_temp_free(tmp2); \ |
1388 | a7812ae4 | pbrook | } else \
|
1389 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]); \ |
1390 | a7812ae4 | pbrook | tcg_temp_free(tmp1); \ |
1391 | a7812ae4 | pbrook | } \ |
1392 | b3249f63 | aurel32 | } |
1393 | a7812ae4 | pbrook | ARITH3(umulh) |
1394 | 2958620f | Richard Henderson | ARITH3(cmpbge) |
1395 | 13e4df99 | Richard Henderson | ARITH3(minub8) |
1396 | 13e4df99 | Richard Henderson | ARITH3(minsb8) |
1397 | 13e4df99 | Richard Henderson | ARITH3(minuw4) |
1398 | 13e4df99 | Richard Henderson | ARITH3(minsw4) |
1399 | 13e4df99 | Richard Henderson | ARITH3(maxub8) |
1400 | 13e4df99 | Richard Henderson | ARITH3(maxsb8) |
1401 | 13e4df99 | Richard Henderson | ARITH3(maxuw4) |
1402 | 13e4df99 | Richard Henderson | ARITH3(maxsw4) |
1403 | 13e4df99 | Richard Henderson | ARITH3(perr) |
1404 | 13e4df99 | Richard Henderson | |
1405 | 2958620f | Richard Henderson | /* Code to call arith3 helpers */
|
1406 | 2958620f | Richard Henderson | #define ARITH3_EX(name) \
|
1407 | 2958620f | Richard Henderson | static inline void glue(gen_, name)(int ra, int rb, int rc, \ |
1408 | 2958620f | Richard Henderson | int islit, uint8_t lit) \
|
1409 | 2958620f | Richard Henderson | { \ |
1410 | 2958620f | Richard Henderson | if (unlikely(rc == 31)) { \ |
1411 | 2958620f | Richard Henderson | return; \
|
1412 | 2958620f | Richard Henderson | } \ |
1413 | 2958620f | Richard Henderson | if (ra != 31) { \ |
1414 | 2958620f | Richard Henderson | if (islit) { \
|
1415 | 2958620f | Richard Henderson | TCGv tmp = tcg_const_i64(lit); \ |
1416 | 2958620f | Richard Henderson | gen_helper_ ## name(cpu_ir[rc], cpu_env, \ |
1417 | 2958620f | Richard Henderson | cpu_ir[ra], tmp); \ |
1418 | 2958620f | Richard Henderson | tcg_temp_free(tmp); \ |
1419 | 2958620f | Richard Henderson | } else { \
|
1420 | 2958620f | Richard Henderson | gen_helper_ ## name(cpu_ir[rc], cpu_env, \ |
1421 | 2958620f | Richard Henderson | cpu_ir[ra], cpu_ir[rb]); \ |
1422 | 2958620f | Richard Henderson | } \ |
1423 | 2958620f | Richard Henderson | } else { \
|
1424 | 2958620f | Richard Henderson | TCGv tmp1 = tcg_const_i64(0); \
|
1425 | 2958620f | Richard Henderson | if (islit) { \
|
1426 | 2958620f | Richard Henderson | TCGv tmp2 = tcg_const_i64(lit); \ |
1427 | 2958620f | Richard Henderson | gen_helper_ ## name(cpu_ir[rc], cpu_env, tmp1, tmp2); \ |
1428 | 2958620f | Richard Henderson | tcg_temp_free(tmp2); \ |
1429 | 2958620f | Richard Henderson | } else { \
|
1430 | 2958620f | Richard Henderson | gen_helper_ ## name(cpu_ir[rc], cpu_env, tmp1, cpu_ir[rb]); \ |
1431 | 2958620f | Richard Henderson | } \ |
1432 | 2958620f | Richard Henderson | tcg_temp_free(tmp1); \ |
1433 | 2958620f | Richard Henderson | } \ |
1434 | 2958620f | Richard Henderson | } |
1435 | 2958620f | Richard Henderson | ARITH3_EX(addlv) |
1436 | 2958620f | Richard Henderson | ARITH3_EX(sublv) |
1437 | 2958620f | Richard Henderson | ARITH3_EX(addqv) |
1438 | 2958620f | Richard Henderson | ARITH3_EX(subqv) |
1439 | 2958620f | Richard Henderson | ARITH3_EX(mullv) |
1440 | 2958620f | Richard Henderson | ARITH3_EX(mulqv) |
1441 | 2958620f | Richard Henderson | |
1442 | 13e4df99 | Richard Henderson | #define MVIOP2(name) \
|
1443 | 13e4df99 | Richard Henderson | static inline void glue(gen_, name)(int rb, int rc) \ |
1444 | 13e4df99 | Richard Henderson | { \ |
1445 | 13e4df99 | Richard Henderson | if (unlikely(rc == 31)) \ |
1446 | 13e4df99 | Richard Henderson | return; \
|
1447 | 13e4df99 | Richard Henderson | if (unlikely(rb == 31)) \ |
1448 | 13e4df99 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0); \
|
1449 | 13e4df99 | Richard Henderson | else \
|
1450 | 13e4df99 | Richard Henderson | gen_helper_ ## name (cpu_ir[rc], cpu_ir[rb]); \ |
1451 | 13e4df99 | Richard Henderson | } |
1452 | 13e4df99 | Richard Henderson | MVIOP2(pklb) |
1453 | 13e4df99 | Richard Henderson | MVIOP2(pkwb) |
1454 | 13e4df99 | Richard Henderson | MVIOP2(unpkbl) |
1455 | 13e4df99 | Richard Henderson | MVIOP2(unpkbw) |
1456 | b3249f63 | aurel32 | |
1457 | 9e05960f | Richard Henderson | static void gen_cmp(TCGCond cond, int ra, int rb, int rc, |
1458 | 9e05960f | Richard Henderson | int islit, uint8_t lit)
|
1459 | 01ff9cc8 | aurel32 | { |
1460 | 9e05960f | Richard Henderson | TCGv va, vb; |
1461 | 01ff9cc8 | aurel32 | |
1462 | 9e05960f | Richard Henderson | if (unlikely(rc == 31)) { |
1463 | 13e4df99 | Richard Henderson | return;
|
1464 | 9e05960f | Richard Henderson | } |
1465 | 01ff9cc8 | aurel32 | |
1466 | 9e05960f | Richard Henderson | if (ra == 31) { |
1467 | 9e05960f | Richard Henderson | va = tcg_const_i64(0);
|
1468 | 9e05960f | Richard Henderson | } else {
|
1469 | 9e05960f | Richard Henderson | va = cpu_ir[ra]; |
1470 | 9e05960f | Richard Henderson | } |
1471 | 9e05960f | Richard Henderson | if (islit) {
|
1472 | 9e05960f | Richard Henderson | vb = tcg_const_i64(lit); |
1473 | 9e05960f | Richard Henderson | } else {
|
1474 | 9e05960f | Richard Henderson | vb = cpu_ir[rb]; |
1475 | 9e05960f | Richard Henderson | } |
1476 | 01ff9cc8 | aurel32 | |
1477 | 9e05960f | Richard Henderson | tcg_gen_setcond_i64(cond, cpu_ir[rc], va, vb); |
1478 | 01ff9cc8 | aurel32 | |
1479 | 9e05960f | Richard Henderson | if (ra == 31) { |
1480 | 9e05960f | Richard Henderson | tcg_temp_free(va); |
1481 | 9e05960f | Richard Henderson | } |
1482 | 9e05960f | Richard Henderson | if (islit) {
|
1483 | 9e05960f | Richard Henderson | tcg_temp_free(vb); |
1484 | 9e05960f | Richard Henderson | } |
1485 | 01ff9cc8 | aurel32 | } |
1486 | 01ff9cc8 | aurel32 | |
1487 | ac316ca4 | Richard Henderson | static void gen_rx(int ra, int set) |
1488 | ac316ca4 | Richard Henderson | { |
1489 | ac316ca4 | Richard Henderson | TCGv_i32 tmp; |
1490 | ac316ca4 | Richard Henderson | |
1491 | ac316ca4 | Richard Henderson | if (ra != 31) { |
1492 | 4d5712f1 | Andreas Färber | tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUAlphaState, intr_flag)); |
1493 | ac316ca4 | Richard Henderson | } |
1494 | ac316ca4 | Richard Henderson | |
1495 | ac316ca4 | Richard Henderson | tmp = tcg_const_i32(set); |
1496 | 4d5712f1 | Andreas Färber | tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUAlphaState, intr_flag)); |
1497 | ac316ca4 | Richard Henderson | tcg_temp_free_i32(tmp); |
1498 | ac316ca4 | Richard Henderson | } |
1499 | ac316ca4 | Richard Henderson | |
1500 | 2ace7e55 | Richard Henderson | static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) |
1501 | 2ace7e55 | Richard Henderson | { |
1502 | 2ace7e55 | Richard Henderson | /* We're emulating OSF/1 PALcode. Many of these are trivial access
|
1503 | 2ace7e55 | Richard Henderson | to internal cpu registers. */
|
1504 | 2ace7e55 | Richard Henderson | |
1505 | 2ace7e55 | Richard Henderson | /* Unprivileged PAL call */
|
1506 | 2ace7e55 | Richard Henderson | if (palcode >= 0x80 && palcode < 0xC0) { |
1507 | 2ace7e55 | Richard Henderson | switch (palcode) {
|
1508 | 2ace7e55 | Richard Henderson | case 0x86: |
1509 | 2ace7e55 | Richard Henderson | /* IMB */
|
1510 | 2ace7e55 | Richard Henderson | /* No-op inside QEMU. */
|
1511 | 2ace7e55 | Richard Henderson | break;
|
1512 | 2ace7e55 | Richard Henderson | case 0x9E: |
1513 | 2ace7e55 | Richard Henderson | /* RDUNIQUE */
|
1514 | 2ace7e55 | Richard Henderson | tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_unique); |
1515 | 2ace7e55 | Richard Henderson | break;
|
1516 | 2ace7e55 | Richard Henderson | case 0x9F: |
1517 | 2ace7e55 | Richard Henderson | /* WRUNIQUE */
|
1518 | 2ace7e55 | Richard Henderson | tcg_gen_mov_i64(cpu_unique, cpu_ir[IR_A0]); |
1519 | 2ace7e55 | Richard Henderson | break;
|
1520 | 2ace7e55 | Richard Henderson | default:
|
1521 | 2ace7e55 | Richard Henderson | return gen_excp(ctx, EXCP_CALL_PAL, palcode & 0xbf); |
1522 | 2ace7e55 | Richard Henderson | } |
1523 | 2ace7e55 | Richard Henderson | return NO_EXIT;
|
1524 | 2ace7e55 | Richard Henderson | } |
1525 | 2ace7e55 | Richard Henderson | |
1526 | 2ace7e55 | Richard Henderson | #ifndef CONFIG_USER_ONLY
|
1527 | 2ace7e55 | Richard Henderson | /* Privileged PAL code */
|
1528 | 2ace7e55 | Richard Henderson | if (palcode < 0x40 && (ctx->tb->flags & TB_FLAGS_USER_MODE) == 0) { |
1529 | 2ace7e55 | Richard Henderson | switch (palcode) {
|
1530 | 2ace7e55 | Richard Henderson | case 0x01: |
1531 | 2ace7e55 | Richard Henderson | /* CFLUSH */
|
1532 | 2ace7e55 | Richard Henderson | /* No-op inside QEMU. */
|
1533 | 2ace7e55 | Richard Henderson | break;
|
1534 | 2ace7e55 | Richard Henderson | case 0x02: |
1535 | 2ace7e55 | Richard Henderson | /* DRAINA */
|
1536 | 2ace7e55 | Richard Henderson | /* No-op inside QEMU. */
|
1537 | 2ace7e55 | Richard Henderson | break;
|
1538 | 2ace7e55 | Richard Henderson | case 0x2D: |
1539 | 2ace7e55 | Richard Henderson | /* WRVPTPTR */
|
1540 | 4d5712f1 | Andreas Färber | tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUAlphaState, vptptr)); |
1541 | 2ace7e55 | Richard Henderson | break;
|
1542 | 2ace7e55 | Richard Henderson | case 0x31: |
1543 | 2ace7e55 | Richard Henderson | /* WRVAL */
|
1544 | 2ace7e55 | Richard Henderson | tcg_gen_mov_i64(cpu_sysval, cpu_ir[IR_A0]); |
1545 | 2ace7e55 | Richard Henderson | break;
|
1546 | 2ace7e55 | Richard Henderson | case 0x32: |
1547 | 2ace7e55 | Richard Henderson | /* RDVAL */
|
1548 | 2ace7e55 | Richard Henderson | tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_sysval); |
1549 | 2ace7e55 | Richard Henderson | break;
|
1550 | 2ace7e55 | Richard Henderson | |
1551 | 2ace7e55 | Richard Henderson | case 0x35: { |
1552 | 2ace7e55 | Richard Henderson | /* SWPIPL */
|
1553 | 2ace7e55 | Richard Henderson | TCGv tmp; |
1554 | 2ace7e55 | Richard Henderson | |
1555 | 2ace7e55 | Richard Henderson | /* Note that we already know we're in kernel mode, so we know
|
1556 | 2ace7e55 | Richard Henderson | that PS only contains the 3 IPL bits. */
|
1557 | 4d5712f1 | Andreas Färber | tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaState, ps)); |
1558 | 2ace7e55 | Richard Henderson | |
1559 | 2ace7e55 | Richard Henderson | /* But make sure and store only the 3 IPL bits from the user. */
|
1560 | 2ace7e55 | Richard Henderson | tmp = tcg_temp_new(); |
1561 | 2ace7e55 | Richard Henderson | tcg_gen_andi_i64(tmp, cpu_ir[IR_A0], PS_INT_MASK); |
1562 | 4d5712f1 | Andreas Färber | tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, ps)); |
1563 | 2ace7e55 | Richard Henderson | tcg_temp_free(tmp); |
1564 | 2ace7e55 | Richard Henderson | break;
|
1565 | 2ace7e55 | Richard Henderson | } |
1566 | 2ace7e55 | Richard Henderson | |
1567 | 2ace7e55 | Richard Henderson | case 0x36: |
1568 | 2ace7e55 | Richard Henderson | /* RDPS */
|
1569 | 4d5712f1 | Andreas Färber | tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaState, ps)); |
1570 | 2ace7e55 | Richard Henderson | break;
|
1571 | 2ace7e55 | Richard Henderson | case 0x38: |
1572 | 2ace7e55 | Richard Henderson | /* WRUSP */
|
1573 | 2ace7e55 | Richard Henderson | tcg_gen_mov_i64(cpu_usp, cpu_ir[IR_A0]); |
1574 | 2ace7e55 | Richard Henderson | break;
|
1575 | 2ace7e55 | Richard Henderson | case 0x3A: |
1576 | 2ace7e55 | Richard Henderson | /* RDUSP */
|
1577 | 2ace7e55 | Richard Henderson | tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_usp); |
1578 | 2ace7e55 | Richard Henderson | break;
|
1579 | 2ace7e55 | Richard Henderson | case 0x3C: |
1580 | 2ace7e55 | Richard Henderson | /* WHAMI */
|
1581 | 2ace7e55 | Richard Henderson | tcg_gen_ld32s_i64(cpu_ir[IR_V0], cpu_env, |
1582 | 4d5712f1 | Andreas Färber | offsetof(CPUAlphaState, cpu_index)); |
1583 | 2ace7e55 | Richard Henderson | break;
|
1584 | 2ace7e55 | Richard Henderson | |
1585 | 2ace7e55 | Richard Henderson | default:
|
1586 | 2ace7e55 | Richard Henderson | return gen_excp(ctx, EXCP_CALL_PAL, palcode & 0x3f); |
1587 | 2ace7e55 | Richard Henderson | } |
1588 | 2ace7e55 | Richard Henderson | return NO_EXIT;
|
1589 | 2ace7e55 | Richard Henderson | } |
1590 | 2ace7e55 | Richard Henderson | #endif
|
1591 | 2ace7e55 | Richard Henderson | |
1592 | 2ace7e55 | Richard Henderson | return gen_invalid(ctx);
|
1593 | 2ace7e55 | Richard Henderson | } |
1594 | 2ace7e55 | Richard Henderson | |
1595 | 26b46094 | Richard Henderson | #ifndef CONFIG_USER_ONLY
|
1596 | 26b46094 | Richard Henderson | |
1597 | 26b46094 | Richard Henderson | #define PR_BYTE 0x100000 |
1598 | 26b46094 | Richard Henderson | #define PR_LONG 0x200000 |
1599 | 26b46094 | Richard Henderson | |
1600 | 26b46094 | Richard Henderson | static int cpu_pr_data(int pr) |
1601 | 26b46094 | Richard Henderson | { |
1602 | 26b46094 | Richard Henderson | switch (pr) {
|
1603 | 26b46094 | Richard Henderson | case 0: return offsetof(CPUAlphaState, ps) | PR_BYTE; |
1604 | 26b46094 | Richard Henderson | case 1: return offsetof(CPUAlphaState, fen) | PR_BYTE; |
1605 | 26b46094 | Richard Henderson | case 2: return offsetof(CPUAlphaState, pcc_ofs) | PR_LONG; |
1606 | 26b46094 | Richard Henderson | case 3: return offsetof(CPUAlphaState, trap_arg0); |
1607 | 26b46094 | Richard Henderson | case 4: return offsetof(CPUAlphaState, trap_arg1); |
1608 | 26b46094 | Richard Henderson | case 5: return offsetof(CPUAlphaState, trap_arg2); |
1609 | 26b46094 | Richard Henderson | case 6: return offsetof(CPUAlphaState, exc_addr); |
1610 | 26b46094 | Richard Henderson | case 7: return offsetof(CPUAlphaState, palbr); |
1611 | 26b46094 | Richard Henderson | case 8: return offsetof(CPUAlphaState, ptbr); |
1612 | 26b46094 | Richard Henderson | case 9: return offsetof(CPUAlphaState, vptptr); |
1613 | 26b46094 | Richard Henderson | case 10: return offsetof(CPUAlphaState, unique); |
1614 | 26b46094 | Richard Henderson | case 11: return offsetof(CPUAlphaState, sysval); |
1615 | 26b46094 | Richard Henderson | case 12: return offsetof(CPUAlphaState, usp); |
1616 | 26b46094 | Richard Henderson | |
1617 | 26b46094 | Richard Henderson | case 32 ... 39: |
1618 | 26b46094 | Richard Henderson | return offsetof(CPUAlphaState, shadow[pr - 32]); |
1619 | 26b46094 | Richard Henderson | case 40 ... 63: |
1620 | 26b46094 | Richard Henderson | return offsetof(CPUAlphaState, scratch[pr - 40]); |
1621 | c781cf96 | Richard Henderson | |
1622 | c781cf96 | Richard Henderson | case 251: |
1623 | c781cf96 | Richard Henderson | return offsetof(CPUAlphaState, alarm_expire);
|
1624 | 26b46094 | Richard Henderson | } |
1625 | 26b46094 | Richard Henderson | return 0; |
1626 | 26b46094 | Richard Henderson | } |
1627 | 26b46094 | Richard Henderson | |
1628 | c781cf96 | Richard Henderson | static ExitStatus gen_mfpr(int ra, int regno) |
1629 | 26b46094 | Richard Henderson | { |
1630 | 26b46094 | Richard Henderson | int data = cpu_pr_data(regno);
|
1631 | 26b46094 | Richard Henderson | |
1632 | 26b46094 | Richard Henderson | /* In our emulated PALcode, these processor registers have no
|
1633 | 26b46094 | Richard Henderson | side effects from reading. */
|
1634 | 26b46094 | Richard Henderson | if (ra == 31) { |
1635 | c781cf96 | Richard Henderson | return NO_EXIT;
|
1636 | c781cf96 | Richard Henderson | } |
1637 | c781cf96 | Richard Henderson | |
1638 | c781cf96 | Richard Henderson | if (regno == 250) { |
1639 | c781cf96 | Richard Henderson | /* WALL_TIME */
|
1640 | c781cf96 | Richard Henderson | if (use_icount) {
|
1641 | c781cf96 | Richard Henderson | gen_io_start(); |
1642 | c781cf96 | Richard Henderson | gen_helper_get_time(cpu_ir[ra]); |
1643 | c781cf96 | Richard Henderson | gen_io_end(); |
1644 | c781cf96 | Richard Henderson | return EXIT_PC_STALE;
|
1645 | c781cf96 | Richard Henderson | } else {
|
1646 | c781cf96 | Richard Henderson | gen_helper_get_time(cpu_ir[ra]); |
1647 | c781cf96 | Richard Henderson | return NO_EXIT;
|
1648 | c781cf96 | Richard Henderson | } |
1649 | 26b46094 | Richard Henderson | } |
1650 | 26b46094 | Richard Henderson | |
1651 | 26b46094 | Richard Henderson | /* The basic registers are data only, and unknown registers
|
1652 | 26b46094 | Richard Henderson | are read-zero, write-ignore. */
|
1653 | 26b46094 | Richard Henderson | if (data == 0) { |
1654 | 26b46094 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[ra], 0);
|
1655 | 26b46094 | Richard Henderson | } else if (data & PR_BYTE) { |
1656 | 26b46094 | Richard Henderson | tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, data & ~PR_BYTE); |
1657 | 26b46094 | Richard Henderson | } else if (data & PR_LONG) { |
1658 | 26b46094 | Richard Henderson | tcg_gen_ld32s_i64(cpu_ir[ra], cpu_env, data & ~PR_LONG); |
1659 | 26b46094 | Richard Henderson | } else {
|
1660 | 26b46094 | Richard Henderson | tcg_gen_ld_i64(cpu_ir[ra], cpu_env, data); |
1661 | 26b46094 | Richard Henderson | } |
1662 | c781cf96 | Richard Henderson | return NO_EXIT;
|
1663 | 26b46094 | Richard Henderson | } |
1664 | 26b46094 | Richard Henderson | |
1665 | bc24270e | Richard Henderson | static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno) |
1666 | 26b46094 | Richard Henderson | { |
1667 | 26b46094 | Richard Henderson | TCGv tmp; |
1668 | bc24270e | Richard Henderson | int data;
|
1669 | 26b46094 | Richard Henderson | |
1670 | 26b46094 | Richard Henderson | if (rb == 31) { |
1671 | 26b46094 | Richard Henderson | tmp = tcg_const_i64(0);
|
1672 | 26b46094 | Richard Henderson | } else {
|
1673 | 26b46094 | Richard Henderson | tmp = cpu_ir[rb]; |
1674 | 26b46094 | Richard Henderson | } |
1675 | 26b46094 | Richard Henderson | |
1676 | bc24270e | Richard Henderson | switch (regno) {
|
1677 | bc24270e | Richard Henderson | case 255: |
1678 | 3b4fefd6 | Richard Henderson | /* TBIA */
|
1679 | 69163fbb | Richard Henderson | gen_helper_tbia(cpu_env); |
1680 | bc24270e | Richard Henderson | break;
|
1681 | bc24270e | Richard Henderson | |
1682 | bc24270e | Richard Henderson | case 254: |
1683 | 3b4fefd6 | Richard Henderson | /* TBIS */
|
1684 | 69163fbb | Richard Henderson | gen_helper_tbis(cpu_env, tmp); |
1685 | bc24270e | Richard Henderson | break;
|
1686 | bc24270e | Richard Henderson | |
1687 | bc24270e | Richard Henderson | case 253: |
1688 | bc24270e | Richard Henderson | /* WAIT */
|
1689 | bc24270e | Richard Henderson | tmp = tcg_const_i64(1);
|
1690 | 4d5712f1 | Andreas Färber | tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUAlphaState, halted)); |
1691 | bc24270e | Richard Henderson | return gen_excp(ctx, EXCP_HLT, 0); |
1692 | bc24270e | Richard Henderson | |
1693 | 034ebc27 | Richard Henderson | case 252: |
1694 | 034ebc27 | Richard Henderson | /* HALT */
|
1695 | 034ebc27 | Richard Henderson | gen_helper_halt(tmp); |
1696 | 034ebc27 | Richard Henderson | return EXIT_PC_STALE;
|
1697 | 034ebc27 | Richard Henderson | |
1698 | c781cf96 | Richard Henderson | case 251: |
1699 | c781cf96 | Richard Henderson | /* ALARM */
|
1700 | 69163fbb | Richard Henderson | gen_helper_set_alarm(cpu_env, tmp); |
1701 | c781cf96 | Richard Henderson | break;
|
1702 | c781cf96 | Richard Henderson | |
1703 | bc24270e | Richard Henderson | default:
|
1704 | 3b4fefd6 | Richard Henderson | /* The basic registers are data only, and unknown registers
|
1705 | 3b4fefd6 | Richard Henderson | are read-zero, write-ignore. */
|
1706 | bc24270e | Richard Henderson | data = cpu_pr_data(regno); |
1707 | 3b4fefd6 | Richard Henderson | if (data != 0) { |
1708 | 3b4fefd6 | Richard Henderson | if (data & PR_BYTE) {
|
1709 | 3b4fefd6 | Richard Henderson | tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); |
1710 | 3b4fefd6 | Richard Henderson | } else if (data & PR_LONG) { |
1711 | 3b4fefd6 | Richard Henderson | tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); |
1712 | 3b4fefd6 | Richard Henderson | } else {
|
1713 | 3b4fefd6 | Richard Henderson | tcg_gen_st_i64(tmp, cpu_env, data); |
1714 | 3b4fefd6 | Richard Henderson | } |
1715 | 26b46094 | Richard Henderson | } |
1716 | bc24270e | Richard Henderson | break;
|
1717 | 26b46094 | Richard Henderson | } |
1718 | 26b46094 | Richard Henderson | |
1719 | 26b46094 | Richard Henderson | if (rb == 31) { |
1720 | 26b46094 | Richard Henderson | tcg_temp_free(tmp); |
1721 | 26b46094 | Richard Henderson | } |
1722 | bc24270e | Richard Henderson | |
1723 | bc24270e | Richard Henderson | return NO_EXIT;
|
1724 | 26b46094 | Richard Henderson | } |
1725 | 26b46094 | Richard Henderson | #endif /* !USER_ONLY*/ |
1726 | 26b46094 | Richard Henderson | |
1727 | 4af70374 | Richard Henderson | static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
|
1728 | 4c9649a9 | j_mayer | { |
1729 | 4c9649a9 | j_mayer | uint32_t palcode; |
1730 | efa64351 | Michael S. Tsirkin | int32_t disp21, disp16; |
1731 | efa64351 | Michael S. Tsirkin | #ifndef CONFIG_USER_ONLY
|
1732 | efa64351 | Michael S. Tsirkin | int32_t disp12; |
1733 | efa64351 | Michael S. Tsirkin | #endif
|
1734 | f88fe4e3 | Blue Swirl | uint16_t fn11; |
1735 | b6fb147c | Michael S. Tsirkin | uint8_t opc, ra, rb, rc, fpfn, fn7, islit, real_islit; |
1736 | adf3c8b6 | aurel32 | uint8_t lit; |
1737 | 4af70374 | Richard Henderson | ExitStatus ret; |
1738 | 4c9649a9 | j_mayer | |
1739 | 4c9649a9 | j_mayer | /* Decode all instruction fields */
|
1740 | 4c9649a9 | j_mayer | opc = insn >> 26;
|
1741 | 4c9649a9 | j_mayer | ra = (insn >> 21) & 0x1F; |
1742 | 4c9649a9 | j_mayer | rb = (insn >> 16) & 0x1F; |
1743 | 4c9649a9 | j_mayer | rc = insn & 0x1F;
|
1744 | 13e4df99 | Richard Henderson | real_islit = islit = (insn >> 12) & 1; |
1745 | dfaa8583 | aurel32 | if (rb == 31 && !islit) { |
1746 | dfaa8583 | aurel32 | islit = 1;
|
1747 | dfaa8583 | aurel32 | lit = 0;
|
1748 | dfaa8583 | aurel32 | } else
|
1749 | dfaa8583 | aurel32 | lit = (insn >> 13) & 0xFF; |
1750 | 4c9649a9 | j_mayer | palcode = insn & 0x03FFFFFF;
|
1751 | 4c9649a9 | j_mayer | disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11; |
1752 | 4c9649a9 | j_mayer | disp16 = (int16_t)(insn & 0x0000FFFF);
|
1753 | efa64351 | Michael S. Tsirkin | #ifndef CONFIG_USER_ONLY
|
1754 | 4c9649a9 | j_mayer | disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20; |
1755 | efa64351 | Michael S. Tsirkin | #endif
|
1756 | 4c9649a9 | j_mayer | fn11 = (insn >> 5) & 0x000007FF; |
1757 | 4c9649a9 | j_mayer | fpfn = fn11 & 0x3F;
|
1758 | 4c9649a9 | j_mayer | fn7 = (insn >> 5) & 0x0000007F; |
1759 | 806991da | Richard Henderson | LOG_DISAS("opc %02x ra %2d rb %2d rc %2d disp16 %6d\n",
|
1760 | d12d51d5 | aliguori | opc, ra, rb, rc, disp16); |
1761 | 806991da | Richard Henderson | |
1762 | 4af70374 | Richard Henderson | ret = NO_EXIT; |
1763 | 4c9649a9 | j_mayer | switch (opc) {
|
1764 | 4c9649a9 | j_mayer | case 0x00: |
1765 | 4c9649a9 | j_mayer | /* CALL_PAL */
|
1766 | 2ace7e55 | Richard Henderson | ret = gen_call_pal(ctx, palcode); |
1767 | 2ace7e55 | Richard Henderson | break;
|
1768 | 4c9649a9 | j_mayer | case 0x01: |
1769 | 4c9649a9 | j_mayer | /* OPC01 */
|
1770 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1771 | 4c9649a9 | j_mayer | case 0x02: |
1772 | 4c9649a9 | j_mayer | /* OPC02 */
|
1773 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1774 | 4c9649a9 | j_mayer | case 0x03: |
1775 | 4c9649a9 | j_mayer | /* OPC03 */
|
1776 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1777 | 4c9649a9 | j_mayer | case 0x04: |
1778 | 4c9649a9 | j_mayer | /* OPC04 */
|
1779 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1780 | 4c9649a9 | j_mayer | case 0x05: |
1781 | 4c9649a9 | j_mayer | /* OPC05 */
|
1782 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1783 | 4c9649a9 | j_mayer | case 0x06: |
1784 | 4c9649a9 | j_mayer | /* OPC06 */
|
1785 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1786 | 4c9649a9 | j_mayer | case 0x07: |
1787 | 4c9649a9 | j_mayer | /* OPC07 */
|
1788 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1789 | 4c9649a9 | j_mayer | case 0x08: |
1790 | 4c9649a9 | j_mayer | /* LDA */
|
1791 | 1ef4ef4e | aurel32 | if (likely(ra != 31)) { |
1792 | 496cb5b9 | aurel32 | if (rb != 31) |
1793 | 3761035f | aurel32 | tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16); |
1794 | 3761035f | aurel32 | else
|
1795 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], disp16); |
1796 | 496cb5b9 | aurel32 | } |
1797 | 4c9649a9 | j_mayer | break;
|
1798 | 4c9649a9 | j_mayer | case 0x09: |
1799 | 4c9649a9 | j_mayer | /* LDAH */
|
1800 | 1ef4ef4e | aurel32 | if (likely(ra != 31)) { |
1801 | 496cb5b9 | aurel32 | if (rb != 31) |
1802 | 3761035f | aurel32 | tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
|
1803 | 3761035f | aurel32 | else
|
1804 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
|
1805 | 496cb5b9 | aurel32 | } |
1806 | 4c9649a9 | j_mayer | break;
|
1807 | 4c9649a9 | j_mayer | case 0x0A: |
1808 | 4c9649a9 | j_mayer | /* LDBU */
|
1809 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_BWX) {
|
1810 | a18ad893 | Richard Henderson | gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); |
1811 | a18ad893 | Richard Henderson | break;
|
1812 | a18ad893 | Richard Henderson | } |
1813 | a18ad893 | Richard Henderson | goto invalid_opc;
|
1814 | 4c9649a9 | j_mayer | case 0x0B: |
1815 | 4c9649a9 | j_mayer | /* LDQ_U */
|
1816 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1); |
1817 | 4c9649a9 | j_mayer | break;
|
1818 | 4c9649a9 | j_mayer | case 0x0C: |
1819 | 4c9649a9 | j_mayer | /* LDWU */
|
1820 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_BWX) {
|
1821 | a18ad893 | Richard Henderson | gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); |
1822 | a18ad893 | Richard Henderson | break;
|
1823 | a18ad893 | Richard Henderson | } |
1824 | a18ad893 | Richard Henderson | goto invalid_opc;
|
1825 | 4c9649a9 | j_mayer | case 0x0D: |
1826 | 4c9649a9 | j_mayer | /* STW */
|
1827 | 6910b8f6 | Richard Henderson | gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); |
1828 | 4c9649a9 | j_mayer | break;
|
1829 | 4c9649a9 | j_mayer | case 0x0E: |
1830 | 4c9649a9 | j_mayer | /* STB */
|
1831 | 6910b8f6 | Richard Henderson | gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0); |
1832 | 4c9649a9 | j_mayer | break;
|
1833 | 4c9649a9 | j_mayer | case 0x0F: |
1834 | 4c9649a9 | j_mayer | /* STQ_U */
|
1835 | 6910b8f6 | Richard Henderson | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1); |
1836 | 4c9649a9 | j_mayer | break;
|
1837 | 4c9649a9 | j_mayer | case 0x10: |
1838 | 4c9649a9 | j_mayer | switch (fn7) {
|
1839 | 4c9649a9 | j_mayer | case 0x00: |
1840 | 4c9649a9 | j_mayer | /* ADDL */
|
1841 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1842 | 30c7183b | aurel32 | if (ra != 31) { |
1843 | 30c7183b | aurel32 | if (islit) {
|
1844 | 30c7183b | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1845 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1846 | dfaa8583 | aurel32 | } else {
|
1847 | 30c7183b | aurel32 | tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1848 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1849 | dfaa8583 | aurel32 | } |
1850 | 30c7183b | aurel32 | } else {
|
1851 | 30c7183b | aurel32 | if (islit)
|
1852 | dfaa8583 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1853 | 30c7183b | aurel32 | else
|
1854 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
1855 | 30c7183b | aurel32 | } |
1856 | 30c7183b | aurel32 | } |
1857 | 4c9649a9 | j_mayer | break;
|
1858 | 4c9649a9 | j_mayer | case 0x02: |
1859 | 4c9649a9 | j_mayer | /* S4ADDL */
|
1860 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1861 | 30c7183b | aurel32 | if (ra != 31) { |
1862 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1863 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
1864 | dfaa8583 | aurel32 | if (islit)
|
1865 | dfaa8583 | aurel32 | tcg_gen_addi_i64(tmp, tmp, lit); |
1866 | dfaa8583 | aurel32 | else
|
1867 | dfaa8583 | aurel32 | tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); |
1868 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
1869 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1870 | 30c7183b | aurel32 | } else {
|
1871 | 30c7183b | aurel32 | if (islit)
|
1872 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1873 | 30c7183b | aurel32 | else
|
1874 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
1875 | 30c7183b | aurel32 | } |
1876 | 30c7183b | aurel32 | } |
1877 | 4c9649a9 | j_mayer | break;
|
1878 | 4c9649a9 | j_mayer | case 0x09: |
1879 | 4c9649a9 | j_mayer | /* SUBL */
|
1880 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1881 | 30c7183b | aurel32 | if (ra != 31) { |
1882 | dfaa8583 | aurel32 | if (islit)
|
1883 | 30c7183b | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1884 | dfaa8583 | aurel32 | else
|
1885 | 30c7183b | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1886 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1887 | 30c7183b | aurel32 | } else {
|
1888 | 30c7183b | aurel32 | if (islit)
|
1889 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
1890 | dfaa8583 | aurel32 | else {
|
1891 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
1892 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1893 | 30c7183b | aurel32 | } |
1894 | 30c7183b | aurel32 | } |
1895 | 4c9649a9 | j_mayer | break;
|
1896 | 4c9649a9 | j_mayer | case 0x0B: |
1897 | 4c9649a9 | j_mayer | /* S4SUBL */
|
1898 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1899 | 30c7183b | aurel32 | if (ra != 31) { |
1900 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1901 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
1902 | dfaa8583 | aurel32 | if (islit)
|
1903 | dfaa8583 | aurel32 | tcg_gen_subi_i64(tmp, tmp, lit); |
1904 | dfaa8583 | aurel32 | else
|
1905 | dfaa8583 | aurel32 | tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); |
1906 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
1907 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1908 | 30c7183b | aurel32 | } else {
|
1909 | 30c7183b | aurel32 | if (islit)
|
1910 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
1911 | dfaa8583 | aurel32 | else {
|
1912 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
1913 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1914 | dfaa8583 | aurel32 | } |
1915 | 30c7183b | aurel32 | } |
1916 | 30c7183b | aurel32 | } |
1917 | 4c9649a9 | j_mayer | break;
|
1918 | 4c9649a9 | j_mayer | case 0x0F: |
1919 | 4c9649a9 | j_mayer | /* CMPBGE */
|
1920 | a7812ae4 | pbrook | gen_cmpbge(ra, rb, rc, islit, lit); |
1921 | 4c9649a9 | j_mayer | break;
|
1922 | 4c9649a9 | j_mayer | case 0x12: |
1923 | 4c9649a9 | j_mayer | /* S8ADDL */
|
1924 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1925 | 30c7183b | aurel32 | if (ra != 31) { |
1926 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1927 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
1928 | dfaa8583 | aurel32 | if (islit)
|
1929 | dfaa8583 | aurel32 | tcg_gen_addi_i64(tmp, tmp, lit); |
1930 | dfaa8583 | aurel32 | else
|
1931 | dfaa8583 | aurel32 | tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); |
1932 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
1933 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1934 | 30c7183b | aurel32 | } else {
|
1935 | 30c7183b | aurel32 | if (islit)
|
1936 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1937 | 30c7183b | aurel32 | else
|
1938 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
1939 | 30c7183b | aurel32 | } |
1940 | 30c7183b | aurel32 | } |
1941 | 4c9649a9 | j_mayer | break;
|
1942 | 4c9649a9 | j_mayer | case 0x1B: |
1943 | 4c9649a9 | j_mayer | /* S8SUBL */
|
1944 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1945 | 30c7183b | aurel32 | if (ra != 31) { |
1946 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1947 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
1948 | dfaa8583 | aurel32 | if (islit)
|
1949 | dfaa8583 | aurel32 | tcg_gen_subi_i64(tmp, tmp, lit); |
1950 | dfaa8583 | aurel32 | else
|
1951 | dfaa8583 | aurel32 | tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); |
1952 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
1953 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1954 | 30c7183b | aurel32 | } else {
|
1955 | 30c7183b | aurel32 | if (islit)
|
1956 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
1957 | dfaa8583 | aurel32 | else
|
1958 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
1959 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1960 | dfaa8583 | aurel32 | } |
1961 | 30c7183b | aurel32 | } |
1962 | 30c7183b | aurel32 | } |
1963 | 4c9649a9 | j_mayer | break;
|
1964 | 4c9649a9 | j_mayer | case 0x1D: |
1965 | 4c9649a9 | j_mayer | /* CMPULT */
|
1966 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit); |
1967 | 4c9649a9 | j_mayer | break;
|
1968 | 4c9649a9 | j_mayer | case 0x20: |
1969 | 4c9649a9 | j_mayer | /* ADDQ */
|
1970 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1971 | 30c7183b | aurel32 | if (ra != 31) { |
1972 | 30c7183b | aurel32 | if (islit)
|
1973 | 30c7183b | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1974 | 30c7183b | aurel32 | else
|
1975 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1976 | 30c7183b | aurel32 | } else {
|
1977 | 30c7183b | aurel32 | if (islit)
|
1978 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1979 | 30c7183b | aurel32 | else
|
1980 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1981 | 30c7183b | aurel32 | } |
1982 | 30c7183b | aurel32 | } |
1983 | 4c9649a9 | j_mayer | break;
|
1984 | 4c9649a9 | j_mayer | case 0x22: |
1985 | 4c9649a9 | j_mayer | /* S4ADDQ */
|
1986 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1987 | 30c7183b | aurel32 | if (ra != 31) { |
1988 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1989 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
1990 | dfaa8583 | aurel32 | if (islit)
|
1991 | dfaa8583 | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
1992 | dfaa8583 | aurel32 | else
|
1993 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
1994 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1995 | 30c7183b | aurel32 | } else {
|
1996 | 30c7183b | aurel32 | if (islit)
|
1997 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1998 | 30c7183b | aurel32 | else
|
1999 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
2000 | 30c7183b | aurel32 | } |
2001 | 30c7183b | aurel32 | } |
2002 | 4c9649a9 | j_mayer | break;
|
2003 | 4c9649a9 | j_mayer | case 0x29: |
2004 | 4c9649a9 | j_mayer | /* SUBQ */
|
2005 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2006 | 30c7183b | aurel32 | if (ra != 31) { |
2007 | 30c7183b | aurel32 | if (islit)
|
2008 | 30c7183b | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
2009 | 30c7183b | aurel32 | else
|
2010 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
2011 | 30c7183b | aurel32 | } else {
|
2012 | 30c7183b | aurel32 | if (islit)
|
2013 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
2014 | 30c7183b | aurel32 | else
|
2015 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
2016 | 30c7183b | aurel32 | } |
2017 | 30c7183b | aurel32 | } |
2018 | 4c9649a9 | j_mayer | break;
|
2019 | 4c9649a9 | j_mayer | case 0x2B: |
2020 | 4c9649a9 | j_mayer | /* S4SUBQ */
|
2021 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2022 | 30c7183b | aurel32 | if (ra != 31) { |
2023 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
2024 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
2025 | dfaa8583 | aurel32 | if (islit)
|
2026 | dfaa8583 | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
2027 | dfaa8583 | aurel32 | else
|
2028 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
2029 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
2030 | 30c7183b | aurel32 | } else {
|
2031 | 30c7183b | aurel32 | if (islit)
|
2032 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
2033 | 30c7183b | aurel32 | else
|
2034 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
2035 | 30c7183b | aurel32 | } |
2036 | 30c7183b | aurel32 | } |
2037 | 4c9649a9 | j_mayer | break;
|
2038 | 4c9649a9 | j_mayer | case 0x2D: |
2039 | 4c9649a9 | j_mayer | /* CMPEQ */
|
2040 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit); |
2041 | 4c9649a9 | j_mayer | break;
|
2042 | 4c9649a9 | j_mayer | case 0x32: |
2043 | 4c9649a9 | j_mayer | /* S8ADDQ */
|
2044 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2045 | 30c7183b | aurel32 | if (ra != 31) { |
2046 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
2047 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
2048 | dfaa8583 | aurel32 | if (islit)
|
2049 | dfaa8583 | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
2050 | dfaa8583 | aurel32 | else
|
2051 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
2052 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
2053 | 30c7183b | aurel32 | } else {
|
2054 | 30c7183b | aurel32 | if (islit)
|
2055 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
2056 | 30c7183b | aurel32 | else
|
2057 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
2058 | 30c7183b | aurel32 | } |
2059 | 30c7183b | aurel32 | } |
2060 | 4c9649a9 | j_mayer | break;
|
2061 | 4c9649a9 | j_mayer | case 0x3B: |
2062 | 4c9649a9 | j_mayer | /* S8SUBQ */
|
2063 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2064 | 30c7183b | aurel32 | if (ra != 31) { |
2065 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
2066 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
2067 | dfaa8583 | aurel32 | if (islit)
|
2068 | dfaa8583 | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
2069 | dfaa8583 | aurel32 | else
|
2070 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
2071 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
2072 | 30c7183b | aurel32 | } else {
|
2073 | 30c7183b | aurel32 | if (islit)
|
2074 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
2075 | 30c7183b | aurel32 | else
|
2076 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
2077 | 30c7183b | aurel32 | } |
2078 | 30c7183b | aurel32 | } |
2079 | 4c9649a9 | j_mayer | break;
|
2080 | 4c9649a9 | j_mayer | case 0x3D: |
2081 | 4c9649a9 | j_mayer | /* CMPULE */
|
2082 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit); |
2083 | 4c9649a9 | j_mayer | break;
|
2084 | 4c9649a9 | j_mayer | case 0x40: |
2085 | 4c9649a9 | j_mayer | /* ADDL/V */
|
2086 | a7812ae4 | pbrook | gen_addlv(ra, rb, rc, islit, lit); |
2087 | 4c9649a9 | j_mayer | break;
|
2088 | 4c9649a9 | j_mayer | case 0x49: |
2089 | 4c9649a9 | j_mayer | /* SUBL/V */
|
2090 | a7812ae4 | pbrook | gen_sublv(ra, rb, rc, islit, lit); |
2091 | 4c9649a9 | j_mayer | break;
|
2092 | 4c9649a9 | j_mayer | case 0x4D: |
2093 | 4c9649a9 | j_mayer | /* CMPLT */
|
2094 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit); |
2095 | 4c9649a9 | j_mayer | break;
|
2096 | 4c9649a9 | j_mayer | case 0x60: |
2097 | 4c9649a9 | j_mayer | /* ADDQ/V */
|
2098 | a7812ae4 | pbrook | gen_addqv(ra, rb, rc, islit, lit); |
2099 | 4c9649a9 | j_mayer | break;
|
2100 | 4c9649a9 | j_mayer | case 0x69: |
2101 | 4c9649a9 | j_mayer | /* SUBQ/V */
|
2102 | a7812ae4 | pbrook | gen_subqv(ra, rb, rc, islit, lit); |
2103 | 4c9649a9 | j_mayer | break;
|
2104 | 4c9649a9 | j_mayer | case 0x6D: |
2105 | 4c9649a9 | j_mayer | /* CMPLE */
|
2106 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit); |
2107 | 4c9649a9 | j_mayer | break;
|
2108 | 4c9649a9 | j_mayer | default:
|
2109 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2110 | 4c9649a9 | j_mayer | } |
2111 | 4c9649a9 | j_mayer | break;
|
2112 | 4c9649a9 | j_mayer | case 0x11: |
2113 | 4c9649a9 | j_mayer | switch (fn7) {
|
2114 | 4c9649a9 | j_mayer | case 0x00: |
2115 | 4c9649a9 | j_mayer | /* AND */
|
2116 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2117 | dfaa8583 | aurel32 | if (ra == 31) |
2118 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
2119 | 30c7183b | aurel32 | else if (islit) |
2120 | 30c7183b | aurel32 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
2121 | 30c7183b | aurel32 | else
|
2122 | 30c7183b | aurel32 | tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
2123 | 30c7183b | aurel32 | } |
2124 | 4c9649a9 | j_mayer | break;
|
2125 | 4c9649a9 | j_mayer | case 0x08: |
2126 | 4c9649a9 | j_mayer | /* BIC */
|
2127 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2128 | 30c7183b | aurel32 | if (ra != 31) { |
2129 | 30c7183b | aurel32 | if (islit)
|
2130 | 30c7183b | aurel32 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
2131 | 1b581c44 | aurel32 | else
|
2132 | 1b581c44 | aurel32 | tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
2133 | 30c7183b | aurel32 | } else
|
2134 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
2135 | 30c7183b | aurel32 | } |
2136 | 4c9649a9 | j_mayer | break;
|
2137 | 4c9649a9 | j_mayer | case 0x14: |
2138 | 4c9649a9 | j_mayer | /* CMOVLBS */
|
2139 | bbe1dab4 | Richard Henderson | gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1);
|
2140 | 4c9649a9 | j_mayer | break;
|
2141 | 4c9649a9 | j_mayer | case 0x16: |
2142 | 4c9649a9 | j_mayer | /* CMOVLBC */
|
2143 | bbe1dab4 | Richard Henderson | gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
|
2144 | 4c9649a9 | j_mayer | break;
|
2145 | 4c9649a9 | j_mayer | case 0x20: |
2146 | 4c9649a9 | j_mayer | /* BIS */
|
2147 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2148 | 30c7183b | aurel32 | if (ra != 31) { |
2149 | 30c7183b | aurel32 | if (islit)
|
2150 | 30c7183b | aurel32 | tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit); |
2151 | 8bb6e981 | aurel32 | else
|
2152 | 30c7183b | aurel32 | tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
2153 | 4c9649a9 | j_mayer | } else {
|
2154 | 30c7183b | aurel32 | if (islit)
|
2155 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
2156 | 30c7183b | aurel32 | else
|
2157 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
2158 | 4c9649a9 | j_mayer | } |
2159 | 4c9649a9 | j_mayer | } |
2160 | 4c9649a9 | j_mayer | break;
|
2161 | 4c9649a9 | j_mayer | case 0x24: |
2162 | 4c9649a9 | j_mayer | /* CMOVEQ */
|
2163 | bbe1dab4 | Richard Henderson | gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
|
2164 | 4c9649a9 | j_mayer | break;
|
2165 | 4c9649a9 | j_mayer | case 0x26: |
2166 | 4c9649a9 | j_mayer | /* CMOVNE */
|
2167 | bbe1dab4 | Richard Henderson | gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0);
|
2168 | 4c9649a9 | j_mayer | break;
|
2169 | 4c9649a9 | j_mayer | case 0x28: |
2170 | 4c9649a9 | j_mayer | /* ORNOT */
|
2171 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2172 | dfaa8583 | aurel32 | if (ra != 31) { |
2173 | 30c7183b | aurel32 | if (islit)
|
2174 | 30c7183b | aurel32 | tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
2175 | 1b581c44 | aurel32 | else
|
2176 | 1b581c44 | aurel32 | tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
2177 | 30c7183b | aurel32 | } else {
|
2178 | 30c7183b | aurel32 | if (islit)
|
2179 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ~lit); |
2180 | 30c7183b | aurel32 | else
|
2181 | 30c7183b | aurel32 | tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); |
2182 | 30c7183b | aurel32 | } |
2183 | 30c7183b | aurel32 | } |
2184 | 4c9649a9 | j_mayer | break;
|
2185 | 4c9649a9 | j_mayer | case 0x40: |
2186 | 4c9649a9 | j_mayer | /* XOR */
|
2187 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2188 | 30c7183b | aurel32 | if (ra != 31) { |
2189 | 30c7183b | aurel32 | if (islit)
|
2190 | 30c7183b | aurel32 | tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit); |
2191 | 30c7183b | aurel32 | else
|
2192 | dfaa8583 | aurel32 | tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
2193 | 30c7183b | aurel32 | } else {
|
2194 | 30c7183b | aurel32 | if (islit)
|
2195 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
2196 | 30c7183b | aurel32 | else
|
2197 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
2198 | 30c7183b | aurel32 | } |
2199 | 30c7183b | aurel32 | } |
2200 | 4c9649a9 | j_mayer | break;
|
2201 | 4c9649a9 | j_mayer | case 0x44: |
2202 | 4c9649a9 | j_mayer | /* CMOVLT */
|
2203 | bbe1dab4 | Richard Henderson | gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0);
|
2204 | 4c9649a9 | j_mayer | break;
|
2205 | 4c9649a9 | j_mayer | case 0x46: |
2206 | 4c9649a9 | j_mayer | /* CMOVGE */
|
2207 | bbe1dab4 | Richard Henderson | gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0);
|
2208 | 4c9649a9 | j_mayer | break;
|
2209 | 4c9649a9 | j_mayer | case 0x48: |
2210 | 4c9649a9 | j_mayer | /* EQV */
|
2211 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2212 | 30c7183b | aurel32 | if (ra != 31) { |
2213 | 30c7183b | aurel32 | if (islit)
|
2214 | 30c7183b | aurel32 | tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
2215 | 1b581c44 | aurel32 | else
|
2216 | 1b581c44 | aurel32 | tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
2217 | 30c7183b | aurel32 | } else {
|
2218 | 30c7183b | aurel32 | if (islit)
|
2219 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ~lit); |
2220 | 30c7183b | aurel32 | else
|
2221 | dfaa8583 | aurel32 | tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); |
2222 | 30c7183b | aurel32 | } |
2223 | 30c7183b | aurel32 | } |
2224 | 4c9649a9 | j_mayer | break;
|
2225 | 4c9649a9 | j_mayer | case 0x61: |
2226 | 4c9649a9 | j_mayer | /* AMASK */
|
2227 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
2228 | a18ad893 | Richard Henderson | uint64_t amask = ctx->tb->flags >> TB_FLAGS_AMASK_SHIFT; |
2229 | a18ad893 | Richard Henderson | |
2230 | a18ad893 | Richard Henderson | if (islit) {
|
2231 | a18ad893 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], lit & ~amask); |
2232 | a18ad893 | Richard Henderson | } else {
|
2233 | a18ad893 | Richard Henderson | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[rb], ~amask); |
2234 | 1a1f7dbc | aurel32 | } |
2235 | ae8ecd42 | aurel32 | } |
2236 | 4c9649a9 | j_mayer | break;
|
2237 | 4c9649a9 | j_mayer | case 0x64: |
2238 | 4c9649a9 | j_mayer | /* CMOVLE */
|
2239 | bbe1dab4 | Richard Henderson | gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0);
|
2240 | 4c9649a9 | j_mayer | break;
|
2241 | 4c9649a9 | j_mayer | case 0x66: |
2242 | 4c9649a9 | j_mayer | /* CMOVGT */
|
2243 | bbe1dab4 | Richard Henderson | gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0);
|
2244 | 4c9649a9 | j_mayer | break;
|
2245 | 4c9649a9 | j_mayer | case 0x6C: |
2246 | 4c9649a9 | j_mayer | /* IMPLVER */
|
2247 | 3761035f | aurel32 | if (rc != 31) |
2248 | 8579095b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ctx->env->implver); |
2249 | 4c9649a9 | j_mayer | break;
|
2250 | 4c9649a9 | j_mayer | default:
|
2251 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2252 | 4c9649a9 | j_mayer | } |
2253 | 4c9649a9 | j_mayer | break;
|
2254 | 4c9649a9 | j_mayer | case 0x12: |
2255 | 4c9649a9 | j_mayer | switch (fn7) {
|
2256 | 4c9649a9 | j_mayer | case 0x02: |
2257 | 4c9649a9 | j_mayer | /* MSKBL */
|
2258 | 14ab1634 | Richard Henderson | gen_msk_l(ra, rb, rc, islit, lit, 0x01);
|
2259 | 4c9649a9 | j_mayer | break;
|
2260 | 4c9649a9 | j_mayer | case 0x06: |
2261 | 4c9649a9 | j_mayer | /* EXTBL */
|
2262 | 377a43b6 | Richard Henderson | gen_ext_l(ra, rb, rc, islit, lit, 0x01);
|
2263 | 4c9649a9 | j_mayer | break;
|
2264 | 4c9649a9 | j_mayer | case 0x0B: |
2265 | 4c9649a9 | j_mayer | /* INSBL */
|
2266 | 248c42f3 | Richard Henderson | gen_ins_l(ra, rb, rc, islit, lit, 0x01);
|
2267 | 4c9649a9 | j_mayer | break;
|
2268 | 4c9649a9 | j_mayer | case 0x12: |
2269 | 4c9649a9 | j_mayer | /* MSKWL */
|
2270 | 14ab1634 | Richard Henderson | gen_msk_l(ra, rb, rc, islit, lit, 0x03);
|
2271 | 4c9649a9 | j_mayer | break;
|
2272 | 4c9649a9 | j_mayer | case 0x16: |
2273 | 4c9649a9 | j_mayer | /* EXTWL */
|
2274 | 377a43b6 | Richard Henderson | gen_ext_l(ra, rb, rc, islit, lit, 0x03);
|
2275 | 4c9649a9 | j_mayer | break;
|
2276 | 4c9649a9 | j_mayer | case 0x1B: |
2277 | 4c9649a9 | j_mayer | /* INSWL */
|
2278 | 248c42f3 | Richard Henderson | gen_ins_l(ra, rb, rc, islit, lit, 0x03);
|
2279 | 4c9649a9 | j_mayer | break;
|
2280 | 4c9649a9 | j_mayer | case 0x22: |
2281 | 4c9649a9 | j_mayer | /* MSKLL */
|
2282 | 14ab1634 | Richard Henderson | gen_msk_l(ra, rb, rc, islit, lit, 0x0f);
|
2283 | 4c9649a9 | j_mayer | break;
|
2284 | 4c9649a9 | j_mayer | case 0x26: |
2285 | 4c9649a9 | j_mayer | /* EXTLL */
|
2286 | 377a43b6 | Richard Henderson | gen_ext_l(ra, rb, rc, islit, lit, 0x0f);
|
2287 | 4c9649a9 | j_mayer | break;
|
2288 | 4c9649a9 | j_mayer | case 0x2B: |
2289 | 4c9649a9 | j_mayer | /* INSLL */
|
2290 | 248c42f3 | Richard Henderson | gen_ins_l(ra, rb, rc, islit, lit, 0x0f);
|
2291 | 4c9649a9 | j_mayer | break;
|
2292 | 4c9649a9 | j_mayer | case 0x30: |
2293 | 4c9649a9 | j_mayer | /* ZAP */
|
2294 | a7812ae4 | pbrook | gen_zap(ra, rb, rc, islit, lit); |
2295 | 4c9649a9 | j_mayer | break;
|
2296 | 4c9649a9 | j_mayer | case 0x31: |
2297 | 4c9649a9 | j_mayer | /* ZAPNOT */
|
2298 | a7812ae4 | pbrook | gen_zapnot(ra, rb, rc, islit, lit); |
2299 | 4c9649a9 | j_mayer | break;
|
2300 | 4c9649a9 | j_mayer | case 0x32: |
2301 | 4c9649a9 | j_mayer | /* MSKQL */
|
2302 | 14ab1634 | Richard Henderson | gen_msk_l(ra, rb, rc, islit, lit, 0xff);
|
2303 | 4c9649a9 | j_mayer | break;
|
2304 | 4c9649a9 | j_mayer | case 0x34: |
2305 | 4c9649a9 | j_mayer | /* SRL */
|
2306 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2307 | 30c7183b | aurel32 | if (ra != 31) { |
2308 | 30c7183b | aurel32 | if (islit)
|
2309 | 30c7183b | aurel32 | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
2310 | dfaa8583 | aurel32 | else {
|
2311 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
2312 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
2313 | 30c7183b | aurel32 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift); |
2314 | 30c7183b | aurel32 | tcg_temp_free(shift); |
2315 | dfaa8583 | aurel32 | } |
2316 | 30c7183b | aurel32 | } else
|
2317 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
2318 | 30c7183b | aurel32 | } |
2319 | 4c9649a9 | j_mayer | break;
|
2320 | 4c9649a9 | j_mayer | case 0x36: |
2321 | 4c9649a9 | j_mayer | /* EXTQL */
|
2322 | 377a43b6 | Richard Henderson | gen_ext_l(ra, rb, rc, islit, lit, 0xff);
|
2323 | 4c9649a9 | j_mayer | break;
|
2324 | 4c9649a9 | j_mayer | case 0x39: |
2325 | 4c9649a9 | j_mayer | /* SLL */
|
2326 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2327 | 30c7183b | aurel32 | if (ra != 31) { |
2328 | 30c7183b | aurel32 | if (islit)
|
2329 | 30c7183b | aurel32 | tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
2330 | dfaa8583 | aurel32 | else {
|
2331 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
2332 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
2333 | 30c7183b | aurel32 | tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift); |
2334 | 30c7183b | aurel32 | tcg_temp_free(shift); |
2335 | dfaa8583 | aurel32 | } |
2336 | 30c7183b | aurel32 | } else
|
2337 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
2338 | 30c7183b | aurel32 | } |
2339 | 4c9649a9 | j_mayer | break;
|
2340 | 4c9649a9 | j_mayer | case 0x3B: |
2341 | 4c9649a9 | j_mayer | /* INSQL */
|
2342 | 248c42f3 | Richard Henderson | gen_ins_l(ra, rb, rc, islit, lit, 0xff);
|
2343 | 4c9649a9 | j_mayer | break;
|
2344 | 4c9649a9 | j_mayer | case 0x3C: |
2345 | 4c9649a9 | j_mayer | /* SRA */
|
2346 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2347 | 30c7183b | aurel32 | if (ra != 31) { |
2348 | 30c7183b | aurel32 | if (islit)
|
2349 | 30c7183b | aurel32 | tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
2350 | dfaa8583 | aurel32 | else {
|
2351 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
2352 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
2353 | 30c7183b | aurel32 | tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift); |
2354 | 30c7183b | aurel32 | tcg_temp_free(shift); |
2355 | dfaa8583 | aurel32 | } |
2356 | 30c7183b | aurel32 | } else
|
2357 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
2358 | 30c7183b | aurel32 | } |
2359 | 4c9649a9 | j_mayer | break;
|
2360 | 4c9649a9 | j_mayer | case 0x52: |
2361 | 4c9649a9 | j_mayer | /* MSKWH */
|
2362 | ffec44f1 | Richard Henderson | gen_msk_h(ra, rb, rc, islit, lit, 0x03);
|
2363 | 4c9649a9 | j_mayer | break;
|
2364 | 4c9649a9 | j_mayer | case 0x57: |
2365 | 4c9649a9 | j_mayer | /* INSWH */
|
2366 | 50eb6e5c | Richard Henderson | gen_ins_h(ra, rb, rc, islit, lit, 0x03);
|
2367 | 4c9649a9 | j_mayer | break;
|
2368 | 4c9649a9 | j_mayer | case 0x5A: |
2369 | 4c9649a9 | j_mayer | /* EXTWH */
|
2370 | 377a43b6 | Richard Henderson | gen_ext_h(ra, rb, rc, islit, lit, 0x03);
|
2371 | 4c9649a9 | j_mayer | break;
|
2372 | 4c9649a9 | j_mayer | case 0x62: |
2373 | 4c9649a9 | j_mayer | /* MSKLH */
|
2374 | ffec44f1 | Richard Henderson | gen_msk_h(ra, rb, rc, islit, lit, 0x0f);
|
2375 | 4c9649a9 | j_mayer | break;
|
2376 | 4c9649a9 | j_mayer | case 0x67: |
2377 | 4c9649a9 | j_mayer | /* INSLH */
|
2378 | 50eb6e5c | Richard Henderson | gen_ins_h(ra, rb, rc, islit, lit, 0x0f);
|
2379 | 4c9649a9 | j_mayer | break;
|
2380 | 4c9649a9 | j_mayer | case 0x6A: |
2381 | 4c9649a9 | j_mayer | /* EXTLH */
|
2382 | 377a43b6 | Richard Henderson | gen_ext_h(ra, rb, rc, islit, lit, 0x0f);
|
2383 | 4c9649a9 | j_mayer | break;
|
2384 | 4c9649a9 | j_mayer | case 0x72: |
2385 | 4c9649a9 | j_mayer | /* MSKQH */
|
2386 | ffec44f1 | Richard Henderson | gen_msk_h(ra, rb, rc, islit, lit, 0xff);
|
2387 | 4c9649a9 | j_mayer | break;
|
2388 | 4c9649a9 | j_mayer | case 0x77: |
2389 | 4c9649a9 | j_mayer | /* INSQH */
|
2390 | 50eb6e5c | Richard Henderson | gen_ins_h(ra, rb, rc, islit, lit, 0xff);
|
2391 | 4c9649a9 | j_mayer | break;
|
2392 | 4c9649a9 | j_mayer | case 0x7A: |
2393 | 4c9649a9 | j_mayer | /* EXTQH */
|
2394 | 377a43b6 | Richard Henderson | gen_ext_h(ra, rb, rc, islit, lit, 0xff);
|
2395 | 4c9649a9 | j_mayer | break;
|
2396 | 4c9649a9 | j_mayer | default:
|
2397 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2398 | 4c9649a9 | j_mayer | } |
2399 | 4c9649a9 | j_mayer | break;
|
2400 | 4c9649a9 | j_mayer | case 0x13: |
2401 | 4c9649a9 | j_mayer | switch (fn7) {
|
2402 | 4c9649a9 | j_mayer | case 0x00: |
2403 | 4c9649a9 | j_mayer | /* MULL */
|
2404 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2405 | dfaa8583 | aurel32 | if (ra == 31) |
2406 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
2407 | 30c7183b | aurel32 | else {
|
2408 | 30c7183b | aurel32 | if (islit)
|
2409 | 30c7183b | aurel32 | tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
2410 | 30c7183b | aurel32 | else
|
2411 | 30c7183b | aurel32 | tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
2412 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
2413 | 30c7183b | aurel32 | } |
2414 | 30c7183b | aurel32 | } |
2415 | 4c9649a9 | j_mayer | break;
|
2416 | 4c9649a9 | j_mayer | case 0x20: |
2417 | 4c9649a9 | j_mayer | /* MULQ */
|
2418 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
2419 | dfaa8583 | aurel32 | if (ra == 31) |
2420 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
2421 | 30c7183b | aurel32 | else if (islit) |
2422 | 30c7183b | aurel32 | tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
2423 | 30c7183b | aurel32 | else
|
2424 | 30c7183b | aurel32 | tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
2425 | 30c7183b | aurel32 | } |
2426 | 4c9649a9 | j_mayer | break;
|
2427 | 4c9649a9 | j_mayer | case 0x30: |
2428 | 4c9649a9 | j_mayer | /* UMULH */
|
2429 | a7812ae4 | pbrook | gen_umulh(ra, rb, rc, islit, lit); |
2430 | 4c9649a9 | j_mayer | break;
|
2431 | 4c9649a9 | j_mayer | case 0x40: |
2432 | 4c9649a9 | j_mayer | /* MULL/V */
|
2433 | a7812ae4 | pbrook | gen_mullv(ra, rb, rc, islit, lit); |
2434 | 4c9649a9 | j_mayer | break;
|
2435 | 4c9649a9 | j_mayer | case 0x60: |
2436 | 4c9649a9 | j_mayer | /* MULQ/V */
|
2437 | a7812ae4 | pbrook | gen_mulqv(ra, rb, rc, islit, lit); |
2438 | 4c9649a9 | j_mayer | break;
|
2439 | 4c9649a9 | j_mayer | default:
|
2440 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2441 | 4c9649a9 | j_mayer | } |
2442 | 4c9649a9 | j_mayer | break;
|
2443 | 4c9649a9 | j_mayer | case 0x14: |
2444 | f24518b5 | Richard Henderson | switch (fpfn) { /* fn11 & 0x3F */ |
2445 | 4c9649a9 | j_mayer | case 0x04: |
2446 | 4c9649a9 | j_mayer | /* ITOFS */
|
2447 | a18ad893 | Richard Henderson | if ((ctx->tb->flags & TB_FLAGS_AMASK_FIX) == 0) { |
2448 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2449 | a18ad893 | Richard Henderson | } |
2450 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
2451 | f18cd223 | aurel32 | if (ra != 31) { |
2452 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_temp_new_i32(); |
2453 | f18cd223 | aurel32 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
2454 | a7812ae4 | pbrook | gen_helper_memory_to_s(cpu_fir[rc], tmp); |
2455 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp); |
2456 | f18cd223 | aurel32 | } else
|
2457 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
2458 | f18cd223 | aurel32 | } |
2459 | 4c9649a9 | j_mayer | break;
|
2460 | 4c9649a9 | j_mayer | case 0x0A: |
2461 | 4c9649a9 | j_mayer | /* SQRTF */
|
2462 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_FIX) {
|
2463 | a18ad893 | Richard Henderson | gen_fsqrtf(rb, rc); |
2464 | a18ad893 | Richard Henderson | break;
|
2465 | a18ad893 | Richard Henderson | } |
2466 | a18ad893 | Richard Henderson | goto invalid_opc;
|
2467 | 4c9649a9 | j_mayer | case 0x0B: |
2468 | 4c9649a9 | j_mayer | /* SQRTS */
|
2469 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_FIX) {
|
2470 | a18ad893 | Richard Henderson | gen_fsqrts(ctx, rb, rc, fn11); |
2471 | a18ad893 | Richard Henderson | break;
|
2472 | a18ad893 | Richard Henderson | } |
2473 | a18ad893 | Richard Henderson | goto invalid_opc;
|
2474 | 4c9649a9 | j_mayer | case 0x14: |
2475 | 4c9649a9 | j_mayer | /* ITOFF */
|
2476 | a18ad893 | Richard Henderson | if ((ctx->tb->flags & TB_FLAGS_AMASK_FIX) == 0) { |
2477 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2478 | a18ad893 | Richard Henderson | } |
2479 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
2480 | f18cd223 | aurel32 | if (ra != 31) { |
2481 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_temp_new_i32(); |
2482 | f18cd223 | aurel32 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
2483 | a7812ae4 | pbrook | gen_helper_memory_to_f(cpu_fir[rc], tmp); |
2484 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp); |
2485 | f18cd223 | aurel32 | } else
|
2486 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
2487 | f18cd223 | aurel32 | } |
2488 | 4c9649a9 | j_mayer | break;
|
2489 | 4c9649a9 | j_mayer | case 0x24: |
2490 | 4c9649a9 | j_mayer | /* ITOFT */
|
2491 | a18ad893 | Richard Henderson | if ((ctx->tb->flags & TB_FLAGS_AMASK_FIX) == 0) { |
2492 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2493 | a18ad893 | Richard Henderson | } |
2494 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
2495 | f18cd223 | aurel32 | if (ra != 31) |
2496 | f18cd223 | aurel32 | tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]); |
2497 | f18cd223 | aurel32 | else
|
2498 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
2499 | f18cd223 | aurel32 | } |
2500 | 4c9649a9 | j_mayer | break;
|
2501 | 4c9649a9 | j_mayer | case 0x2A: |
2502 | 4c9649a9 | j_mayer | /* SQRTG */
|
2503 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_FIX) {
|
2504 | a18ad893 | Richard Henderson | gen_fsqrtg(rb, rc); |
2505 | a18ad893 | Richard Henderson | break;
|
2506 | a18ad893 | Richard Henderson | } |
2507 | a18ad893 | Richard Henderson | goto invalid_opc;
|
2508 | 4c9649a9 | j_mayer | case 0x02B: |
2509 | 4c9649a9 | j_mayer | /* SQRTT */
|
2510 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_FIX) {
|
2511 | a18ad893 | Richard Henderson | gen_fsqrtt(ctx, rb, rc, fn11); |
2512 | a18ad893 | Richard Henderson | break;
|
2513 | a18ad893 | Richard Henderson | } |
2514 | a18ad893 | Richard Henderson | goto invalid_opc;
|
2515 | 4c9649a9 | j_mayer | default:
|
2516 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2517 | 4c9649a9 | j_mayer | } |
2518 | 4c9649a9 | j_mayer | break;
|
2519 | 4c9649a9 | j_mayer | case 0x15: |
2520 | 4c9649a9 | j_mayer | /* VAX floating point */
|
2521 | 4c9649a9 | j_mayer | /* XXX: rounding mode and trap are ignored (!) */
|
2522 | f24518b5 | Richard Henderson | switch (fpfn) { /* fn11 & 0x3F */ |
2523 | 4c9649a9 | j_mayer | case 0x00: |
2524 | 4c9649a9 | j_mayer | /* ADDF */
|
2525 | a7812ae4 | pbrook | gen_faddf(ra, rb, rc); |
2526 | 4c9649a9 | j_mayer | break;
|
2527 | 4c9649a9 | j_mayer | case 0x01: |
2528 | 4c9649a9 | j_mayer | /* SUBF */
|
2529 | a7812ae4 | pbrook | gen_fsubf(ra, rb, rc); |
2530 | 4c9649a9 | j_mayer | break;
|
2531 | 4c9649a9 | j_mayer | case 0x02: |
2532 | 4c9649a9 | j_mayer | /* MULF */
|
2533 | a7812ae4 | pbrook | gen_fmulf(ra, rb, rc); |
2534 | 4c9649a9 | j_mayer | break;
|
2535 | 4c9649a9 | j_mayer | case 0x03: |
2536 | 4c9649a9 | j_mayer | /* DIVF */
|
2537 | a7812ae4 | pbrook | gen_fdivf(ra, rb, rc); |
2538 | 4c9649a9 | j_mayer | break;
|
2539 | 4c9649a9 | j_mayer | case 0x1E: |
2540 | 4c9649a9 | j_mayer | /* CVTDG */
|
2541 | 4c9649a9 | j_mayer | #if 0 // TODO
|
2542 | a7812ae4 | pbrook | gen_fcvtdg(rb, rc);
|
2543 | 4c9649a9 | j_mayer | #else
|
2544 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2545 | 4c9649a9 | j_mayer | #endif
|
2546 | 4c9649a9 | j_mayer | break;
|
2547 | 4c9649a9 | j_mayer | case 0x20: |
2548 | 4c9649a9 | j_mayer | /* ADDG */
|
2549 | a7812ae4 | pbrook | gen_faddg(ra, rb, rc); |
2550 | 4c9649a9 | j_mayer | break;
|
2551 | 4c9649a9 | j_mayer | case 0x21: |
2552 | 4c9649a9 | j_mayer | /* SUBG */
|
2553 | a7812ae4 | pbrook | gen_fsubg(ra, rb, rc); |
2554 | 4c9649a9 | j_mayer | break;
|
2555 | 4c9649a9 | j_mayer | case 0x22: |
2556 | 4c9649a9 | j_mayer | /* MULG */
|
2557 | a7812ae4 | pbrook | gen_fmulg(ra, rb, rc); |
2558 | 4c9649a9 | j_mayer | break;
|
2559 | 4c9649a9 | j_mayer | case 0x23: |
2560 | 4c9649a9 | j_mayer | /* DIVG */
|
2561 | a7812ae4 | pbrook | gen_fdivg(ra, rb, rc); |
2562 | 4c9649a9 | j_mayer | break;
|
2563 | 4c9649a9 | j_mayer | case 0x25: |
2564 | 4c9649a9 | j_mayer | /* CMPGEQ */
|
2565 | a7812ae4 | pbrook | gen_fcmpgeq(ra, rb, rc); |
2566 | 4c9649a9 | j_mayer | break;
|
2567 | 4c9649a9 | j_mayer | case 0x26: |
2568 | 4c9649a9 | j_mayer | /* CMPGLT */
|
2569 | a7812ae4 | pbrook | gen_fcmpglt(ra, rb, rc); |
2570 | 4c9649a9 | j_mayer | break;
|
2571 | 4c9649a9 | j_mayer | case 0x27: |
2572 | 4c9649a9 | j_mayer | /* CMPGLE */
|
2573 | a7812ae4 | pbrook | gen_fcmpgle(ra, rb, rc); |
2574 | 4c9649a9 | j_mayer | break;
|
2575 | 4c9649a9 | j_mayer | case 0x2C: |
2576 | 4c9649a9 | j_mayer | /* CVTGF */
|
2577 | a7812ae4 | pbrook | gen_fcvtgf(rb, rc); |
2578 | 4c9649a9 | j_mayer | break;
|
2579 | 4c9649a9 | j_mayer | case 0x2D: |
2580 | 4c9649a9 | j_mayer | /* CVTGD */
|
2581 | 4c9649a9 | j_mayer | #if 0 // TODO
|
2582 | a7812ae4 | pbrook | gen_fcvtgd(rb, rc);
|
2583 | 4c9649a9 | j_mayer | #else
|
2584 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2585 | 4c9649a9 | j_mayer | #endif
|
2586 | 4c9649a9 | j_mayer | break;
|
2587 | 4c9649a9 | j_mayer | case 0x2F: |
2588 | 4c9649a9 | j_mayer | /* CVTGQ */
|
2589 | a7812ae4 | pbrook | gen_fcvtgq(rb, rc); |
2590 | 4c9649a9 | j_mayer | break;
|
2591 | 4c9649a9 | j_mayer | case 0x3C: |
2592 | 4c9649a9 | j_mayer | /* CVTQF */
|
2593 | a7812ae4 | pbrook | gen_fcvtqf(rb, rc); |
2594 | 4c9649a9 | j_mayer | break;
|
2595 | 4c9649a9 | j_mayer | case 0x3E: |
2596 | 4c9649a9 | j_mayer | /* CVTQG */
|
2597 | a7812ae4 | pbrook | gen_fcvtqg(rb, rc); |
2598 | 4c9649a9 | j_mayer | break;
|
2599 | 4c9649a9 | j_mayer | default:
|
2600 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2601 | 4c9649a9 | j_mayer | } |
2602 | 4c9649a9 | j_mayer | break;
|
2603 | 4c9649a9 | j_mayer | case 0x16: |
2604 | 4c9649a9 | j_mayer | /* IEEE floating-point */
|
2605 | f24518b5 | Richard Henderson | switch (fpfn) { /* fn11 & 0x3F */ |
2606 | 4c9649a9 | j_mayer | case 0x00: |
2607 | 4c9649a9 | j_mayer | /* ADDS */
|
2608 | f24518b5 | Richard Henderson | gen_fadds(ctx, ra, rb, rc, fn11); |
2609 | 4c9649a9 | j_mayer | break;
|
2610 | 4c9649a9 | j_mayer | case 0x01: |
2611 | 4c9649a9 | j_mayer | /* SUBS */
|
2612 | f24518b5 | Richard Henderson | gen_fsubs(ctx, ra, rb, rc, fn11); |
2613 | 4c9649a9 | j_mayer | break;
|
2614 | 4c9649a9 | j_mayer | case 0x02: |
2615 | 4c9649a9 | j_mayer | /* MULS */
|
2616 | f24518b5 | Richard Henderson | gen_fmuls(ctx, ra, rb, rc, fn11); |
2617 | 4c9649a9 | j_mayer | break;
|
2618 | 4c9649a9 | j_mayer | case 0x03: |
2619 | 4c9649a9 | j_mayer | /* DIVS */
|
2620 | f24518b5 | Richard Henderson | gen_fdivs(ctx, ra, rb, rc, fn11); |
2621 | 4c9649a9 | j_mayer | break;
|
2622 | 4c9649a9 | j_mayer | case 0x20: |
2623 | 4c9649a9 | j_mayer | /* ADDT */
|
2624 | f24518b5 | Richard Henderson | gen_faddt(ctx, ra, rb, rc, fn11); |
2625 | 4c9649a9 | j_mayer | break;
|
2626 | 4c9649a9 | j_mayer | case 0x21: |
2627 | 4c9649a9 | j_mayer | /* SUBT */
|
2628 | f24518b5 | Richard Henderson | gen_fsubt(ctx, ra, rb, rc, fn11); |
2629 | 4c9649a9 | j_mayer | break;
|
2630 | 4c9649a9 | j_mayer | case 0x22: |
2631 | 4c9649a9 | j_mayer | /* MULT */
|
2632 | f24518b5 | Richard Henderson | gen_fmult(ctx, ra, rb, rc, fn11); |
2633 | 4c9649a9 | j_mayer | break;
|
2634 | 4c9649a9 | j_mayer | case 0x23: |
2635 | 4c9649a9 | j_mayer | /* DIVT */
|
2636 | f24518b5 | Richard Henderson | gen_fdivt(ctx, ra, rb, rc, fn11); |
2637 | 4c9649a9 | j_mayer | break;
|
2638 | 4c9649a9 | j_mayer | case 0x24: |
2639 | 4c9649a9 | j_mayer | /* CMPTUN */
|
2640 | f24518b5 | Richard Henderson | gen_fcmptun(ctx, ra, rb, rc, fn11); |
2641 | 4c9649a9 | j_mayer | break;
|
2642 | 4c9649a9 | j_mayer | case 0x25: |
2643 | 4c9649a9 | j_mayer | /* CMPTEQ */
|
2644 | f24518b5 | Richard Henderson | gen_fcmpteq(ctx, ra, rb, rc, fn11); |
2645 | 4c9649a9 | j_mayer | break;
|
2646 | 4c9649a9 | j_mayer | case 0x26: |
2647 | 4c9649a9 | j_mayer | /* CMPTLT */
|
2648 | f24518b5 | Richard Henderson | gen_fcmptlt(ctx, ra, rb, rc, fn11); |
2649 | 4c9649a9 | j_mayer | break;
|
2650 | 4c9649a9 | j_mayer | case 0x27: |
2651 | 4c9649a9 | j_mayer | /* CMPTLE */
|
2652 | f24518b5 | Richard Henderson | gen_fcmptle(ctx, ra, rb, rc, fn11); |
2653 | 4c9649a9 | j_mayer | break;
|
2654 | 4c9649a9 | j_mayer | case 0x2C: |
2655 | a74b4d2c | aurel32 | if (fn11 == 0x2AC || fn11 == 0x6AC) { |
2656 | 4c9649a9 | j_mayer | /* CVTST */
|
2657 | f24518b5 | Richard Henderson | gen_fcvtst(ctx, rb, rc, fn11); |
2658 | 4c9649a9 | j_mayer | } else {
|
2659 | 4c9649a9 | j_mayer | /* CVTTS */
|
2660 | f24518b5 | Richard Henderson | gen_fcvtts(ctx, rb, rc, fn11); |
2661 | 4c9649a9 | j_mayer | } |
2662 | 4c9649a9 | j_mayer | break;
|
2663 | 4c9649a9 | j_mayer | case 0x2F: |
2664 | 4c9649a9 | j_mayer | /* CVTTQ */
|
2665 | f24518b5 | Richard Henderson | gen_fcvttq(ctx, rb, rc, fn11); |
2666 | 4c9649a9 | j_mayer | break;
|
2667 | 4c9649a9 | j_mayer | case 0x3C: |
2668 | 4c9649a9 | j_mayer | /* CVTQS */
|
2669 | f24518b5 | Richard Henderson | gen_fcvtqs(ctx, rb, rc, fn11); |
2670 | 4c9649a9 | j_mayer | break;
|
2671 | 4c9649a9 | j_mayer | case 0x3E: |
2672 | 4c9649a9 | j_mayer | /* CVTQT */
|
2673 | f24518b5 | Richard Henderson | gen_fcvtqt(ctx, rb, rc, fn11); |
2674 | 4c9649a9 | j_mayer | break;
|
2675 | 4c9649a9 | j_mayer | default:
|
2676 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2677 | 4c9649a9 | j_mayer | } |
2678 | 4c9649a9 | j_mayer | break;
|
2679 | 4c9649a9 | j_mayer | case 0x17: |
2680 | 4c9649a9 | j_mayer | switch (fn11) {
|
2681 | 4c9649a9 | j_mayer | case 0x010: |
2682 | 4c9649a9 | j_mayer | /* CVTLQ */
|
2683 | a7812ae4 | pbrook | gen_fcvtlq(rb, rc); |
2684 | 4c9649a9 | j_mayer | break;
|
2685 | 4c9649a9 | j_mayer | case 0x020: |
2686 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
2687 | a06d48d9 | Richard Henderson | if (ra == rb) {
|
2688 | 4c9649a9 | j_mayer | /* FMOV */
|
2689 | a06d48d9 | Richard Henderson | if (ra == 31) |
2690 | a06d48d9 | Richard Henderson | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
2691 | a06d48d9 | Richard Henderson | else
|
2692 | a06d48d9 | Richard Henderson | tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); |
2693 | a06d48d9 | Richard Henderson | } else {
|
2694 | f18cd223 | aurel32 | /* CPYS */
|
2695 | a7812ae4 | pbrook | gen_fcpys(ra, rb, rc); |
2696 | a06d48d9 | Richard Henderson | } |
2697 | 4c9649a9 | j_mayer | } |
2698 | 4c9649a9 | j_mayer | break;
|
2699 | 4c9649a9 | j_mayer | case 0x021: |
2700 | 4c9649a9 | j_mayer | /* CPYSN */
|
2701 | a7812ae4 | pbrook | gen_fcpysn(ra, rb, rc); |
2702 | 4c9649a9 | j_mayer | break;
|
2703 | 4c9649a9 | j_mayer | case 0x022: |
2704 | 4c9649a9 | j_mayer | /* CPYSE */
|
2705 | a7812ae4 | pbrook | gen_fcpyse(ra, rb, rc); |
2706 | 4c9649a9 | j_mayer | break;
|
2707 | 4c9649a9 | j_mayer | case 0x024: |
2708 | 4c9649a9 | j_mayer | /* MT_FPCR */
|
2709 | f18cd223 | aurel32 | if (likely(ra != 31)) |
2710 | a44a2777 | Richard Henderson | gen_helper_store_fpcr(cpu_env, cpu_fir[ra]); |
2711 | f18cd223 | aurel32 | else {
|
2712 | f18cd223 | aurel32 | TCGv tmp = tcg_const_i64(0);
|
2713 | a44a2777 | Richard Henderson | gen_helper_store_fpcr(cpu_env, tmp); |
2714 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
2715 | f18cd223 | aurel32 | } |
2716 | 4c9649a9 | j_mayer | break;
|
2717 | 4c9649a9 | j_mayer | case 0x025: |
2718 | 4c9649a9 | j_mayer | /* MF_FPCR */
|
2719 | f18cd223 | aurel32 | if (likely(ra != 31)) |
2720 | a44a2777 | Richard Henderson | gen_helper_load_fpcr(cpu_fir[ra], cpu_env); |
2721 | 4c9649a9 | j_mayer | break;
|
2722 | 4c9649a9 | j_mayer | case 0x02A: |
2723 | 4c9649a9 | j_mayer | /* FCMOVEQ */
|
2724 | bbe1dab4 | Richard Henderson | gen_fcmov(TCG_COND_EQ, ra, rb, rc); |
2725 | 4c9649a9 | j_mayer | break;
|
2726 | 4c9649a9 | j_mayer | case 0x02B: |
2727 | 4c9649a9 | j_mayer | /* FCMOVNE */
|
2728 | bbe1dab4 | Richard Henderson | gen_fcmov(TCG_COND_NE, ra, rb, rc); |
2729 | 4c9649a9 | j_mayer | break;
|
2730 | 4c9649a9 | j_mayer | case 0x02C: |
2731 | 4c9649a9 | j_mayer | /* FCMOVLT */
|
2732 | bbe1dab4 | Richard Henderson | gen_fcmov(TCG_COND_LT, ra, rb, rc); |
2733 | 4c9649a9 | j_mayer | break;
|
2734 | 4c9649a9 | j_mayer | case 0x02D: |
2735 | 4c9649a9 | j_mayer | /* FCMOVGE */
|
2736 | bbe1dab4 | Richard Henderson | gen_fcmov(TCG_COND_GE, ra, rb, rc); |
2737 | 4c9649a9 | j_mayer | break;
|
2738 | 4c9649a9 | j_mayer | case 0x02E: |
2739 | 4c9649a9 | j_mayer | /* FCMOVLE */
|
2740 | bbe1dab4 | Richard Henderson | gen_fcmov(TCG_COND_LE, ra, rb, rc); |
2741 | 4c9649a9 | j_mayer | break;
|
2742 | 4c9649a9 | j_mayer | case 0x02F: |
2743 | 4c9649a9 | j_mayer | /* FCMOVGT */
|
2744 | bbe1dab4 | Richard Henderson | gen_fcmov(TCG_COND_GT, ra, rb, rc); |
2745 | 4c9649a9 | j_mayer | break;
|
2746 | 4c9649a9 | j_mayer | case 0x030: |
2747 | 4c9649a9 | j_mayer | /* CVTQL */
|
2748 | a7812ae4 | pbrook | gen_fcvtql(rb, rc); |
2749 | 4c9649a9 | j_mayer | break;
|
2750 | 4c9649a9 | j_mayer | case 0x130: |
2751 | 4c9649a9 | j_mayer | /* CVTQL/V */
|
2752 | 4c9649a9 | j_mayer | case 0x530: |
2753 | 4c9649a9 | j_mayer | /* CVTQL/SV */
|
2754 | 735cf45f | Richard Henderson | /* ??? I'm pretty sure there's nothing that /sv needs to do that
|
2755 | 735cf45f | Richard Henderson | /v doesn't do. The only thing I can think is that /sv is a
|
2756 | 735cf45f | Richard Henderson | valid instruction merely for completeness in the ISA. */
|
2757 | 735cf45f | Richard Henderson | gen_fcvtql_v(ctx, rb, rc); |
2758 | 4c9649a9 | j_mayer | break;
|
2759 | 4c9649a9 | j_mayer | default:
|
2760 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2761 | 4c9649a9 | j_mayer | } |
2762 | 4c9649a9 | j_mayer | break;
|
2763 | 4c9649a9 | j_mayer | case 0x18: |
2764 | 4c9649a9 | j_mayer | switch ((uint16_t)disp16) {
|
2765 | 4c9649a9 | j_mayer | case 0x0000: |
2766 | 4c9649a9 | j_mayer | /* TRAPB */
|
2767 | 4af70374 | Richard Henderson | /* No-op. */
|
2768 | 4c9649a9 | j_mayer | break;
|
2769 | 4c9649a9 | j_mayer | case 0x0400: |
2770 | 4c9649a9 | j_mayer | /* EXCB */
|
2771 | 4af70374 | Richard Henderson | /* No-op. */
|
2772 | 4c9649a9 | j_mayer | break;
|
2773 | 4c9649a9 | j_mayer | case 0x4000: |
2774 | 4c9649a9 | j_mayer | /* MB */
|
2775 | 4c9649a9 | j_mayer | /* No-op */
|
2776 | 4c9649a9 | j_mayer | break;
|
2777 | 4c9649a9 | j_mayer | case 0x4400: |
2778 | 4c9649a9 | j_mayer | /* WMB */
|
2779 | 4c9649a9 | j_mayer | /* No-op */
|
2780 | 4c9649a9 | j_mayer | break;
|
2781 | 4c9649a9 | j_mayer | case 0x8000: |
2782 | 4c9649a9 | j_mayer | /* FETCH */
|
2783 | 4c9649a9 | j_mayer | /* No-op */
|
2784 | 4c9649a9 | j_mayer | break;
|
2785 | 4c9649a9 | j_mayer | case 0xA000: |
2786 | 4c9649a9 | j_mayer | /* FETCH_M */
|
2787 | 4c9649a9 | j_mayer | /* No-op */
|
2788 | 4c9649a9 | j_mayer | break;
|
2789 | 4c9649a9 | j_mayer | case 0xC000: |
2790 | 4c9649a9 | j_mayer | /* RPCC */
|
2791 | a9406ea1 | Richard Henderson | if (ra != 31) { |
2792 | a9406ea1 | Richard Henderson | if (use_icount) {
|
2793 | a9406ea1 | Richard Henderson | gen_io_start(); |
2794 | 69163fbb | Richard Henderson | gen_helper_load_pcc(cpu_ir[ra], cpu_env); |
2795 | a9406ea1 | Richard Henderson | gen_io_end(); |
2796 | a9406ea1 | Richard Henderson | ret = EXIT_PC_STALE; |
2797 | a9406ea1 | Richard Henderson | } else {
|
2798 | 69163fbb | Richard Henderson | gen_helper_load_pcc(cpu_ir[ra], cpu_env); |
2799 | a9406ea1 | Richard Henderson | } |
2800 | a9406ea1 | Richard Henderson | } |
2801 | 4c9649a9 | j_mayer | break;
|
2802 | 4c9649a9 | j_mayer | case 0xE000: |
2803 | 4c9649a9 | j_mayer | /* RC */
|
2804 | ac316ca4 | Richard Henderson | gen_rx(ra, 0);
|
2805 | 4c9649a9 | j_mayer | break;
|
2806 | 4c9649a9 | j_mayer | case 0xE800: |
2807 | 4c9649a9 | j_mayer | /* ECB */
|
2808 | 4c9649a9 | j_mayer | break;
|
2809 | 4c9649a9 | j_mayer | case 0xF000: |
2810 | 4c9649a9 | j_mayer | /* RS */
|
2811 | ac316ca4 | Richard Henderson | gen_rx(ra, 1);
|
2812 | 4c9649a9 | j_mayer | break;
|
2813 | 4c9649a9 | j_mayer | case 0xF800: |
2814 | 4c9649a9 | j_mayer | /* WH64 */
|
2815 | 4c9649a9 | j_mayer | /* No-op */
|
2816 | 4c9649a9 | j_mayer | break;
|
2817 | 4c9649a9 | j_mayer | default:
|
2818 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2819 | 4c9649a9 | j_mayer | } |
2820 | 4c9649a9 | j_mayer | break;
|
2821 | 4c9649a9 | j_mayer | case 0x19: |
2822 | 4c9649a9 | j_mayer | /* HW_MFPR (PALcode) */
|
2823 | 26b46094 | Richard Henderson | #ifndef CONFIG_USER_ONLY
|
2824 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
|
2825 | c781cf96 | Richard Henderson | return gen_mfpr(ra, insn & 0xffff); |
2826 | 26b46094 | Richard Henderson | } |
2827 | 26b46094 | Richard Henderson | #endif
|
2828 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2829 | 4c9649a9 | j_mayer | case 0x1A: |
2830 | 49563a72 | Richard Henderson | /* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch
|
2831 | 49563a72 | Richard Henderson | prediction stack action, which of course we don't implement. */
|
2832 | 49563a72 | Richard Henderson | if (rb != 31) { |
2833 | 3761035f | aurel32 | tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
|
2834 | 49563a72 | Richard Henderson | } else {
|
2835 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_pc, 0);
|
2836 | 49563a72 | Richard Henderson | } |
2837 | 49563a72 | Richard Henderson | if (ra != 31) { |
2838 | 1304ca87 | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
2839 | 49563a72 | Richard Henderson | } |
2840 | 4af70374 | Richard Henderson | ret = EXIT_PC_UPDATED; |
2841 | 4c9649a9 | j_mayer | break;
|
2842 | 4c9649a9 | j_mayer | case 0x1B: |
2843 | 4c9649a9 | j_mayer | /* HW_LD (PALcode) */
|
2844 | a18ad893 | Richard Henderson | #ifndef CONFIG_USER_ONLY
|
2845 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
|
2846 | a18ad893 | Richard Henderson | TCGv addr; |
2847 | a18ad893 | Richard Henderson | |
2848 | a18ad893 | Richard Henderson | if (ra == 31) { |
2849 | a18ad893 | Richard Henderson | break;
|
2850 | a18ad893 | Richard Henderson | } |
2851 | a18ad893 | Richard Henderson | |
2852 | a18ad893 | Richard Henderson | addr = tcg_temp_new(); |
2853 | 8bb6e981 | aurel32 | if (rb != 31) |
2854 | 8bb6e981 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
2855 | 8bb6e981 | aurel32 | else
|
2856 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(addr, disp12); |
2857 | 8bb6e981 | aurel32 | switch ((insn >> 12) & 0xF) { |
2858 | 8bb6e981 | aurel32 | case 0x0: |
2859 | b5d51029 | aurel32 | /* Longword physical access (hw_ldl/p) */
|
2860 | 2374e73e | Richard Henderson | gen_helper_ldl_phys(cpu_ir[ra], addr); |
2861 | 8bb6e981 | aurel32 | break;
|
2862 | 8bb6e981 | aurel32 | case 0x1: |
2863 | b5d51029 | aurel32 | /* Quadword physical access (hw_ldq/p) */
|
2864 | 2374e73e | Richard Henderson | gen_helper_ldq_phys(cpu_ir[ra], addr); |
2865 | 8bb6e981 | aurel32 | break;
|
2866 | 8bb6e981 | aurel32 | case 0x2: |
2867 | b5d51029 | aurel32 | /* Longword physical access with lock (hw_ldl_l/p) */
|
2868 | c3082755 | Richard Henderson | gen_helper_ldl_l_phys(cpu_ir[ra], cpu_env, addr); |
2869 | 8bb6e981 | aurel32 | break;
|
2870 | 8bb6e981 | aurel32 | case 0x3: |
2871 | b5d51029 | aurel32 | /* Quadword physical access with lock (hw_ldq_l/p) */
|
2872 | c3082755 | Richard Henderson | gen_helper_ldq_l_phys(cpu_ir[ra], cpu_env, addr); |
2873 | 8bb6e981 | aurel32 | break;
|
2874 | 8bb6e981 | aurel32 | case 0x4: |
2875 | b5d51029 | aurel32 | /* Longword virtual PTE fetch (hw_ldl/v) */
|
2876 | 2374e73e | Richard Henderson | goto invalid_opc;
|
2877 | 8bb6e981 | aurel32 | case 0x5: |
2878 | b5d51029 | aurel32 | /* Quadword virtual PTE fetch (hw_ldq/v) */
|
2879 | 2374e73e | Richard Henderson | goto invalid_opc;
|
2880 | 8bb6e981 | aurel32 | break;
|
2881 | 8bb6e981 | aurel32 | case 0x6: |
2882 | 8bb6e981 | aurel32 | /* Incpu_ir[ra]id */
|
2883 | b5d51029 | aurel32 | goto invalid_opc;
|
2884 | 8bb6e981 | aurel32 | case 0x7: |
2885 | 8bb6e981 | aurel32 | /* Incpu_ir[ra]id */
|
2886 | b5d51029 | aurel32 | goto invalid_opc;
|
2887 | 8bb6e981 | aurel32 | case 0x8: |
2888 | b5d51029 | aurel32 | /* Longword virtual access (hw_ldl) */
|
2889 | 2374e73e | Richard Henderson | goto invalid_opc;
|
2890 | 8bb6e981 | aurel32 | case 0x9: |
2891 | b5d51029 | aurel32 | /* Quadword virtual access (hw_ldq) */
|
2892 | 2374e73e | Richard Henderson | goto invalid_opc;
|
2893 | 8bb6e981 | aurel32 | case 0xA: |
2894 | b5d51029 | aurel32 | /* Longword virtual access with protection check (hw_ldl/w) */
|
2895 | 8417845e | Richard Henderson | tcg_gen_qemu_ld32s(cpu_ir[ra], addr, MMU_KERNEL_IDX); |
2896 | 8bb6e981 | aurel32 | break;
|
2897 | 8bb6e981 | aurel32 | case 0xB: |
2898 | b5d51029 | aurel32 | /* Quadword virtual access with protection check (hw_ldq/w) */
|
2899 | 8417845e | Richard Henderson | tcg_gen_qemu_ld64(cpu_ir[ra], addr, MMU_KERNEL_IDX); |
2900 | 8bb6e981 | aurel32 | break;
|
2901 | 8bb6e981 | aurel32 | case 0xC: |
2902 | b5d51029 | aurel32 | /* Longword virtual access with alt access mode (hw_ldl/a)*/
|
2903 | 2374e73e | Richard Henderson | goto invalid_opc;
|
2904 | 8bb6e981 | aurel32 | case 0xD: |
2905 | b5d51029 | aurel32 | /* Quadword virtual access with alt access mode (hw_ldq/a) */
|
2906 | 2374e73e | Richard Henderson | goto invalid_opc;
|
2907 | 8bb6e981 | aurel32 | case 0xE: |
2908 | 8bb6e981 | aurel32 | /* Longword virtual access with alternate access mode and
|
2909 | 2374e73e | Richard Henderson | protection checks (hw_ldl/wa) */
|
2910 | 2374e73e | Richard Henderson | tcg_gen_qemu_ld32s(cpu_ir[ra], addr, MMU_USER_IDX); |
2911 | 8bb6e981 | aurel32 | break;
|
2912 | 8bb6e981 | aurel32 | case 0xF: |
2913 | 8bb6e981 | aurel32 | /* Quadword virtual access with alternate access mode and
|
2914 | 2374e73e | Richard Henderson | protection checks (hw_ldq/wa) */
|
2915 | 2374e73e | Richard Henderson | tcg_gen_qemu_ld64(cpu_ir[ra], addr, MMU_USER_IDX); |
2916 | 8bb6e981 | aurel32 | break;
|
2917 | 8bb6e981 | aurel32 | } |
2918 | 8bb6e981 | aurel32 | tcg_temp_free(addr); |
2919 | a18ad893 | Richard Henderson | break;
|
2920 | 4c9649a9 | j_mayer | } |
2921 | 4c9649a9 | j_mayer | #endif
|
2922 | a18ad893 | Richard Henderson | goto invalid_opc;
|
2923 | 4c9649a9 | j_mayer | case 0x1C: |
2924 | 4c9649a9 | j_mayer | switch (fn7) {
|
2925 | 4c9649a9 | j_mayer | case 0x00: |
2926 | 4c9649a9 | j_mayer | /* SEXTB */
|
2927 | a18ad893 | Richard Henderson | if ((ctx->tb->flags & TB_FLAGS_AMASK_BWX) == 0) { |
2928 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2929 | a18ad893 | Richard Henderson | } |
2930 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
2931 | ae8ecd42 | aurel32 | if (islit)
|
2932 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit)); |
2933 | ae8ecd42 | aurel32 | else
|
2934 | dfaa8583 | aurel32 | tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]); |
2935 | ae8ecd42 | aurel32 | } |
2936 | 4c9649a9 | j_mayer | break;
|
2937 | 4c9649a9 | j_mayer | case 0x01: |
2938 | 4c9649a9 | j_mayer | /* SEXTW */
|
2939 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_BWX) {
|
2940 | a18ad893 | Richard Henderson | if (likely(rc != 31)) { |
2941 | a18ad893 | Richard Henderson | if (islit) {
|
2942 | a18ad893 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit)); |
2943 | a18ad893 | Richard Henderson | } else {
|
2944 | a18ad893 | Richard Henderson | tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]); |
2945 | a18ad893 | Richard Henderson | } |
2946 | a18ad893 | Richard Henderson | } |
2947 | a18ad893 | Richard Henderson | break;
|
2948 | ae8ecd42 | aurel32 | } |
2949 | a18ad893 | Richard Henderson | goto invalid_opc;
|
2950 | 4c9649a9 | j_mayer | case 0x30: |
2951 | 4c9649a9 | j_mayer | /* CTPOP */
|
2952 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_CIX) {
|
2953 | a18ad893 | Richard Henderson | if (likely(rc != 31)) { |
2954 | a18ad893 | Richard Henderson | if (islit) {
|
2955 | a18ad893 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit)); |
2956 | a18ad893 | Richard Henderson | } else {
|
2957 | a18ad893 | Richard Henderson | gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]); |
2958 | a18ad893 | Richard Henderson | } |
2959 | a18ad893 | Richard Henderson | } |
2960 | a18ad893 | Richard Henderson | break;
|
2961 | ae8ecd42 | aurel32 | } |
2962 | a18ad893 | Richard Henderson | goto invalid_opc;
|
2963 | 4c9649a9 | j_mayer | case 0x31: |
2964 | 4c9649a9 | j_mayer | /* PERR */
|
2965 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
2966 | a18ad893 | Richard Henderson | gen_perr(ra, rb, rc, islit, lit); |
2967 | a18ad893 | Richard Henderson | break;
|
2968 | a18ad893 | Richard Henderson | } |
2969 | a18ad893 | Richard Henderson | goto invalid_opc;
|
2970 | 4c9649a9 | j_mayer | case 0x32: |
2971 | 4c9649a9 | j_mayer | /* CTLZ */
|
2972 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_CIX) {
|
2973 | a18ad893 | Richard Henderson | if (likely(rc != 31)) { |
2974 | a18ad893 | Richard Henderson | if (islit) {
|
2975 | a18ad893 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], clz64(lit)); |
2976 | a18ad893 | Richard Henderson | } else {
|
2977 | a18ad893 | Richard Henderson | gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]); |
2978 | a18ad893 | Richard Henderson | } |
2979 | a18ad893 | Richard Henderson | } |
2980 | a18ad893 | Richard Henderson | break;
|
2981 | ae8ecd42 | aurel32 | } |
2982 | a18ad893 | Richard Henderson | goto invalid_opc;
|
2983 | 4c9649a9 | j_mayer | case 0x33: |
2984 | 4c9649a9 | j_mayer | /* CTTZ */
|
2985 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_CIX) {
|
2986 | a18ad893 | Richard Henderson | if (likely(rc != 31)) { |
2987 | a18ad893 | Richard Henderson | if (islit) {
|
2988 | a18ad893 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit)); |
2989 | a18ad893 | Richard Henderson | } else {
|
2990 | a18ad893 | Richard Henderson | gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]); |
2991 | a18ad893 | Richard Henderson | } |
2992 | a18ad893 | Richard Henderson | } |
2993 | a18ad893 | Richard Henderson | break;
|
2994 | ae8ecd42 | aurel32 | } |
2995 | a18ad893 | Richard Henderson | goto invalid_opc;
|
2996 | 4c9649a9 | j_mayer | case 0x34: |
2997 | 4c9649a9 | j_mayer | /* UNPKBW */
|
2998 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
2999 | a18ad893 | Richard Henderson | if (real_islit || ra != 31) { |
3000 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3001 | a18ad893 | Richard Henderson | } |
3002 | a18ad893 | Richard Henderson | gen_unpkbw(rb, rc); |
3003 | a18ad893 | Richard Henderson | break;
|
3004 | a18ad893 | Richard Henderson | } |
3005 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3006 | 4c9649a9 | j_mayer | case 0x35: |
3007 | 13e4df99 | Richard Henderson | /* UNPKBL */
|
3008 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
3009 | a18ad893 | Richard Henderson | if (real_islit || ra != 31) { |
3010 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3011 | a18ad893 | Richard Henderson | } |
3012 | a18ad893 | Richard Henderson | gen_unpkbl(rb, rc); |
3013 | a18ad893 | Richard Henderson | break;
|
3014 | a18ad893 | Richard Henderson | } |
3015 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3016 | 4c9649a9 | j_mayer | case 0x36: |
3017 | 4c9649a9 | j_mayer | /* PKWB */
|
3018 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
3019 | a18ad893 | Richard Henderson | if (real_islit || ra != 31) { |
3020 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3021 | a18ad893 | Richard Henderson | } |
3022 | a18ad893 | Richard Henderson | gen_pkwb(rb, rc); |
3023 | a18ad893 | Richard Henderson | break;
|
3024 | a18ad893 | Richard Henderson | } |
3025 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3026 | 4c9649a9 | j_mayer | case 0x37: |
3027 | 4c9649a9 | j_mayer | /* PKLB */
|
3028 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
3029 | a18ad893 | Richard Henderson | if (real_islit || ra != 31) { |
3030 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3031 | a18ad893 | Richard Henderson | } |
3032 | a18ad893 | Richard Henderson | gen_pklb(rb, rc); |
3033 | a18ad893 | Richard Henderson | break;
|
3034 | a18ad893 | Richard Henderson | } |
3035 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3036 | 4c9649a9 | j_mayer | case 0x38: |
3037 | 4c9649a9 | j_mayer | /* MINSB8 */
|
3038 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
3039 | a18ad893 | Richard Henderson | gen_minsb8(ra, rb, rc, islit, lit); |
3040 | a18ad893 | Richard Henderson | break;
|
3041 | a18ad893 | Richard Henderson | } |
3042 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3043 | 4c9649a9 | j_mayer | case 0x39: |
3044 | 4c9649a9 | j_mayer | /* MINSW4 */
|
3045 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
3046 | a18ad893 | Richard Henderson | gen_minsw4(ra, rb, rc, islit, lit); |
3047 | a18ad893 | Richard Henderson | break;
|
3048 | a18ad893 | Richard Henderson | } |
3049 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3050 | 4c9649a9 | j_mayer | case 0x3A: |
3051 | 4c9649a9 | j_mayer | /* MINUB8 */
|
3052 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
3053 | a18ad893 | Richard Henderson | gen_minub8(ra, rb, rc, islit, lit); |
3054 | a18ad893 | Richard Henderson | break;
|
3055 | a18ad893 | Richard Henderson | } |
3056 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3057 | 4c9649a9 | j_mayer | case 0x3B: |
3058 | 4c9649a9 | j_mayer | /* MINUW4 */
|
3059 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
3060 | a18ad893 | Richard Henderson | gen_minuw4(ra, rb, rc, islit, lit); |
3061 | a18ad893 | Richard Henderson | break;
|
3062 | a18ad893 | Richard Henderson | } |
3063 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3064 | 4c9649a9 | j_mayer | case 0x3C: |
3065 | 4c9649a9 | j_mayer | /* MAXUB8 */
|
3066 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
3067 | a18ad893 | Richard Henderson | gen_maxub8(ra, rb, rc, islit, lit); |
3068 | a18ad893 | Richard Henderson | break;
|
3069 | a18ad893 | Richard Henderson | } |
3070 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3071 | 4c9649a9 | j_mayer | case 0x3D: |
3072 | 4c9649a9 | j_mayer | /* MAXUW4 */
|
3073 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
3074 | a18ad893 | Richard Henderson | gen_maxuw4(ra, rb, rc, islit, lit); |
3075 | a18ad893 | Richard Henderson | break;
|
3076 | a18ad893 | Richard Henderson | } |
3077 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3078 | 4c9649a9 | j_mayer | case 0x3E: |
3079 | 4c9649a9 | j_mayer | /* MAXSB8 */
|
3080 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
3081 | a18ad893 | Richard Henderson | gen_maxsb8(ra, rb, rc, islit, lit); |
3082 | a18ad893 | Richard Henderson | break;
|
3083 | a18ad893 | Richard Henderson | } |
3084 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3085 | 4c9649a9 | j_mayer | case 0x3F: |
3086 | 4c9649a9 | j_mayer | /* MAXSW4 */
|
3087 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_AMASK_MVI) {
|
3088 | a18ad893 | Richard Henderson | gen_maxsw4(ra, rb, rc, islit, lit); |
3089 | a18ad893 | Richard Henderson | break;
|
3090 | a18ad893 | Richard Henderson | } |
3091 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3092 | 4c9649a9 | j_mayer | case 0x70: |
3093 | 4c9649a9 | j_mayer | /* FTOIT */
|
3094 | a18ad893 | Richard Henderson | if ((ctx->tb->flags & TB_FLAGS_AMASK_FIX) == 0) { |
3095 | 4c9649a9 | j_mayer | goto invalid_opc;
|
3096 | a18ad893 | Richard Henderson | } |
3097 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
3098 | f18cd223 | aurel32 | if (ra != 31) |
3099 | f18cd223 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]); |
3100 | f18cd223 | aurel32 | else
|
3101 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
3102 | f18cd223 | aurel32 | } |
3103 | 4c9649a9 | j_mayer | break;
|
3104 | 4c9649a9 | j_mayer | case 0x78: |
3105 | 4c9649a9 | j_mayer | /* FTOIS */
|
3106 | a18ad893 | Richard Henderson | if ((ctx->tb->flags & TB_FLAGS_AMASK_FIX) == 0) { |
3107 | 4c9649a9 | j_mayer | goto invalid_opc;
|
3108 | a18ad893 | Richard Henderson | } |
3109 | f18cd223 | aurel32 | if (rc != 31) { |
3110 | a7812ae4 | pbrook | TCGv_i32 tmp1 = tcg_temp_new_i32(); |
3111 | f18cd223 | aurel32 | if (ra != 31) |
3112 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp1, cpu_fir[ra]); |
3113 | f18cd223 | aurel32 | else {
|
3114 | f18cd223 | aurel32 | TCGv tmp2 = tcg_const_i64(0);
|
3115 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp1, tmp2); |
3116 | f18cd223 | aurel32 | tcg_temp_free(tmp2); |
3117 | f18cd223 | aurel32 | } |
3118 | f18cd223 | aurel32 | tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1); |
3119 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp1); |
3120 | f18cd223 | aurel32 | } |
3121 | 4c9649a9 | j_mayer | break;
|
3122 | 4c9649a9 | j_mayer | default:
|
3123 | 4c9649a9 | j_mayer | goto invalid_opc;
|
3124 | 4c9649a9 | j_mayer | } |
3125 | 4c9649a9 | j_mayer | break;
|
3126 | 4c9649a9 | j_mayer | case 0x1D: |
3127 | 4c9649a9 | j_mayer | /* HW_MTPR (PALcode) */
|
3128 | 26b46094 | Richard Henderson | #ifndef CONFIG_USER_ONLY
|
3129 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
|
3130 | bc24270e | Richard Henderson | return gen_mtpr(ctx, rb, insn & 0xffff); |
3131 | 26b46094 | Richard Henderson | } |
3132 | 26b46094 | Richard Henderson | #endif
|
3133 | 4c9649a9 | j_mayer | goto invalid_opc;
|
3134 | 4c9649a9 | j_mayer | case 0x1E: |
3135 | 508b43ea | Richard Henderson | /* HW_RET (PALcode) */
|
3136 | a18ad893 | Richard Henderson | #ifndef CONFIG_USER_ONLY
|
3137 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
|
3138 | a18ad893 | Richard Henderson | if (rb == 31) { |
3139 | a18ad893 | Richard Henderson | /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return
|
3140 | a18ad893 | Richard Henderson | address from EXC_ADDR. This turns out to be useful for our
|
3141 | a18ad893 | Richard Henderson | emulation PALcode, so continue to accept it. */
|
3142 | a18ad893 | Richard Henderson | TCGv tmp = tcg_temp_new(); |
3143 | 4d5712f1 | Andreas Färber | tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr)); |
3144 | 69163fbb | Richard Henderson | gen_helper_hw_ret(cpu_env, tmp); |
3145 | a18ad893 | Richard Henderson | tcg_temp_free(tmp); |
3146 | a18ad893 | Richard Henderson | } else {
|
3147 | 69163fbb | Richard Henderson | gen_helper_hw_ret(cpu_env, cpu_ir[rb]); |
3148 | a18ad893 | Richard Henderson | } |
3149 | a18ad893 | Richard Henderson | ret = EXIT_PC_UPDATED; |
3150 | a18ad893 | Richard Henderson | break;
|
3151 | 4c9649a9 | j_mayer | } |
3152 | 4c9649a9 | j_mayer | #endif
|
3153 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3154 | 4c9649a9 | j_mayer | case 0x1F: |
3155 | 4c9649a9 | j_mayer | /* HW_ST (PALcode) */
|
3156 | a18ad893 | Richard Henderson | #ifndef CONFIG_USER_ONLY
|
3157 | a18ad893 | Richard Henderson | if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
|
3158 | 8bb6e981 | aurel32 | TCGv addr, val; |
3159 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
3160 | 8bb6e981 | aurel32 | if (rb != 31) |
3161 | 8bb6e981 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
3162 | 8bb6e981 | aurel32 | else
|
3163 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(addr, disp12); |
3164 | 8bb6e981 | aurel32 | if (ra != 31) |
3165 | 8bb6e981 | aurel32 | val = cpu_ir[ra]; |
3166 | 8bb6e981 | aurel32 | else {
|
3167 | a7812ae4 | pbrook | val = tcg_temp_new(); |
3168 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(val, 0);
|
3169 | 8bb6e981 | aurel32 | } |
3170 | 8bb6e981 | aurel32 | switch ((insn >> 12) & 0xF) { |
3171 | 8bb6e981 | aurel32 | case 0x0: |
3172 | 8bb6e981 | aurel32 | /* Longword physical access */
|
3173 | 2374e73e | Richard Henderson | gen_helper_stl_phys(addr, val); |
3174 | 8bb6e981 | aurel32 | break;
|
3175 | 8bb6e981 | aurel32 | case 0x1: |
3176 | 8bb6e981 | aurel32 | /* Quadword physical access */
|
3177 | 2374e73e | Richard Henderson | gen_helper_stq_phys(addr, val); |
3178 | 8bb6e981 | aurel32 | break;
|
3179 | 8bb6e981 | aurel32 | case 0x2: |
3180 | 8bb6e981 | aurel32 | /* Longword physical access with lock */
|
3181 | c3082755 | Richard Henderson | gen_helper_stl_c_phys(val, cpu_env, addr, val); |
3182 | 8bb6e981 | aurel32 | break;
|
3183 | 8bb6e981 | aurel32 | case 0x3: |
3184 | 8bb6e981 | aurel32 | /* Quadword physical access with lock */
|
3185 | c3082755 | Richard Henderson | gen_helper_stq_c_phys(val, cpu_env, addr, val); |
3186 | 8bb6e981 | aurel32 | break;
|
3187 | 8bb6e981 | aurel32 | case 0x4: |
3188 | 8bb6e981 | aurel32 | /* Longword virtual access */
|
3189 | 2374e73e | Richard Henderson | goto invalid_opc;
|
3190 | 8bb6e981 | aurel32 | case 0x5: |
3191 | 8bb6e981 | aurel32 | /* Quadword virtual access */
|
3192 | 2374e73e | Richard Henderson | goto invalid_opc;
|
3193 | 8bb6e981 | aurel32 | case 0x6: |
3194 | 8bb6e981 | aurel32 | /* Invalid */
|
3195 | 8bb6e981 | aurel32 | goto invalid_opc;
|
3196 | 8bb6e981 | aurel32 | case 0x7: |
3197 | 8bb6e981 | aurel32 | /* Invalid */
|
3198 | 8bb6e981 | aurel32 | goto invalid_opc;
|
3199 | 8bb6e981 | aurel32 | case 0x8: |
3200 | 8bb6e981 | aurel32 | /* Invalid */
|
3201 | 8bb6e981 | aurel32 | goto invalid_opc;
|
3202 | 8bb6e981 | aurel32 | case 0x9: |
3203 | 8bb6e981 | aurel32 | /* Invalid */
|
3204 | 8bb6e981 | aurel32 | goto invalid_opc;
|
3205 | 8bb6e981 | aurel32 | case 0xA: |
3206 | 8bb6e981 | aurel32 | /* Invalid */
|
3207 | 8bb6e981 | aurel32 | goto invalid_opc;
|
3208 | 8bb6e981 | aurel32 | case 0xB: |
3209 | 8bb6e981 | aurel32 | /* Invalid */
|
3210 | 8bb6e981 | aurel32 | goto invalid_opc;
|
3211 | 8bb6e981 | aurel32 | case 0xC: |
3212 | 8bb6e981 | aurel32 | /* Longword virtual access with alternate access mode */
|
3213 | 2374e73e | Richard Henderson | goto invalid_opc;
|
3214 | 8bb6e981 | aurel32 | case 0xD: |
3215 | 8bb6e981 | aurel32 | /* Quadword virtual access with alternate access mode */
|
3216 | 2374e73e | Richard Henderson | goto invalid_opc;
|
3217 | 8bb6e981 | aurel32 | case 0xE: |
3218 | 8bb6e981 | aurel32 | /* Invalid */
|
3219 | 8bb6e981 | aurel32 | goto invalid_opc;
|
3220 | 8bb6e981 | aurel32 | case 0xF: |
3221 | 8bb6e981 | aurel32 | /* Invalid */
|
3222 | 8bb6e981 | aurel32 | goto invalid_opc;
|
3223 | 8bb6e981 | aurel32 | } |
3224 | 45d46ce8 | aurel32 | if (ra == 31) |
3225 | 8bb6e981 | aurel32 | tcg_temp_free(val); |
3226 | 8bb6e981 | aurel32 | tcg_temp_free(addr); |
3227 | a18ad893 | Richard Henderson | break;
|
3228 | 4c9649a9 | j_mayer | } |
3229 | 4c9649a9 | j_mayer | #endif
|
3230 | a18ad893 | Richard Henderson | goto invalid_opc;
|
3231 | 4c9649a9 | j_mayer | case 0x20: |
3232 | 4c9649a9 | j_mayer | /* LDF */
|
3233 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); |
3234 | 4c9649a9 | j_mayer | break;
|
3235 | 4c9649a9 | j_mayer | case 0x21: |
3236 | 4c9649a9 | j_mayer | /* LDG */
|
3237 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0); |
3238 | 4c9649a9 | j_mayer | break;
|
3239 | 4c9649a9 | j_mayer | case 0x22: |
3240 | 4c9649a9 | j_mayer | /* LDS */
|
3241 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0); |
3242 | 4c9649a9 | j_mayer | break;
|
3243 | 4c9649a9 | j_mayer | case 0x23: |
3244 | 4c9649a9 | j_mayer | /* LDT */
|
3245 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0); |
3246 | 4c9649a9 | j_mayer | break;
|
3247 | 4c9649a9 | j_mayer | case 0x24: |
3248 | 4c9649a9 | j_mayer | /* STF */
|
3249 | 6910b8f6 | Richard Henderson | gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0); |
3250 | 4c9649a9 | j_mayer | break;
|
3251 | 4c9649a9 | j_mayer | case 0x25: |
3252 | 4c9649a9 | j_mayer | /* STG */
|
3253 | 6910b8f6 | Richard Henderson | gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0); |
3254 | 4c9649a9 | j_mayer | break;
|
3255 | 4c9649a9 | j_mayer | case 0x26: |
3256 | 4c9649a9 | j_mayer | /* STS */
|
3257 | 6910b8f6 | Richard Henderson | gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0); |
3258 | 4c9649a9 | j_mayer | break;
|
3259 | 4c9649a9 | j_mayer | case 0x27: |
3260 | 4c9649a9 | j_mayer | /* STT */
|
3261 | 6910b8f6 | Richard Henderson | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0); |
3262 | 4c9649a9 | j_mayer | break;
|
3263 | 4c9649a9 | j_mayer | case 0x28: |
3264 | 4c9649a9 | j_mayer | /* LDL */
|
3265 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0); |
3266 | 4c9649a9 | j_mayer | break;
|
3267 | 4c9649a9 | j_mayer | case 0x29: |
3268 | 4c9649a9 | j_mayer | /* LDQ */
|
3269 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0); |
3270 | 4c9649a9 | j_mayer | break;
|
3271 | 4c9649a9 | j_mayer | case 0x2A: |
3272 | 4c9649a9 | j_mayer | /* LDL_L */
|
3273 | f4ed8679 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0); |
3274 | 4c9649a9 | j_mayer | break;
|
3275 | 4c9649a9 | j_mayer | case 0x2B: |
3276 | 4c9649a9 | j_mayer | /* LDQ_L */
|
3277 | f4ed8679 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0); |
3278 | 4c9649a9 | j_mayer | break;
|
3279 | 4c9649a9 | j_mayer | case 0x2C: |
3280 | 4c9649a9 | j_mayer | /* STL */
|
3281 | 6910b8f6 | Richard Henderson | gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0); |
3282 | 4c9649a9 | j_mayer | break;
|
3283 | 4c9649a9 | j_mayer | case 0x2D: |
3284 | 4c9649a9 | j_mayer | /* STQ */
|
3285 | 6910b8f6 | Richard Henderson | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0); |
3286 | 4c9649a9 | j_mayer | break;
|
3287 | 4c9649a9 | j_mayer | case 0x2E: |
3288 | 4c9649a9 | j_mayer | /* STL_C */
|
3289 | 6910b8f6 | Richard Henderson | ret = gen_store_conditional(ctx, ra, rb, disp16, 0);
|
3290 | 4c9649a9 | j_mayer | break;
|
3291 | 4c9649a9 | j_mayer | case 0x2F: |
3292 | 4c9649a9 | j_mayer | /* STQ_C */
|
3293 | 6910b8f6 | Richard Henderson | ret = gen_store_conditional(ctx, ra, rb, disp16, 1);
|
3294 | 4c9649a9 | j_mayer | break;
|
3295 | 4c9649a9 | j_mayer | case 0x30: |
3296 | 4c9649a9 | j_mayer | /* BR */
|
3297 | 4af70374 | Richard Henderson | ret = gen_bdirect(ctx, ra, disp21); |
3298 | 4c9649a9 | j_mayer | break;
|
3299 | a7812ae4 | pbrook | case 0x31: /* FBEQ */ |
3300 | 4af70374 | Richard Henderson | ret = gen_fbcond(ctx, TCG_COND_EQ, ra, disp21); |
3301 | dbb30fe6 | Richard Henderson | break;
|
3302 | a7812ae4 | pbrook | case 0x32: /* FBLT */ |
3303 | 4af70374 | Richard Henderson | ret = gen_fbcond(ctx, TCG_COND_LT, ra, disp21); |
3304 | dbb30fe6 | Richard Henderson | break;
|
3305 | a7812ae4 | pbrook | case 0x33: /* FBLE */ |
3306 | 4af70374 | Richard Henderson | ret = gen_fbcond(ctx, TCG_COND_LE, ra, disp21); |
3307 | 4c9649a9 | j_mayer | break;
|
3308 | 4c9649a9 | j_mayer | case 0x34: |
3309 | 4c9649a9 | j_mayer | /* BSR */
|
3310 | 4af70374 | Richard Henderson | ret = gen_bdirect(ctx, ra, disp21); |
3311 | 4c9649a9 | j_mayer | break;
|
3312 | a7812ae4 | pbrook | case 0x35: /* FBNE */ |
3313 | 4af70374 | Richard Henderson | ret = gen_fbcond(ctx, TCG_COND_NE, ra, disp21); |
3314 | dbb30fe6 | Richard Henderson | break;
|
3315 | a7812ae4 | pbrook | case 0x36: /* FBGE */ |
3316 | 4af70374 | Richard Henderson | ret = gen_fbcond(ctx, TCG_COND_GE, ra, disp21); |
3317 | dbb30fe6 | Richard Henderson | break;
|
3318 | a7812ae4 | pbrook | case 0x37: /* FBGT */ |
3319 | 4af70374 | Richard Henderson | ret = gen_fbcond(ctx, TCG_COND_GT, ra, disp21); |
3320 | 4c9649a9 | j_mayer | break;
|
3321 | 4c9649a9 | j_mayer | case 0x38: |
3322 | 4c9649a9 | j_mayer | /* BLBC */
|
3323 | 4af70374 | Richard Henderson | ret = gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1);
|
3324 | 4c9649a9 | j_mayer | break;
|
3325 | 4c9649a9 | j_mayer | case 0x39: |
3326 | 4c9649a9 | j_mayer | /* BEQ */
|
3327 | 4af70374 | Richard Henderson | ret = gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0);
|
3328 | 4c9649a9 | j_mayer | break;
|
3329 | 4c9649a9 | j_mayer | case 0x3A: |
3330 | 4c9649a9 | j_mayer | /* BLT */
|
3331 | 4af70374 | Richard Henderson | ret = gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0);
|
3332 | 4c9649a9 | j_mayer | break;
|
3333 | 4c9649a9 | j_mayer | case 0x3B: |
3334 | 4c9649a9 | j_mayer | /* BLE */
|
3335 | 4af70374 | Richard Henderson | ret = gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0);
|
3336 | 4c9649a9 | j_mayer | break;
|
3337 | 4c9649a9 | j_mayer | case 0x3C: |
3338 | 4c9649a9 | j_mayer | /* BLBS */
|
3339 | 4af70374 | Richard Henderson | ret = gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1);
|
3340 | 4c9649a9 | j_mayer | break;
|
3341 | 4c9649a9 | j_mayer | case 0x3D: |
3342 | 4c9649a9 | j_mayer | /* BNE */
|
3343 | 4af70374 | Richard Henderson | ret = gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0);
|
3344 | 4c9649a9 | j_mayer | break;
|
3345 | 4c9649a9 | j_mayer | case 0x3E: |
3346 | 4c9649a9 | j_mayer | /* BGE */
|
3347 | 4af70374 | Richard Henderson | ret = gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0);
|
3348 | 4c9649a9 | j_mayer | break;
|
3349 | 4c9649a9 | j_mayer | case 0x3F: |
3350 | 4c9649a9 | j_mayer | /* BGT */
|
3351 | 4af70374 | Richard Henderson | ret = gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0);
|
3352 | 4c9649a9 | j_mayer | break;
|
3353 | 4c9649a9 | j_mayer | invalid_opc:
|
3354 | 8aa3fa20 | Richard Henderson | ret = gen_invalid(ctx); |
3355 | 4c9649a9 | j_mayer | break;
|
3356 | 4c9649a9 | j_mayer | } |
3357 | 4c9649a9 | j_mayer | |
3358 | 4c9649a9 | j_mayer | return ret;
|
3359 | 4c9649a9 | j_mayer | } |
3360 | 4c9649a9 | j_mayer | |
3361 | 4d5712f1 | Andreas Färber | static inline void gen_intermediate_code_internal(CPUAlphaState *env, |
3362 | 636aa200 | Blue Swirl | TranslationBlock *tb, |
3363 | 636aa200 | Blue Swirl | int search_pc)
|
3364 | 4c9649a9 | j_mayer | { |
3365 | 4c9649a9 | j_mayer | DisasContext ctx, *ctxp = &ctx; |
3366 | 4c9649a9 | j_mayer | target_ulong pc_start; |
3367 | 4c9649a9 | j_mayer | uint32_t insn; |
3368 | 4c9649a9 | j_mayer | uint16_t *gen_opc_end; |
3369 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
3370 | 4c9649a9 | j_mayer | int j, lj = -1; |
3371 | 4af70374 | Richard Henderson | ExitStatus ret; |
3372 | 2e70f6ef | pbrook | int num_insns;
|
3373 | 2e70f6ef | pbrook | int max_insns;
|
3374 | 4c9649a9 | j_mayer | |
3375 | 4c9649a9 | j_mayer | pc_start = tb->pc; |
3376 | 4c9649a9 | j_mayer | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
3377 | 4af70374 | Richard Henderson | |
3378 | 4af70374 | Richard Henderson | ctx.tb = tb; |
3379 | 4af70374 | Richard Henderson | ctx.env = env; |
3380 | 4c9649a9 | j_mayer | ctx.pc = pc_start; |
3381 | bba9bdce | Richard Henderson | ctx.mem_idx = cpu_mmu_index(env); |
3382 | f24518b5 | Richard Henderson | |
3383 | f24518b5 | Richard Henderson | /* ??? Every TB begins with unset rounding mode, to be initialized on
|
3384 | f24518b5 | Richard Henderson | the first fp insn of the TB. Alternately we could define a proper
|
3385 | f24518b5 | Richard Henderson | default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure
|
3386 | f24518b5 | Richard Henderson | to reset the FP_STATUS to that default at the end of any TB that
|
3387 | f24518b5 | Richard Henderson | changes the default. We could even (gasp) dynamiclly figure out
|
3388 | f24518b5 | Richard Henderson | what default would be most efficient given the running program. */
|
3389 | f24518b5 | Richard Henderson | ctx.tb_rm = -1;
|
3390 | f24518b5 | Richard Henderson | /* Similarly for flush-to-zero. */
|
3391 | f24518b5 | Richard Henderson | ctx.tb_ftz = -1;
|
3392 | f24518b5 | Richard Henderson | |
3393 | 2e70f6ef | pbrook | num_insns = 0;
|
3394 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
3395 | 2e70f6ef | pbrook | if (max_insns == 0) |
3396 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
3397 | 2e70f6ef | pbrook | |
3398 | 2e70f6ef | pbrook | gen_icount_start(); |
3399 | 4af70374 | Richard Henderson | do {
|
3400 | 72cf2d4f | Blue Swirl | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
3401 | 72cf2d4f | Blue Swirl | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
3402 | a1d1bb31 | aliguori | if (bp->pc == ctx.pc) {
|
3403 | 4c9649a9 | j_mayer | gen_excp(&ctx, EXCP_DEBUG, 0);
|
3404 | 4c9649a9 | j_mayer | break;
|
3405 | 4c9649a9 | j_mayer | } |
3406 | 4c9649a9 | j_mayer | } |
3407 | 4c9649a9 | j_mayer | } |
3408 | 4c9649a9 | j_mayer | if (search_pc) {
|
3409 | 4c9649a9 | j_mayer | j = gen_opc_ptr - gen_opc_buf; |
3410 | 4c9649a9 | j_mayer | if (lj < j) {
|
3411 | 4c9649a9 | j_mayer | lj++; |
3412 | 4c9649a9 | j_mayer | while (lj < j)
|
3413 | 4c9649a9 | j_mayer | gen_opc_instr_start[lj++] = 0;
|
3414 | 4c9649a9 | j_mayer | } |
3415 | ed1dda53 | aurel32 | gen_opc_pc[lj] = ctx.pc; |
3416 | ed1dda53 | aurel32 | gen_opc_instr_start[lj] = 1;
|
3417 | ed1dda53 | aurel32 | gen_opc_icount[lj] = num_insns; |
3418 | 4c9649a9 | j_mayer | } |
3419 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
3420 | 2e70f6ef | pbrook | gen_io_start(); |
3421 | c3082755 | Richard Henderson | insn = cpu_ldl_code(env, ctx.pc); |
3422 | 2e70f6ef | pbrook | num_insns++; |
3423 | c4b3be39 | Richard Henderson | |
3424 | fdefe51c | Richard Henderson | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
|
3425 | c4b3be39 | Richard Henderson | tcg_gen_debug_insn_start(ctx.pc); |
3426 | c4b3be39 | Richard Henderson | } |
3427 | c4b3be39 | Richard Henderson | |
3428 | 4c9649a9 | j_mayer | ctx.pc += 4;
|
3429 | 4c9649a9 | j_mayer | ret = translate_one(ctxp, insn); |
3430 | 19bf517b | aurel32 | |
3431 | bf1b03fe | Richard Henderson | /* If we reach a page boundary, are single stepping,
|
3432 | bf1b03fe | Richard Henderson | or exhaust instruction count, stop generation. */
|
3433 | bf1b03fe | Richard Henderson | if (ret == NO_EXIT
|
3434 | bf1b03fe | Richard Henderson | && ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0 |
3435 | bf1b03fe | Richard Henderson | || gen_opc_ptr >= gen_opc_end |
3436 | bf1b03fe | Richard Henderson | || num_insns >= max_insns |
3437 | bf1b03fe | Richard Henderson | || singlestep |
3438 | bf1b03fe | Richard Henderson | || env->singlestep_enabled)) { |
3439 | bf1b03fe | Richard Henderson | ret = EXIT_PC_STALE; |
3440 | 1b530a6d | aurel32 | } |
3441 | 4af70374 | Richard Henderson | } while (ret == NO_EXIT);
|
3442 | 4af70374 | Richard Henderson | |
3443 | 4af70374 | Richard Henderson | if (tb->cflags & CF_LAST_IO) {
|
3444 | 4af70374 | Richard Henderson | gen_io_end(); |
3445 | 4c9649a9 | j_mayer | } |
3446 | 4af70374 | Richard Henderson | |
3447 | 4af70374 | Richard Henderson | switch (ret) {
|
3448 | 4af70374 | Richard Henderson | case EXIT_GOTO_TB:
|
3449 | 8aa3fa20 | Richard Henderson | case EXIT_NORETURN:
|
3450 | 4af70374 | Richard Henderson | break;
|
3451 | 4af70374 | Richard Henderson | case EXIT_PC_STALE:
|
3452 | 496cb5b9 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx.pc); |
3453 | 4af70374 | Richard Henderson | /* FALLTHRU */
|
3454 | 4af70374 | Richard Henderson | case EXIT_PC_UPDATED:
|
3455 | bf1b03fe | Richard Henderson | if (env->singlestep_enabled) {
|
3456 | bf1b03fe | Richard Henderson | gen_excp_1(EXCP_DEBUG, 0);
|
3457 | bf1b03fe | Richard Henderson | } else {
|
3458 | bf1b03fe | Richard Henderson | tcg_gen_exit_tb(0);
|
3459 | bf1b03fe | Richard Henderson | } |
3460 | 4af70374 | Richard Henderson | break;
|
3461 | 4af70374 | Richard Henderson | default:
|
3462 | 4af70374 | Richard Henderson | abort(); |
3463 | 4c9649a9 | j_mayer | } |
3464 | 4af70374 | Richard Henderson | |
3465 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
3466 | 4c9649a9 | j_mayer | *gen_opc_ptr = INDEX_op_end; |
3467 | 4c9649a9 | j_mayer | if (search_pc) {
|
3468 | 4c9649a9 | j_mayer | j = gen_opc_ptr - gen_opc_buf; |
3469 | 4c9649a9 | j_mayer | lj++; |
3470 | 4c9649a9 | j_mayer | while (lj <= j)
|
3471 | 4c9649a9 | j_mayer | gen_opc_instr_start[lj++] = 0;
|
3472 | 4c9649a9 | j_mayer | } else {
|
3473 | 4c9649a9 | j_mayer | tb->size = ctx.pc - pc_start; |
3474 | 2e70f6ef | pbrook | tb->icount = num_insns; |
3475 | 4c9649a9 | j_mayer | } |
3476 | 4af70374 | Richard Henderson | |
3477 | 806991da | Richard Henderson | #ifdef DEBUG_DISAS
|
3478 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
3479 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
3480 | 93fcfe39 | aliguori | log_target_disas(pc_start, ctx.pc - pc_start, 1);
|
3481 | 93fcfe39 | aliguori | qemu_log("\n");
|
3482 | 4c9649a9 | j_mayer | } |
3483 | 4c9649a9 | j_mayer | #endif
|
3484 | 4c9649a9 | j_mayer | } |
3485 | 4c9649a9 | j_mayer | |
3486 | 4d5712f1 | Andreas Färber | void gen_intermediate_code (CPUAlphaState *env, struct TranslationBlock *tb) |
3487 | 4c9649a9 | j_mayer | { |
3488 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
3489 | 4c9649a9 | j_mayer | } |
3490 | 4c9649a9 | j_mayer | |
3491 | 4d5712f1 | Andreas Färber | void gen_intermediate_code_pc (CPUAlphaState *env, struct TranslationBlock *tb) |
3492 | 4c9649a9 | j_mayer | { |
3493 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
3494 | 4c9649a9 | j_mayer | } |
3495 | 4c9649a9 | j_mayer | |
3496 | a964acc6 | Richard Henderson | struct cpu_def_t {
|
3497 | a964acc6 | Richard Henderson | const char *name; |
3498 | a964acc6 | Richard Henderson | int implver, amask;
|
3499 | a964acc6 | Richard Henderson | }; |
3500 | a964acc6 | Richard Henderson | |
3501 | a964acc6 | Richard Henderson | static const struct cpu_def_t cpu_defs[] = { |
3502 | a964acc6 | Richard Henderson | { "ev4", IMPLVER_2106x, 0 }, |
3503 | a964acc6 | Richard Henderson | { "ev5", IMPLVER_21164, 0 }, |
3504 | a964acc6 | Richard Henderson | { "ev56", IMPLVER_21164, AMASK_BWX },
|
3505 | a964acc6 | Richard Henderson | { "pca56", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
|
3506 | a964acc6 | Richard Henderson | { "ev6", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
|
3507 | a964acc6 | Richard Henderson | { "ev67", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
|
3508 | a964acc6 | Richard Henderson | | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }, |
3509 | a964acc6 | Richard Henderson | { "ev68", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
|
3510 | a964acc6 | Richard Henderson | | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }, |
3511 | a964acc6 | Richard Henderson | { "21064", IMPLVER_2106x, 0 }, |
3512 | a964acc6 | Richard Henderson | { "21164", IMPLVER_21164, 0 }, |
3513 | a964acc6 | Richard Henderson | { "21164a", IMPLVER_21164, AMASK_BWX },
|
3514 | a964acc6 | Richard Henderson | { "21164pc", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
|
3515 | a964acc6 | Richard Henderson | { "21264", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
|
3516 | a964acc6 | Richard Henderson | { "21264a", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
|
3517 | a964acc6 | Richard Henderson | | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), } |
3518 | a964acc6 | Richard Henderson | }; |
3519 | a964acc6 | Richard Henderson | |
3520 | aaed909a | bellard | CPUAlphaState * cpu_alpha_init (const char *cpu_model) |
3521 | 4c9649a9 | j_mayer | { |
3522 | 25ebd80f | Andreas Färber | AlphaCPU *cpu; |
3523 | 4c9649a9 | j_mayer | CPUAlphaState *env; |
3524 | a964acc6 | Richard Henderson | int implver, amask, i, max;
|
3525 | 4c9649a9 | j_mayer | |
3526 | 25ebd80f | Andreas Färber | cpu = ALPHA_CPU(object_new(TYPE_ALPHA_CPU)); |
3527 | 25ebd80f | Andreas Färber | env = &cpu->env; |
3528 | 9444006f | Andreas Färber | |
3529 | 2e70f6ef | pbrook | alpha_translate_init(); |
3530 | a964acc6 | Richard Henderson | |
3531 | a964acc6 | Richard Henderson | /* Default to ev67; no reason not to emulate insns by default. */
|
3532 | a964acc6 | Richard Henderson | implver = IMPLVER_21264; |
3533 | a964acc6 | Richard Henderson | amask = (AMASK_BWX | AMASK_FIX | AMASK_CIX | AMASK_MVI |
3534 | a964acc6 | Richard Henderson | | AMASK_TRAP | AMASK_PREFETCH); |
3535 | a964acc6 | Richard Henderson | |
3536 | a964acc6 | Richard Henderson | max = ARRAY_SIZE(cpu_defs); |
3537 | a964acc6 | Richard Henderson | for (i = 0; i < max; i++) { |
3538 | a964acc6 | Richard Henderson | if (strcmp (cpu_model, cpu_defs[i].name) == 0) { |
3539 | a964acc6 | Richard Henderson | implver = cpu_defs[i].implver; |
3540 | a964acc6 | Richard Henderson | amask = cpu_defs[i].amask; |
3541 | a964acc6 | Richard Henderson | break;
|
3542 | a964acc6 | Richard Henderson | } |
3543 | a964acc6 | Richard Henderson | } |
3544 | a964acc6 | Richard Henderson | env->implver = implver; |
3545 | a964acc6 | Richard Henderson | env->amask = amask; |
3546 | 2b85cf0e | Richard Henderson | env->cpu_model_str = cpu_model; |
3547 | a964acc6 | Richard Henderson | |
3548 | 0bf46a40 | aliguori | qemu_init_vcpu(env); |
3549 | 4c9649a9 | j_mayer | return env;
|
3550 | 4c9649a9 | j_mayer | } |
3551 | aaed909a | bellard | |
3552 | 4d5712f1 | Andreas Färber | void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, int pc_pos) |
3553 | d2856f1a | aurel32 | { |
3554 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
3555 | d2856f1a | aurel32 | } |