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/*
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   SPARC micro operations
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   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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   This library is free software; you can redistribute it and/or
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   modify it under the terms of the GNU Lesser General Public
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   License as published by the Free Software Foundation; either
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   version 2 of the License, or (at your option) any later version.
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   This library is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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   Lesser General Public License for more details.
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   You should have received a copy of the GNU Lesser General Public
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   License along with this library; if not, write to the Free Software
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   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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*/
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#include "exec.h"
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 /*XXX*/
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#define REGNAME g0
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#define REG (env->gregs[0])
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#include "op_template.h"
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#define REGNAME g1
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#define REG (env->gregs[1])
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#include "op_template.h"
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#define REGNAME g2
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#define REG (env->gregs[2])
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#include "op_template.h"
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#define REGNAME g3
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#define REG (env->gregs[3])
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#include "op_template.h"
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#define REGNAME g4
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#define REG (env->gregs[4])
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#include "op_template.h"
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#define REGNAME g5
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#define REG (env->gregs[5])
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#include "op_template.h"
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#define REGNAME g6
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#define REG (env->gregs[6])
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#include "op_template.h"
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#define REGNAME g7
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#define REG (env->gregs[7])
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#include "op_template.h"
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#define REGNAME i0
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#define REG (REGWPTR[16])
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#include "op_template.h"
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#define REGNAME i1
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#define REG (REGWPTR[17])
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#include "op_template.h"
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#define REGNAME i2
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#define REG (REGWPTR[18])
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#include "op_template.h"
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#define REGNAME i3
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#define REG (REGWPTR[19])
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#include "op_template.h"
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#define REGNAME i4
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#define REG (REGWPTR[20])
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#include "op_template.h"
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#define REGNAME i5
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#define REG (REGWPTR[21])
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#include "op_template.h"
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#define REGNAME i6
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#define REG (REGWPTR[22])
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#include "op_template.h"
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#define REGNAME i7
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#define REG (REGWPTR[23])
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#include "op_template.h"
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#define REGNAME l0
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#define REG (REGWPTR[8])
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#include "op_template.h"
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#define REGNAME l1
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#define REG (REGWPTR[9])
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#include "op_template.h"
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#define REGNAME l2
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#define REG (REGWPTR[10])
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#include "op_template.h"
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#define REGNAME l3
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#define REG (REGWPTR[11])
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#include "op_template.h"
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#define REGNAME l4
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#define REG (REGWPTR[12])
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#include "op_template.h"
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#define REGNAME l5
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#define REG (REGWPTR[13])
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#include "op_template.h"
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#define REGNAME l6
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#define REG (REGWPTR[14])
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#include "op_template.h"
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#define REGNAME l7
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#define REG (REGWPTR[15])
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#include "op_template.h"
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#define REGNAME o0
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#define REG (REGWPTR[0])
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#include "op_template.h"
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#define REGNAME o1
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#define REG (REGWPTR[1])
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#include "op_template.h"
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#define REGNAME o2
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#define REG (REGWPTR[2])
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#include "op_template.h"
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#define REGNAME o3
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#define REG (REGWPTR[3])
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#include "op_template.h"
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#define REGNAME o4
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#define REG (REGWPTR[4])
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#include "op_template.h"
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#define REGNAME o5
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#define REG (REGWPTR[5])
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#include "op_template.h"
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#define REGNAME o6
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#define REG (REGWPTR[6])
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#include "op_template.h"
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#define REGNAME o7
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#define REG (REGWPTR[7])
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#include "op_template.h"
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#define REGNAME f0
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#define REG (env->fpr[0])
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#include "fop_template.h"
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#define REGNAME f1
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#define REG (env->fpr[1])
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#include "fop_template.h"
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#define REGNAME f2
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#define REG (env->fpr[2])
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#include "fop_template.h"
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#define REGNAME f3
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#define REG (env->fpr[3])
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#include "fop_template.h"
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#define REGNAME f4
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#define REG (env->fpr[4])
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#include "fop_template.h"
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#define REGNAME f5
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#define REG (env->fpr[5])
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#include "fop_template.h"
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#define REGNAME f6
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#define REG (env->fpr[6])
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#include "fop_template.h"
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#define REGNAME f7
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#define REG (env->fpr[7])
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#include "fop_template.h"
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#define REGNAME f8
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#define REG (env->fpr[8])
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#include "fop_template.h"
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#define REGNAME f9
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#define REG (env->fpr[9])
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#include "fop_template.h"
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#define REGNAME f10
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#define REG (env->fpr[10])
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#include "fop_template.h"
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#define REGNAME f11
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#define REG (env->fpr[11])
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#include "fop_template.h"
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#define REGNAME f12
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#define REG (env->fpr[12])
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#include "fop_template.h"
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#define REGNAME f13
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#define REG (env->fpr[13])
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#include "fop_template.h"
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#define REGNAME f14
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#define REG (env->fpr[14])
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#include "fop_template.h"
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#define REGNAME f15
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#define REG (env->fpr[15])
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#include "fop_template.h"
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#define REGNAME f16
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#define REG (env->fpr[16])
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#include "fop_template.h"
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#define REGNAME f17
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#define REG (env->fpr[17])
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#include "fop_template.h"
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#define REGNAME f18
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#define REG (env->fpr[18])
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#include "fop_template.h"
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#define REGNAME f19
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#define REG (env->fpr[19])
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#include "fop_template.h"
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#define REGNAME f20
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#define REG (env->fpr[20])
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#include "fop_template.h"
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#define REGNAME f21
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#define REG (env->fpr[21])
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#include "fop_template.h"
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#define REGNAME f22
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#define REG (env->fpr[22])
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#include "fop_template.h"
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#define REGNAME f23
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#define REG (env->fpr[23])
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#include "fop_template.h"
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#define REGNAME f24
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#define REG (env->fpr[24])
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#include "fop_template.h"
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#define REGNAME f25
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#define REG (env->fpr[25])
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#include "fop_template.h"
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#define REGNAME f26
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#define REG (env->fpr[26])
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#include "fop_template.h"
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#define REGNAME f27
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#define REG (env->fpr[27])
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#include "fop_template.h"
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#define REGNAME f28
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#define REG (env->fpr[28])
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#include "fop_template.h"
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#define REGNAME f29
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#define REG (env->fpr[29])
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#include "fop_template.h"
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#define REGNAME f30
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#define REG (env->fpr[30])
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#include "fop_template.h"
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#define REGNAME f31
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#define REG (env->fpr[31])
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#include "fop_template.h"
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#ifdef TARGET_SPARC64
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#define REGNAME f32
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#define REG (env->fpr[32])
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#include "fop_template.h"
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#define REGNAME f34
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#define REG (env->fpr[34])
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#include "fop_template.h"
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#define REGNAME f36
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#define REG (env->fpr[36])
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#include "fop_template.h"
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#define REGNAME f38
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#define REG (env->fpr[38])
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#include "fop_template.h"
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#define REGNAME f40
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#define REG (env->fpr[40])
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#include "fop_template.h"
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#define REGNAME f42
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#define REG (env->fpr[42])
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#include "fop_template.h"
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#define REGNAME f44
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#define REG (env->fpr[44])
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#include "fop_template.h"
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#define REGNAME f46
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#define REG (env->fpr[46])
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#include "fop_template.h"
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#define REGNAME f48
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#define REG (env->fpr[47])
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#include "fop_template.h"
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#define REGNAME f50
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#define REG (env->fpr[50])
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#include "fop_template.h"
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#define REGNAME f52
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#define REG (env->fpr[52])
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#include "fop_template.h"
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#define REGNAME f54
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#define REG (env->fpr[54])
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#include "fop_template.h"
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#define REGNAME f56
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#define REG (env->fpr[56])
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#include "fop_template.h"
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#define REGNAME f58
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#define REG (env->fpr[58])
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#include "fop_template.h"
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#define REGNAME f60
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#define REG (env->fpr[60])
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#include "fop_template.h"
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#define REGNAME f62
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#define REG (env->fpr[62])
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#include "fop_template.h"
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#endif
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#ifdef TARGET_SPARC64
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#ifdef WORDS_BIGENDIAN
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typedef union UREG64 {
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    struct { uint16_t v3, v2, v1, v0; } w;
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    struct { uint32_t v1, v0; } l;
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    uint64_t q;
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} UREG64;
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#else
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typedef union UREG64 {
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    struct { uint16_t v0, v1, v2, v3; } w;
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    struct { uint32_t v0, v1; } l;
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    uint64_t q;
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} UREG64;
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#endif
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#define PARAMQ1 \
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({\
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    UREG64 __p;\
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    __p.l.v1 = PARAM1;\
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    __p.l.v0 = PARAM2;\
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    __p.q;\
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}) 
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void OPPROTO op_movq_T0_im64(void)
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{
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    T0 = PARAMQ1;
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}
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void OPPROTO op_movq_T1_im64(void)
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{
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    T1 = PARAMQ1;
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}
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#define XFLAG_SET(x) ((env->xcc&x)?1:0)
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#else
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#define EIP (env->pc)
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#endif
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#define FLAG_SET(x) ((env->psr&x)?1:0)
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void OPPROTO op_movl_T0_0(void)
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{
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    T0 = 0;
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}
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void OPPROTO op_movl_T0_im(void)
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{
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    T0 = (uint32_t)PARAM1;
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}
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void OPPROTO op_movl_T1_im(void)
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{
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    T1 = (uint32_t)PARAM1;
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}
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void OPPROTO op_movl_T2_im(void)
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{
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    T2 = (uint32_t)PARAM1;
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}
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void OPPROTO op_movl_T0_sim(void)
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{
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    T0 = (int32_t)PARAM1;
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}
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void OPPROTO op_movl_T1_sim(void)
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{
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    T1 = (int32_t)PARAM1;
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}
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void OPPROTO op_movl_T2_sim(void)
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{
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    T2 = (int32_t)PARAM1;
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}
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void OPPROTO op_movl_T0_env(void)
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{
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    T0 = *(uint32_t *)((char *)env + PARAM1);
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}
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void OPPROTO op_movl_env_T0(void)
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{
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    *(uint32_t *)((char *)env + PARAM1) = T0;
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}
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void OPPROTO op_movtl_T0_env(void)
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{
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    T0 = *(target_ulong *)((char *)env + PARAM1);
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}
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void OPPROTO op_movtl_env_T0(void)
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{
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    *(target_ulong *)((char *)env + PARAM1) = T0;
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}
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void OPPROTO op_add_T1_T0(void)
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{
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    T0 += T1;
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}
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void OPPROTO op_add_T1_T0_cc(void)
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{
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    target_ulong src1;
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    src1 = T0;
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    T0 += T1;
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    env->psr = 0;
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#ifdef TARGET_SPARC64
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    if (!(T0 & 0xffffffff))
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        env->psr |= PSR_ZERO;
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    if ((int32_t) T0 < 0)
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        env->psr |= PSR_NEG;
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    if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
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        env->psr |= PSR_CARRY;
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    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
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         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
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        env->psr |= PSR_OVF;
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    env->xcc = 0;
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    if (!T0)
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        env->xcc |= PSR_ZERO;
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    if ((int64_t) T0 < 0)
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        env->xcc |= PSR_NEG;
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    if (T0 < src1)
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        env->xcc |= PSR_CARRY;
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    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
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        env->xcc |= PSR_OVF;
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#else
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    if (!T0)
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        env->psr |= PSR_ZERO;
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    if ((int32_t) T0 < 0)
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        env->psr |= PSR_NEG;
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    if (T0 < src1)
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        env->psr |= PSR_CARRY;
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    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
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        env->psr |= PSR_OVF;
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#endif
407 af7bf89b bellard
    FORCE_RET();
408 7a3f1944 bellard
}
409 7a3f1944 bellard
410 af7bf89b bellard
void OPPROTO op_addx_T1_T0(void)
411 7a3f1944 bellard
{
412 af7bf89b bellard
    T0 += T1 + FLAG_SET(PSR_CARRY);
413 7a3f1944 bellard
}
414 7a3f1944 bellard
415 af7bf89b bellard
void OPPROTO op_addx_T1_T0_cc(void)
416 7a3f1944 bellard
{
417 af7bf89b bellard
    target_ulong src1;
418 cf495bcf bellard
    src1 = T0;
419 b854608e bellard
    if (FLAG_SET(PSR_CARRY))
420 b854608e bellard
    {
421 b854608e bellard
      T0 += T1 + 1;
422 b854608e bellard
      env->psr = 0;
423 b854608e bellard
#ifdef TARGET_SPARC64
424 b854608e bellard
      if ((T0 & 0xffffffff) <= (src1 & 0xffffffff))
425 b854608e bellard
        env->psr |= PSR_CARRY;
426 b854608e bellard
      env->xcc = 0;
427 b854608e bellard
      if (T0 <= src1)
428 b854608e bellard
        env->xcc |= PSR_CARRY;
429 b854608e bellard
#else
430 b854608e bellard
      if (T0 <= src1)
431 b854608e bellard
        env->psr |= PSR_CARRY;
432 b854608e bellard
#endif
433 b854608e bellard
    }
434 b854608e bellard
    else
435 b854608e bellard
    {
436 b854608e bellard
      T0 += T1;
437 b854608e bellard
      env->psr = 0;
438 b854608e bellard
#ifdef TARGET_SPARC64
439 b854608e bellard
      if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
440 b854608e bellard
        env->psr |= PSR_CARRY;
441 b854608e bellard
      env->xcc = 0;
442 b854608e bellard
      if (T0 < src1)
443 b854608e bellard
        env->xcc |= PSR_CARRY;
444 b854608e bellard
#else
445 b854608e bellard
      if (T0 < src1)
446 b854608e bellard
        env->psr |= PSR_CARRY;
447 b854608e bellard
#endif
448 b854608e bellard
    }
449 3475187d bellard
#ifdef TARGET_SPARC64
450 3475187d bellard
    if (!(T0 & 0xffffffff))
451 3475187d bellard
        env->psr |= PSR_ZERO;
452 3475187d bellard
    if ((int32_t) T0 < 0)
453 3475187d bellard
        env->psr |= PSR_NEG;
454 3475187d bellard
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
455 3475187d bellard
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
456 3475187d bellard
        env->psr |= PSR_OVF;
457 3475187d bellard
458 3475187d bellard
    if (!T0)
459 3475187d bellard
        env->xcc |= PSR_ZERO;
460 3475187d bellard
    if ((int64_t) T0 < 0)
461 3475187d bellard
        env->xcc |= PSR_NEG;
462 3475187d bellard
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
463 3475187d bellard
        env->xcc |= PSR_OVF;
464 3475187d bellard
#else
465 cf495bcf bellard
    if (!T0)
466 cf495bcf bellard
        env->psr |= PSR_ZERO;
467 af7bf89b bellard
    if ((int32_t) T0 < 0)
468 cf495bcf bellard
        env->psr |= PSR_NEG;
469 cf495bcf bellard
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
470 cf495bcf bellard
        env->psr |= PSR_OVF;
471 3475187d bellard
#endif
472 cf495bcf bellard
    FORCE_RET();
473 7a3f1944 bellard
}
474 7a3f1944 bellard
475 cf495bcf bellard
void OPPROTO op_sub_T1_T0(void)
476 7a3f1944 bellard
{
477 cf495bcf bellard
    T0 -= T1;
478 7a3f1944 bellard
}
479 7a3f1944 bellard
480 cf495bcf bellard
void OPPROTO op_sub_T1_T0_cc(void)
481 7a3f1944 bellard
{
482 af7bf89b bellard
    target_ulong src1;
483 cf495bcf bellard
484 cf495bcf bellard
    src1 = T0;
485 cf495bcf bellard
    T0 -= T1;
486 cf495bcf bellard
    env->psr = 0;
487 3475187d bellard
#ifdef TARGET_SPARC64
488 3475187d bellard
    if (!(T0 & 0xffffffff))
489 3475187d bellard
        env->psr |= PSR_ZERO;
490 3475187d bellard
    if ((int32_t) T0 < 0)
491 3475187d bellard
        env->psr |= PSR_NEG;
492 83469015 bellard
    if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
493 3475187d bellard
        env->psr |= PSR_CARRY;
494 3475187d bellard
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
495 3475187d bellard
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
496 3475187d bellard
        env->psr |= PSR_OVF;
497 3475187d bellard
498 3475187d bellard
    env->xcc = 0;
499 3475187d bellard
    if (!T0)
500 3475187d bellard
        env->xcc |= PSR_ZERO;
501 3475187d bellard
    if ((int64_t) T0 < 0)
502 3475187d bellard
        env->xcc |= PSR_NEG;
503 bb3911a6 bellard
    if (src1 < T1)
504 3475187d bellard
        env->xcc |= PSR_CARRY;
505 3475187d bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
506 3475187d bellard
        env->xcc |= PSR_OVF;
507 3475187d bellard
#else
508 cf495bcf bellard
    if (!T0)
509 cf495bcf bellard
        env->psr |= PSR_ZERO;
510 af7bf89b bellard
    if ((int32_t) T0 < 0)
511 cf495bcf bellard
        env->psr |= PSR_NEG;
512 cf495bcf bellard
    if (src1 < T1)
513 cf495bcf bellard
        env->psr |= PSR_CARRY;
514 cf495bcf bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
515 cf495bcf bellard
        env->psr |= PSR_OVF;
516 3475187d bellard
#endif
517 af7bf89b bellard
    FORCE_RET();
518 af7bf89b bellard
}
519 af7bf89b bellard
520 af7bf89b bellard
void OPPROTO op_subx_T1_T0(void)
521 af7bf89b bellard
{
522 af7bf89b bellard
    T0 -= T1 + FLAG_SET(PSR_CARRY);
523 af7bf89b bellard
}
524 af7bf89b bellard
525 af7bf89b bellard
void OPPROTO op_subx_T1_T0_cc(void)
526 af7bf89b bellard
{
527 af7bf89b bellard
    target_ulong src1;
528 af7bf89b bellard
    src1 = T0;
529 b854608e bellard
    if (FLAG_SET(PSR_CARRY))
530 b854608e bellard
    {
531 b854608e bellard
      T0 -= T1 + 1;
532 b854608e bellard
      env->psr = 0;
533 b854608e bellard
#ifdef TARGET_SPARC64
534 b854608e bellard
      if ((src1 & 0xffffffff) <= (T1 & 0xffffffff))
535 b854608e bellard
        env->psr |= PSR_CARRY;
536 b854608e bellard
      env->xcc = 0;
537 b854608e bellard
      if (src1 <= T1)
538 b854608e bellard
        env->xcc |= PSR_CARRY;
539 b854608e bellard
#else
540 b854608e bellard
      if (src1 <= T1)
541 b854608e bellard
        env->psr |= PSR_CARRY;
542 b854608e bellard
#endif
543 b854608e bellard
    }
544 b854608e bellard
    else
545 b854608e bellard
    {
546 b854608e bellard
      T0 -= T1;
547 b854608e bellard
      env->psr = 0;
548 b854608e bellard
#ifdef TARGET_SPARC64
549 b854608e bellard
      if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
550 b854608e bellard
        env->psr |= PSR_CARRY;
551 b854608e bellard
      env->xcc = 0;
552 b854608e bellard
      if (src1 < T1)
553 b854608e bellard
        env->xcc |= PSR_CARRY;
554 b854608e bellard
#else
555 b854608e bellard
      if (src1 < T1)
556 b854608e bellard
        env->psr |= PSR_CARRY;
557 b854608e bellard
#endif
558 b854608e bellard
    }
559 3475187d bellard
#ifdef TARGET_SPARC64
560 3475187d bellard
    if (!(T0 & 0xffffffff))
561 3475187d bellard
        env->psr |= PSR_ZERO;
562 3475187d bellard
    if ((int32_t) T0 < 0)
563 3475187d bellard
        env->psr |= PSR_NEG;
564 3475187d bellard
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
565 3475187d bellard
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
566 3475187d bellard
        env->psr |= PSR_OVF;
567 3475187d bellard
568 3475187d bellard
    if (!T0)
569 3475187d bellard
        env->xcc |= PSR_ZERO;
570 3475187d bellard
    if ((int64_t) T0 < 0)
571 3475187d bellard
        env->xcc |= PSR_NEG;
572 3475187d bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
573 3475187d bellard
        env->xcc |= PSR_OVF;
574 3475187d bellard
#else
575 af7bf89b bellard
    if (!T0)
576 af7bf89b bellard
        env->psr |= PSR_ZERO;
577 af7bf89b bellard
    if ((int32_t) T0 < 0)
578 af7bf89b bellard
        env->psr |= PSR_NEG;
579 af7bf89b bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
580 af7bf89b bellard
        env->psr |= PSR_OVF;
581 3475187d bellard
#endif
582 cf495bcf bellard
    FORCE_RET();
583 7a3f1944 bellard
}
584 7a3f1944 bellard
585 cf495bcf bellard
void OPPROTO op_and_T1_T0(void)
586 7a3f1944 bellard
{
587 cf495bcf bellard
    T0 &= T1;
588 7a3f1944 bellard
}
589 7a3f1944 bellard
590 cf495bcf bellard
void OPPROTO op_or_T1_T0(void)
591 7a3f1944 bellard
{
592 cf495bcf bellard
    T0 |= T1;
593 7a3f1944 bellard
}
594 7a3f1944 bellard
595 cf495bcf bellard
void OPPROTO op_xor_T1_T0(void)
596 7a3f1944 bellard
{
597 cf495bcf bellard
    T0 ^= T1;
598 7a3f1944 bellard
}
599 7a3f1944 bellard
600 cf495bcf bellard
void OPPROTO op_andn_T1_T0(void)
601 7a3f1944 bellard
{
602 cf495bcf bellard
    T0 &= ~T1;
603 7a3f1944 bellard
}
604 7a3f1944 bellard
605 cf495bcf bellard
void OPPROTO op_orn_T1_T0(void)
606 7a3f1944 bellard
{
607 cf495bcf bellard
    T0 |= ~T1;
608 7a3f1944 bellard
}
609 7a3f1944 bellard
610 cf495bcf bellard
void OPPROTO op_xnor_T1_T0(void)
611 7a3f1944 bellard
{
612 cf495bcf bellard
    T0 ^= ~T1;
613 7a3f1944 bellard
}
614 7a3f1944 bellard
615 cf495bcf bellard
void OPPROTO op_umul_T1_T0(void)
616 7a3f1944 bellard
{
617 cf495bcf bellard
    uint64_t res;
618 af7bf89b bellard
    res = (uint64_t) T0 * (uint64_t) T1;
619 83469015 bellard
#ifdef TARGET_SPARC64
620 83469015 bellard
    T0 = res;
621 83469015 bellard
#else
622 cf495bcf bellard
    T0 = res & 0xffffffff;
623 83469015 bellard
#endif
624 cf495bcf bellard
    env->y = res >> 32;
625 7a3f1944 bellard
}
626 7a3f1944 bellard
627 cf495bcf bellard
void OPPROTO op_smul_T1_T0(void)
628 7a3f1944 bellard
{
629 cf495bcf bellard
    uint64_t res;
630 cf495bcf bellard
    res = (int64_t) ((int32_t) T0) * (int64_t) ((int32_t) T1);
631 83469015 bellard
#ifdef TARGET_SPARC64
632 83469015 bellard
    T0 = res;
633 83469015 bellard
#else
634 cf495bcf bellard
    T0 = res & 0xffffffff;
635 83469015 bellard
#endif
636 cf495bcf bellard
    env->y = res >> 32;
637 7a3f1944 bellard
}
638 7a3f1944 bellard
639 cf495bcf bellard
void OPPROTO op_mulscc_T1_T0(void)
640 7a3f1944 bellard
{
641 af7bf89b bellard
    unsigned int b1, N, V, b2;
642 af7bf89b bellard
    target_ulong src1;
643 af7bf89b bellard
644 4e8b5da2 bellard
    N = FLAG_SET(PSR_NEG);
645 cf495bcf bellard
    V = FLAG_SET(PSR_OVF);
646 4e8b5da2 bellard
    b1 = N ^ V;
647 cf495bcf bellard
    b2 = T0 & 1;
648 cf495bcf bellard
    T0 = (b1 << 31) | (T0 >> 1);
649 cf495bcf bellard
    if (!(env->y & 1))
650 cf495bcf bellard
        T1 = 0;
651 cf495bcf bellard
    /* do addition and update flags */
652 cf495bcf bellard
    src1 = T0;
653 cf495bcf bellard
    T0 += T1;
654 cf495bcf bellard
    env->psr = 0;
655 cf495bcf bellard
    if (!T0)
656 cf495bcf bellard
        env->psr |= PSR_ZERO;
657 af7bf89b bellard
    if ((int32_t) T0 < 0)
658 cf495bcf bellard
        env->psr |= PSR_NEG;
659 cf495bcf bellard
    if (T0 < src1)
660 cf495bcf bellard
        env->psr |= PSR_CARRY;
661 cf495bcf bellard
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
662 cf495bcf bellard
        env->psr |= PSR_OVF;
663 cf495bcf bellard
    env->y = (b2 << 31) | (env->y >> 1);
664 cf495bcf bellard
    FORCE_RET();
665 cf495bcf bellard
}
666 cf495bcf bellard
667 cf495bcf bellard
void OPPROTO op_udiv_T1_T0(void)
668 cf495bcf bellard
{
669 cf495bcf bellard
    uint64_t x0;
670 cf495bcf bellard
    uint32_t x1;
671 cf495bcf bellard
672 cf495bcf bellard
    x0 = T0 | ((uint64_t) (env->y) << 32);
673 cf495bcf bellard
    x1 = T1;
674 cf495bcf bellard
    x0 = x0 / x1;
675 cf495bcf bellard
    if (x0 > 0xffffffff) {
676 cf495bcf bellard
        T0 = 0xffffffff;
677 cf495bcf bellard
        T1 = 1;
678 cf495bcf bellard
    } else {
679 cf495bcf bellard
        T0 = x0;
680 cf495bcf bellard
        T1 = 0;
681 cf495bcf bellard
    }
682 cf495bcf bellard
    FORCE_RET();
683 7a3f1944 bellard
}
684 7a3f1944 bellard
685 cf495bcf bellard
void OPPROTO op_sdiv_T1_T0(void)
686 7a3f1944 bellard
{
687 cf495bcf bellard
    int64_t x0;
688 cf495bcf bellard
    int32_t x1;
689 cf495bcf bellard
690 af7bf89b bellard
    x0 = T0 | ((int64_t) (env->y) << 32);
691 cf495bcf bellard
    x1 = T1;
692 cf495bcf bellard
    x0 = x0 / x1;
693 cf495bcf bellard
    if ((int32_t) x0 != x0) {
694 af7bf89b bellard
        T0 = x0 < 0? 0x80000000: 0x7fffffff;
695 cf495bcf bellard
        T1 = 1;
696 cf495bcf bellard
    } else {
697 cf495bcf bellard
        T0 = x0;
698 cf495bcf bellard
        T1 = 0;
699 cf495bcf bellard
    }
700 cf495bcf bellard
    FORCE_RET();
701 7a3f1944 bellard
}
702 7a3f1944 bellard
703 cf495bcf bellard
void OPPROTO op_div_cc(void)
704 7a3f1944 bellard
{
705 cf495bcf bellard
    env->psr = 0;
706 3475187d bellard
#ifdef TARGET_SPARC64
707 3475187d bellard
    if (!T0)
708 3475187d bellard
        env->psr |= PSR_ZERO;
709 3475187d bellard
    if ((int32_t) T0 < 0)
710 3475187d bellard
        env->psr |= PSR_NEG;
711 3475187d bellard
    if (T1)
712 3475187d bellard
        env->psr |= PSR_OVF;
713 3475187d bellard
714 3475187d bellard
    env->xcc = 0;
715 3475187d bellard
    if (!T0)
716 3475187d bellard
        env->xcc |= PSR_ZERO;
717 3475187d bellard
    if ((int64_t) T0 < 0)
718 3475187d bellard
        env->xcc |= PSR_NEG;
719 3475187d bellard
#else
720 cf495bcf bellard
    if (!T0)
721 cf495bcf bellard
        env->psr |= PSR_ZERO;
722 af7bf89b bellard
    if ((int32_t) T0 < 0)
723 cf495bcf bellard
        env->psr |= PSR_NEG;
724 cf495bcf bellard
    if (T1)
725 cf495bcf bellard
        env->psr |= PSR_OVF;
726 3475187d bellard
#endif
727 cf495bcf bellard
    FORCE_RET();
728 7a3f1944 bellard
}
729 7a3f1944 bellard
730 3475187d bellard
#ifdef TARGET_SPARC64
731 3475187d bellard
void OPPROTO op_mulx_T1_T0(void)
732 3475187d bellard
{
733 3475187d bellard
    T0 *= T1;
734 3475187d bellard
    FORCE_RET();
735 3475187d bellard
}
736 3475187d bellard
737 3475187d bellard
void OPPROTO op_udivx_T1_T0(void)
738 3475187d bellard
{
739 3475187d bellard
    T0 /= T1;
740 3475187d bellard
    FORCE_RET();
741 3475187d bellard
}
742 3475187d bellard
743 3475187d bellard
void OPPROTO op_sdivx_T1_T0(void)
744 3475187d bellard
{
745 3475187d bellard
    if (T0 == INT64_MIN && T1 == -1)
746 3475187d bellard
        T0 = INT64_MIN;
747 3475187d bellard
    else
748 3475187d bellard
        T0 /= (target_long) T1;
749 3475187d bellard
    FORCE_RET();
750 3475187d bellard
}
751 3475187d bellard
#endif
752 3475187d bellard
753 cf495bcf bellard
void OPPROTO op_logic_T0_cc(void)
754 7a3f1944 bellard
{
755 cf495bcf bellard
    env->psr = 0;
756 3475187d bellard
#ifdef TARGET_SPARC64
757 3475187d bellard
    if (!(T0 & 0xffffffff))
758 3475187d bellard
        env->psr |= PSR_ZERO;
759 3475187d bellard
    if ((int32_t) T0 < 0)
760 3475187d bellard
        env->psr |= PSR_NEG;
761 3475187d bellard
762 3475187d bellard
    env->xcc = 0;
763 3475187d bellard
    if (!T0)
764 3475187d bellard
        env->xcc |= PSR_ZERO;
765 3475187d bellard
    if ((int64_t) T0 < 0)
766 3475187d bellard
        env->xcc |= PSR_NEG;
767 3475187d bellard
#else
768 cf495bcf bellard
    if (!T0)
769 cf495bcf bellard
        env->psr |= PSR_ZERO;
770 af7bf89b bellard
    if ((int32_t) T0 < 0)
771 cf495bcf bellard
        env->psr |= PSR_NEG;
772 3475187d bellard
#endif
773 cf495bcf bellard
    FORCE_RET();
774 7a3f1944 bellard
}
775 7a3f1944 bellard
776 cf495bcf bellard
void OPPROTO op_sll(void)
777 7a3f1944 bellard
{
778 cf495bcf bellard
    T0 <<= T1;
779 7a3f1944 bellard
}
780 7a3f1944 bellard
781 3475187d bellard
#ifdef TARGET_SPARC64
782 3475187d bellard
void OPPROTO op_srl(void)
783 3475187d bellard
{
784 3475187d bellard
    T0 = (T0 & 0xffffffff) >> T1;
785 3475187d bellard
}
786 3475187d bellard
787 3475187d bellard
void OPPROTO op_srlx(void)
788 3475187d bellard
{
789 3475187d bellard
    T0 >>= T1;
790 3475187d bellard
}
791 3475187d bellard
792 3475187d bellard
void OPPROTO op_sra(void)
793 3475187d bellard
{
794 3475187d bellard
    T0 = ((int32_t) (T0 & 0xffffffff)) >> T1;
795 3475187d bellard
}
796 3475187d bellard
797 3475187d bellard
void OPPROTO op_srax(void)
798 3475187d bellard
{
799 3475187d bellard
    T0 = ((int64_t) T0) >> T1;
800 3475187d bellard
}
801 3475187d bellard
#else
802 cf495bcf bellard
void OPPROTO op_srl(void)
803 7a3f1944 bellard
{
804 cf495bcf bellard
    T0 >>= T1;
805 7a3f1944 bellard
}
806 7a3f1944 bellard
807 cf495bcf bellard
void OPPROTO op_sra(void)
808 7a3f1944 bellard
{
809 cf495bcf bellard
    T0 = ((int32_t) T0) >> T1;
810 7a3f1944 bellard
}
811 3475187d bellard
#endif
812 7a3f1944 bellard
813 e8af50a3 bellard
/* Load and store */
814 e8af50a3 bellard
#define MEMSUFFIX _raw
815 e8af50a3 bellard
#include "op_mem.h"
816 e8af50a3 bellard
#if !defined(CONFIG_USER_ONLY)
817 e8af50a3 bellard
#define MEMSUFFIX _user
818 e8af50a3 bellard
#include "op_mem.h"
819 e8af50a3 bellard
820 e8af50a3 bellard
#define MEMSUFFIX _kernel
821 e8af50a3 bellard
#include "op_mem.h"
822 e8af50a3 bellard
#endif
823 e8af50a3 bellard
824 e8af50a3 bellard
void OPPROTO op_ldfsr(void)
825 e8af50a3 bellard
{
826 3475187d bellard
    PUT_FSR32(env, *((uint32_t *) &FT0));
827 8d5f07fa bellard
    helper_ldfsr();
828 e8af50a3 bellard
}
829 e8af50a3 bellard
830 e8af50a3 bellard
void OPPROTO op_stfsr(void)
831 e8af50a3 bellard
{
832 3475187d bellard
    *((uint32_t *) &FT0) = GET_FSR32(env);
833 e8af50a3 bellard
}
834 e8af50a3 bellard
835 3475187d bellard
#ifndef TARGET_SPARC64
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void OPPROTO op_rdpsr(void)
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{
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    do_rdpsr();
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}
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void OPPROTO op_wrpsr(void)
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{
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    do_wrpsr();
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    FORCE_RET();
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}
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void OPPROTO op_wrwim(void)
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{
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#if NWINDOWS == 32
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    env->wim = T0;
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#else
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    env->wim = T0 & ((1 << NWINDOWS) - 1);
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#endif
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}
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void OPPROTO op_rett(void)
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{
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    helper_rett();
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    FORCE_RET();
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}
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/* XXX: use another pointer for %iN registers to avoid slow wrapping
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   handling ? */
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void OPPROTO op_save(void)
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{
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    uint32_t cwp;
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    cwp = (env->cwp - 1) & (NWINDOWS - 1); 
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    if (env->wim & (1 << cwp)) {
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        raise_exception(TT_WIN_OVF);
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    }
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    set_cwp(cwp);
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    FORCE_RET();
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}
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void OPPROTO op_restore(void)
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{
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    uint32_t cwp;
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    cwp = (env->cwp + 1) & (NWINDOWS - 1); 
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    if (env->wim & (1 << cwp)) {
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        raise_exception(TT_WIN_UNF);
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    }
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    set_cwp(cwp);
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    FORCE_RET();
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}
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#else
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void OPPROTO op_rdccr(void)
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{
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    T0 = GET_CCR(env);
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}
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void OPPROTO op_wrccr(void)
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{
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    PUT_CCR(env, T0);
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}
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void OPPROTO op_rdtick(void)
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{
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    T0 = 0; // XXX read cycle counter and bit 31
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}
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void OPPROTO op_wrtick(void)
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{
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    // XXX write cycle counter and bit 31
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}
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void OPPROTO op_rdtpc(void)
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{
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    T0 = env->tpc[env->tl];
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}
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void OPPROTO op_wrtpc(void)
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{
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    env->tpc[env->tl] = T0;
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}
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void OPPROTO op_rdtnpc(void)
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{
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    T0 = env->tnpc[env->tl];
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}
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void OPPROTO op_wrtnpc(void)
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{
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    env->tnpc[env->tl] = T0;
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}
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void OPPROTO op_rdtstate(void)
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{
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    T0 = env->tstate[env->tl];
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}
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void OPPROTO op_wrtstate(void)
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{
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    env->tstate[env->tl] = T0;
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}
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void OPPROTO op_rdtt(void)
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{
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    T0 = env->tt[env->tl];
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}
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void OPPROTO op_wrtt(void)
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{
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    env->tt[env->tl] = T0;
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}
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void OPPROTO op_rdpstate(void)
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{
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    T0 = env->pstate;
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}
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void OPPROTO op_wrpstate(void)
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{
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    do_wrpstate();
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}
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// CWP handling is reversed in V9, but we still use the V8 register
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// order.
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void OPPROTO op_rdcwp(void)
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{
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    T0 = NWINDOWS - 1 - env->cwp;
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}
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void OPPROTO op_wrcwp(void)
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{
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    env->cwp = NWINDOWS - 1 - T0;
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}
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/* XXX: use another pointer for %iN registers to avoid slow wrapping
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   handling ? */
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void OPPROTO op_save(void)
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{
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    uint32_t cwp;
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    cwp = (env->cwp - 1) & (NWINDOWS - 1); 
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    if (env->cansave == 0) {
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        raise_exception(TT_SPILL | (env->otherwin != 0 ? 
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                                    (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
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                                    ((env->wstate & 0x7) << 2)));
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    } else {
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        if (env->cleanwin - env->canrestore == 0) {
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            // XXX Clean windows without trap
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            raise_exception(TT_CLRWIN);
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        } else {
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            env->cansave--;
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            env->canrestore++;
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            set_cwp(cwp);
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        }
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    }
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    FORCE_RET();
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}
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void OPPROTO op_restore(void)
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{
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    uint32_t cwp;
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    cwp = (env->cwp + 1) & (NWINDOWS - 1); 
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    if (env->canrestore == 0) {
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        raise_exception(TT_FILL | (env->otherwin != 0 ? 
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                                   (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
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                                   ((env->wstate & 0x7) << 2)));
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    } else {
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        env->cansave++;
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        env->canrestore--;
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        set_cwp(cwp);
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    }
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    FORCE_RET();
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}
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#endif
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void OPPROTO op_exception(void)
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{
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    env->exception_index = PARAM1;
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    cpu_loop_exit();
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}
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void OPPROTO op_trap_T0(void)
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{
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    env->exception_index = TT_TRAP + (T0 & 0x7f);
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    cpu_loop_exit();
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}
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void OPPROTO op_trapcc_T0(void)
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{
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    if (T2) {
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        env->exception_index = TT_TRAP + (T0 & 0x7f);
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        cpu_loop_exit();
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    }
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    FORCE_RET();
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}
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void OPPROTO op_fpexception_im(void)
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{
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    env->exception_index = TT_FP_EXCP;
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    env->fsr &= ~FSR_FTT_MASK;
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    env->fsr |= PARAM1;
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    cpu_loop_exit();
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    FORCE_RET();
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}
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void OPPROTO op_debug(void)
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{
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    helper_debug();
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}
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void OPPROTO op_exit_tb(void)
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{
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    EXIT_TB();
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}
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void OPPROTO op_eval_ba(void)
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{
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    T2 = 1;
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}
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void OPPROTO op_eval_be(void)
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{
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    T2 = FLAG_SET(PSR_ZERO);
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}
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void OPPROTO op_eval_ble(void)
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{
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    target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
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    T2 = Z | (N ^ V);
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}
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void OPPROTO op_eval_bl(void)
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{
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    target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
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    T2 = N ^ V;
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}
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void OPPROTO op_eval_bleu(void)
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{
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    target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
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    T2 = C | Z;
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}
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void OPPROTO op_eval_bcs(void)
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{
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    T2 = FLAG_SET(PSR_CARRY);
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}
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void OPPROTO op_eval_bvs(void)
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{
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    T2 = FLAG_SET(PSR_OVF);
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}
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void OPPROTO op_eval_bn(void)
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{
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    T2 = 0;
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}
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void OPPROTO op_eval_bneg(void)
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{
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    T2 = FLAG_SET(PSR_NEG);
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}
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void OPPROTO op_eval_bne(void)
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{
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    T2 = !FLAG_SET(PSR_ZERO);
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}
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void OPPROTO op_eval_bg(void)
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{
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    target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
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    T2 = !(Z | (N ^ V));
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}
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void OPPROTO op_eval_bge(void)
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{
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    target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
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    T2 = !(N ^ V);
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}
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void OPPROTO op_eval_bgu(void)
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{
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    target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
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    T2 = !(C | Z);
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}
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void OPPROTO op_eval_bcc(void)
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{
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    T2 = !FLAG_SET(PSR_CARRY);
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}
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void OPPROTO op_eval_bpos(void)
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{
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    T2 = !FLAG_SET(PSR_NEG);
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}
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void OPPROTO op_eval_bvc(void)
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{
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    T2 = !FLAG_SET(PSR_OVF);
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}
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#ifdef TARGET_SPARC64
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void OPPROTO op_eval_xbe(void)
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{
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    T2 = XFLAG_SET(PSR_ZERO);
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}
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void OPPROTO op_eval_xble(void)
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{
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    target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
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    T2 = Z | (N ^ V);
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}
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void OPPROTO op_eval_xbl(void)
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{
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    target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
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    T2 = N ^ V;
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}
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void OPPROTO op_eval_xbleu(void)
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{
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    target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY);
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    T2 = C | Z;
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}
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void OPPROTO op_eval_xbcs(void)
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{
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    T2 = XFLAG_SET(PSR_CARRY);
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}
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void OPPROTO op_eval_xbvs(void)
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{
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    T2 = XFLAG_SET(PSR_OVF);
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}
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void OPPROTO op_eval_xbneg(void)
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{
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    T2 = XFLAG_SET(PSR_NEG);
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}
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void OPPROTO op_eval_xbne(void)
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{
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    T2 = !XFLAG_SET(PSR_ZERO);
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}
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void OPPROTO op_eval_xbg(void)
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{
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    target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
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    T2 = !(Z | (N ^ V));
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}
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void OPPROTO op_eval_xbge(void)
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{
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    target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
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    T2 = !(N ^ V);
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}
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void OPPROTO op_eval_xbgu(void)
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{
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    target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY);
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    T2 = !(C | Z);
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}
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void OPPROTO op_eval_xbcc(void)
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{
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    T2 = !XFLAG_SET(PSR_CARRY);
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}
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void OPPROTO op_eval_xbpos(void)
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{
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    T2 = !XFLAG_SET(PSR_NEG);
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}
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void OPPROTO op_eval_xbvc(void)
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{
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    T2 = !XFLAG_SET(PSR_OVF);
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}
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#endif
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#define FCC
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#define FFLAG_SET(x) (env->fsr & x? 1: 0)
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#include "fbranch_template.h"
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#ifdef TARGET_SPARC64
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#define FCC _fcc1
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#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 32))? 1: 0)
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#include "fbranch_template.h"
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#define FCC _fcc2
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#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 34))? 1: 0)
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#include "fbranch_template.h"
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#define FCC _fcc3
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#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 36))? 1: 0)
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#include "fbranch_template.h"
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#endif
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#ifdef TARGET_SPARC64
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void OPPROTO op_eval_brz(void)
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{
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    T2 = (T0 == 0);
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}
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void OPPROTO op_eval_brnz(void)
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{
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    T2 = (T0 != 0);
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}
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void OPPROTO op_eval_brlz(void)
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{
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    T2 = ((int64_t)T0 < 0);
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}
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void OPPROTO op_eval_brlez(void)
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{
1258 3475187d bellard
    T2 = ((int64_t)T0 <= 0);
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}
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void OPPROTO op_eval_brgz(void)
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{
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    T2 = ((int64_t)T0 > 0);
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}
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void OPPROTO op_eval_brgez(void)
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{
1268 3475187d bellard
    T2 = ((int64_t)T0 >= 0);
1269 e8af50a3 bellard
}
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void OPPROTO op_jmp_im64(void)
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{
1273 3475187d bellard
    env->pc = PARAMQ1;
1274 3475187d bellard
}
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void OPPROTO op_movq_npc_im64(void)
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{
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    env->npc = PARAMQ1;
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}
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#endif
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void OPPROTO op_jmp_im(void)
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{
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    env->pc = (uint32_t)PARAM1;
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}
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void OPPROTO op_movl_npc_im(void)
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{
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    env->npc = (uint32_t)PARAM1;
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}
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void OPPROTO op_movl_npc_T0(void)
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{
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    env->npc = T0;
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}
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void OPPROTO op_mov_pc_npc(void)
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{
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    env->pc = env->npc;
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}
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void OPPROTO op_next_insn(void)
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{
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    env->pc = env->npc;
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    env->npc = env->npc + 4;
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}
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void OPPROTO op_goto_tb0(void)
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{
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    GOTO_TB(op_goto_tb0, PARAM1, 0);
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}
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void OPPROTO op_goto_tb1(void)
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{
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    GOTO_TB(op_goto_tb1, PARAM1, 1);
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}
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void OPPROTO op_jmp_label(void)
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{
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    GOTO_LABEL_PARAM(1);
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}
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void OPPROTO op_jnz_T2_label(void)
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{
1325 83469015 bellard
    if (T2)
1326 83469015 bellard
        GOTO_LABEL_PARAM(1);
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    FORCE_RET();
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}
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void OPPROTO op_jz_T2_label(void)
1331 7a3f1944 bellard
{
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    if (!T2)
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        GOTO_LABEL_PARAM(1);
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    FORCE_RET();
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}
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void OPPROTO op_flush_T0(void)
1338 658138bc bellard
{
1339 658138bc bellard
    helper_flush(T0);
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}
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#define F_OP(name, p) void OPPROTO op_f##name##p(void)
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#define F_BINOP(name)                                           \
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    F_OP(name, s)                                               \
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    {                                                           \
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        FT0 = float32_ ## name (FT0, FT1, &env->fp_status);     \
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    }                                                           \
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    F_OP(name, d)                                               \
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    {                                                           \
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        DT0 = float64_ ## name (DT0, DT1, &env->fp_status);     \
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    }
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F_BINOP(add);
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F_BINOP(sub);
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F_BINOP(mul);
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F_BINOP(div);
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#undef F_BINOP
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void OPPROTO op_fsmuld(void)
1361 e8af50a3 bellard
{
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    DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
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                      float32_to_float64(FT1, &env->fp_status),
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                      &env->fp_status);
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}
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#define F_HELPER(name)    \
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    F_OP(name, s)         \
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    {                     \
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        do_f##name##s();  \
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    }                     \
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    F_OP(name, d)         \
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    {                     \
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        do_f##name##d();  \
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    }
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F_HELPER(sqrt);
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F_OP(neg, s)
1380 e8af50a3 bellard
{
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    FT0 = float32_chs(FT1);
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}
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F_OP(abs, s)
1385 e8af50a3 bellard
{
1386 65ce8c2f bellard
    do_fabss();
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}
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F_HELPER(cmp);
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#ifdef TARGET_SPARC64
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F_OP(neg, d)
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{
1394 65ce8c2f bellard
    DT0 = float64_chs(DT1);
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}
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F_OP(abs, d)
1398 e8af50a3 bellard
{
1399 65ce8c2f bellard
    do_fabsd();
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}
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void OPPROTO op_fcmps_fcc1(void)
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{
1404 3475187d bellard
    do_fcmps_fcc1();
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}
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void OPPROTO op_fcmpd_fcc1(void)
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{
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    do_fcmpd_fcc1();
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}
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void OPPROTO op_fcmps_fcc2(void)
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{
1414 3475187d bellard
    do_fcmps_fcc2();
1415 3475187d bellard
}
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void OPPROTO op_fcmpd_fcc2(void)
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{
1419 3475187d bellard
    do_fcmpd_fcc2();
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}
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void OPPROTO op_fcmps_fcc3(void)
1423 3475187d bellard
{
1424 3475187d bellard
    do_fcmps_fcc3();
1425 3475187d bellard
}
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void OPPROTO op_fcmpd_fcc3(void)
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{
1429 3475187d bellard
    do_fcmpd_fcc3();
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}
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#endif
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/* Integer to float conversion.  */
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#ifdef USE_INT_TO_FLOAT_HELPERS
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F_HELPER(ito);
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#else
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F_OP(ito, s)
1438 a0c4cb4a bellard
{
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    FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
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}
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F_OP(ito, d)
1443 e8af50a3 bellard
{
1444 65ce8c2f bellard
    DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
1445 e8af50a3 bellard
}
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#ifdef TARGET_SPARC64
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F_OP(xto, s)
1449 3475187d bellard
{
1450 65ce8c2f bellard
    FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
1451 3475187d bellard
}
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F_OP(xto, d)
1454 3475187d bellard
{
1455 65ce8c2f bellard
    DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
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}
1457 3475187d bellard
#endif
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#endif
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#undef F_HELPER
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/* floating point conversion */
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void OPPROTO op_fdtos(void)
1463 a0c4cb4a bellard
{
1464 65ce8c2f bellard
    FT0 = float64_to_float32(DT1, &env->fp_status);
1465 a0c4cb4a bellard
}
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1467 e8af50a3 bellard
void OPPROTO op_fstod(void)
1468 e8af50a3 bellard
{
1469 65ce8c2f bellard
    DT0 = float32_to_float64(FT1, &env->fp_status);
1470 e8af50a3 bellard
}
1471 e8af50a3 bellard
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/* Float to integer conversion.  */
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void OPPROTO op_fstoi(void)
1474 e8af50a3 bellard
{
1475 65ce8c2f bellard
    *((int32_t *)&FT0) = float32_to_int32(FT1, &env->fp_status);
1476 e8af50a3 bellard
}
1477 e8af50a3 bellard
1478 e8af50a3 bellard
void OPPROTO op_fdtoi(void)
1479 e8af50a3 bellard
{
1480 65ce8c2f bellard
    *((int32_t *)&FT0) = float64_to_int32(DT1, &env->fp_status);
1481 e8af50a3 bellard
}
1482 e8af50a3 bellard
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#ifdef TARGET_SPARC64
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void OPPROTO op_fstox(void)
1485 3475187d bellard
{
1486 65ce8c2f bellard
    *((int64_t *)&DT0) = float32_to_int64(FT1, &env->fp_status);
1487 3475187d bellard
}
1488 3475187d bellard
1489 3475187d bellard
void OPPROTO op_fdtox(void)
1490 3475187d bellard
{
1491 65ce8c2f bellard
    *((int64_t *)&DT0) = float64_to_int64(DT1, &env->fp_status);
1492 3475187d bellard
}
1493 3475187d bellard
1494 3475187d bellard
void OPPROTO op_fmovs_cc(void)
1495 3475187d bellard
{
1496 3475187d bellard
    if (T2)
1497 3475187d bellard
        FT0 = FT1;
1498 3475187d bellard
}
1499 3475187d bellard
1500 3475187d bellard
void OPPROTO op_fmovd_cc(void)
1501 3475187d bellard
{
1502 3475187d bellard
    if (T2)
1503 3475187d bellard
        DT0 = DT1;
1504 3475187d bellard
}
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1506 3475187d bellard
void OPPROTO op_mov_cc(void)
1507 3475187d bellard
{
1508 3475187d bellard
    if (T2)
1509 3475187d bellard
        T0 = T1;
1510 3475187d bellard
}
1511 3475187d bellard
1512 3475187d bellard
void OPPROTO op_flushw(void)
1513 3475187d bellard
{
1514 3475187d bellard
    if (env->cansave != NWINDOWS - 2) {
1515 3475187d bellard
        raise_exception(TT_SPILL | (env->otherwin != 0 ? 
1516 3475187d bellard
                                    (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1517 3475187d bellard
                                    ((env->wstate & 0x7) << 2)));
1518 3475187d bellard
    }
1519 3475187d bellard
}
1520 3475187d bellard
1521 3475187d bellard
void OPPROTO op_saved(void)
1522 3475187d bellard
{
1523 3475187d bellard
    env->cansave++;
1524 3475187d bellard
    if (env->otherwin == 0)
1525 3475187d bellard
        env->canrestore--;
1526 725cb90b bellard
    else
1527 725cb90b bellard
        env->otherwin--;
1528 725cb90b bellard
    FORCE_RET();
1529 3475187d bellard
}
1530 3475187d bellard
1531 3475187d bellard
void OPPROTO op_restored(void)
1532 3475187d bellard
{
1533 3475187d bellard
    env->canrestore++;
1534 3475187d bellard
    if (env->cleanwin < NWINDOWS - 1)
1535 3475187d bellard
        env->cleanwin++;
1536 3475187d bellard
    if (env->otherwin == 0)
1537 3475187d bellard
        env->cansave--;
1538 3475187d bellard
    else
1539 3475187d bellard
        env->otherwin--;
1540 725cb90b bellard
    FORCE_RET();
1541 3475187d bellard
}
1542 3475187d bellard
1543 3475187d bellard
void OPPROTO op_popc(void)
1544 3475187d bellard
{
1545 3475187d bellard
    do_popc();
1546 3475187d bellard
}
1547 3475187d bellard
1548 3475187d bellard
void OPPROTO op_done(void)
1549 3475187d bellard
{
1550 83469015 bellard
    do_done();
1551 3475187d bellard
}
1552 3475187d bellard
1553 3475187d bellard
void OPPROTO op_retry(void)
1554 3475187d bellard
{
1555 83469015 bellard
    do_retry();
1556 3475187d bellard
}
1557 3475187d bellard
1558 3475187d bellard
void OPPROTO op_sir(void)
1559 3475187d bellard
{
1560 3475187d bellard
    // XXX
1561 3475187d bellard
1562 3475187d bellard
}
1563 3475187d bellard
1564 3475187d bellard
void OPPROTO op_ld_asi_reg()
1565 3475187d bellard
{
1566 3475187d bellard
    T0 += PARAM1;
1567 3475187d bellard
    helper_ld_asi(env->asi, PARAM2, PARAM3);
1568 3475187d bellard
}
1569 3475187d bellard
1570 3475187d bellard
void OPPROTO op_st_asi_reg()
1571 3475187d bellard
{
1572 3475187d bellard
    T0 += PARAM1;
1573 3475187d bellard
    helper_st_asi(env->asi, PARAM2, PARAM3);
1574 3475187d bellard
}
1575 3475187d bellard
#endif
1576 3475187d bellard
1577 e8af50a3 bellard
void OPPROTO op_ld_asi()
1578 e8af50a3 bellard
{
1579 e8af50a3 bellard
    helper_ld_asi(PARAM1, PARAM2, PARAM3);
1580 e8af50a3 bellard
}
1581 e8af50a3 bellard
1582 e8af50a3 bellard
void OPPROTO op_st_asi()
1583 e8af50a3 bellard
{
1584 e8af50a3 bellard
    helper_st_asi(PARAM1, PARAM2, PARAM3);
1585 e8af50a3 bellard
}
1586 e8af50a3 bellard
1587 725cb90b bellard
#ifdef TARGET_SPARC64
1588 725cb90b bellard
void OPPROTO op_alignaddr()
1589 725cb90b bellard
{
1590 725cb90b bellard
    uint64_t tmp;
1591 725cb90b bellard
1592 725cb90b bellard
    tmp = T0 + T1;
1593 725cb90b bellard
    env->gsr &= ~7ULL;
1594 725cb90b bellard
    env->gsr |= tmp & 7ULL;
1595 725cb90b bellard
    T0 = tmp & ~7ULL;
1596 725cb90b bellard
}
1597 725cb90b bellard
1598 725cb90b bellard
void OPPROTO op_faligndata()
1599 725cb90b bellard
{
1600 725cb90b bellard
    uint64_t tmp;
1601 725cb90b bellard
1602 725cb90b bellard
    tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
1603 725cb90b bellard
    tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
1604 725cb90b bellard
    (*((uint64_t *)&DT0)) = tmp;
1605 725cb90b bellard
}
1606 725cb90b bellard
#endif