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/*
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 * QEMU System Emulator header
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 * 
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 * Copyright (c) 2003 Fabrice Bellard
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 * 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifdef __sun__
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#define ENOMEDIUM 4097
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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#define ENOMEDIUM 4097
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "audio/audio.h"
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#include "cpu.h"
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#include "gdbstub.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern int vm_running;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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/* XXX: make it dynamic */
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#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#else
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#define BIOS_SIZE ((256 + 64) * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd, 
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                         IOCanRWHandler *fd_read_poll, 
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                         IOHandler *fd_read, 
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                         IOHandler *fd_write, 
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read, 
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque);
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int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_add_read_handler)(struct CharDriverState *s, 
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                                 IOCanRWHandler *fd_can_read, 
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                                 IOReadHandler *fd_read, void *opaque);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_read_handler(CharDriverState *s, 
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                               IOCanRWHandler *fd_can_read, 
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                               IOReadHandler *fd_read, void *opaque);
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void qemu_chr_add_event_handler(CharDriverState *s, IOEventHandler *chr_event);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
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void vga_hw_invalidate(void);
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void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
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CharDriverState *text_console_init(DisplayState *ds);
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void console_select(unsigned int index);
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/* serial ports */
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#define MAX_SERIAL_PORTS 4
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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/* VLANs support */
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typedef struct VLANClientState VLANClientState;
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struct VLANClientState {
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    IOReadHandler *fd_read;
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    /* Packets may still be sent if this returns zero.  It's used to
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       rate-limit the slirp code.  */
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    IOCanRWHandler *fd_can_read;
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    void *opaque;
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    struct VLANClientState *next;
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    struct VLANState *vlan;
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    char info_str[256];
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};
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typedef struct VLANState {
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    int id;
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    VLANClientState *first_client;
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    struct VLANState *next;
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} VLANState;
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VLANState *qemu_find_vlan(int id);
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VLANClientState *qemu_new_vlan_client(VLANState *vlan,
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                                      IOReadHandler *fd_read,
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                                      IOCanRWHandler *fd_can_read,
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                                      void *opaque);
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int qemu_can_send_packet(VLANClientState *vc);
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void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
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void qemu_handler_true(void *opaque);
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void do_info_network(void);
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/* TAP win32 */
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int tap_win32_init(VLANState *vlan, const char *ifname);
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/* NIC info */
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#define MAX_NICS 8
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typedef struct NICInfo {
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    uint8_t macaddr[6];
392 a41b2ff2 pbrook
    const char *model;
393 7c9d8e07 bellard
    VLANState *vlan;
394 7c9d8e07 bellard
} NICInfo;
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396 c4b1fcc0 bellard
extern int nb_nics;
397 7c9d8e07 bellard
extern NICInfo nd_table[MAX_NICS];
398 8a7ddc38 bellard
399 8a7ddc38 bellard
/* timers */
400 8a7ddc38 bellard
401 8a7ddc38 bellard
typedef struct QEMUClock QEMUClock;
402 8a7ddc38 bellard
typedef struct QEMUTimer QEMUTimer;
403 8a7ddc38 bellard
typedef void QEMUTimerCB(void *opaque);
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405 8a7ddc38 bellard
/* The real time clock should be used only for stuff which does not
406 8a7ddc38 bellard
   change the virtual machine state, as it is run even if the virtual
407 69b91039 bellard
   machine is stopped. The real time clock has a frequency of 1000
408 8a7ddc38 bellard
   Hz. */
409 8a7ddc38 bellard
extern QEMUClock *rt_clock;
410 8a7ddc38 bellard
411 e80cfcfc bellard
/* The virtual clock is only run during the emulation. It is stopped
412 8a7ddc38 bellard
   when the virtual machine is stopped. Virtual timers use a high
413 8a7ddc38 bellard
   precision clock, usually cpu cycles (use ticks_per_sec). */
414 8a7ddc38 bellard
extern QEMUClock *vm_clock;
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416 8a7ddc38 bellard
int64_t qemu_get_clock(QEMUClock *clock);
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QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
419 8a7ddc38 bellard
void qemu_free_timer(QEMUTimer *ts);
420 8a7ddc38 bellard
void qemu_del_timer(QEMUTimer *ts);
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void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
422 8a7ddc38 bellard
int qemu_timer_pending(QEMUTimer *ts);
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extern int64_t ticks_per_sec;
425 8a7ddc38 bellard
extern int pit_min_timer_count;
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int64_t cpu_get_ticks(void);
428 8a7ddc38 bellard
void cpu_enable_ticks(void);
429 8a7ddc38 bellard
void cpu_disable_ticks(void);
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/* VM Load/Save */
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typedef struct QEMUFile QEMUFile;
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QEMUFile *qemu_fopen(const char *filename, const char *mode);
436 faea38e7 bellard
void qemu_fflush(QEMUFile *f);
437 faea38e7 bellard
void qemu_fclose(QEMUFile *f);
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void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
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void qemu_put_byte(QEMUFile *f, int v);
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void qemu_put_be16(QEMUFile *f, unsigned int v);
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void qemu_put_be32(QEMUFile *f, unsigned int v);
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void qemu_put_be64(QEMUFile *f, uint64_t v);
443 8a7ddc38 bellard
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
444 8a7ddc38 bellard
int qemu_get_byte(QEMUFile *f);
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unsigned int qemu_get_be16(QEMUFile *f);
446 8a7ddc38 bellard
unsigned int qemu_get_be32(QEMUFile *f);
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uint64_t qemu_get_be64(QEMUFile *f);
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static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
450 8a7ddc38 bellard
{
451 8a7ddc38 bellard
    qemu_put_be64(f, *pv);
452 8a7ddc38 bellard
}
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static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
455 8a7ddc38 bellard
{
456 8a7ddc38 bellard
    qemu_put_be32(f, *pv);
457 8a7ddc38 bellard
}
458 8a7ddc38 bellard
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static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
460 8a7ddc38 bellard
{
461 8a7ddc38 bellard
    qemu_put_be16(f, *pv);
462 8a7ddc38 bellard
}
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static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
465 8a7ddc38 bellard
{
466 8a7ddc38 bellard
    qemu_put_byte(f, *pv);
467 8a7ddc38 bellard
}
468 8a7ddc38 bellard
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static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
470 8a7ddc38 bellard
{
471 8a7ddc38 bellard
    *pv = qemu_get_be64(f);
472 8a7ddc38 bellard
}
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static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
475 8a7ddc38 bellard
{
476 8a7ddc38 bellard
    *pv = qemu_get_be32(f);
477 8a7ddc38 bellard
}
478 8a7ddc38 bellard
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static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
480 8a7ddc38 bellard
{
481 8a7ddc38 bellard
    *pv = qemu_get_be16(f);
482 8a7ddc38 bellard
}
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static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
485 8a7ddc38 bellard
{
486 8a7ddc38 bellard
    *pv = qemu_get_byte(f);
487 8a7ddc38 bellard
}
488 8a7ddc38 bellard
489 c27004ec bellard
#if TARGET_LONG_BITS == 64
490 c27004ec bellard
#define qemu_put_betl qemu_put_be64
491 c27004ec bellard
#define qemu_get_betl qemu_get_be64
492 c27004ec bellard
#define qemu_put_betls qemu_put_be64s
493 c27004ec bellard
#define qemu_get_betls qemu_get_be64s
494 c27004ec bellard
#else
495 c27004ec bellard
#define qemu_put_betl qemu_put_be32
496 c27004ec bellard
#define qemu_get_betl qemu_get_be32
497 c27004ec bellard
#define qemu_put_betls qemu_put_be32s
498 c27004ec bellard
#define qemu_get_betls qemu_get_be32s
499 c27004ec bellard
#endif
500 c27004ec bellard
501 8a7ddc38 bellard
int64_t qemu_ftell(QEMUFile *f);
502 8a7ddc38 bellard
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
503 8a7ddc38 bellard
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typedef void SaveStateHandler(QEMUFile *f, void *opaque);
505 8a7ddc38 bellard
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
506 8a7ddc38 bellard
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int register_savevm(const char *idstr, 
508 8a7ddc38 bellard
                    int instance_id, 
509 8a7ddc38 bellard
                    int version_id,
510 8a7ddc38 bellard
                    SaveStateHandler *save_state,
511 8a7ddc38 bellard
                    LoadStateHandler *load_state,
512 8a7ddc38 bellard
                    void *opaque);
513 8a7ddc38 bellard
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
514 8a7ddc38 bellard
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
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void cpu_save(QEMUFile *f, void *opaque);
517 6a00d601 bellard
int cpu_load(QEMUFile *f, void *opaque, int version_id);
518 6a00d601 bellard
519 faea38e7 bellard
void do_savevm(const char *name);
520 faea38e7 bellard
void do_loadvm(const char *name);
521 faea38e7 bellard
void do_delvm(const char *name);
522 faea38e7 bellard
void do_info_snapshots(void);
523 faea38e7 bellard
524 83f64091 bellard
/* bottom halves */
525 83f64091 bellard
typedef void QEMUBHFunc(void *opaque);
526 83f64091 bellard
527 83f64091 bellard
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
528 83f64091 bellard
void qemu_bh_schedule(QEMUBH *bh);
529 83f64091 bellard
void qemu_bh_cancel(QEMUBH *bh);
530 83f64091 bellard
void qemu_bh_delete(QEMUBH *bh);
531 6eb5733a bellard
int qemu_bh_poll(void);
532 83f64091 bellard
533 fc01f7e7 bellard
/* block.c */
534 fc01f7e7 bellard
typedef struct BlockDriverState BlockDriverState;
535 ea2384d3 bellard
typedef struct BlockDriver BlockDriver;
536 ea2384d3 bellard
537 ea2384d3 bellard
extern BlockDriver bdrv_raw;
538 19cb3738 bellard
extern BlockDriver bdrv_host_device;
539 ea2384d3 bellard
extern BlockDriver bdrv_cow;
540 ea2384d3 bellard
extern BlockDriver bdrv_qcow;
541 ea2384d3 bellard
extern BlockDriver bdrv_vmdk;
542 3c56521b bellard
extern BlockDriver bdrv_cloop;
543 585d0ed9 bellard
extern BlockDriver bdrv_dmg;
544 a8753c34 bellard
extern BlockDriver bdrv_bochs;
545 6a0f9e82 bellard
extern BlockDriver bdrv_vpc;
546 de167e41 bellard
extern BlockDriver bdrv_vvfat;
547 faea38e7 bellard
extern BlockDriver bdrv_qcow2;
548 faea38e7 bellard
549 faea38e7 bellard
typedef struct BlockDriverInfo {
550 faea38e7 bellard
    /* in bytes, 0 if irrelevant */
551 faea38e7 bellard
    int cluster_size; 
552 faea38e7 bellard
    /* offset at which the VM state can be saved (0 if not possible) */
553 faea38e7 bellard
    int64_t vm_state_offset; 
554 faea38e7 bellard
} BlockDriverInfo;
555 faea38e7 bellard
556 faea38e7 bellard
typedef struct QEMUSnapshotInfo {
557 faea38e7 bellard
    char id_str[128]; /* unique snapshot id */
558 faea38e7 bellard
    /* the following fields are informative. They are not needed for
559 faea38e7 bellard
       the consistency of the snapshot */
560 faea38e7 bellard
    char name[256]; /* user choosen name */
561 faea38e7 bellard
    uint32_t vm_state_size; /* VM state info size */
562 faea38e7 bellard
    uint32_t date_sec; /* UTC date of the snapshot */
563 faea38e7 bellard
    uint32_t date_nsec;
564 faea38e7 bellard
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
565 faea38e7 bellard
} QEMUSnapshotInfo;
566 ea2384d3 bellard
567 83f64091 bellard
#define BDRV_O_RDONLY      0x0000
568 83f64091 bellard
#define BDRV_O_RDWR        0x0002
569 83f64091 bellard
#define BDRV_O_ACCESS      0x0003
570 83f64091 bellard
#define BDRV_O_CREAT       0x0004 /* create an empty file */
571 83f64091 bellard
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
572 83f64091 bellard
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
573 83f64091 bellard
                                     use a disk image format on top of
574 83f64091 bellard
                                     it (default for
575 83f64091 bellard
                                     bdrv_file_open()) */
576 83f64091 bellard
577 ea2384d3 bellard
void bdrv_init(void);
578 ea2384d3 bellard
BlockDriver *bdrv_find_format(const char *format_name);
579 ea2384d3 bellard
int bdrv_create(BlockDriver *drv, 
580 ea2384d3 bellard
                const char *filename, int64_t size_in_sectors,
581 ea2384d3 bellard
                const char *backing_file, int flags);
582 c4b1fcc0 bellard
BlockDriverState *bdrv_new(const char *device_name);
583 c4b1fcc0 bellard
void bdrv_delete(BlockDriverState *bs);
584 83f64091 bellard
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
585 83f64091 bellard
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
586 83f64091 bellard
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
587 ea2384d3 bellard
               BlockDriver *drv);
588 fc01f7e7 bellard
void bdrv_close(BlockDriverState *bs);
589 fc01f7e7 bellard
int bdrv_read(BlockDriverState *bs, int64_t sector_num, 
590 fc01f7e7 bellard
              uint8_t *buf, int nb_sectors);
591 fc01f7e7 bellard
int bdrv_write(BlockDriverState *bs, int64_t sector_num, 
592 fc01f7e7 bellard
               const uint8_t *buf, int nb_sectors);
593 83f64091 bellard
int bdrv_pread(BlockDriverState *bs, int64_t offset, 
594 83f64091 bellard
               void *buf, int count);
595 83f64091 bellard
int bdrv_pwrite(BlockDriverState *bs, int64_t offset, 
596 83f64091 bellard
                const void *buf, int count);
597 83f64091 bellard
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
598 83f64091 bellard
int64_t bdrv_getlength(BlockDriverState *bs);
599 fc01f7e7 bellard
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
600 33e3963e bellard
int bdrv_commit(BlockDriverState *bs);
601 77fef8c1 bellard
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
602 83f64091 bellard
/* async block I/O */
603 83f64091 bellard
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
604 83f64091 bellard
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
605 83f64091 bellard
606 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
607 ce1a14dc pbrook
                                uint8_t *buf, int nb_sectors,
608 ce1a14dc pbrook
                                BlockDriverCompletionFunc *cb, void *opaque);
609 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
610 ce1a14dc pbrook
                                 const uint8_t *buf, int nb_sectors,
611 ce1a14dc pbrook
                                 BlockDriverCompletionFunc *cb, void *opaque);
612 83f64091 bellard
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
613 83f64091 bellard
614 83f64091 bellard
void qemu_aio_init(void);
615 83f64091 bellard
void qemu_aio_poll(void);
616 6192bc37 pbrook
void qemu_aio_flush(void);
617 83f64091 bellard
void qemu_aio_wait_start(void);
618 83f64091 bellard
void qemu_aio_wait(void);
619 83f64091 bellard
void qemu_aio_wait_end(void);
620 83f64091 bellard
621 7a6cba61 pbrook
/* Ensure contents are flushed to disk.  */
622 7a6cba61 pbrook
void bdrv_flush(BlockDriverState *bs);
623 33e3963e bellard
624 c4b1fcc0 bellard
#define BDRV_TYPE_HD     0
625 c4b1fcc0 bellard
#define BDRV_TYPE_CDROM  1
626 c4b1fcc0 bellard
#define BDRV_TYPE_FLOPPY 2
627 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_AUTO   0
628 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_NONE   1
629 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LBA    2
630 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LARGE  3
631 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_RECHS  4
632 c4b1fcc0 bellard
633 c4b1fcc0 bellard
void bdrv_set_geometry_hint(BlockDriverState *bs, 
634 c4b1fcc0 bellard
                            int cyls, int heads, int secs);
635 c4b1fcc0 bellard
void bdrv_set_type_hint(BlockDriverState *bs, int type);
636 46d4767d bellard
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
637 c4b1fcc0 bellard
void bdrv_get_geometry_hint(BlockDriverState *bs, 
638 c4b1fcc0 bellard
                            int *pcyls, int *pheads, int *psecs);
639 c4b1fcc0 bellard
int bdrv_get_type_hint(BlockDriverState *bs);
640 46d4767d bellard
int bdrv_get_translation_hint(BlockDriverState *bs);
641 c4b1fcc0 bellard
int bdrv_is_removable(BlockDriverState *bs);
642 c4b1fcc0 bellard
int bdrv_is_read_only(BlockDriverState *bs);
643 c4b1fcc0 bellard
int bdrv_is_inserted(BlockDriverState *bs);
644 19cb3738 bellard
int bdrv_media_changed(BlockDriverState *bs);
645 c4b1fcc0 bellard
int bdrv_is_locked(BlockDriverState *bs);
646 c4b1fcc0 bellard
void bdrv_set_locked(BlockDriverState *bs, int locked);
647 19cb3738 bellard
void bdrv_eject(BlockDriverState *bs, int eject_flag);
648 c4b1fcc0 bellard
void bdrv_set_change_cb(BlockDriverState *bs, 
649 c4b1fcc0 bellard
                        void (*change_cb)(void *opaque), void *opaque);
650 ea2384d3 bellard
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
651 c4b1fcc0 bellard
void bdrv_info(void);
652 c4b1fcc0 bellard
BlockDriverState *bdrv_find(const char *name);
653 82c643ff bellard
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
654 ea2384d3 bellard
int bdrv_is_encrypted(BlockDriverState *bs);
655 ea2384d3 bellard
int bdrv_set_key(BlockDriverState *bs, const char *key);
656 ea2384d3 bellard
void bdrv_iterate_format(void (*it)(void *opaque, const char *name), 
657 ea2384d3 bellard
                         void *opaque);
658 ea2384d3 bellard
const char *bdrv_get_device_name(BlockDriverState *bs);
659 faea38e7 bellard
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num, 
660 faea38e7 bellard
                          const uint8_t *buf, int nb_sectors);
661 faea38e7 bellard
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
662 c4b1fcc0 bellard
663 83f64091 bellard
void bdrv_get_backing_filename(BlockDriverState *bs, 
664 83f64091 bellard
                               char *filename, int filename_size);
665 faea38e7 bellard
int bdrv_snapshot_create(BlockDriverState *bs, 
666 faea38e7 bellard
                         QEMUSnapshotInfo *sn_info);
667 faea38e7 bellard
int bdrv_snapshot_goto(BlockDriverState *bs, 
668 faea38e7 bellard
                       const char *snapshot_id);
669 faea38e7 bellard
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
670 faea38e7 bellard
int bdrv_snapshot_list(BlockDriverState *bs, 
671 faea38e7 bellard
                       QEMUSnapshotInfo **psn_info);
672 faea38e7 bellard
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
673 faea38e7 bellard
674 faea38e7 bellard
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
675 83f64091 bellard
int path_is_absolute(const char *path);
676 83f64091 bellard
void path_combine(char *dest, int dest_size,
677 83f64091 bellard
                  const char *base_path,
678 83f64091 bellard
                  const char *filename);
679 ea2384d3 bellard
680 ea2384d3 bellard
#ifndef QEMU_TOOL
681 54fa5af5 bellard
682 54fa5af5 bellard
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, 
683 54fa5af5 bellard
                                 int boot_device,
684 54fa5af5 bellard
             DisplayState *ds, const char **fd_filename, int snapshot,
685 54fa5af5 bellard
             const char *kernel_filename, const char *kernel_cmdline,
686 54fa5af5 bellard
             const char *initrd_filename);
687 54fa5af5 bellard
688 54fa5af5 bellard
typedef struct QEMUMachine {
689 54fa5af5 bellard
    const char *name;
690 54fa5af5 bellard
    const char *desc;
691 54fa5af5 bellard
    QEMUMachineInitFunc *init;
692 54fa5af5 bellard
    struct QEMUMachine *next;
693 54fa5af5 bellard
} QEMUMachine;
694 54fa5af5 bellard
695 54fa5af5 bellard
int qemu_register_machine(QEMUMachine *m);
696 54fa5af5 bellard
697 54fa5af5 bellard
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
698 3de388f6 bellard
typedef void IRQRequestFunc(void *opaque, int level);
699 54fa5af5 bellard
700 26aa7d72 bellard
/* ISA bus */
701 26aa7d72 bellard
702 26aa7d72 bellard
extern target_phys_addr_t isa_mem_base;
703 26aa7d72 bellard
704 26aa7d72 bellard
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
705 26aa7d72 bellard
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
706 26aa7d72 bellard
707 26aa7d72 bellard
int register_ioport_read(int start, int length, int size, 
708 26aa7d72 bellard
                         IOPortReadFunc *func, void *opaque);
709 26aa7d72 bellard
int register_ioport_write(int start, int length, int size, 
710 26aa7d72 bellard
                          IOPortWriteFunc *func, void *opaque);
711 69b91039 bellard
void isa_unassign_ioport(int start, int length);
712 69b91039 bellard
713 aef445bd pbrook
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
714 aef445bd pbrook
715 69b91039 bellard
/* PCI bus */
716 69b91039 bellard
717 69b91039 bellard
extern target_phys_addr_t pci_mem_base;
718 69b91039 bellard
719 46e50e9d bellard
typedef struct PCIBus PCIBus;
720 69b91039 bellard
typedef struct PCIDevice PCIDevice;
721 69b91039 bellard
722 69b91039 bellard
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 
723 69b91039 bellard
                                uint32_t address, uint32_t data, int len);
724 69b91039 bellard
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 
725 69b91039 bellard
                                   uint32_t address, int len);
726 69b91039 bellard
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 
727 69b91039 bellard
                                uint32_t addr, uint32_t size, int type);
728 69b91039 bellard
729 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM                0x00
730 69b91039 bellard
#define PCI_ADDRESS_SPACE_IO                0x01
731 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
732 69b91039 bellard
733 69b91039 bellard
typedef struct PCIIORegion {
734 5768f5ac bellard
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
735 69b91039 bellard
    uint32_t size;
736 69b91039 bellard
    uint8_t type;
737 69b91039 bellard
    PCIMapIORegionFunc *map_func;
738 69b91039 bellard
} PCIIORegion;
739 69b91039 bellard
740 8a8696a3 bellard
#define PCI_ROM_SLOT 6
741 8a8696a3 bellard
#define PCI_NUM_REGIONS 7
742 502a5395 pbrook
743 502a5395 pbrook
#define PCI_DEVICES_MAX 64
744 502a5395 pbrook
745 502a5395 pbrook
#define PCI_VENDOR_ID                0x00        /* 16 bits */
746 502a5395 pbrook
#define PCI_DEVICE_ID                0x02        /* 16 bits */
747 502a5395 pbrook
#define PCI_COMMAND                0x04        /* 16 bits */
748 502a5395 pbrook
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
749 502a5395 pbrook
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
750 502a5395 pbrook
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
751 502a5395 pbrook
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
752 502a5395 pbrook
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
753 502a5395 pbrook
#define PCI_MIN_GNT                0x3e        /* 8 bits */
754 502a5395 pbrook
#define PCI_MAX_LAT                0x3f        /* 8 bits */
755 502a5395 pbrook
756 69b91039 bellard
struct PCIDevice {
757 69b91039 bellard
    /* PCI config space */
758 69b91039 bellard
    uint8_t config[256];
759 69b91039 bellard
760 69b91039 bellard
    /* the following fields are read only */
761 46e50e9d bellard
    PCIBus *bus;
762 69b91039 bellard
    int devfn;
763 69b91039 bellard
    char name[64];
764 8a8696a3 bellard
    PCIIORegion io_regions[PCI_NUM_REGIONS];
765 69b91039 bellard
    
766 69b91039 bellard
    /* do not access the following fields */
767 69b91039 bellard
    PCIConfigReadFunc *config_read;
768 69b91039 bellard
    PCIConfigWriteFunc *config_write;
769 502a5395 pbrook
    /* ??? This is a PC-specific hack, and should be removed.  */
770 5768f5ac bellard
    int irq_index;
771 d2b59317 pbrook
772 d2b59317 pbrook
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
773 d2b59317 pbrook
    int irq_state[4];
774 69b91039 bellard
};
775 69b91039 bellard
776 46e50e9d bellard
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
777 46e50e9d bellard
                               int instance_size, int devfn,
778 69b91039 bellard
                               PCIConfigReadFunc *config_read, 
779 69b91039 bellard
                               PCIConfigWriteFunc *config_write);
780 69b91039 bellard
781 69b91039 bellard
void pci_register_io_region(PCIDevice *pci_dev, int region_num, 
782 69b91039 bellard
                            uint32_t size, int type, 
783 69b91039 bellard
                            PCIMapIORegionFunc *map_func);
784 69b91039 bellard
785 5768f5ac bellard
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level);
786 5768f5ac bellard
787 5768f5ac bellard
uint32_t pci_default_read_config(PCIDevice *d, 
788 5768f5ac bellard
                                 uint32_t address, int len);
789 5768f5ac bellard
void pci_default_write_config(PCIDevice *d, 
790 5768f5ac bellard
                              uint32_t address, uint32_t val, int len);
791 89b6b508 bellard
void pci_device_save(PCIDevice *s, QEMUFile *f);
792 89b6b508 bellard
int pci_device_load(PCIDevice *s, QEMUFile *f);
793 5768f5ac bellard
794 d2b59317 pbrook
typedef void (*pci_set_irq_fn)(void *pic, int irq_num, int level);
795 d2b59317 pbrook
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
796 d2b59317 pbrook
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
797 80b3ada7 pbrook
                         void *pic, int devfn_min, int nirq);
798 502a5395 pbrook
799 abcebc7e ths
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
800 502a5395 pbrook
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
801 502a5395 pbrook
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
802 502a5395 pbrook
int pci_bus_num(PCIBus *s);
803 80b3ada7 pbrook
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
804 9995c51f bellard
805 5768f5ac bellard
void pci_info(void);
806 80b3ada7 pbrook
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
807 80b3ada7 pbrook
                        pci_map_irq_fn map_irq, const char *name);
808 26aa7d72 bellard
809 502a5395 pbrook
/* prep_pci.c */
810 46e50e9d bellard
PCIBus *pci_prep_init(void);
811 77d4bc34 bellard
812 502a5395 pbrook
/* grackle_pci.c */
813 502a5395 pbrook
PCIBus *pci_grackle_init(uint32_t base, void *pic);
814 502a5395 pbrook
815 502a5395 pbrook
/* unin_pci.c */
816 502a5395 pbrook
PCIBus *pci_pmac_init(void *pic);
817 502a5395 pbrook
818 502a5395 pbrook
/* apb_pci.c */
819 502a5395 pbrook
PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
820 502a5395 pbrook
                     void *pic);
821 502a5395 pbrook
822 e69954b9 pbrook
PCIBus *pci_vpb_init(void *pic, int irq, int realview);
823 502a5395 pbrook
824 502a5395 pbrook
/* piix_pci.c */
825 f00fc47c bellard
PCIBus *i440fx_init(PCIDevice **pi440fx_state);
826 f00fc47c bellard
void i440fx_set_smm(PCIDevice *d, int val);
827 8f1c91d8 ths
int piix3_init(PCIBus *bus, int devfn);
828 f00fc47c bellard
void i440fx_init_memory_mappings(PCIDevice *d);
829 a41b2ff2 pbrook
830 5856de80 ths
int piix4_init(PCIBus *bus, int devfn);
831 5856de80 ths
832 28b9b5af bellard
/* openpic.c */
833 28b9b5af bellard
typedef struct openpic_t openpic_t;
834 54fa5af5 bellard
void openpic_set_irq(void *opaque, int n_IRQ, int level);
835 7668a27f bellard
openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
836 7668a27f bellard
                         CPUState **envp);
837 28b9b5af bellard
838 54fa5af5 bellard
/* heathrow_pic.c */
839 54fa5af5 bellard
typedef struct HeathrowPICS HeathrowPICS;
840 54fa5af5 bellard
void heathrow_pic_set_irq(void *opaque, int num, int level);
841 54fa5af5 bellard
HeathrowPICS *heathrow_pic_init(int *pmem_index);
842 54fa5af5 bellard
843 fde7d5bd ths
/* gt64xxx.c */
844 fde7d5bd ths
PCIBus *pci_gt64120_init(void *pic);
845 fde7d5bd ths
846 6a36d84e bellard
#ifdef HAS_AUDIO
847 6a36d84e bellard
struct soundhw {
848 6a36d84e bellard
    const char *name;
849 6a36d84e bellard
    const char *descr;
850 6a36d84e bellard
    int enabled;
851 6a36d84e bellard
    int isa;
852 6a36d84e bellard
    union {
853 6a36d84e bellard
        int (*init_isa) (AudioState *s);
854 6a36d84e bellard
        int (*init_pci) (PCIBus *bus, AudioState *s);
855 6a36d84e bellard
    } init;
856 6a36d84e bellard
};
857 6a36d84e bellard
858 6a36d84e bellard
extern struct soundhw soundhw[];
859 6a36d84e bellard
#endif
860 6a36d84e bellard
861 313aa567 bellard
/* vga.c */
862 313aa567 bellard
863 74a14f22 bellard
#define VGA_RAM_SIZE (8192 * 1024)
864 313aa567 bellard
865 82c643ff bellard
struct DisplayState {
866 313aa567 bellard
    uint8_t *data;
867 313aa567 bellard
    int linesize;
868 313aa567 bellard
    int depth;
869 d3079cd2 bellard
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
870 82c643ff bellard
    int width;
871 82c643ff bellard
    int height;
872 24236869 bellard
    void *opaque;
873 24236869 bellard
874 313aa567 bellard
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
875 313aa567 bellard
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
876 313aa567 bellard
    void (*dpy_refresh)(struct DisplayState *s);
877 24236869 bellard
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, int dst_x, int dst_y, int w, int h);
878 82c643ff bellard
};
879 313aa567 bellard
880 313aa567 bellard
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
881 313aa567 bellard
{
882 313aa567 bellard
    s->dpy_update(s, x, y, w, h);
883 313aa567 bellard
}
884 313aa567 bellard
885 313aa567 bellard
static inline void dpy_resize(DisplayState *s, int w, int h)
886 313aa567 bellard
{
887 313aa567 bellard
    s->dpy_resize(s, w, h);
888 313aa567 bellard
}
889 313aa567 bellard
890 89b6b508 bellard
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 
891 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size);
892 89b6b508 bellard
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
893 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size,
894 89b6b508 bellard
                 unsigned long vga_bios_offset, int vga_bios_size);
895 313aa567 bellard
896 d6bfa22f bellard
/* cirrus_vga.c */
897 46e50e9d bellard
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
898 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
899 d6bfa22f bellard
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 
900 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
901 d6bfa22f bellard
902 313aa567 bellard
/* sdl.c */
903 d63d307f bellard
void sdl_display_init(DisplayState *ds, int full_screen);
904 313aa567 bellard
905 da4dbf74 bellard
/* cocoa.m */
906 da4dbf74 bellard
void cocoa_display_init(DisplayState *ds, int full_screen);
907 da4dbf74 bellard
908 24236869 bellard
/* vnc.c */
909 73fc9742 ths
void vnc_display_init(DisplayState *ds, const char *display);
910 24236869 bellard
911 5391d806 bellard
/* ide.c */
912 5391d806 bellard
#define MAX_DISKS 4
913 5391d806 bellard
914 faea38e7 bellard
extern BlockDriverState *bs_table[MAX_DISKS + 1];
915 5391d806 bellard
916 69b91039 bellard
void isa_ide_init(int iobase, int iobase2, int irq,
917 69b91039 bellard
                  BlockDriverState *hd0, BlockDriverState *hd1);
918 54fa5af5 bellard
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
919 54fa5af5 bellard
                         int secondary_ide_enabled);
920 502a5395 pbrook
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn);
921 28b9b5af bellard
int pmac_ide_init (BlockDriverState **hd_table,
922 54fa5af5 bellard
                   SetIRQFunc *set_irq, void *irq_opaque, int irq);
923 5391d806 bellard
924 2e5d83bb pbrook
/* cdrom.c */
925 2e5d83bb pbrook
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
926 2e5d83bb pbrook
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
927 2e5d83bb pbrook
928 1d14ffa9 bellard
/* es1370.c */
929 c0fe3827 bellard
int es1370_init (PCIBus *bus, AudioState *s);
930 1d14ffa9 bellard
931 fb065187 bellard
/* sb16.c */
932 c0fe3827 bellard
int SB16_init (AudioState *s);
933 fb065187 bellard
934 fb065187 bellard
/* adlib.c */
935 c0fe3827 bellard
int Adlib_init (AudioState *s);
936 fb065187 bellard
937 fb065187 bellard
/* gus.c */
938 c0fe3827 bellard
int GUS_init (AudioState *s);
939 27503323 bellard
940 27503323 bellard
/* dma.c */
941 85571bc7 bellard
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
942 27503323 bellard
int DMA_get_channel_mode (int nchan);
943 85571bc7 bellard
int DMA_read_memory (int nchan, void *buf, int pos, int size);
944 85571bc7 bellard
int DMA_write_memory (int nchan, void *buf, int pos, int size);
945 27503323 bellard
void DMA_hold_DREQ (int nchan);
946 27503323 bellard
void DMA_release_DREQ (int nchan);
947 16f62432 bellard
void DMA_schedule(int nchan);
948 27503323 bellard
void DMA_run (void);
949 28b9b5af bellard
void DMA_init (int high_page_enable);
950 27503323 bellard
void DMA_register_channel (int nchan,
951 85571bc7 bellard
                           DMA_transfer_handler transfer_handler,
952 85571bc7 bellard
                           void *opaque);
953 7138fcfb bellard
/* fdc.c */
954 7138fcfb bellard
#define MAX_FD 2
955 7138fcfb bellard
extern BlockDriverState *fd_table[MAX_FD];
956 7138fcfb bellard
957 baca51fa bellard
typedef struct fdctrl_t fdctrl_t;
958 baca51fa bellard
959 baca51fa bellard
fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped, 
960 baca51fa bellard
                       uint32_t io_base,
961 baca51fa bellard
                       BlockDriverState **fds);
962 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
963 7138fcfb bellard
964 80cabfad bellard
/* ne2000.c */
965 80cabfad bellard
966 7c9d8e07 bellard
void isa_ne2000_init(int base, int irq, NICInfo *nd);
967 abcebc7e ths
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
968 80cabfad bellard
969 a41b2ff2 pbrook
/* rtl8139.c */
970 a41b2ff2 pbrook
971 abcebc7e ths
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
972 a41b2ff2 pbrook
973 e3c2613f bellard
/* pcnet.c */
974 e3c2613f bellard
975 abcebc7e ths
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
976 67e999be bellard
void pcnet_h_reset(void *opaque);
977 67e999be bellard
void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque);
978 67e999be bellard
979 e3c2613f bellard
980 80cabfad bellard
/* pckbd.c */
981 80cabfad bellard
982 80cabfad bellard
void kbd_init(void);
983 80cabfad bellard
984 80cabfad bellard
/* mc146818rtc.c */
985 80cabfad bellard
986 8a7ddc38 bellard
typedef struct RTCState RTCState;
987 80cabfad bellard
988 8a7ddc38 bellard
RTCState *rtc_init(int base, int irq);
989 8a7ddc38 bellard
void rtc_set_memory(RTCState *s, int addr, int val);
990 8a7ddc38 bellard
void rtc_set_date(RTCState *s, const struct tm *tm);
991 80cabfad bellard
992 80cabfad bellard
/* serial.c */
993 80cabfad bellard
994 c4b1fcc0 bellard
typedef struct SerialState SerialState;
995 e5d13e2f bellard
SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
996 e5d13e2f bellard
                         int base, int irq, CharDriverState *chr);
997 e5d13e2f bellard
SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
998 e5d13e2f bellard
                             target_ulong base, int it_shift,
999 e5d13e2f bellard
                             int irq, CharDriverState *chr);
1000 80cabfad bellard
1001 6508fe59 bellard
/* parallel.c */
1002 6508fe59 bellard
1003 6508fe59 bellard
typedef struct ParallelState ParallelState;
1004 6508fe59 bellard
ParallelState *parallel_init(int base, int irq, CharDriverState *chr);
1005 6508fe59 bellard
1006 80cabfad bellard
/* i8259.c */
1007 80cabfad bellard
1008 3de388f6 bellard
typedef struct PicState2 PicState2;
1009 3de388f6 bellard
extern PicState2 *isa_pic;
1010 80cabfad bellard
void pic_set_irq(int irq, int level);
1011 54fa5af5 bellard
void pic_set_irq_new(void *opaque, int irq, int level);
1012 3de388f6 bellard
PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque);
1013 d592d303 bellard
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1014 d592d303 bellard
                          void *alt_irq_opaque);
1015 3de388f6 bellard
int pic_read_irq(PicState2 *s);
1016 3de388f6 bellard
void pic_update_irq(PicState2 *s);
1017 3de388f6 bellard
uint32_t pic_intack_read(PicState2 *s);
1018 c20709aa bellard
void pic_info(void);
1019 4a0fb71e bellard
void irq_info(void);
1020 80cabfad bellard
1021 c27004ec bellard
/* APIC */
1022 d592d303 bellard
typedef struct IOAPICState IOAPICState;
1023 d592d303 bellard
1024 c27004ec bellard
int apic_init(CPUState *env);
1025 c27004ec bellard
int apic_get_interrupt(CPUState *env);
1026 d592d303 bellard
IOAPICState *ioapic_init(void);
1027 d592d303 bellard
void ioapic_set_irq(void *opaque, int vector, int level);
1028 c27004ec bellard
1029 80cabfad bellard
/* i8254.c */
1030 80cabfad bellard
1031 80cabfad bellard
#define PIT_FREQ 1193182
1032 80cabfad bellard
1033 ec844b96 bellard
typedef struct PITState PITState;
1034 ec844b96 bellard
1035 ec844b96 bellard
PITState *pit_init(int base, int irq);
1036 ec844b96 bellard
void pit_set_gate(PITState *pit, int channel, int val);
1037 ec844b96 bellard
int pit_get_gate(PITState *pit, int channel);
1038 fd06c375 bellard
int pit_get_initial_count(PITState *pit, int channel);
1039 fd06c375 bellard
int pit_get_mode(PITState *pit, int channel);
1040 ec844b96 bellard
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1041 80cabfad bellard
1042 fd06c375 bellard
/* pcspk.c */
1043 fd06c375 bellard
void pcspk_init(PITState *);
1044 fd06c375 bellard
int pcspk_audio_init(AudioState *);
1045 fd06c375 bellard
1046 6515b203 bellard
/* acpi.c */
1047 6515b203 bellard
extern int acpi_enabled;
1048 502a5395 pbrook
void piix4_pm_init(PCIBus *bus, int devfn);
1049 6515b203 bellard
void acpi_bios_init(void);
1050 6515b203 bellard
1051 80cabfad bellard
/* pc.c */
1052 54fa5af5 bellard
extern QEMUMachine pc_machine;
1053 3dbbdc25 bellard
extern QEMUMachine isapc_machine;
1054 52ca8d6a bellard
extern int fd_bootchk;
1055 80cabfad bellard
1056 6a00d601 bellard
void ioport_set_a20(int enable);
1057 6a00d601 bellard
int ioport_get_a20(void);
1058 6a00d601 bellard
1059 26aa7d72 bellard
/* ppc.c */
1060 54fa5af5 bellard
extern QEMUMachine prep_machine;
1061 54fa5af5 bellard
extern QEMUMachine core99_machine;
1062 54fa5af5 bellard
extern QEMUMachine heathrow_machine;
1063 54fa5af5 bellard
1064 6af0bf9c bellard
/* mips_r4k.c */
1065 6af0bf9c bellard
extern QEMUMachine mips_machine;
1066 6af0bf9c bellard
1067 5856de80 ths
/* mips_malta.c */
1068 5856de80 ths
extern QEMUMachine mips_malta_machine;
1069 5856de80 ths
1070 e16fe40c ths
/* mips_timer.c */
1071 e16fe40c ths
extern void cpu_mips_clock_init(CPUState *);
1072 e16fe40c ths
extern void cpu_mips_irqctrl_init (void);
1073 e16fe40c ths
1074 27c7ca7e bellard
/* shix.c */
1075 27c7ca7e bellard
extern QEMUMachine shix_machine;
1076 27c7ca7e bellard
1077 8cc43fef bellard
#ifdef TARGET_PPC
1078 8cc43fef bellard
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1079 8cc43fef bellard
#endif
1080 64201201 bellard
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1081 77d4bc34 bellard
1082 77d4bc34 bellard
extern CPUWriteMemoryFunc *PPC_io_write[];
1083 77d4bc34 bellard
extern CPUReadMemoryFunc *PPC_io_read[];
1084 54fa5af5 bellard
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1085 26aa7d72 bellard
1086 e95c8d51 bellard
/* sun4m.c */
1087 54fa5af5 bellard
extern QEMUMachine sun4m_machine;
1088 ba3c64fb bellard
void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
1089 e95c8d51 bellard
1090 e95c8d51 bellard
/* iommu.c */
1091 e80cfcfc bellard
void *iommu_init(uint32_t addr);
1092 67e999be bellard
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1093 a917d384 pbrook
                                 uint8_t *buf, int len, int is_write);
1094 67e999be bellard
static inline void sparc_iommu_memory_read(void *opaque,
1095 67e999be bellard
                                           target_phys_addr_t addr,
1096 67e999be bellard
                                           uint8_t *buf, int len)
1097 67e999be bellard
{
1098 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1099 67e999be bellard
}
1100 e95c8d51 bellard
1101 67e999be bellard
static inline void sparc_iommu_memory_write(void *opaque,
1102 67e999be bellard
                                            target_phys_addr_t addr,
1103 67e999be bellard
                                            uint8_t *buf, int len)
1104 67e999be bellard
{
1105 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1106 67e999be bellard
}
1107 e95c8d51 bellard
1108 e95c8d51 bellard
/* tcx.c */
1109 95219897 pbrook
void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
1110 6f7e9aec bellard
               unsigned long vram_offset, int vram_size, int width, int height);
1111 e80cfcfc bellard
1112 e80cfcfc bellard
/* slavio_intctl.c */
1113 e80cfcfc bellard
void *slavio_intctl_init();
1114 ba3c64fb bellard
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
1115 e80cfcfc bellard
void slavio_pic_info(void *opaque);
1116 e80cfcfc bellard
void slavio_irq_info(void *opaque);
1117 e80cfcfc bellard
void slavio_pic_set_irq(void *opaque, int irq, int level);
1118 ba3c64fb bellard
void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
1119 e95c8d51 bellard
1120 5fe141fd bellard
/* loader.c */
1121 5fe141fd bellard
int get_image_size(const char *filename);
1122 5fe141fd bellard
int load_image(const char *filename, uint8_t *addr);
1123 9ee3c029 bellard
int load_elf(const char *filename, int64_t virt_to_phys_addend, uint64_t *pentry);
1124 e80cfcfc bellard
int load_aout(const char *filename, uint8_t *addr);
1125 e80cfcfc bellard
1126 e80cfcfc bellard
/* slavio_timer.c */
1127 ba3c64fb bellard
void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu);
1128 8d5f07fa bellard
1129 e80cfcfc bellard
/* slavio_serial.c */
1130 e80cfcfc bellard
SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2);
1131 e80cfcfc bellard
void slavio_serial_ms_kbd_init(int base, int irq);
1132 e95c8d51 bellard
1133 3475187d bellard
/* slavio_misc.c */
1134 3475187d bellard
void *slavio_misc_init(uint32_t base, int irq);
1135 3475187d bellard
void slavio_set_power_fail(void *opaque, int power_failing);
1136 3475187d bellard
1137 6f7e9aec bellard
/* esp.c */
1138 fa1fb14c ths
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1139 67e999be bellard
void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque);
1140 67e999be bellard
void esp_reset(void *opaque);
1141 67e999be bellard
1142 67e999be bellard
/* sparc32_dma.c */
1143 67e999be bellard
void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu,
1144 67e999be bellard
                       void *intctl);
1145 67e999be bellard
void ledma_set_irq(void *opaque, int isr);
1146 9b94dc32 bellard
void ledma_memory_read(void *opaque, target_phys_addr_t addr, 
1147 9b94dc32 bellard
                       uint8_t *buf, int len, int do_bswap);
1148 9b94dc32 bellard
void ledma_memory_write(void *opaque, target_phys_addr_t addr, 
1149 9b94dc32 bellard
                        uint8_t *buf, int len, int do_bswap);
1150 67e999be bellard
void espdma_raise_irq(void *opaque);
1151 67e999be bellard
void espdma_clear_irq(void *opaque);
1152 67e999be bellard
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1153 67e999be bellard
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1154 67e999be bellard
void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
1155 67e999be bellard
                                void *lance_opaque);
1156 6f7e9aec bellard
1157 b8174937 bellard
/* cs4231.c */
1158 b8174937 bellard
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1159 b8174937 bellard
1160 3475187d bellard
/* sun4u.c */
1161 3475187d bellard
extern QEMUMachine sun4u_machine;
1162 3475187d bellard
1163 64201201 bellard
/* NVRAM helpers */
1164 64201201 bellard
#include "hw/m48t59.h"
1165 64201201 bellard
1166 64201201 bellard
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1167 64201201 bellard
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1168 64201201 bellard
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1169 64201201 bellard
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1170 64201201 bellard
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1171 64201201 bellard
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1172 64201201 bellard
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1173 64201201 bellard
                       const unsigned char *str, uint32_t max);
1174 64201201 bellard
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1175 64201201 bellard
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1176 64201201 bellard
                    uint32_t start, uint32_t count);
1177 64201201 bellard
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1178 64201201 bellard
                          const unsigned char *arch,
1179 64201201 bellard
                          uint32_t RAM_size, int boot_device,
1180 64201201 bellard
                          uint32_t kernel_image, uint32_t kernel_size,
1181 28b9b5af bellard
                          const char *cmdline,
1182 64201201 bellard
                          uint32_t initrd_image, uint32_t initrd_size,
1183 28b9b5af bellard
                          uint32_t NVRAM_image,
1184 28b9b5af bellard
                          int width, int height, int depth);
1185 64201201 bellard
1186 63066f4f bellard
/* adb.c */
1187 63066f4f bellard
1188 63066f4f bellard
#define MAX_ADB_DEVICES 16
1189 63066f4f bellard
1190 e2733d20 bellard
#define ADB_MAX_OUT_LEN 16
1191 63066f4f bellard
1192 e2733d20 bellard
typedef struct ADBDevice ADBDevice;
1193 63066f4f bellard
1194 e2733d20 bellard
/* buf = NULL means polling */
1195 e2733d20 bellard
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1196 e2733d20 bellard
                              const uint8_t *buf, int len);
1197 12c28fed bellard
typedef int ADBDeviceReset(ADBDevice *d);
1198 12c28fed bellard
1199 63066f4f bellard
struct ADBDevice {
1200 63066f4f bellard
    struct ADBBusState *bus;
1201 63066f4f bellard
    int devaddr;
1202 63066f4f bellard
    int handler;
1203 e2733d20 bellard
    ADBDeviceRequest *devreq;
1204 12c28fed bellard
    ADBDeviceReset *devreset;
1205 63066f4f bellard
    void *opaque;
1206 63066f4f bellard
};
1207 63066f4f bellard
1208 63066f4f bellard
typedef struct ADBBusState {
1209 63066f4f bellard
    ADBDevice devices[MAX_ADB_DEVICES];
1210 63066f4f bellard
    int nb_devices;
1211 e2733d20 bellard
    int poll_index;
1212 63066f4f bellard
} ADBBusState;
1213 63066f4f bellard
1214 e2733d20 bellard
int adb_request(ADBBusState *s, uint8_t *buf_out,
1215 e2733d20 bellard
                const uint8_t *buf, int len);
1216 e2733d20 bellard
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1217 63066f4f bellard
1218 63066f4f bellard
ADBDevice *adb_register_device(ADBBusState *s, int devaddr, 
1219 e2733d20 bellard
                               ADBDeviceRequest *devreq, 
1220 12c28fed bellard
                               ADBDeviceReset *devreset, 
1221 63066f4f bellard
                               void *opaque);
1222 63066f4f bellard
void adb_kbd_init(ADBBusState *bus);
1223 63066f4f bellard
void adb_mouse_init(ADBBusState *bus);
1224 63066f4f bellard
1225 63066f4f bellard
/* cuda.c */
1226 63066f4f bellard
1227 63066f4f bellard
extern ADBBusState adb_bus;
1228 54fa5af5 bellard
int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq);
1229 63066f4f bellard
1230 bb36d470 bellard
#include "hw/usb.h"
1231 bb36d470 bellard
1232 a594cfbf bellard
/* usb ports of the VM */
1233 a594cfbf bellard
1234 0d92ed30 pbrook
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1235 0d92ed30 pbrook
                            usb_attachfn attach);
1236 a594cfbf bellard
1237 0d92ed30 pbrook
#define VM_USB_HUB_SIZE 8
1238 a594cfbf bellard
1239 a594cfbf bellard
void do_usb_add(const char *devname);
1240 a594cfbf bellard
void do_usb_del(const char *devname);
1241 a594cfbf bellard
void usb_info(void);
1242 a594cfbf bellard
1243 2e5d83bb pbrook
/* scsi-disk.c */
1244 4d611c9a pbrook
enum scsi_reason {
1245 4d611c9a pbrook
    SCSI_REASON_DONE, /* Command complete.  */
1246 4d611c9a pbrook
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1247 4d611c9a pbrook
};
1248 4d611c9a pbrook
1249 2e5d83bb pbrook
typedef struct SCSIDevice SCSIDevice;
1250 a917d384 pbrook
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1251 a917d384 pbrook
                                  uint32_t arg);
1252 2e5d83bb pbrook
1253 2e5d83bb pbrook
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1254 a917d384 pbrook
                           int tcq,
1255 2e5d83bb pbrook
                           scsi_completionfn completion,
1256 2e5d83bb pbrook
                           void *opaque);
1257 2e5d83bb pbrook
void scsi_disk_destroy(SCSIDevice *s);
1258 2e5d83bb pbrook
1259 0fc5c15a pbrook
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1260 4d611c9a pbrook
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1261 4d611c9a pbrook
   layer the completion routine may be called directly by
1262 4d611c9a pbrook
   scsi_{read,write}_data.  */
1263 a917d384 pbrook
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1264 a917d384 pbrook
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1265 a917d384 pbrook
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1266 a917d384 pbrook
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1267 2e5d83bb pbrook
1268 7d8406be pbrook
/* lsi53c895a.c */
1269 7d8406be pbrook
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1270 7d8406be pbrook
void *lsi_scsi_init(PCIBus *bus, int devfn);
1271 7d8406be pbrook
1272 b5ff1b31 bellard
/* integratorcp.c */
1273 40f137e1 pbrook
extern QEMUMachine integratorcp926_machine;
1274 40f137e1 pbrook
extern QEMUMachine integratorcp1026_machine;
1275 b5ff1b31 bellard
1276 cdbdb648 pbrook
/* versatilepb.c */
1277 cdbdb648 pbrook
extern QEMUMachine versatilepb_machine;
1278 16406950 pbrook
extern QEMUMachine versatileab_machine;
1279 cdbdb648 pbrook
1280 e69954b9 pbrook
/* realview.c */
1281 e69954b9 pbrook
extern QEMUMachine realview_machine;
1282 e69954b9 pbrook
1283 daa57963 bellard
/* ps2.c */
1284 daa57963 bellard
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1285 daa57963 bellard
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1286 daa57963 bellard
void ps2_write_mouse(void *, int val);
1287 daa57963 bellard
void ps2_write_keyboard(void *, int val);
1288 daa57963 bellard
uint32_t ps2_read_data(void *);
1289 daa57963 bellard
void ps2_queue(void *, int b);
1290 f94f5d71 pbrook
void ps2_keyboard_set_translation(void *opaque, int mode);
1291 daa57963 bellard
1292 80337b66 bellard
/* smc91c111.c */
1293 80337b66 bellard
void smc91c111_init(NICInfo *, uint32_t, void *, int);
1294 80337b66 bellard
1295 bdd5003a pbrook
/* pl110.c */
1296 95219897 pbrook
void *pl110_init(DisplayState *ds, uint32_t base, void *pic, int irq, int);
1297 bdd5003a pbrook
1298 cdbdb648 pbrook
/* pl011.c */
1299 cdbdb648 pbrook
void pl011_init(uint32_t base, void *pic, int irq, CharDriverState *chr);
1300 cdbdb648 pbrook
1301 cdbdb648 pbrook
/* pl050.c */
1302 cdbdb648 pbrook
void pl050_init(uint32_t base, void *pic, int irq, int is_mouse);
1303 cdbdb648 pbrook
1304 cdbdb648 pbrook
/* pl080.c */
1305 e69954b9 pbrook
void *pl080_init(uint32_t base, void *pic, int irq, int nchannels);
1306 cdbdb648 pbrook
1307 cdbdb648 pbrook
/* pl190.c */
1308 cdbdb648 pbrook
void *pl190_init(uint32_t base, void *parent, int irq, int fiq);
1309 cdbdb648 pbrook
1310 cdbdb648 pbrook
/* arm-timer.c */
1311 cdbdb648 pbrook
void sp804_init(uint32_t base, void *pic, int irq);
1312 cdbdb648 pbrook
void icp_pit_init(uint32_t base, void *pic, int irq);
1313 cdbdb648 pbrook
1314 e69954b9 pbrook
/* arm_sysctl.c */
1315 e69954b9 pbrook
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1316 e69954b9 pbrook
1317 e69954b9 pbrook
/* arm_gic.c */
1318 e69954b9 pbrook
void *arm_gic_init(uint32_t base, void *parent, int parent_irq);
1319 e69954b9 pbrook
1320 16406950 pbrook
/* arm_boot.c */
1321 16406950 pbrook
1322 daf90626 pbrook
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1323 16406950 pbrook
                     const char *kernel_cmdline, const char *initrd_filename,
1324 16406950 pbrook
                     int board_id);
1325 16406950 pbrook
1326 27c7ca7e bellard
/* sh7750.c */
1327 27c7ca7e bellard
struct SH7750State;
1328 27c7ca7e bellard
1329 008a8818 pbrook
struct SH7750State *sh7750_init(CPUState * cpu);
1330 27c7ca7e bellard
1331 27c7ca7e bellard
typedef struct {
1332 27c7ca7e bellard
    /* The callback will be triggered if any of the designated lines change */
1333 27c7ca7e bellard
    uint16_t portamask_trigger;
1334 27c7ca7e bellard
    uint16_t portbmask_trigger;
1335 27c7ca7e bellard
    /* Return 0 if no action was taken */
1336 27c7ca7e bellard
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1337 27c7ca7e bellard
                           uint16_t * periph_pdtra,
1338 27c7ca7e bellard
                           uint16_t * periph_portdira,
1339 27c7ca7e bellard
                           uint16_t * periph_pdtrb,
1340 27c7ca7e bellard
                           uint16_t * periph_portdirb);
1341 27c7ca7e bellard
} sh7750_io_device;
1342 27c7ca7e bellard
1343 27c7ca7e bellard
int sh7750_register_io_device(struct SH7750State *s,
1344 27c7ca7e bellard
                              sh7750_io_device * device);
1345 27c7ca7e bellard
/* tc58128.c */
1346 27c7ca7e bellard
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1347 27c7ca7e bellard
1348 29133e9a bellard
/* NOR flash devices */
1349 29133e9a bellard
typedef struct pflash_t pflash_t;
1350 29133e9a bellard
1351 29133e9a bellard
pflash_t *pflash_register (target_ulong base, ram_addr_t off,
1352 29133e9a bellard
                           BlockDriverState *bs,
1353 29133e9a bellard
                           target_ulong sector_len, int nb_blocs, int width,
1354 29133e9a bellard
                           uint16_t id0, uint16_t id1, 
1355 29133e9a bellard
                           uint16_t id2, uint16_t id3);
1356 29133e9a bellard
1357 ea2384d3 bellard
#endif /* defined(QEMU_TOOL) */
1358 ea2384d3 bellard
1359 c4b1fcc0 bellard
/* monitor.c */
1360 82c643ff bellard
void monitor_init(CharDriverState *hd, int show_banner);
1361 ea2384d3 bellard
void term_puts(const char *str);
1362 ea2384d3 bellard
void term_vprintf(const char *fmt, va_list ap);
1363 40c3bac3 bellard
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1364 fef30743 ths
void term_print_filename(const char *filename);
1365 c4b1fcc0 bellard
void term_flush(void);
1366 c4b1fcc0 bellard
void term_print_help(void);
1367 ea2384d3 bellard
void monitor_readline(const char *prompt, int is_password,
1368 ea2384d3 bellard
                      char *buf, int buf_size);
1369 ea2384d3 bellard
1370 ea2384d3 bellard
/* readline.c */
1371 ea2384d3 bellard
typedef void ReadLineFunc(void *opaque, const char *str);
1372 ea2384d3 bellard
1373 ea2384d3 bellard
extern int completion_index;
1374 ea2384d3 bellard
void add_completion(const char *str);
1375 ea2384d3 bellard
void readline_handle_byte(int ch);
1376 ea2384d3 bellard
void readline_find_completion(const char *cmdline);
1377 ea2384d3 bellard
const char *readline_get_history(unsigned int index);
1378 ea2384d3 bellard
void readline_start(const char *prompt, int is_password,
1379 ea2384d3 bellard
                    ReadLineFunc *readline_func, void *opaque);
1380 c4b1fcc0 bellard
1381 5e6ad6f9 bellard
void kqemu_record_dump(void);
1382 5e6ad6f9 bellard
1383 fc01f7e7 bellard
#endif /* VL_H */