root / hw / lm832x.c @ 18be5187
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/*
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* National Semiconductor LM8322/8323 GPIO keyboard & PWM chips.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "hw.h" |
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#include "i2c.h" |
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#include "qemu-timer.h" |
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#include "console.h" |
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struct lm_kbd_s {
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i2c_slave i2c; |
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int i2c_dir;
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int i2c_cycle;
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int reg;
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qemu_irq nirq; |
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uint16_t model; |
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struct {
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qemu_irq out[2];
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int in[2][2]; |
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} mux; |
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uint8_t config; |
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uint8_t status; |
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uint8_t acttime; |
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uint8_t error; |
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uint8_t clock; |
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|
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struct {
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uint16_t pull; |
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uint16_t mask; |
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uint16_t dir; |
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uint16_t level; |
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qemu_irq out[16];
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} gpio; |
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struct {
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uint8_t dbnctime; |
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uint8_t size; |
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int start;
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int len;
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uint8_t fifo[16];
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} kbd; |
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|
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struct {
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uint16_t file[256];
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uint8_t faddr; |
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uint8_t addr[3];
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QEMUTimer *tm[3];
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} pwm; |
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}; |
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#define INT_KEYPAD (1 << 0) |
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#define INT_ERROR (1 << 3) |
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#define INT_NOINIT (1 << 4) |
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#define INT_PWMEND(n) (1 << (5 + n)) |
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|
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#define ERR_BADPAR (1 << 0) |
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#define ERR_CMDUNK (1 << 1) |
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#define ERR_KEYOVR (1 << 2) |
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#define ERR_FIFOOVR (1 << 6) |
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static void lm_kbd_irq_update(struct lm_kbd_s *s) |
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{ |
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qemu_set_irq(s->nirq, !s->status); |
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} |
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static void lm_kbd_gpio_update(struct lm_kbd_s *s) |
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{ |
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} |
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static void lm_kbd_reset(struct lm_kbd_s *s) |
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{ |
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s->config = 0x80;
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s->status = INT_NOINIT; |
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s->acttime = 125;
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s->kbd.dbnctime = 3;
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s->kbd.size = 0x33;
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s->clock = 0x08;
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lm_kbd_irq_update(s); |
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lm_kbd_gpio_update(s); |
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} |
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static void lm_kbd_error(struct lm_kbd_s *s, int err) |
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{ |
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s->error |= err; |
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s->status |= INT_ERROR; |
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lm_kbd_irq_update(s); |
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} |
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static void lm_kbd_pwm_tick(struct lm_kbd_s *s, int line) |
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{ |
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} |
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static void lm_kbd_pwm_start(struct lm_kbd_s *s, int line) |
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{ |
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lm_kbd_pwm_tick(s, line); |
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} |
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static void lm_kbd_pwm0_tick(void *opaque) |
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{ |
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lm_kbd_pwm_tick(opaque, 0);
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} |
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static void lm_kbd_pwm1_tick(void *opaque) |
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{ |
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lm_kbd_pwm_tick(opaque, 1);
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} |
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static void lm_kbd_pwm2_tick(void *opaque) |
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{ |
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lm_kbd_pwm_tick(opaque, 2);
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} |
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enum {
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LM832x_CMD_READ_ID = 0x80, /* Read chip ID. */ |
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LM832x_CMD_WRITE_CFG = 0x81, /* Set configuration item. */ |
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LM832x_CMD_READ_INT = 0x82, /* Get interrupt status. */ |
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LM832x_CMD_RESET = 0x83, /* Reset, same as external one */ |
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LM823x_CMD_WRITE_PULL_DOWN = 0x84, /* Select GPIO pull-up/down. */ |
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LM832x_CMD_WRITE_PORT_SEL = 0x85, /* Select GPIO in/out. */ |
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LM832x_CMD_WRITE_PORT_STATE = 0x86, /* Set GPIO pull-up/down. */ |
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LM832x_CMD_READ_PORT_SEL = 0x87, /* Get GPIO in/out. */ |
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LM832x_CMD_READ_PORT_STATE = 0x88, /* Get GPIO pull-up/down. */ |
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LM832x_CMD_READ_FIFO = 0x89, /* Read byte from FIFO. */ |
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LM832x_CMD_RPT_READ_FIFO = 0x8a, /* Read FIFO (no increment). */ |
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LM832x_CMD_SET_ACTIVE = 0x8b, /* Set active time. */ |
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LM832x_CMD_READ_ERROR = 0x8c, /* Get error status. */ |
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LM832x_CMD_READ_ROTATOR = 0x8e, /* Read rotator status. */ |
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LM832x_CMD_SET_DEBOUNCE = 0x8f, /* Set debouncing time. */ |
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LM832x_CMD_SET_KEY_SIZE = 0x90, /* Set keypad size. */ |
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LM832x_CMD_READ_KEY_SIZE = 0x91, /* Get keypad size. */ |
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LM832x_CMD_READ_CFG = 0x92, /* Get configuration item. */ |
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LM832x_CMD_WRITE_CLOCK = 0x93, /* Set clock config. */ |
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LM832x_CMD_READ_CLOCK = 0x94, /* Get clock config. */ |
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LM832x_CMD_PWM_WRITE = 0x95, /* Write PWM script. */ |
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LM832x_CMD_PWM_START = 0x96, /* Start PWM engine. */ |
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LM832x_CMD_PWM_STOP = 0x97, /* Stop PWM engine. */ |
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}; |
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#define LM832x_MAX_KPX 8 |
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#define LM832x_MAX_KPY 12 |
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static uint8_t lm_kbd_read(struct lm_kbd_s *s, int reg, int byte) |
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{ |
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int ret;
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switch (reg) {
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case LM832x_CMD_READ_ID:
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ret = 0x0400;
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break;
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case LM832x_CMD_READ_INT:
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ret = s->status; |
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if (!(s->status & INT_NOINIT)) {
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s->status = 0;
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lm_kbd_irq_update(s); |
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} |
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break;
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case LM832x_CMD_READ_PORT_SEL:
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ret = s->gpio.dir; |
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break;
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case LM832x_CMD_READ_PORT_STATE:
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ret = s->gpio.mask; |
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break;
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case LM832x_CMD_READ_FIFO:
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if (s->kbd.len <= 1) |
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return 0x00; |
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/* Example response from the two commands after a INT_KEYPAD
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* interrupt caused by the key 0x3c being pressed:
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* RPT_READ_FIFO: 55 bc 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
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* READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
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* RPT_READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
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*
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* 55 is the code of the key release event serviced in the previous
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* interrupt handling.
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*
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* TODO: find out whether the FIFO is advanced a single character
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* before reading every byte or the whole size of the FIFO at the
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* last LM832x_CMD_READ_FIFO. This affects LM832x_CMD_RPT_READ_FIFO
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* output in cases where there are more than one event in the FIFO.
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* Assume 0xbc and 0x3c events are in the FIFO:
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* RPT_READ_FIFO: 55 bc 3c 00 4e ff 0a 50 08 00 29 d9 08 01 c9
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* READ_FIFO: bc 3c 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9
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* Does RPT_READ_FIFO now return 0xbc and 0x3c or only 0x3c?
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*/
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s->kbd.start ++; |
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s->kbd.start &= sizeof(s->kbd.fifo) - 1; |
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s->kbd.len --; |
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return s->kbd.fifo[s->kbd.start];
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case LM832x_CMD_RPT_READ_FIFO:
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if (byte >= s->kbd.len)
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return 0x00; |
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return s->kbd.fifo[(s->kbd.start + byte) & (sizeof(s->kbd.fifo) - 1)]; |
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case LM832x_CMD_READ_ERROR:
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return s->error;
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case LM832x_CMD_READ_ROTATOR:
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return 0; |
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case LM832x_CMD_READ_KEY_SIZE:
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return s->kbd.size;
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case LM832x_CMD_READ_CFG:
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return s->config & 0xf; |
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case LM832x_CMD_READ_CLOCK:
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return (s->clock & 0xfc) | 2; |
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default:
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lm_kbd_error(s, ERR_CMDUNK); |
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fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, reg);
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return 0x00; |
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} |
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return ret >> (byte << 3); |
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} |
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static void lm_kbd_write(struct lm_kbd_s *s, int reg, int byte, uint8_t value) |
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{ |
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switch (reg) {
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case LM832x_CMD_WRITE_CFG:
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s->config = value; |
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/* This must be done whenever s->mux.in is updated (never). */
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if ((s->config >> 1) & 1) /* MUX1EN */ |
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qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 0) & 1]); |
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if ((s->config >> 3) & 1) /* MUX2EN */ |
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qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 2) & 1]); |
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/* TODO: check that this is issued only following the chip reset
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* and not in the middle of operation and that it is followed by
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* the GPIO ports re-resablishing through WRITE_PORT_SEL and
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* WRITE_PORT_STATE (using a timer perhaps) and otherwise output
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* warnings. */
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s->status = 0;
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lm_kbd_irq_update(s); |
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s->kbd.len = 0;
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s->kbd.start = 0;
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s->reg = -1;
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break;
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case LM832x_CMD_RESET:
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if (value == 0xaa) |
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lm_kbd_reset(s); |
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else
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lm_kbd_error(s, ERR_BADPAR); |
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s->reg = -1;
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break;
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case LM823x_CMD_WRITE_PULL_DOWN:
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if (!byte)
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s->gpio.pull = value; |
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else {
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s->gpio.pull |= value << 8;
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lm_kbd_gpio_update(s); |
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s->reg = -1;
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} |
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break;
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case LM832x_CMD_WRITE_PORT_SEL:
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if (!byte)
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s->gpio.dir = value; |
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else {
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s->gpio.dir |= value << 8;
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lm_kbd_gpio_update(s); |
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s->reg = -1;
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} |
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break;
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case LM832x_CMD_WRITE_PORT_STATE:
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if (!byte)
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s->gpio.mask = value; |
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else {
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s->gpio.mask |= value << 8;
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lm_kbd_gpio_update(s); |
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s->reg = -1;
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} |
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break;
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case LM832x_CMD_SET_ACTIVE:
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s->acttime = value; |
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s->reg = -1;
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break;
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case LM832x_CMD_SET_DEBOUNCE:
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s->kbd.dbnctime = value; |
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s->reg = -1;
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if (!value)
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lm_kbd_error(s, ERR_BADPAR); |
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break;
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case LM832x_CMD_SET_KEY_SIZE:
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s->kbd.size = value; |
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s->reg = -1;
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if (
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(value & 0xf) < 3 || (value & 0xf) > LM832x_MAX_KPY || |
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(value >> 4) < 3 || (value >> 4) > LM832x_MAX_KPX) |
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lm_kbd_error(s, ERR_BADPAR); |
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break;
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case LM832x_CMD_WRITE_CLOCK:
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s->clock = value; |
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s->reg = -1;
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if ((value & 3) && (value & 3) != 3) { |
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lm_kbd_error(s, ERR_BADPAR); |
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fprintf(stderr, "%s: invalid clock setting in RCPWM\n",
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__FUNCTION__); |
329 |
} |
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/* TODO: Validate that the command is only issued once */
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break;
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|
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case LM832x_CMD_PWM_WRITE:
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if (byte == 0) { |
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if (!(value & 3) || (value >> 2) > 59) { |
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lm_kbd_error(s, ERR_BADPAR); |
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s->reg = -1;
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break;
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} |
340 |
|
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s->pwm.faddr = value; |
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s->pwm.file[s->pwm.faddr] = 0;
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} else if (byte == 1) { |
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s->pwm.file[s->pwm.faddr] |= value << 8;
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} else if (byte == 2) { |
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s->pwm.file[s->pwm.faddr] |= value << 0;
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s->reg = -1;
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} |
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break;
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case LM832x_CMD_PWM_START:
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s->reg = -1;
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if (!(value & 3) || (value >> 2) > 59) { |
353 |
lm_kbd_error(s, ERR_BADPAR); |
354 |
break;
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} |
356 |
|
357 |
s->pwm.addr[(value & 3) - 1] = value >> 2; |
358 |
lm_kbd_pwm_start(s, (value & 3) - 1); |
359 |
break;
|
360 |
case LM832x_CMD_PWM_STOP:
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s->reg = -1;
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362 |
if (!(value & 3)) { |
363 |
lm_kbd_error(s, ERR_BADPAR); |
364 |
break;
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} |
366 |
|
367 |
qemu_del_timer(s->pwm.tm[(value & 3) - 1]); |
368 |
break;
|
369 |
|
370 |
case -1: |
371 |
lm_kbd_error(s, ERR_BADPAR); |
372 |
break;
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default:
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374 |
lm_kbd_error(s, ERR_CMDUNK); |
375 |
fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, reg);
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376 |
break;
|
377 |
} |
378 |
} |
379 |
|
380 |
static void lm_i2c_event(i2c_slave *i2c, enum i2c_event event) |
381 |
{ |
382 |
struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
383 |
|
384 |
switch (event) {
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385 |
case I2C_START_RECV:
|
386 |
case I2C_START_SEND:
|
387 |
s->i2c_cycle = 0;
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388 |
s->i2c_dir = (event == I2C_START_SEND); |
389 |
break;
|
390 |
|
391 |
default:
|
392 |
break;
|
393 |
} |
394 |
} |
395 |
|
396 |
static int lm_i2c_rx(i2c_slave *i2c) |
397 |
{ |
398 |
struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
399 |
|
400 |
return lm_kbd_read(s, s->reg, s->i2c_cycle ++);
|
401 |
} |
402 |
|
403 |
static int lm_i2c_tx(i2c_slave *i2c, uint8_t data) |
404 |
{ |
405 |
struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
406 |
|
407 |
if (!s->i2c_cycle)
|
408 |
s->reg = data; |
409 |
else
|
410 |
lm_kbd_write(s, s->reg, s->i2c_cycle - 1, data);
|
411 |
s->i2c_cycle ++; |
412 |
|
413 |
return 0; |
414 |
} |
415 |
|
416 |
static void lm_kbd_save(QEMUFile *f, void *opaque) |
417 |
{ |
418 |
struct lm_kbd_s *s = (struct lm_kbd_s *) opaque; |
419 |
int i;
|
420 |
|
421 |
i2c_slave_save(f, &s->i2c); |
422 |
qemu_put_byte(f, s->i2c_dir); |
423 |
qemu_put_byte(f, s->i2c_cycle); |
424 |
qemu_put_byte(f, (uint8_t) s->reg); |
425 |
|
426 |
qemu_put_8s(f, &s->config); |
427 |
qemu_put_8s(f, &s->status); |
428 |
qemu_put_8s(f, &s->acttime); |
429 |
qemu_put_8s(f, &s->error); |
430 |
qemu_put_8s(f, &s->clock); |
431 |
|
432 |
qemu_put_be16s(f, &s->gpio.pull); |
433 |
qemu_put_be16s(f, &s->gpio.mask); |
434 |
qemu_put_be16s(f, &s->gpio.dir); |
435 |
qemu_put_be16s(f, &s->gpio.level); |
436 |
|
437 |
qemu_put_byte(f, s->kbd.dbnctime); |
438 |
qemu_put_byte(f, s->kbd.size); |
439 |
qemu_put_byte(f, s->kbd.start); |
440 |
qemu_put_byte(f, s->kbd.len); |
441 |
qemu_put_buffer(f, s->kbd.fifo, sizeof(s->kbd.fifo));
|
442 |
|
443 |
for (i = 0; i < sizeof(s->pwm.file); i ++) |
444 |
qemu_put_be16s(f, &s->pwm.file[i]); |
445 |
qemu_put_8s(f, &s->pwm.faddr); |
446 |
qemu_put_buffer(f, s->pwm.addr, sizeof(s->pwm.addr));
|
447 |
qemu_put_timer(f, s->pwm.tm[0]);
|
448 |
qemu_put_timer(f, s->pwm.tm[1]);
|
449 |
qemu_put_timer(f, s->pwm.tm[2]);
|
450 |
} |
451 |
|
452 |
static int lm_kbd_load(QEMUFile *f, void *opaque, int version_id) |
453 |
{ |
454 |
struct lm_kbd_s *s = (struct lm_kbd_s *) opaque; |
455 |
int i;
|
456 |
|
457 |
i2c_slave_load(f, &s->i2c); |
458 |
s->i2c_dir = qemu_get_byte(f); |
459 |
s->i2c_cycle = qemu_get_byte(f); |
460 |
s->reg = (int8_t) qemu_get_byte(f); |
461 |
|
462 |
qemu_get_8s(f, &s->config); |
463 |
qemu_get_8s(f, &s->status); |
464 |
qemu_get_8s(f, &s->acttime); |
465 |
qemu_get_8s(f, &s->error); |
466 |
qemu_get_8s(f, &s->clock); |
467 |
|
468 |
qemu_get_be16s(f, &s->gpio.pull); |
469 |
qemu_get_be16s(f, &s->gpio.mask); |
470 |
qemu_get_be16s(f, &s->gpio.dir); |
471 |
qemu_get_be16s(f, &s->gpio.level); |
472 |
|
473 |
s->kbd.dbnctime = qemu_get_byte(f); |
474 |
s->kbd.size = qemu_get_byte(f); |
475 |
s->kbd.start = qemu_get_byte(f); |
476 |
s->kbd.len = qemu_get_byte(f); |
477 |
qemu_get_buffer(f, s->kbd.fifo, sizeof(s->kbd.fifo));
|
478 |
|
479 |
for (i = 0; i < sizeof(s->pwm.file); i ++) |
480 |
qemu_get_be16s(f, &s->pwm.file[i]); |
481 |
qemu_get_8s(f, &s->pwm.faddr); |
482 |
qemu_get_buffer(f, s->pwm.addr, sizeof(s->pwm.addr));
|
483 |
qemu_get_timer(f, s->pwm.tm[0]);
|
484 |
qemu_get_timer(f, s->pwm.tm[1]);
|
485 |
qemu_get_timer(f, s->pwm.tm[2]);
|
486 |
|
487 |
lm_kbd_irq_update(s); |
488 |
lm_kbd_gpio_update(s); |
489 |
|
490 |
return 0; |
491 |
} |
492 |
|
493 |
struct i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq)
|
494 |
{ |
495 |
struct lm_kbd_s *s;
|
496 |
|
497 |
s = (struct lm_kbd_s *) i2c_slave_init(bus, 0, sizeof(struct lm_kbd_s)); |
498 |
s->model = 0x8323;
|
499 |
s->pwm.tm[0] = qemu_new_timer(vm_clock, lm_kbd_pwm0_tick, s);
|
500 |
s->pwm.tm[1] = qemu_new_timer(vm_clock, lm_kbd_pwm1_tick, s);
|
501 |
s->pwm.tm[2] = qemu_new_timer(vm_clock, lm_kbd_pwm2_tick, s);
|
502 |
s->nirq = nirq; |
503 |
|
504 |
s->i2c.event = lm_i2c_event; |
505 |
s->i2c.recv = lm_i2c_rx; |
506 |
s->i2c.send = lm_i2c_tx; |
507 |
|
508 |
lm_kbd_reset(s); |
509 |
|
510 |
qemu_register_reset((void *) lm_kbd_reset, s);
|
511 |
register_savevm("LM8323", -1, 0, lm_kbd_save, lm_kbd_load, s); |
512 |
|
513 |
return &s->i2c;
|
514 |
} |
515 |
|
516 |
void lm832x_key_event(struct i2c_slave *i2c, int key, int state) |
517 |
{ |
518 |
struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
519 |
|
520 |
if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR))
|
521 |
return;
|
522 |
|
523 |
if (s->kbd.len >= sizeof(s->kbd.fifo)) |
524 |
return lm_kbd_error(s, ERR_FIFOOVR);
|
525 |
|
526 |
s->kbd.fifo[(s->kbd.start + s->kbd.len ++) & (sizeof(s->kbd.fifo) - 1)] = |
527 |
key | (state << 7);
|
528 |
|
529 |
/* We never set ERR_KEYOVR because we support multiple keys fine. */
|
530 |
s->status |= INT_KEYPAD; |
531 |
lm_kbd_irq_update(s); |
532 |
} |