root / hw / slavio_misc.c @ 18ebcc86
History | View | Annotate | Download (12.2 kB)
1 | 3475187d | bellard | /*
|
---|---|---|---|
2 | 3475187d | bellard | * QEMU Sparc SLAVIO aux io port emulation
|
3 | 5fafdf24 | ths | *
|
4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
|
12 | 3475187d | bellard | *
|
13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 3475187d | bellard | * all copies or substantial portions of the Software.
|
15 | 3475187d | bellard | *
|
16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 3475187d | bellard | * THE SOFTWARE.
|
23 | 3475187d | bellard | */
|
24 | 2582cfa0 | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "sysemu.h" |
26 | 2582cfa0 | Blue Swirl | #include "sysbus.h" |
27 | 97bf4851 | Blue Swirl | #include "trace.h" |
28 | 3475187d | bellard | |
29 | 3475187d | bellard | /*
|
30 | 3475187d | bellard | * This is the auxio port, chip control and system control part of
|
31 | 3475187d | bellard | * chip STP2001 (Slave I/O), also produced as NCR89C105. See
|
32 | 3475187d | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
|
33 | 3475187d | bellard | *
|
34 | 3475187d | bellard | * This also includes the PMC CPU idle controller.
|
35 | 3475187d | bellard | */
|
36 | 3475187d | bellard | |
37 | 3475187d | bellard | typedef struct MiscState { |
38 | 2582cfa0 | Blue Swirl | SysBusDevice busdev; |
39 | d537cf6c | pbrook | qemu_irq irq; |
40 | 97bbb109 | Blue Swirl | qemu_irq fdc_tc; |
41 | d37adb09 | Blue Swirl | uint32_t dummy; |
42 | 3475187d | bellard | uint8_t config; |
43 | 3475187d | bellard | uint8_t aux1, aux2; |
44 | bfa30a38 | blueswir1 | uint8_t diag, mctrl; |
45 | d37adb09 | Blue Swirl | uint8_t sysctrl; |
46 | 6a3b9cc9 | blueswir1 | uint16_t leds; |
47 | 3475187d | bellard | } MiscState; |
48 | 3475187d | bellard | |
49 | 2582cfa0 | Blue Swirl | typedef struct APCState { |
50 | 2582cfa0 | Blue Swirl | SysBusDevice busdev; |
51 | 2582cfa0 | Blue Swirl | qemu_irq cpu_halt; |
52 | 2582cfa0 | Blue Swirl | } APCState; |
53 | 2582cfa0 | Blue Swirl | |
54 | 5aca8c3b | blueswir1 | #define MISC_SIZE 1 |
55 | a8f48dcc | blueswir1 | #define SYSCTRL_SIZE 4 |
56 | 3475187d | bellard | |
57 | 2be17ebd | blueswir1 | #define AUX1_TC 0x02 |
58 | 2be17ebd | blueswir1 | |
59 | 7debeb82 | blueswir1 | #define AUX2_PWROFF 0x01 |
60 | 7debeb82 | blueswir1 | #define AUX2_PWRINTCLR 0x02 |
61 | 7debeb82 | blueswir1 | #define AUX2_PWRFAIL 0x20 |
62 | 7debeb82 | blueswir1 | |
63 | 7debeb82 | blueswir1 | #define CFG_PWRINTEN 0x08 |
64 | 7debeb82 | blueswir1 | |
65 | 7debeb82 | blueswir1 | #define SYS_RESET 0x01 |
66 | 7debeb82 | blueswir1 | #define SYS_RESETSTAT 0x02 |
67 | 7debeb82 | blueswir1 | |
68 | 3475187d | bellard | static void slavio_misc_update_irq(void *opaque) |
69 | 3475187d | bellard | { |
70 | 3475187d | bellard | MiscState *s = opaque; |
71 | 3475187d | bellard | |
72 | 7debeb82 | blueswir1 | if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
|
73 | 97bf4851 | Blue Swirl | trace_slavio_misc_update_irq_raise(); |
74 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
75 | 3475187d | bellard | } else {
|
76 | 97bf4851 | Blue Swirl | trace_slavio_misc_update_irq_lower(); |
77 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
78 | 3475187d | bellard | } |
79 | 3475187d | bellard | } |
80 | 3475187d | bellard | |
81 | 1795057a | Blue Swirl | static void slavio_misc_reset(DeviceState *d) |
82 | 3475187d | bellard | { |
83 | 1795057a | Blue Swirl | MiscState *s = container_of(d, MiscState, busdev.qdev); |
84 | 3475187d | bellard | |
85 | 4e3b1ea1 | bellard | // Diagnostic and system control registers not cleared in reset
|
86 | 3475187d | bellard | s->config = s->aux1 = s->aux2 = s->mctrl = 0;
|
87 | 3475187d | bellard | } |
88 | 3475187d | bellard | |
89 | b2b6f6ec | Blue Swirl | static void slavio_set_power_fail(void *opaque, int irq, int power_failing) |
90 | 3475187d | bellard | { |
91 | 3475187d | bellard | MiscState *s = opaque; |
92 | 3475187d | bellard | |
93 | 97bf4851 | Blue Swirl | trace_slavio_set_power_fail(power_failing, s->config); |
94 | 7debeb82 | blueswir1 | if (power_failing && (s->config & CFG_PWRINTEN)) {
|
95 | 7debeb82 | blueswir1 | s->aux2 |= AUX2_PWRFAIL; |
96 | 3475187d | bellard | } else {
|
97 | 7debeb82 | blueswir1 | s->aux2 &= ~AUX2_PWRFAIL; |
98 | 3475187d | bellard | } |
99 | 3475187d | bellard | slavio_misc_update_irq(s); |
100 | 3475187d | bellard | } |
101 | 3475187d | bellard | |
102 | c227f099 | Anthony Liguori | static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr, |
103 | a8f48dcc | blueswir1 | uint32_t val) |
104 | a8f48dcc | blueswir1 | { |
105 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
106 | a8f48dcc | blueswir1 | |
107 | 97bf4851 | Blue Swirl | trace_slavio_cfg_mem_writeb(val & 0xff);
|
108 | a8f48dcc | blueswir1 | s->config = val & 0xff;
|
109 | a8f48dcc | blueswir1 | slavio_misc_update_irq(s); |
110 | a8f48dcc | blueswir1 | } |
111 | a8f48dcc | blueswir1 | |
112 | c227f099 | Anthony Liguori | static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr) |
113 | a8f48dcc | blueswir1 | { |
114 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
115 | a8f48dcc | blueswir1 | uint32_t ret = 0;
|
116 | a8f48dcc | blueswir1 | |
117 | a8f48dcc | blueswir1 | ret = s->config; |
118 | 97bf4851 | Blue Swirl | trace_slavio_cfg_mem_readb(ret); |
119 | a8f48dcc | blueswir1 | return ret;
|
120 | a8f48dcc | blueswir1 | } |
121 | a8f48dcc | blueswir1 | |
122 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = { |
123 | a8f48dcc | blueswir1 | slavio_cfg_mem_readb, |
124 | a8f48dcc | blueswir1 | NULL,
|
125 | a8f48dcc | blueswir1 | NULL,
|
126 | a8f48dcc | blueswir1 | }; |
127 | a8f48dcc | blueswir1 | |
128 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = { |
129 | a8f48dcc | blueswir1 | slavio_cfg_mem_writeb, |
130 | a8f48dcc | blueswir1 | NULL,
|
131 | a8f48dcc | blueswir1 | NULL,
|
132 | a8f48dcc | blueswir1 | }; |
133 | a8f48dcc | blueswir1 | |
134 | c227f099 | Anthony Liguori | static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr, |
135 | bfa30a38 | blueswir1 | uint32_t val) |
136 | 3475187d | bellard | { |
137 | 3475187d | bellard | MiscState *s = opaque; |
138 | 3475187d | bellard | |
139 | 97bf4851 | Blue Swirl | trace_slavio_diag_mem_writeb(val & 0xff);
|
140 | a8f48dcc | blueswir1 | s->diag = val & 0xff;
|
141 | 3475187d | bellard | } |
142 | 3475187d | bellard | |
143 | c227f099 | Anthony Liguori | static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr) |
144 | 3475187d | bellard | { |
145 | 3475187d | bellard | MiscState *s = opaque; |
146 | 3475187d | bellard | uint32_t ret = 0;
|
147 | 3475187d | bellard | |
148 | a8f48dcc | blueswir1 | ret = s->diag; |
149 | 97bf4851 | Blue Swirl | trace_slavio_diag_mem_readb(ret); |
150 | a8f48dcc | blueswir1 | return ret;
|
151 | a8f48dcc | blueswir1 | } |
152 | a8f48dcc | blueswir1 | |
153 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = { |
154 | a8f48dcc | blueswir1 | slavio_diag_mem_readb, |
155 | a8f48dcc | blueswir1 | NULL,
|
156 | a8f48dcc | blueswir1 | NULL,
|
157 | a8f48dcc | blueswir1 | }; |
158 | a8f48dcc | blueswir1 | |
159 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = { |
160 | a8f48dcc | blueswir1 | slavio_diag_mem_writeb, |
161 | a8f48dcc | blueswir1 | NULL,
|
162 | a8f48dcc | blueswir1 | NULL,
|
163 | a8f48dcc | blueswir1 | }; |
164 | a8f48dcc | blueswir1 | |
165 | c227f099 | Anthony Liguori | static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr, |
166 | a8f48dcc | blueswir1 | uint32_t val) |
167 | a8f48dcc | blueswir1 | { |
168 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
169 | a8f48dcc | blueswir1 | |
170 | 97bf4851 | Blue Swirl | trace_slavio_mdm_mem_writeb(val & 0xff);
|
171 | a8f48dcc | blueswir1 | s->mctrl = val & 0xff;
|
172 | a8f48dcc | blueswir1 | } |
173 | a8f48dcc | blueswir1 | |
174 | c227f099 | Anthony Liguori | static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr) |
175 | a8f48dcc | blueswir1 | { |
176 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
177 | a8f48dcc | blueswir1 | uint32_t ret = 0;
|
178 | a8f48dcc | blueswir1 | |
179 | a8f48dcc | blueswir1 | ret = s->mctrl; |
180 | 97bf4851 | Blue Swirl | trace_slavio_mdm_mem_readb(ret); |
181 | 3475187d | bellard | return ret;
|
182 | 3475187d | bellard | } |
183 | 3475187d | bellard | |
184 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = { |
185 | a8f48dcc | blueswir1 | slavio_mdm_mem_readb, |
186 | 7c560456 | blueswir1 | NULL,
|
187 | 7c560456 | blueswir1 | NULL,
|
188 | 3475187d | bellard | }; |
189 | 3475187d | bellard | |
190 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = { |
191 | a8f48dcc | blueswir1 | slavio_mdm_mem_writeb, |
192 | 7c560456 | blueswir1 | NULL,
|
193 | 7c560456 | blueswir1 | NULL,
|
194 | 3475187d | bellard | }; |
195 | 3475187d | bellard | |
196 | c227f099 | Anthony Liguori | static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr, |
197 | 0019ad53 | blueswir1 | uint32_t val) |
198 | 0019ad53 | blueswir1 | { |
199 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
200 | 0019ad53 | blueswir1 | |
201 | 97bf4851 | Blue Swirl | trace_slavio_aux1_mem_writeb(val & 0xff);
|
202 | 2be17ebd | blueswir1 | if (val & AUX1_TC) {
|
203 | 2be17ebd | blueswir1 | // Send a pulse to floppy terminal count line
|
204 | 2be17ebd | blueswir1 | if (s->fdc_tc) {
|
205 | 2be17ebd | blueswir1 | qemu_irq_raise(s->fdc_tc); |
206 | 2be17ebd | blueswir1 | qemu_irq_lower(s->fdc_tc); |
207 | 2be17ebd | blueswir1 | } |
208 | 2be17ebd | blueswir1 | val &= ~AUX1_TC; |
209 | 2be17ebd | blueswir1 | } |
210 | 0019ad53 | blueswir1 | s->aux1 = val & 0xff;
|
211 | 0019ad53 | blueswir1 | } |
212 | 0019ad53 | blueswir1 | |
213 | c227f099 | Anthony Liguori | static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr) |
214 | 0019ad53 | blueswir1 | { |
215 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
216 | 0019ad53 | blueswir1 | uint32_t ret = 0;
|
217 | 0019ad53 | blueswir1 | |
218 | 0019ad53 | blueswir1 | ret = s->aux1; |
219 | 97bf4851 | Blue Swirl | trace_slavio_aux1_mem_readb(ret); |
220 | 0019ad53 | blueswir1 | return ret;
|
221 | 0019ad53 | blueswir1 | } |
222 | 0019ad53 | blueswir1 | |
223 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = { |
224 | 0019ad53 | blueswir1 | slavio_aux1_mem_readb, |
225 | 0019ad53 | blueswir1 | NULL,
|
226 | 0019ad53 | blueswir1 | NULL,
|
227 | 0019ad53 | blueswir1 | }; |
228 | 0019ad53 | blueswir1 | |
229 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = { |
230 | 0019ad53 | blueswir1 | slavio_aux1_mem_writeb, |
231 | 0019ad53 | blueswir1 | NULL,
|
232 | 0019ad53 | blueswir1 | NULL,
|
233 | 0019ad53 | blueswir1 | }; |
234 | 0019ad53 | blueswir1 | |
235 | c227f099 | Anthony Liguori | static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr, |
236 | 0019ad53 | blueswir1 | uint32_t val) |
237 | 0019ad53 | blueswir1 | { |
238 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
239 | 0019ad53 | blueswir1 | |
240 | 0019ad53 | blueswir1 | val &= AUX2_PWRINTCLR | AUX2_PWROFF; |
241 | 97bf4851 | Blue Swirl | trace_slavio_aux2_mem_writeb(val & 0xff);
|
242 | 0019ad53 | blueswir1 | val |= s->aux2 & AUX2_PWRFAIL; |
243 | 0019ad53 | blueswir1 | if (val & AUX2_PWRINTCLR) // Clear Power Fail int |
244 | 0019ad53 | blueswir1 | val &= AUX2_PWROFF; |
245 | 0019ad53 | blueswir1 | s->aux2 = val; |
246 | 0019ad53 | blueswir1 | if (val & AUX2_PWROFF)
|
247 | 0019ad53 | blueswir1 | qemu_system_shutdown_request(); |
248 | 0019ad53 | blueswir1 | slavio_misc_update_irq(s); |
249 | 0019ad53 | blueswir1 | } |
250 | 0019ad53 | blueswir1 | |
251 | c227f099 | Anthony Liguori | static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr) |
252 | 0019ad53 | blueswir1 | { |
253 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
254 | 0019ad53 | blueswir1 | uint32_t ret = 0;
|
255 | 0019ad53 | blueswir1 | |
256 | 0019ad53 | blueswir1 | ret = s->aux2; |
257 | 97bf4851 | Blue Swirl | trace_slavio_aux2_mem_readb(ret); |
258 | 0019ad53 | blueswir1 | return ret;
|
259 | 0019ad53 | blueswir1 | } |
260 | 0019ad53 | blueswir1 | |
261 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = { |
262 | 0019ad53 | blueswir1 | slavio_aux2_mem_readb, |
263 | 0019ad53 | blueswir1 | NULL,
|
264 | 0019ad53 | blueswir1 | NULL,
|
265 | 0019ad53 | blueswir1 | }; |
266 | 0019ad53 | blueswir1 | |
267 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = { |
268 | 0019ad53 | blueswir1 | slavio_aux2_mem_writeb, |
269 | 0019ad53 | blueswir1 | NULL,
|
270 | 0019ad53 | blueswir1 | NULL,
|
271 | 0019ad53 | blueswir1 | }; |
272 | 0019ad53 | blueswir1 | |
273 | c227f099 | Anthony Liguori | static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
274 | 0019ad53 | blueswir1 | { |
275 | 2582cfa0 | Blue Swirl | APCState *s = opaque; |
276 | 0019ad53 | blueswir1 | |
277 | 97bf4851 | Blue Swirl | trace_apc_mem_writeb(val & 0xff);
|
278 | 6d0c293d | blueswir1 | qemu_irq_raise(s->cpu_halt); |
279 | 0019ad53 | blueswir1 | } |
280 | 0019ad53 | blueswir1 | |
281 | c227f099 | Anthony Liguori | static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr) |
282 | 0019ad53 | blueswir1 | { |
283 | 0019ad53 | blueswir1 | uint32_t ret = 0;
|
284 | 0019ad53 | blueswir1 | |
285 | 97bf4851 | Blue Swirl | trace_apc_mem_readb(ret); |
286 | 0019ad53 | blueswir1 | return ret;
|
287 | 0019ad53 | blueswir1 | } |
288 | 0019ad53 | blueswir1 | |
289 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const apc_mem_read[3] = { |
290 | 0019ad53 | blueswir1 | apc_mem_readb, |
291 | 0019ad53 | blueswir1 | NULL,
|
292 | 0019ad53 | blueswir1 | NULL,
|
293 | 0019ad53 | blueswir1 | }; |
294 | 0019ad53 | blueswir1 | |
295 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const apc_mem_write[3] = { |
296 | 0019ad53 | blueswir1 | apc_mem_writeb, |
297 | 0019ad53 | blueswir1 | NULL,
|
298 | 0019ad53 | blueswir1 | NULL,
|
299 | 0019ad53 | blueswir1 | }; |
300 | 0019ad53 | blueswir1 | |
301 | c227f099 | Anthony Liguori | static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) |
302 | bfa30a38 | blueswir1 | { |
303 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
304 | a8f48dcc | blueswir1 | uint32_t ret = 0;
|
305 | bfa30a38 | blueswir1 | |
306 | a8f48dcc | blueswir1 | switch (addr) {
|
307 | bfa30a38 | blueswir1 | case 0: |
308 | bfa30a38 | blueswir1 | ret = s->sysctrl; |
309 | bfa30a38 | blueswir1 | break;
|
310 | bfa30a38 | blueswir1 | default:
|
311 | bfa30a38 | blueswir1 | break;
|
312 | bfa30a38 | blueswir1 | } |
313 | 97bf4851 | Blue Swirl | trace_slavio_sysctrl_mem_readl(ret); |
314 | bfa30a38 | blueswir1 | return ret;
|
315 | bfa30a38 | blueswir1 | } |
316 | bfa30a38 | blueswir1 | |
317 | c227f099 | Anthony Liguori | static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr, |
318 | bfa30a38 | blueswir1 | uint32_t val) |
319 | bfa30a38 | blueswir1 | { |
320 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
321 | bfa30a38 | blueswir1 | |
322 | 97bf4851 | Blue Swirl | trace_slavio_sysctrl_mem_writel(val); |
323 | a8f48dcc | blueswir1 | switch (addr) {
|
324 | bfa30a38 | blueswir1 | case 0: |
325 | 7debeb82 | blueswir1 | if (val & SYS_RESET) {
|
326 | 7debeb82 | blueswir1 | s->sysctrl = SYS_RESETSTAT; |
327 | bfa30a38 | blueswir1 | qemu_system_reset_request(); |
328 | bfa30a38 | blueswir1 | } |
329 | bfa30a38 | blueswir1 | break;
|
330 | bfa30a38 | blueswir1 | default:
|
331 | bfa30a38 | blueswir1 | break;
|
332 | bfa30a38 | blueswir1 | } |
333 | bfa30a38 | blueswir1 | } |
334 | bfa30a38 | blueswir1 | |
335 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = { |
336 | 7c560456 | blueswir1 | NULL,
|
337 | 7c560456 | blueswir1 | NULL,
|
338 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_readl, |
339 | bfa30a38 | blueswir1 | }; |
340 | bfa30a38 | blueswir1 | |
341 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = { |
342 | 7c560456 | blueswir1 | NULL,
|
343 | 7c560456 | blueswir1 | NULL,
|
344 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_writel, |
345 | bfa30a38 | blueswir1 | }; |
346 | bfa30a38 | blueswir1 | |
347 | c227f099 | Anthony Liguori | static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr) |
348 | 6a3b9cc9 | blueswir1 | { |
349 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
350 | a8f48dcc | blueswir1 | uint32_t ret = 0;
|
351 | 6a3b9cc9 | blueswir1 | |
352 | a8f48dcc | blueswir1 | switch (addr) {
|
353 | 6a3b9cc9 | blueswir1 | case 0: |
354 | 6a3b9cc9 | blueswir1 | ret = s->leds; |
355 | 6a3b9cc9 | blueswir1 | break;
|
356 | 6a3b9cc9 | blueswir1 | default:
|
357 | 6a3b9cc9 | blueswir1 | break;
|
358 | 6a3b9cc9 | blueswir1 | } |
359 | 97bf4851 | Blue Swirl | trace_slavio_led_mem_readw(ret); |
360 | 6a3b9cc9 | blueswir1 | return ret;
|
361 | 6a3b9cc9 | blueswir1 | } |
362 | 6a3b9cc9 | blueswir1 | |
363 | c227f099 | Anthony Liguori | static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr, |
364 | 6a3b9cc9 | blueswir1 | uint32_t val) |
365 | 6a3b9cc9 | blueswir1 | { |
366 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
367 | 6a3b9cc9 | blueswir1 | |
368 | 97bf4851 | Blue Swirl | trace_slavio_led_mem_readw(val & 0xffff);
|
369 | a8f48dcc | blueswir1 | switch (addr) {
|
370 | 6a3b9cc9 | blueswir1 | case 0: |
371 | d5296cb5 | blueswir1 | s->leds = val; |
372 | 6a3b9cc9 | blueswir1 | break;
|
373 | 6a3b9cc9 | blueswir1 | default:
|
374 | 6a3b9cc9 | blueswir1 | break;
|
375 | 6a3b9cc9 | blueswir1 | } |
376 | 6a3b9cc9 | blueswir1 | } |
377 | 6a3b9cc9 | blueswir1 | |
378 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_led_mem_read[3] = { |
379 | 7c560456 | blueswir1 | NULL,
|
380 | 7c560456 | blueswir1 | slavio_led_mem_readw, |
381 | 7c560456 | blueswir1 | NULL,
|
382 | 6a3b9cc9 | blueswir1 | }; |
383 | 6a3b9cc9 | blueswir1 | |
384 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = { |
385 | 7c560456 | blueswir1 | NULL,
|
386 | 7c560456 | blueswir1 | slavio_led_mem_writew, |
387 | 7c560456 | blueswir1 | NULL,
|
388 | 6a3b9cc9 | blueswir1 | }; |
389 | 6a3b9cc9 | blueswir1 | |
390 | d37adb09 | Blue Swirl | static const VMStateDescription vmstate_misc = { |
391 | d37adb09 | Blue Swirl | .name ="slavio_misc",
|
392 | d37adb09 | Blue Swirl | .version_id = 1,
|
393 | d37adb09 | Blue Swirl | .minimum_version_id = 1,
|
394 | d37adb09 | Blue Swirl | .minimum_version_id_old = 1,
|
395 | d37adb09 | Blue Swirl | .fields = (VMStateField []) { |
396 | d37adb09 | Blue Swirl | VMSTATE_UINT32(dummy, MiscState), |
397 | d37adb09 | Blue Swirl | VMSTATE_UINT8(config, MiscState), |
398 | d37adb09 | Blue Swirl | VMSTATE_UINT8(aux1, MiscState), |
399 | d37adb09 | Blue Swirl | VMSTATE_UINT8(aux2, MiscState), |
400 | d37adb09 | Blue Swirl | VMSTATE_UINT8(diag, MiscState), |
401 | d37adb09 | Blue Swirl | VMSTATE_UINT8(mctrl, MiscState), |
402 | d37adb09 | Blue Swirl | VMSTATE_UINT8(sysctrl, MiscState), |
403 | d37adb09 | Blue Swirl | VMSTATE_END_OF_LIST() |
404 | d37adb09 | Blue Swirl | } |
405 | d37adb09 | Blue Swirl | }; |
406 | 3475187d | bellard | |
407 | 81a322d4 | Gerd Hoffmann | static int apc_init1(SysBusDevice *dev) |
408 | 2582cfa0 | Blue Swirl | { |
409 | 2582cfa0 | Blue Swirl | APCState *s = FROM_SYSBUS(APCState, dev); |
410 | 2582cfa0 | Blue Swirl | int io;
|
411 | 3475187d | bellard | |
412 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->cpu_halt); |
413 | 2582cfa0 | Blue Swirl | |
414 | 2582cfa0 | Blue Swirl | /* Power management (APC) XXX: not a Slavio device */
|
415 | 2507c12a | Alexander Graf | io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s, |
416 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
417 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
418 | 81a322d4 | Gerd Hoffmann | return 0; |
419 | 2582cfa0 | Blue Swirl | } |
420 | 2582cfa0 | Blue Swirl | |
421 | 81a322d4 | Gerd Hoffmann | static int slavio_misc_init1(SysBusDevice *dev) |
422 | 2582cfa0 | Blue Swirl | { |
423 | 2582cfa0 | Blue Swirl | MiscState *s = FROM_SYSBUS(MiscState, dev); |
424 | 2582cfa0 | Blue Swirl | int io;
|
425 | 2582cfa0 | Blue Swirl | |
426 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
427 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->fdc_tc); |
428 | 2582cfa0 | Blue Swirl | |
429 | 2582cfa0 | Blue Swirl | /* 8 bit registers */
|
430 | 2582cfa0 | Blue Swirl | /* Slavio control */
|
431 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_cfg_mem_read, |
432 | 2507c12a | Alexander Graf | slavio_cfg_mem_write, s, |
433 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
434 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
435 | 2582cfa0 | Blue Swirl | |
436 | 2582cfa0 | Blue Swirl | /* Diagnostics */
|
437 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_diag_mem_read, |
438 | 2507c12a | Alexander Graf | slavio_diag_mem_write, s, |
439 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
440 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
441 | 2582cfa0 | Blue Swirl | |
442 | 2582cfa0 | Blue Swirl | /* Modem control */
|
443 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_mdm_mem_read, |
444 | 2507c12a | Alexander Graf | slavio_mdm_mem_write, s, |
445 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
446 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
447 | 2582cfa0 | Blue Swirl | |
448 | 2582cfa0 | Blue Swirl | /* 16 bit registers */
|
449 | 2582cfa0 | Blue Swirl | /* ss600mp diag LEDs */
|
450 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_led_mem_read, |
451 | 2507c12a | Alexander Graf | slavio_led_mem_write, s, |
452 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
453 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
454 | 2582cfa0 | Blue Swirl | |
455 | 2582cfa0 | Blue Swirl | /* 32 bit registers */
|
456 | 2582cfa0 | Blue Swirl | /* System control */
|
457 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_sysctrl_mem_read, |
458 | 2507c12a | Alexander Graf | slavio_sysctrl_mem_write, s, |
459 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
460 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, SYSCTRL_SIZE, io); |
461 | 2582cfa0 | Blue Swirl | |
462 | 2582cfa0 | Blue Swirl | /* AUX 1 (Misc System Functions) */
|
463 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_aux1_mem_read, |
464 | 2507c12a | Alexander Graf | slavio_aux1_mem_write, s, |
465 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
466 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
467 | 2582cfa0 | Blue Swirl | |
468 | 2582cfa0 | Blue Swirl | /* AUX 2 (Software Powerdown Control) */
|
469 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_aux2_mem_read, |
470 | 2507c12a | Alexander Graf | slavio_aux2_mem_write, s, |
471 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
472 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
473 | 2582cfa0 | Blue Swirl | |
474 | b2b6f6ec | Blue Swirl | qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
|
475 | b2b6f6ec | Blue Swirl | |
476 | 81a322d4 | Gerd Hoffmann | return 0; |
477 | 2582cfa0 | Blue Swirl | } |
478 | 0019ad53 | blueswir1 | |
479 | 2582cfa0 | Blue Swirl | static SysBusDeviceInfo slavio_misc_info = {
|
480 | 2582cfa0 | Blue Swirl | .init = slavio_misc_init1, |
481 | 2582cfa0 | Blue Swirl | .qdev.name = "slavio_misc",
|
482 | 2582cfa0 | Blue Swirl | .qdev.size = sizeof(MiscState),
|
483 | 1795057a | Blue Swirl | .qdev.vmsd = &vmstate_misc, |
484 | 1795057a | Blue Swirl | .qdev.reset = slavio_misc_reset, |
485 | 2582cfa0 | Blue Swirl | }; |
486 | 2582cfa0 | Blue Swirl | |
487 | 2582cfa0 | Blue Swirl | static SysBusDeviceInfo apc_info = {
|
488 | 2582cfa0 | Blue Swirl | .init = apc_init1, |
489 | 2582cfa0 | Blue Swirl | .qdev.name = "apc",
|
490 | 2582cfa0 | Blue Swirl | .qdev.size = sizeof(MiscState),
|
491 | 2582cfa0 | Blue Swirl | }; |
492 | 2582cfa0 | Blue Swirl | |
493 | 2582cfa0 | Blue Swirl | static void slavio_misc_register_devices(void) |
494 | 2582cfa0 | Blue Swirl | { |
495 | 2582cfa0 | Blue Swirl | sysbus_register_withprop(&slavio_misc_info); |
496 | 2582cfa0 | Blue Swirl | sysbus_register_withprop(&apc_info); |
497 | 3475187d | bellard | } |
498 | 2582cfa0 | Blue Swirl | |
499 | 2582cfa0 | Blue Swirl | device_init(slavio_misc_register_devices) |