root / tcg / i386 / tcg-target.h @ 18ebcc86
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1 | c896fe29 | bellard | /*
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2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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3 | c896fe29 | bellard | *
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4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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5 | c896fe29 | bellard | *
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6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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12 | c896fe29 | bellard | *
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13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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15 | c896fe29 | bellard | *
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16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | c896fe29 | bellard | * THE SOFTWARE.
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23 | c896fe29 | bellard | */
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24 | c896fe29 | bellard | #define TCG_TARGET_I386 1 |
25 | c896fe29 | bellard | |
26 | 5d8a4f8f | Richard Henderson | #if defined(__x86_64__)
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27 | 5d8a4f8f | Richard Henderson | # define TCG_TARGET_REG_BITS 64 |
28 | 5d8a4f8f | Richard Henderson | #else
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29 | 5d8a4f8f | Richard Henderson | # define TCG_TARGET_REG_BITS 32 |
30 | 5d8a4f8f | Richard Henderson | #endif
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31 | c896fe29 | bellard | //#define TCG_TARGET_WORDS_BIGENDIAN
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32 | c896fe29 | bellard | |
33 | 5d8a4f8f | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
34 | 5d8a4f8f | Richard Henderson | # define TCG_TARGET_NB_REGS 16 |
35 | 5d8a4f8f | Richard Henderson | #else
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36 | 5d8a4f8f | Richard Henderson | # define TCG_TARGET_NB_REGS 8 |
37 | 5d8a4f8f | Richard Henderson | #endif
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38 | c896fe29 | bellard | |
39 | c896fe29 | bellard | enum {
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40 | c896fe29 | bellard | TCG_REG_EAX = 0,
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41 | c896fe29 | bellard | TCG_REG_ECX, |
42 | c896fe29 | bellard | TCG_REG_EDX, |
43 | c896fe29 | bellard | TCG_REG_EBX, |
44 | c896fe29 | bellard | TCG_REG_ESP, |
45 | c896fe29 | bellard | TCG_REG_EBP, |
46 | c896fe29 | bellard | TCG_REG_ESI, |
47 | c896fe29 | bellard | TCG_REG_EDI, |
48 | 5d8a4f8f | Richard Henderson | |
49 | 5d8a4f8f | Richard Henderson | /* 64-bit registers; always define the symbols to avoid
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50 | 5d8a4f8f | Richard Henderson | too much if-deffing. */
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51 | 5d8a4f8f | Richard Henderson | TCG_REG_R8, |
52 | 5d8a4f8f | Richard Henderson | TCG_REG_R9, |
53 | 5d8a4f8f | Richard Henderson | TCG_REG_R10, |
54 | 5d8a4f8f | Richard Henderson | TCG_REG_R11, |
55 | 5d8a4f8f | Richard Henderson | TCG_REG_R12, |
56 | 5d8a4f8f | Richard Henderson | TCG_REG_R13, |
57 | 5d8a4f8f | Richard Henderson | TCG_REG_R14, |
58 | 5d8a4f8f | Richard Henderson | TCG_REG_R15, |
59 | 5d8a4f8f | Richard Henderson | TCG_REG_RAX = TCG_REG_EAX, |
60 | 5d8a4f8f | Richard Henderson | TCG_REG_RCX = TCG_REG_ECX, |
61 | 5d8a4f8f | Richard Henderson | TCG_REG_RDX = TCG_REG_EDX, |
62 | 5d8a4f8f | Richard Henderson | TCG_REG_RBX = TCG_REG_EBX, |
63 | 5d8a4f8f | Richard Henderson | TCG_REG_RSP = TCG_REG_ESP, |
64 | 5d8a4f8f | Richard Henderson | TCG_REG_RBP = TCG_REG_EBP, |
65 | 5d8a4f8f | Richard Henderson | TCG_REG_RSI = TCG_REG_ESI, |
66 | 5d8a4f8f | Richard Henderson | TCG_REG_RDI = TCG_REG_EDI, |
67 | c896fe29 | bellard | }; |
68 | c896fe29 | bellard | |
69 | 5d8a4f8f | Richard Henderson | #define TCG_CT_CONST_S32 0x100 |
70 | 5d8a4f8f | Richard Henderson | #define TCG_CT_CONST_U32 0x200 |
71 | 5d8a4f8f | Richard Henderson | |
72 | c896fe29 | bellard | /* used for function call generation */
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73 | c896fe29 | bellard | #define TCG_REG_CALL_STACK TCG_REG_ESP
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74 | c896fe29 | bellard | #define TCG_TARGET_STACK_ALIGN 16 |
75 | 39cf05d3 | bellard | #define TCG_TARGET_CALL_STACK_OFFSET 0 |
76 | c896fe29 | bellard | |
77 | 9619376c | aurel32 | /* optional instructions */
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78 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_div2_i32 1 |
79 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_rot_i32 1 |
80 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_ext8s_i32 1 |
81 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_ext16s_i32 1 |
82 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_ext8u_i32 1 |
83 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_ext16u_i32 1 |
84 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_bswap16_i32 1 |
85 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_bswap32_i32 1 |
86 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_neg_i32 1 |
87 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_not_i32 1 |
88 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_andc_i32 0 |
89 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_orc_i32 0 |
90 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_eqv_i32 0 |
91 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_nand_i32 0 |
92 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_nor_i32 0 |
93 | a4773324 | Jan Kiszka | #define TCG_TARGET_HAS_deposit_i32 1 |
94 | 9619376c | aurel32 | |
95 | 5d8a4f8f | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
96 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_div2_i64 1 |
97 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_rot_i64 1 |
98 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_ext8s_i64 1 |
99 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_ext16s_i64 1 |
100 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_ext32s_i64 1 |
101 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_ext8u_i64 1 |
102 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_ext16u_i64 1 |
103 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_ext32u_i64 1 |
104 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_bswap16_i64 1 |
105 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_bswap32_i64 1 |
106 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_bswap64_i64 1 |
107 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_neg_i64 1 |
108 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_not_i64 1 |
109 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_andc_i64 0 |
110 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_orc_i64 0 |
111 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_eqv_i64 0 |
112 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_nand_i64 0 |
113 | 25c4d9cc | Richard Henderson | #define TCG_TARGET_HAS_nor_i64 0 |
114 | a4773324 | Jan Kiszka | #define TCG_TARGET_HAS_deposit_i64 1 |
115 | 5d8a4f8f | Richard Henderson | #endif
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116 | 5d8a4f8f | Richard Henderson | |
117 | a4773324 | Jan Kiszka | #define TCG_TARGET_deposit_i32_valid(ofs, len) \
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118 | a4773324 | Jan Kiszka | (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \ |
119 | a4773324 | Jan Kiszka | ((ofs) == 0 && (len) == 16)) |
120 | a4773324 | Jan Kiszka | #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid
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121 | a4773324 | Jan Kiszka | |
122 | 379f6698 | Paul Brook | #define TCG_TARGET_HAS_GUEST_BASE
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123 | 379f6698 | Paul Brook | |
124 | c896fe29 | bellard | /* Note: must be synced with dyngen-exec.h */
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125 | 5d8a4f8f | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
126 | 5d8a4f8f | Richard Henderson | # define TCG_AREG0 TCG_REG_R14
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127 | 5d8a4f8f | Richard Henderson | #else
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128 | 5d8a4f8f | Richard Henderson | # define TCG_AREG0 TCG_REG_EBP
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129 | 5d8a4f8f | Richard Henderson | #endif
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130 | c896fe29 | bellard | |
131 | c896fe29 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
132 | c896fe29 | bellard | { |
133 | c896fe29 | bellard | } |