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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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int gen_new_label(void);
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static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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}
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static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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}
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static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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}
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static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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}
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static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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}
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static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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}
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static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1,
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                                    TCGv_i32 arg2, TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1,
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                                    TCGv_i64 arg2, TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
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                                       TCGv_ptr base, TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
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                                       TCGv_ptr base, TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
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                                                TCGv_i32 addr, TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I32(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
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                                                TCGv_i64 addr, TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I64(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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}
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static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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}
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static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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}
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static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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}
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static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
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                                     TCGv_i32 arg2, TCGv_i32 arg3,
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                                     TCGArg arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = arg4;
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
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                                     TCGv_i64 arg2, TCGv_i64 arg3,
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                                     TCGArg arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = arg4;
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
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                                   TCGv_i32 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
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}
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static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
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                                   TCGv_i64 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
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}
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static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGv_i32 arg4,
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                                    TCGv_i32 arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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    *gen_opparam_ptr++ = arg6;
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}
319 be210acb Richard Henderson
320 a9751609 Richard Henderson
static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
321 be210acb Richard Henderson
                                    TCGv_i64 arg3, TCGv_i64 arg4,
322 be210acb Richard Henderson
                                    TCGv_i64 arg5, TCGArg arg6)
323 be210acb Richard Henderson
{
324 be210acb Richard Henderson
    *gen_opc_ptr++ = opc;
325 be210acb Richard Henderson
    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
326 be210acb Richard Henderson
    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
327 be210acb Richard Henderson
    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
328 be210acb Richard Henderson
    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
329 be210acb Richard Henderson
    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
330 be210acb Richard Henderson
    *gen_opparam_ptr++ = arg6;
331 be210acb Richard Henderson
}
332 be210acb Richard Henderson
333 a9751609 Richard Henderson
static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1,
334 a9751609 Richard Henderson
                                     TCGv_i32 arg2, TCGv_i32 arg3,
335 a9751609 Richard Henderson
                                     TCGv_i32 arg4, TCGArg arg5, TCGArg arg6)
336 ac56dd48 pbrook
{
337 ac56dd48 pbrook
    *gen_opc_ptr++ = opc;
338 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
339 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
340 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
341 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
342 a7812ae4 pbrook
    *gen_opparam_ptr++ = arg5;
343 a7812ae4 pbrook
    *gen_opparam_ptr++ = arg6;
344 a7812ae4 pbrook
}
345 a7812ae4 pbrook
346 a9751609 Richard Henderson
static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1,
347 a9751609 Richard Henderson
                                     TCGv_i64 arg2, TCGv_i64 arg3,
348 a9751609 Richard Henderson
                                     TCGv_i64 arg4, TCGArg arg5, TCGArg arg6)
349 a7812ae4 pbrook
{
350 a7812ae4 pbrook
    *gen_opc_ptr++ = opc;
351 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
352 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
353 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
354 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
355 c896fe29 bellard
    *gen_opparam_ptr++ = arg5;
356 c896fe29 bellard
    *gen_opparam_ptr++ = arg6;
357 c896fe29 bellard
}
358 c896fe29 bellard
359 c896fe29 bellard
static inline void gen_set_label(int n)
360 c896fe29 bellard
{
361 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_set_label, n);
362 c896fe29 bellard
}
363 c896fe29 bellard
364 fb50d413 blueswir1
static inline void tcg_gen_br(int label)
365 fb50d413 blueswir1
{
366 fb50d413 blueswir1
    tcg_gen_op1i(INDEX_op_br, label);
367 fb50d413 blueswir1
}
368 fb50d413 blueswir1
369 a7812ae4 pbrook
static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
370 c896fe29 bellard
{
371 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I32(ret, arg))
372 a7812ae4 pbrook
        tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
373 c896fe29 bellard
}
374 c896fe29 bellard
375 a7812ae4 pbrook
static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
376 c896fe29 bellard
{
377 a7812ae4 pbrook
    tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
378 c896fe29 bellard
}
379 c896fe29 bellard
380 2bece2c8 Richard Henderson
/* A version of dh_sizemask from def-helper.h that doesn't rely on
381 2bece2c8 Richard Henderson
   preprocessor magic.  */
382 2bece2c8 Richard Henderson
static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed)
383 2bece2c8 Richard Henderson
{
384 2bece2c8 Richard Henderson
    return (is_64bit << n*2) | (is_signed << (n*2 + 1));
385 2bece2c8 Richard Henderson
}
386 2bece2c8 Richard Henderson
387 c896fe29 bellard
/* helper calls */
388 a7812ae4 pbrook
static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
389 a7812ae4 pbrook
                                   TCGArg ret, int nargs, TCGArg *args)
390 a7812ae4 pbrook
{
391 a7812ae4 pbrook
    TCGv_ptr fn;
392 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
393 a7812ae4 pbrook
    tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
394 a7812ae4 pbrook
                  nargs, args);
395 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
396 a7812ae4 pbrook
}
397 c896fe29 bellard
398 dbfff4de Aurelien Jarno
/* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
399 dbfff4de Aurelien Jarno
   reserved for helpers in tcg-runtime.c. These helpers are all const
400 dbfff4de Aurelien Jarno
   and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
401 dbfff4de Aurelien Jarno
   TCG_CALL_PURE. This may need to be adjusted if these functions
402 dbfff4de Aurelien Jarno
   start to be used with other helpers. */
403 2bece2c8 Richard Henderson
static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret,
404 31d66551 Aurelien Jarno
                                    TCGv_i32 a, TCGv_i32 b)
405 31d66551 Aurelien Jarno
{
406 31d66551 Aurelien Jarno
    TCGv_ptr fn;
407 31d66551 Aurelien Jarno
    TCGArg args[2];
408 31d66551 Aurelien Jarno
    fn = tcg_const_ptr((tcg_target_long)func);
409 31d66551 Aurelien Jarno
    args[0] = GET_TCGV_I32(a);
410 31d66551 Aurelien Jarno
    args[1] = GET_TCGV_I32(b);
411 2bece2c8 Richard Henderson
    tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
412 2bece2c8 Richard Henderson
                  GET_TCGV_I32(ret), 2, args);
413 31d66551 Aurelien Jarno
    tcg_temp_free_ptr(fn);
414 31d66551 Aurelien Jarno
}
415 31d66551 Aurelien Jarno
416 2bece2c8 Richard Henderson
static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret,
417 a7812ae4 pbrook
                                    TCGv_i64 a, TCGv_i64 b)
418 c896fe29 bellard
{
419 a7812ae4 pbrook
    TCGv_ptr fn;
420 a7812ae4 pbrook
    TCGArg args[2];
421 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
422 a7812ae4 pbrook
    args[0] = GET_TCGV_I64(a);
423 a7812ae4 pbrook
    args[1] = GET_TCGV_I64(b);
424 2bece2c8 Richard Henderson
    tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
425 2bece2c8 Richard Henderson
                  GET_TCGV_I64(ret), 2, args);
426 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
427 f8422f52 blueswir1
}
428 f8422f52 blueswir1
429 c896fe29 bellard
/* 32 bit ops */
430 c896fe29 bellard
431 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
432 c896fe29 bellard
{
433 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
434 c896fe29 bellard
}
435 c896fe29 bellard
436 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
437 c896fe29 bellard
{
438 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
439 c896fe29 bellard
}
440 c896fe29 bellard
441 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
442 c896fe29 bellard
{
443 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
444 c896fe29 bellard
}
445 c896fe29 bellard
446 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
447 c896fe29 bellard
{
448 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
449 c896fe29 bellard
}
450 c896fe29 bellard
451 a7812ae4 pbrook
static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
452 c896fe29 bellard
{
453 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
454 c896fe29 bellard
}
455 c896fe29 bellard
456 a7812ae4 pbrook
static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
457 c896fe29 bellard
{
458 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
459 c896fe29 bellard
}
460 c896fe29 bellard
461 a7812ae4 pbrook
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
462 c896fe29 bellard
{
463 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
464 c896fe29 bellard
}
465 c896fe29 bellard
466 a7812ae4 pbrook
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
467 c896fe29 bellard
{
468 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
469 c896fe29 bellard
}
470 c896fe29 bellard
471 a7812ae4 pbrook
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
472 c896fe29 bellard
{
473 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
474 c896fe29 bellard
}
475 c896fe29 bellard
476 a7812ae4 pbrook
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
477 c896fe29 bellard
{
478 7089442c blueswir1
    /* some cases can be optimized here */
479 7089442c blueswir1
    if (arg2 == 0) {
480 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
481 7089442c blueswir1
    } else {
482 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
483 e8996ee0 bellard
        tcg_gen_add_i32(ret, arg1, t0);
484 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
485 7089442c blueswir1
    }
486 c896fe29 bellard
}
487 c896fe29 bellard
488 a7812ae4 pbrook
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
489 c896fe29 bellard
{
490 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
491 c896fe29 bellard
}
492 c896fe29 bellard
493 a7812ae4 pbrook
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
494 0045734a aurel32
{
495 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg1);
496 0045734a aurel32
    tcg_gen_sub_i32(ret, t0, arg2);
497 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
498 0045734a aurel32
}
499 0045734a aurel32
500 a7812ae4 pbrook
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
501 c896fe29 bellard
{
502 7089442c blueswir1
    /* some cases can be optimized here */
503 7089442c blueswir1
    if (arg2 == 0) {
504 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
505 7089442c blueswir1
    } else {
506 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
507 e8996ee0 bellard
        tcg_gen_sub_i32(ret, arg1, t0);
508 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
509 7089442c blueswir1
    }
510 c896fe29 bellard
}
511 c896fe29 bellard
512 a7812ae4 pbrook
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
513 c896fe29 bellard
{
514 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
515 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
516 7fc81051 aurel32
    } else {
517 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
518 7fc81051 aurel32
    }
519 c896fe29 bellard
}
520 c896fe29 bellard
521 a7812ae4 pbrook
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
522 c896fe29 bellard
{
523 c896fe29 bellard
    /* some cases can be optimized here */
524 c896fe29 bellard
    if (arg2 == 0) {
525 c896fe29 bellard
        tcg_gen_movi_i32(ret, 0);
526 c896fe29 bellard
    } else if (arg2 == 0xffffffff) {
527 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
528 c896fe29 bellard
    } else {
529 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
530 e8996ee0 bellard
        tcg_gen_and_i32(ret, arg1, t0);
531 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
532 c896fe29 bellard
    }
533 c896fe29 bellard
}
534 c896fe29 bellard
535 a7812ae4 pbrook
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
536 c896fe29 bellard
{
537 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
538 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
539 7fc81051 aurel32
    } else {
540 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
541 7fc81051 aurel32
    }
542 c896fe29 bellard
}
543 c896fe29 bellard
544 a7812ae4 pbrook
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
545 c896fe29 bellard
{
546 c896fe29 bellard
    /* some cases can be optimized here */
547 c896fe29 bellard
    if (arg2 == 0xffffffff) {
548 7089442c blueswir1
        tcg_gen_movi_i32(ret, 0xffffffff);
549 c896fe29 bellard
    } else if (arg2 == 0) {
550 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
551 c896fe29 bellard
    } else {
552 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
553 e8996ee0 bellard
        tcg_gen_or_i32(ret, arg1, t0);
554 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
555 c896fe29 bellard
    }
556 c896fe29 bellard
}
557 c896fe29 bellard
558 a7812ae4 pbrook
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
559 c896fe29 bellard
{
560 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
561 7fc81051 aurel32
        tcg_gen_movi_i32(ret, 0);
562 7fc81051 aurel32
    } else {
563 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
564 7fc81051 aurel32
    }
565 c896fe29 bellard
}
566 c896fe29 bellard
567 a7812ae4 pbrook
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
568 c896fe29 bellard
{
569 c896fe29 bellard
    /* some cases can be optimized here */
570 c896fe29 bellard
    if (arg2 == 0) {
571 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
572 c896fe29 bellard
    } else {
573 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
574 e8996ee0 bellard
        tcg_gen_xor_i32(ret, arg1, t0);
575 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
576 c896fe29 bellard
    }
577 c896fe29 bellard
}
578 c896fe29 bellard
579 a7812ae4 pbrook
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
580 c896fe29 bellard
{
581 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
582 c896fe29 bellard
}
583 c896fe29 bellard
584 a7812ae4 pbrook
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
585 c896fe29 bellard
{
586 34151a20 bellard
    if (arg2 == 0) {
587 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
588 34151a20 bellard
    } else {
589 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
590 e8996ee0 bellard
        tcg_gen_shl_i32(ret, arg1, t0);
591 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
592 34151a20 bellard
    }
593 c896fe29 bellard
}
594 c896fe29 bellard
595 a7812ae4 pbrook
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
596 c896fe29 bellard
{
597 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
598 c896fe29 bellard
}
599 c896fe29 bellard
600 a7812ae4 pbrook
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
601 c896fe29 bellard
{
602 34151a20 bellard
    if (arg2 == 0) {
603 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
604 34151a20 bellard
    } else {
605 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
606 e8996ee0 bellard
        tcg_gen_shr_i32(ret, arg1, t0);
607 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
608 34151a20 bellard
    }
609 c896fe29 bellard
}
610 c896fe29 bellard
611 a7812ae4 pbrook
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
612 c896fe29 bellard
{
613 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
614 c896fe29 bellard
}
615 c896fe29 bellard
616 a7812ae4 pbrook
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
617 c896fe29 bellard
{
618 34151a20 bellard
    if (arg2 == 0) {
619 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
620 34151a20 bellard
    } else {
621 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
622 e8996ee0 bellard
        tcg_gen_sar_i32(ret, arg1, t0);
623 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
624 34151a20 bellard
    }
625 c896fe29 bellard
}
626 c896fe29 bellard
627 8a56e840 Richard Henderson
static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1,
628 8a56e840 Richard Henderson
                                      TCGv_i32 arg2, int label_index)
629 c896fe29 bellard
{
630 a7812ae4 pbrook
    tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
631 c896fe29 bellard
}
632 c896fe29 bellard
633 8a56e840 Richard Henderson
static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1,
634 8a56e840 Richard Henderson
                                       int32_t arg2, int label_index)
635 cb63669a pbrook
{
636 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
637 cb63669a pbrook
    tcg_gen_brcond_i32(cond, arg1, t0, label_index);
638 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
639 cb63669a pbrook
}
640 cb63669a pbrook
641 8a56e840 Richard Henderson
static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
642 5105c556 Aurelien Jarno
                                       TCGv_i32 arg1, TCGv_i32 arg2)
643 5105c556 Aurelien Jarno
{
644 5105c556 Aurelien Jarno
    tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
645 5105c556 Aurelien Jarno
}
646 5105c556 Aurelien Jarno
647 8a56e840 Richard Henderson
static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
648 8a56e840 Richard Henderson
                                        TCGv_i32 arg1, int32_t arg2)
649 5105c556 Aurelien Jarno
{
650 5105c556 Aurelien Jarno
    TCGv_i32 t0 = tcg_const_i32(arg2);
651 5105c556 Aurelien Jarno
    tcg_gen_setcond_i32(cond, ret, arg1, t0);
652 5105c556 Aurelien Jarno
    tcg_temp_free_i32(t0);
653 5105c556 Aurelien Jarno
}
654 5105c556 Aurelien Jarno
655 a7812ae4 pbrook
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
656 c896fe29 bellard
{
657 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
658 c896fe29 bellard
}
659 c896fe29 bellard
660 a7812ae4 pbrook
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
661 f730fd27 ths
{
662 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
663 e8996ee0 bellard
    tcg_gen_mul_i32(ret, arg1, t0);
664 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
665 f730fd27 ths
}
666 f730fd27 ths
667 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
668 c896fe29 bellard
{
669 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_div_i32) {
670 25c4d9cc Richard Henderson
        tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
671 25c4d9cc Richard Henderson
    } else if (TCG_TARGET_HAS_div2_i32) {
672 25c4d9cc Richard Henderson
        TCGv_i32 t0 = tcg_temp_new_i32();
673 25c4d9cc Richard Henderson
        tcg_gen_sari_i32(t0, arg1, 31);
674 25c4d9cc Richard Henderson
        tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
675 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t0);
676 25c4d9cc Richard Henderson
    } else {
677 25c4d9cc Richard Henderson
        int sizemask = 0;
678 25c4d9cc Richard Henderson
        /* Return value and both arguments are 32-bit and signed.  */
679 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(0, 0, 1);
680 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(1, 0, 1);
681 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(2, 0, 1);
682 25c4d9cc Richard Henderson
        tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2);
683 25c4d9cc Richard Henderson
    }
684 31d66551 Aurelien Jarno
}
685 31d66551 Aurelien Jarno
686 31d66551 Aurelien Jarno
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
687 31d66551 Aurelien Jarno
{
688 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_div_i32) {
689 25c4d9cc Richard Henderson
        tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
690 25c4d9cc Richard Henderson
    } else if (TCG_TARGET_HAS_div2_i32) {
691 25c4d9cc Richard Henderson
        TCGv_i32 t0 = tcg_temp_new_i32();
692 25c4d9cc Richard Henderson
        tcg_gen_sari_i32(t0, arg1, 31);
693 25c4d9cc Richard Henderson
        tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
694 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t0);
695 25c4d9cc Richard Henderson
    } else {
696 25c4d9cc Richard Henderson
        int sizemask = 0;
697 25c4d9cc Richard Henderson
        /* Return value and both arguments are 32-bit and signed.  */
698 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(0, 0, 1);
699 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(1, 0, 1);
700 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(2, 0, 1);
701 25c4d9cc Richard Henderson
        tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2);
702 25c4d9cc Richard Henderson
    }
703 31d66551 Aurelien Jarno
}
704 31d66551 Aurelien Jarno
705 31d66551 Aurelien Jarno
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
706 31d66551 Aurelien Jarno
{
707 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_div_i32) {
708 25c4d9cc Richard Henderson
        tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
709 25c4d9cc Richard Henderson
    } else if (TCG_TARGET_HAS_div2_i32) {
710 25c4d9cc Richard Henderson
        TCGv_i32 t0 = tcg_temp_new_i32();
711 25c4d9cc Richard Henderson
        tcg_gen_movi_i32(t0, 0);
712 25c4d9cc Richard Henderson
        tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
713 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t0);
714 25c4d9cc Richard Henderson
    } else {
715 25c4d9cc Richard Henderson
        int sizemask = 0;
716 25c4d9cc Richard Henderson
        /* Return value and both arguments are 32-bit and unsigned.  */
717 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(0, 0, 0);
718 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(1, 0, 0);
719 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(2, 0, 0);
720 25c4d9cc Richard Henderson
        tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2);
721 25c4d9cc Richard Henderson
    }
722 31d66551 Aurelien Jarno
}
723 31d66551 Aurelien Jarno
724 31d66551 Aurelien Jarno
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
725 31d66551 Aurelien Jarno
{
726 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_div_i32) {
727 25c4d9cc Richard Henderson
        tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
728 25c4d9cc Richard Henderson
    } else if (TCG_TARGET_HAS_div2_i32) {
729 25c4d9cc Richard Henderson
        TCGv_i32 t0 = tcg_temp_new_i32();
730 25c4d9cc Richard Henderson
        tcg_gen_movi_i32(t0, 0);
731 25c4d9cc Richard Henderson
        tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
732 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t0);
733 25c4d9cc Richard Henderson
    } else {
734 25c4d9cc Richard Henderson
        int sizemask = 0;
735 25c4d9cc Richard Henderson
        /* Return value and both arguments are 32-bit and unsigned.  */
736 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(0, 0, 0);
737 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(1, 0, 0);
738 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(2, 0, 0);
739 25c4d9cc Richard Henderson
        tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2);
740 25c4d9cc Richard Henderson
    }
741 31d66551 Aurelien Jarno
}
742 c896fe29 bellard
743 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
744 c896fe29 bellard
745 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
746 c896fe29 bellard
{
747 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg)) {
748 a7812ae4 pbrook
        tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
749 4d07272d blueswir1
        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
750 4d07272d blueswir1
    }
751 c896fe29 bellard
}
752 c896fe29 bellard
753 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
754 c896fe29 bellard
{
755 a7812ae4 pbrook
    tcg_gen_movi_i32(TCGV_LOW(ret), arg);
756 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
757 c896fe29 bellard
}
758 c896fe29 bellard
759 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
760 a7812ae4 pbrook
                                    tcg_target_long offset)
761 c896fe29 bellard
{
762 a7812ae4 pbrook
    tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
763 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
764 c896fe29 bellard
}
765 c896fe29 bellard
766 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
767 a7812ae4 pbrook
                                    tcg_target_long offset)
768 c896fe29 bellard
{
769 a7812ae4 pbrook
    tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
770 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
771 c896fe29 bellard
}
772 c896fe29 bellard
773 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
774 a7812ae4 pbrook
                                     tcg_target_long offset)
775 c896fe29 bellard
{
776 a747723b aurel32
    tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
777 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
778 c896fe29 bellard
}
779 c896fe29 bellard
780 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
781 a7812ae4 pbrook
                                     tcg_target_long offset)
782 c896fe29 bellard
{
783 a7812ae4 pbrook
    tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
784 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
785 c896fe29 bellard
}
786 c896fe29 bellard
787 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
788 a7812ae4 pbrook
                                     tcg_target_long offset)
789 c896fe29 bellard
{
790 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
791 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
792 c896fe29 bellard
}
793 c896fe29 bellard
794 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
795 a7812ae4 pbrook
                                     tcg_target_long offset)
796 c896fe29 bellard
{
797 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
798 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
799 c896fe29 bellard
}
800 c896fe29 bellard
801 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
802 a7812ae4 pbrook
                                  tcg_target_long offset)
803 c896fe29 bellard
{
804 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
805 c896fe29 bellard
       same temporary */
806 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
807 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
808 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
809 c896fe29 bellard
#else
810 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
811 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
812 c896fe29 bellard
#endif
813 c896fe29 bellard
}
814 c896fe29 bellard
815 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
816 a7812ae4 pbrook
                                   tcg_target_long offset)
817 c896fe29 bellard
{
818 a7812ae4 pbrook
    tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
819 c896fe29 bellard
}
820 c896fe29 bellard
821 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
822 a7812ae4 pbrook
                                    tcg_target_long offset)
823 c896fe29 bellard
{
824 a7812ae4 pbrook
    tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
825 c896fe29 bellard
}
826 c896fe29 bellard
827 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
828 a7812ae4 pbrook
                                    tcg_target_long offset)
829 c896fe29 bellard
{
830 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
831 c896fe29 bellard
}
832 c896fe29 bellard
833 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
834 a7812ae4 pbrook
                                  tcg_target_long offset)
835 c896fe29 bellard
{
836 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
837 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
838 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
839 c896fe29 bellard
#else
840 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
841 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
842 c896fe29 bellard
#endif
843 c896fe29 bellard
}
844 c896fe29 bellard
845 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
846 c896fe29 bellard
{
847 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
848 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
849 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
850 c896fe29 bellard
}
851 c896fe29 bellard
852 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
853 c896fe29 bellard
{
854 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
855 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
856 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
857 c896fe29 bellard
}
858 c896fe29 bellard
859 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
860 c896fe29 bellard
{
861 a7812ae4 pbrook
    tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
862 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
863 c896fe29 bellard
}
864 c896fe29 bellard
865 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
866 c896fe29 bellard
{
867 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
868 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
869 c896fe29 bellard
}
870 c896fe29 bellard
871 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
872 c896fe29 bellard
{
873 e5105083 aurel32
    tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
874 e5105083 aurel32
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
875 c896fe29 bellard
}
876 c896fe29 bellard
877 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
878 c896fe29 bellard
{
879 a7812ae4 pbrook
    tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
880 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
881 c896fe29 bellard
}
882 c896fe29 bellard
883 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
884 c896fe29 bellard
{
885 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
886 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
887 c896fe29 bellard
}
888 c896fe29 bellard
889 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
890 c896fe29 bellard
{
891 a7812ae4 pbrook
    tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
892 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
893 c896fe29 bellard
}
894 c896fe29 bellard
895 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
896 c896fe29 bellard
   specific code (x86) */
897 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
898 c896fe29 bellard
{
899 2bece2c8 Richard Henderson
    int sizemask = 0;
900 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
901 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
902 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
903 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
904 2bece2c8 Richard Henderson
905 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2);
906 c896fe29 bellard
}
907 c896fe29 bellard
908 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
909 c896fe29 bellard
{
910 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
911 c896fe29 bellard
}
912 c896fe29 bellard
913 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
914 c896fe29 bellard
{
915 2bece2c8 Richard Henderson
    int sizemask = 0;
916 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
917 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
918 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
919 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
920 2bece2c8 Richard Henderson
921 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2);
922 c896fe29 bellard
}
923 c896fe29 bellard
924 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
925 c896fe29 bellard
{
926 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
927 c896fe29 bellard
}
928 c896fe29 bellard
929 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
930 c896fe29 bellard
{
931 2bece2c8 Richard Henderson
    int sizemask = 0;
932 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
933 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
934 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
935 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
936 2bece2c8 Richard Henderson
937 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2);
938 c896fe29 bellard
}
939 c896fe29 bellard
940 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
941 c896fe29 bellard
{
942 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
943 c896fe29 bellard
}
944 c896fe29 bellard
945 8a56e840 Richard Henderson
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
946 8a56e840 Richard Henderson
                                      TCGv_i64 arg2, int label_index)
947 c896fe29 bellard
{
948 a7812ae4 pbrook
    tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
949 a7812ae4 pbrook
                      TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
950 a7812ae4 pbrook
                      TCGV_HIGH(arg2), cond, label_index);
951 c896fe29 bellard
}
952 c896fe29 bellard
953 8a56e840 Richard Henderson
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
954 5105c556 Aurelien Jarno
                                       TCGv_i64 arg1, TCGv_i64 arg2)
955 5105c556 Aurelien Jarno
{
956 5105c556 Aurelien Jarno
    tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
957 5105c556 Aurelien Jarno
                     TCGV_LOW(arg1), TCGV_HIGH(arg1),
958 5105c556 Aurelien Jarno
                     TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
959 5105c556 Aurelien Jarno
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
960 5105c556 Aurelien Jarno
}
961 5105c556 Aurelien Jarno
962 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
963 c896fe29 bellard
{
964 a7812ae4 pbrook
    TCGv_i64 t0;
965 a7812ae4 pbrook
    TCGv_i32 t1;
966 c896fe29 bellard
967 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
968 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
969 a7812ae4 pbrook
970 a7812ae4 pbrook
    tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
971 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_LOW(arg2));
972 a7812ae4 pbrook
973 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
974 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
975 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
976 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
977 a7812ae4 pbrook
978 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
979 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
980 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
981 c896fe29 bellard
}
982 c896fe29 bellard
983 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
984 c896fe29 bellard
{
985 2bece2c8 Richard Henderson
    int sizemask = 0;
986 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
987 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
988 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
989 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
990 2bece2c8 Richard Henderson
991 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
992 c896fe29 bellard
}
993 c896fe29 bellard
994 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
995 c896fe29 bellard
{
996 2bece2c8 Richard Henderson
    int sizemask = 0;
997 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
998 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
999 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
1000 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
1001 2bece2c8 Richard Henderson
1002 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1003 c896fe29 bellard
}
1004 c896fe29 bellard
1005 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1006 c896fe29 bellard
{
1007 2bece2c8 Richard Henderson
    int sizemask = 0;
1008 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and unsigned.  */
1009 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 0);
1010 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 0);
1011 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 0);
1012 2bece2c8 Richard Henderson
1013 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1014 c896fe29 bellard
}
1015 c896fe29 bellard
1016 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1017 c896fe29 bellard
{
1018 2bece2c8 Richard Henderson
    int sizemask = 0;
1019 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and unsigned.  */
1020 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 0);
1021 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 0);
1022 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 0);
1023 2bece2c8 Richard Henderson
1024 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1025 c896fe29 bellard
}
1026 c896fe29 bellard
1027 c896fe29 bellard
#else
1028 c896fe29 bellard
1029 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
1030 c896fe29 bellard
{
1031 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg))
1032 a7812ae4 pbrook
        tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
1033 c896fe29 bellard
}
1034 c896fe29 bellard
1035 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
1036 c896fe29 bellard
{
1037 a7812ae4 pbrook
    tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
1038 c896fe29 bellard
}
1039 c896fe29 bellard
1040 6bd4b08a Peter Maydell
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1041 ac56dd48 pbrook
                                    tcg_target_long offset)
1042 c896fe29 bellard
{
1043 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
1044 c896fe29 bellard
}
1045 c896fe29 bellard
1046 6bd4b08a Peter Maydell
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1047 ac56dd48 pbrook
                                    tcg_target_long offset)
1048 c896fe29 bellard
{
1049 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
1050 c896fe29 bellard
}
1051 c896fe29 bellard
1052 6bd4b08a Peter Maydell
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1053 ac56dd48 pbrook
                                     tcg_target_long offset)
1054 c896fe29 bellard
{
1055 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
1056 c896fe29 bellard
}
1057 c896fe29 bellard
1058 6bd4b08a Peter Maydell
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1059 ac56dd48 pbrook
                                     tcg_target_long offset)
1060 c896fe29 bellard
{
1061 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
1062 c896fe29 bellard
}
1063 c896fe29 bellard
1064 6bd4b08a Peter Maydell
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1065 ac56dd48 pbrook
                                     tcg_target_long offset)
1066 c896fe29 bellard
{
1067 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
1068 c896fe29 bellard
}
1069 c896fe29 bellard
1070 6bd4b08a Peter Maydell
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1071 ac56dd48 pbrook
                                     tcg_target_long offset)
1072 c896fe29 bellard
{
1073 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
1074 c896fe29 bellard
}
1075 c896fe29 bellard
1076 6bd4b08a Peter Maydell
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
1077 c896fe29 bellard
{
1078 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
1079 c896fe29 bellard
}
1080 c896fe29 bellard
1081 6bd4b08a Peter Maydell
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1082 ac56dd48 pbrook
                                   tcg_target_long offset)
1083 c896fe29 bellard
{
1084 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
1085 c896fe29 bellard
}
1086 c896fe29 bellard
1087 6bd4b08a Peter Maydell
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1088 ac56dd48 pbrook
                                    tcg_target_long offset)
1089 c896fe29 bellard
{
1090 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
1091 c896fe29 bellard
}
1092 c896fe29 bellard
1093 6bd4b08a Peter Maydell
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1094 ac56dd48 pbrook
                                    tcg_target_long offset)
1095 c896fe29 bellard
{
1096 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
1097 c896fe29 bellard
}
1098 c896fe29 bellard
1099 6bd4b08a Peter Maydell
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
1100 c896fe29 bellard
{
1101 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
1102 c896fe29 bellard
}
1103 c896fe29 bellard
1104 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1105 c896fe29 bellard
{
1106 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
1107 c896fe29 bellard
}
1108 c896fe29 bellard
1109 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1110 c896fe29 bellard
{
1111 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
1112 c896fe29 bellard
}
1113 c896fe29 bellard
1114 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1115 c896fe29 bellard
{
1116 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
1117 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
1118 7fc81051 aurel32
    } else {
1119 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
1120 7fc81051 aurel32
    }
1121 c896fe29 bellard
}
1122 c896fe29 bellard
1123 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1124 c896fe29 bellard
{
1125 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1126 e8996ee0 bellard
    tcg_gen_and_i64(ret, arg1, t0);
1127 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1128 c896fe29 bellard
}
1129 c896fe29 bellard
1130 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1131 c896fe29 bellard
{
1132 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
1133 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
1134 7fc81051 aurel32
    } else {
1135 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1136 7fc81051 aurel32
    }
1137 c896fe29 bellard
}
1138 c896fe29 bellard
1139 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1140 c896fe29 bellard
{
1141 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1142 e8996ee0 bellard
    tcg_gen_or_i64(ret, arg1, t0);
1143 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1144 c896fe29 bellard
}
1145 c896fe29 bellard
1146 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1147 c896fe29 bellard
{
1148 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
1149 7fc81051 aurel32
        tcg_gen_movi_i64(ret, 0);
1150 7fc81051 aurel32
    } else {
1151 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1152 7fc81051 aurel32
    }
1153 c896fe29 bellard
}
1154 c896fe29 bellard
1155 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1156 c896fe29 bellard
{
1157 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1158 e8996ee0 bellard
    tcg_gen_xor_i64(ret, arg1, t0);
1159 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1160 c896fe29 bellard
}
1161 c896fe29 bellard
1162 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1163 c896fe29 bellard
{
1164 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1165 c896fe29 bellard
}
1166 c896fe29 bellard
1167 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1168 c896fe29 bellard
{
1169 34151a20 bellard
    if (arg2 == 0) {
1170 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1171 34151a20 bellard
    } else {
1172 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1173 e8996ee0 bellard
        tcg_gen_shl_i64(ret, arg1, t0);
1174 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1175 34151a20 bellard
    }
1176 c896fe29 bellard
}
1177 c896fe29 bellard
1178 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1179 c896fe29 bellard
{
1180 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1181 c896fe29 bellard
}
1182 c896fe29 bellard
1183 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1184 c896fe29 bellard
{
1185 34151a20 bellard
    if (arg2 == 0) {
1186 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1187 34151a20 bellard
    } else {
1188 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1189 e8996ee0 bellard
        tcg_gen_shr_i64(ret, arg1, t0);
1190 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1191 34151a20 bellard
    }
1192 c896fe29 bellard
}
1193 c896fe29 bellard
1194 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1195 c896fe29 bellard
{
1196 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1197 c896fe29 bellard
}
1198 c896fe29 bellard
1199 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1200 c896fe29 bellard
{
1201 34151a20 bellard
    if (arg2 == 0) {
1202 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1203 34151a20 bellard
    } else {
1204 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1205 e8996ee0 bellard
        tcg_gen_sar_i64(ret, arg1, t0);
1206 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1207 34151a20 bellard
    }
1208 c896fe29 bellard
}
1209 c896fe29 bellard
1210 8a56e840 Richard Henderson
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1211 8a56e840 Richard Henderson
                                      TCGv_i64 arg2, int label_index)
1212 c896fe29 bellard
{
1213 a7812ae4 pbrook
    tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1214 c896fe29 bellard
}
1215 c896fe29 bellard
1216 8a56e840 Richard Henderson
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
1217 5105c556 Aurelien Jarno
                                       TCGv_i64 arg1, TCGv_i64 arg2)
1218 5105c556 Aurelien Jarno
{
1219 5105c556 Aurelien Jarno
    tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1220 5105c556 Aurelien Jarno
}
1221 5105c556 Aurelien Jarno
1222 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1223 c896fe29 bellard
{
1224 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1225 c896fe29 bellard
}
1226 c896fe29 bellard
1227 31d66551 Aurelien Jarno
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1228 31d66551 Aurelien Jarno
{
1229 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_div_i64) {
1230 25c4d9cc Richard Henderson
        tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1231 25c4d9cc Richard Henderson
    } else if (TCG_TARGET_HAS_div2_i64) {
1232 25c4d9cc Richard Henderson
        TCGv_i64 t0 = tcg_temp_new_i64();
1233 25c4d9cc Richard Henderson
        tcg_gen_sari_i64(t0, arg1, 63);
1234 25c4d9cc Richard Henderson
        tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1235 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
1236 25c4d9cc Richard Henderson
    } else {
1237 25c4d9cc Richard Henderson
        int sizemask = 0;
1238 25c4d9cc Richard Henderson
        /* Return value and both arguments are 64-bit and signed.  */
1239 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(0, 1, 1);
1240 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(1, 1, 1);
1241 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(2, 1, 1);
1242 25c4d9cc Richard Henderson
        tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1243 25c4d9cc Richard Henderson
    }
1244 31d66551 Aurelien Jarno
}
1245 31d66551 Aurelien Jarno
1246 31d66551 Aurelien Jarno
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1247 31d66551 Aurelien Jarno
{
1248 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_div_i64) {
1249 25c4d9cc Richard Henderson
        tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1250 25c4d9cc Richard Henderson
    } else if (TCG_TARGET_HAS_div2_i64) {
1251 25c4d9cc Richard Henderson
        TCGv_i64 t0 = tcg_temp_new_i64();
1252 25c4d9cc Richard Henderson
        tcg_gen_sari_i64(t0, arg1, 63);
1253 25c4d9cc Richard Henderson
        tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1254 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
1255 25c4d9cc Richard Henderson
    } else {
1256 25c4d9cc Richard Henderson
        int sizemask = 0;
1257 25c4d9cc Richard Henderson
        /* Return value and both arguments are 64-bit and signed.  */
1258 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(0, 1, 1);
1259 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(1, 1, 1);
1260 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(2, 1, 1);
1261 25c4d9cc Richard Henderson
        tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1262 25c4d9cc Richard Henderson
    }
1263 31d66551 Aurelien Jarno
}
1264 31d66551 Aurelien Jarno
1265 31d66551 Aurelien Jarno
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1266 31d66551 Aurelien Jarno
{
1267 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_div_i64) {
1268 25c4d9cc Richard Henderson
        tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1269 25c4d9cc Richard Henderson
    } else if (TCG_TARGET_HAS_div2_i64) {
1270 25c4d9cc Richard Henderson
        TCGv_i64 t0 = tcg_temp_new_i64();
1271 25c4d9cc Richard Henderson
        tcg_gen_movi_i64(t0, 0);
1272 25c4d9cc Richard Henderson
        tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1273 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
1274 25c4d9cc Richard Henderson
    } else {
1275 25c4d9cc Richard Henderson
        int sizemask = 0;
1276 25c4d9cc Richard Henderson
        /* Return value and both arguments are 64-bit and unsigned.  */
1277 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(0, 1, 0);
1278 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(1, 1, 0);
1279 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(2, 1, 0);
1280 25c4d9cc Richard Henderson
        tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1281 25c4d9cc Richard Henderson
    }
1282 31d66551 Aurelien Jarno
}
1283 31d66551 Aurelien Jarno
1284 31d66551 Aurelien Jarno
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1285 31d66551 Aurelien Jarno
{
1286 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_div_i64) {
1287 25c4d9cc Richard Henderson
        tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1288 25c4d9cc Richard Henderson
    } else if (TCG_TARGET_HAS_div2_i64) {
1289 25c4d9cc Richard Henderson
        TCGv_i64 t0 = tcg_temp_new_i64();
1290 25c4d9cc Richard Henderson
        tcg_gen_movi_i64(t0, 0);
1291 25c4d9cc Richard Henderson
        tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1292 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
1293 25c4d9cc Richard Henderson
    } else {
1294 25c4d9cc Richard Henderson
        int sizemask = 0;
1295 25c4d9cc Richard Henderson
        /* Return value and both arguments are 64-bit and unsigned.  */
1296 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(0, 1, 0);
1297 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(1, 1, 0);
1298 25c4d9cc Richard Henderson
        sizemask |= tcg_gen_sizemask(2, 1, 0);
1299 25c4d9cc Richard Henderson
        tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1300 25c4d9cc Richard Henderson
    }
1301 31d66551 Aurelien Jarno
}
1302 25c4d9cc Richard Henderson
#endif /* TCG_TARGET_REG_BITS == 32 */
1303 c896fe29 bellard
1304 a7812ae4 pbrook
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1305 6359706f aurel32
{
1306 6359706f aurel32
    /* some cases can be optimized here */
1307 6359706f aurel32
    if (arg2 == 0) {
1308 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1309 6359706f aurel32
    } else {
1310 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1311 6359706f aurel32
        tcg_gen_add_i64(ret, arg1, t0);
1312 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1313 6359706f aurel32
    }
1314 6359706f aurel32
}
1315 6359706f aurel32
1316 a7812ae4 pbrook
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1317 0045734a aurel32
{
1318 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg1);
1319 0045734a aurel32
    tcg_gen_sub_i64(ret, t0, arg2);
1320 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1321 0045734a aurel32
}
1322 0045734a aurel32
1323 a7812ae4 pbrook
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1324 6359706f aurel32
{
1325 6359706f aurel32
    /* some cases can be optimized here */
1326 6359706f aurel32
    if (arg2 == 0) {
1327 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1328 6359706f aurel32
    } else {
1329 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1330 6359706f aurel32
        tcg_gen_sub_i64(ret, arg1, t0);
1331 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1332 6359706f aurel32
    }
1333 6359706f aurel32
}
1334 8a56e840 Richard Henderson
static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1,
1335 8a56e840 Richard Henderson
                                       int64_t arg2, int label_index)
1336 f02bb954 aurel32
{
1337 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1338 f02bb954 aurel32
    tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1339 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1340 f02bb954 aurel32
}
1341 f02bb954 aurel32
1342 8a56e840 Richard Henderson
static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1343 8a56e840 Richard Henderson
                                        TCGv_i64 arg1, int64_t arg2)
1344 5105c556 Aurelien Jarno
{
1345 5105c556 Aurelien Jarno
    TCGv_i64 t0 = tcg_const_i64(arg2);
1346 5105c556 Aurelien Jarno
    tcg_gen_setcond_i64(cond, ret, arg1, t0);
1347 5105c556 Aurelien Jarno
    tcg_temp_free_i64(t0);
1348 5105c556 Aurelien Jarno
}
1349 5105c556 Aurelien Jarno
1350 a7812ae4 pbrook
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1351 f02bb954 aurel32
{
1352 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1353 f02bb954 aurel32
    tcg_gen_mul_i64(ret, arg1, t0);
1354 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1355 f02bb954 aurel32
}
1356 f02bb954 aurel32
1357 6359706f aurel32
1358 c896fe29 bellard
/***************************************/
1359 c896fe29 bellard
/* optional operations */
1360 c896fe29 bellard
1361 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1362 c896fe29 bellard
{
1363 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_ext8s_i32) {
1364 25c4d9cc Richard Henderson
        tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1365 25c4d9cc Richard Henderson
    } else {
1366 25c4d9cc Richard Henderson
        tcg_gen_shli_i32(ret, arg, 24);
1367 25c4d9cc Richard Henderson
        tcg_gen_sari_i32(ret, ret, 24);
1368 25c4d9cc Richard Henderson
    }
1369 c896fe29 bellard
}
1370 c896fe29 bellard
1371 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1372 c896fe29 bellard
{
1373 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_ext16s_i32) {
1374 25c4d9cc Richard Henderson
        tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1375 25c4d9cc Richard Henderson
    } else {
1376 25c4d9cc Richard Henderson
        tcg_gen_shli_i32(ret, arg, 16);
1377 25c4d9cc Richard Henderson
        tcg_gen_sari_i32(ret, ret, 16);
1378 25c4d9cc Richard Henderson
    }
1379 c896fe29 bellard
}
1380 c896fe29 bellard
1381 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1382 86831435 pbrook
{
1383 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_ext8u_i32) {
1384 25c4d9cc Richard Henderson
        tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1385 25c4d9cc Richard Henderson
    } else {
1386 25c4d9cc Richard Henderson
        tcg_gen_andi_i32(ret, arg, 0xffu);
1387 25c4d9cc Richard Henderson
    }
1388 86831435 pbrook
}
1389 86831435 pbrook
1390 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1391 86831435 pbrook
{
1392 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_ext16u_i32) {
1393 25c4d9cc Richard Henderson
        tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1394 25c4d9cc Richard Henderson
    } else {
1395 25c4d9cc Richard Henderson
        tcg_gen_andi_i32(ret, arg, 0xffffu);
1396 25c4d9cc Richard Henderson
    }
1397 86831435 pbrook
}
1398 86831435 pbrook
1399 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
1400 a7812ae4 pbrook
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1401 c896fe29 bellard
{
1402 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_bswap16_i32) {
1403 25c4d9cc Richard Henderson
        tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1404 25c4d9cc Richard Henderson
    } else {
1405 25c4d9cc Richard Henderson
        TCGv_i32 t0 = tcg_temp_new_i32();
1406 c896fe29 bellard
    
1407 25c4d9cc Richard Henderson
        tcg_gen_ext8u_i32(t0, arg);
1408 25c4d9cc Richard Henderson
        tcg_gen_shli_i32(t0, t0, 8);
1409 25c4d9cc Richard Henderson
        tcg_gen_shri_i32(ret, arg, 8);
1410 25c4d9cc Richard Henderson
        tcg_gen_or_i32(ret, ret, t0);
1411 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t0);
1412 25c4d9cc Richard Henderson
    }
1413 c896fe29 bellard
}
1414 c896fe29 bellard
1415 66896cb8 aurel32
static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1416 c896fe29 bellard
{
1417 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_bswap32_i32) {
1418 25c4d9cc Richard Henderson
        tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1419 25c4d9cc Richard Henderson
    } else {
1420 25c4d9cc Richard Henderson
        TCGv_i32 t0, t1;
1421 25c4d9cc Richard Henderson
        t0 = tcg_temp_new_i32();
1422 25c4d9cc Richard Henderson
        t1 = tcg_temp_new_i32();
1423 c896fe29 bellard
    
1424 25c4d9cc Richard Henderson
        tcg_gen_shli_i32(t0, arg, 24);
1425 c896fe29 bellard
    
1426 25c4d9cc Richard Henderson
        tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1427 25c4d9cc Richard Henderson
        tcg_gen_shli_i32(t1, t1, 8);
1428 25c4d9cc Richard Henderson
        tcg_gen_or_i32(t0, t0, t1);
1429 c896fe29 bellard
    
1430 25c4d9cc Richard Henderson
        tcg_gen_shri_i32(t1, arg, 8);
1431 25c4d9cc Richard Henderson
        tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1432 25c4d9cc Richard Henderson
        tcg_gen_or_i32(t0, t0, t1);
1433 c896fe29 bellard
    
1434 25c4d9cc Richard Henderson
        tcg_gen_shri_i32(t1, arg, 24);
1435 25c4d9cc Richard Henderson
        tcg_gen_or_i32(ret, t0, t1);
1436 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t0);
1437 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t1);
1438 25c4d9cc Richard Henderson
    }
1439 c896fe29 bellard
}
1440 c896fe29 bellard
1441 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1442 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1443 c896fe29 bellard
{
1444 a7812ae4 pbrook
    tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1445 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1446 c896fe29 bellard
}
1447 c896fe29 bellard
1448 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1449 c896fe29 bellard
{
1450 a7812ae4 pbrook
    tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1451 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1452 c896fe29 bellard
}
1453 c896fe29 bellard
1454 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1455 c896fe29 bellard
{
1456 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1457 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1458 c896fe29 bellard
}
1459 c896fe29 bellard
1460 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1461 86831435 pbrook
{
1462 a7812ae4 pbrook
    tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1463 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1464 86831435 pbrook
}
1465 86831435 pbrook
1466 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1467 86831435 pbrook
{
1468 a7812ae4 pbrook
    tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1469 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1470 86831435 pbrook
}
1471 86831435 pbrook
1472 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1473 86831435 pbrook
{
1474 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1475 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1476 86831435 pbrook
}
1477 86831435 pbrook
1478 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1479 c896fe29 bellard
{
1480 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1481 c896fe29 bellard
}
1482 c896fe29 bellard
1483 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1484 c896fe29 bellard
{
1485 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1486 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1487 c896fe29 bellard
}
1488 c896fe29 bellard
1489 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1490 c896fe29 bellard
{
1491 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1492 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1493 c896fe29 bellard
}
1494 c896fe29 bellard
1495 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1496 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1497 9a5c57fd aurel32
{
1498 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1499 9a5c57fd aurel32
    tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1500 9a5c57fd aurel32
}
1501 9a5c57fd aurel32
1502 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1503 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1504 9a5c57fd aurel32
{
1505 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1506 9a5c57fd aurel32
    tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1507 9a5c57fd aurel32
}
1508 9a5c57fd aurel32
1509 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1510 c896fe29 bellard
{
1511 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1512 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1513 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1514 c896fe29 bellard
1515 66896cb8 aurel32
    tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1516 66896cb8 aurel32
    tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1517 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1518 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1519 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1520 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1521 c896fe29 bellard
}
1522 c896fe29 bellard
#else
1523 c896fe29 bellard
1524 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1525 c896fe29 bellard
{
1526 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_ext8s_i64) {
1527 25c4d9cc Richard Henderson
        tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1528 25c4d9cc Richard Henderson
    } else {
1529 25c4d9cc Richard Henderson
        tcg_gen_shli_i64(ret, arg, 56);
1530 25c4d9cc Richard Henderson
        tcg_gen_sari_i64(ret, ret, 56);
1531 25c4d9cc Richard Henderson
    }
1532 c896fe29 bellard
}
1533 c896fe29 bellard
1534 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1535 c896fe29 bellard
{
1536 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_ext16s_i64) {
1537 25c4d9cc Richard Henderson
        tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1538 25c4d9cc Richard Henderson
    } else {
1539 25c4d9cc Richard Henderson
        tcg_gen_shli_i64(ret, arg, 48);
1540 25c4d9cc Richard Henderson
        tcg_gen_sari_i64(ret, ret, 48);
1541 25c4d9cc Richard Henderson
    }
1542 c896fe29 bellard
}
1543 c896fe29 bellard
1544 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1545 c896fe29 bellard
{
1546 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_ext32s_i64) {
1547 25c4d9cc Richard Henderson
        tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1548 25c4d9cc Richard Henderson
    } else {
1549 25c4d9cc Richard Henderson
        tcg_gen_shli_i64(ret, arg, 32);
1550 25c4d9cc Richard Henderson
        tcg_gen_sari_i64(ret, ret, 32);
1551 25c4d9cc Richard Henderson
    }
1552 c896fe29 bellard
}
1553 c896fe29 bellard
1554 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1555 86831435 pbrook
{
1556 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_ext8u_i64) {
1557 25c4d9cc Richard Henderson
        tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1558 25c4d9cc Richard Henderson
    } else {
1559 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(ret, arg, 0xffu);
1560 25c4d9cc Richard Henderson
    }
1561 86831435 pbrook
}
1562 86831435 pbrook
1563 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1564 86831435 pbrook
{
1565 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_ext16u_i64) {
1566 25c4d9cc Richard Henderson
        tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1567 25c4d9cc Richard Henderson
    } else {
1568 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(ret, arg, 0xffffu);
1569 25c4d9cc Richard Henderson
    }
1570 86831435 pbrook
}
1571 86831435 pbrook
1572 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1573 86831435 pbrook
{
1574 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_ext32u_i64) {
1575 25c4d9cc Richard Henderson
        tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1576 25c4d9cc Richard Henderson
    } else {
1577 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1578 25c4d9cc Richard Henderson
    }
1579 86831435 pbrook
}
1580 86831435 pbrook
1581 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1582 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1583 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1584 c896fe29 bellard
{
1585 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1586 c896fe29 bellard
}
1587 c896fe29 bellard
1588 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1589 c896fe29 bellard
   registers */
1590 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1591 c896fe29 bellard
{
1592 cfc86988 Aurelien Jarno
    tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1593 c896fe29 bellard
}
1594 c896fe29 bellard
1595 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1596 c896fe29 bellard
   registers */
1597 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1598 c896fe29 bellard
{
1599 a7812ae4 pbrook
    tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1600 c896fe29 bellard
}
1601 c896fe29 bellard
1602 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1603 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1604 9a5c57fd aurel32
{
1605 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_bswap16_i64) {
1606 25c4d9cc Richard Henderson
        tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1607 25c4d9cc Richard Henderson
    } else {
1608 25c4d9cc Richard Henderson
        TCGv_i64 t0 = tcg_temp_new_i64();
1609 9a5c57fd aurel32
1610 25c4d9cc Richard Henderson
        tcg_gen_ext8u_i64(t0, arg);
1611 25c4d9cc Richard Henderson
        tcg_gen_shli_i64(t0, t0, 8);
1612 25c4d9cc Richard Henderson
        tcg_gen_shri_i64(ret, arg, 8);
1613 25c4d9cc Richard Henderson
        tcg_gen_or_i64(ret, ret, t0);
1614 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
1615 25c4d9cc Richard Henderson
    }
1616 9a5c57fd aurel32
}
1617 9a5c57fd aurel32
1618 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1619 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1620 9a5c57fd aurel32
{
1621 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_bswap32_i64) {
1622 25c4d9cc Richard Henderson
        tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1623 25c4d9cc Richard Henderson
    } else {
1624 25c4d9cc Richard Henderson
        TCGv_i64 t0, t1;
1625 25c4d9cc Richard Henderson
        t0 = tcg_temp_new_i64();
1626 25c4d9cc Richard Henderson
        t1 = tcg_temp_new_i64();
1627 9a5c57fd aurel32
1628 25c4d9cc Richard Henderson
        tcg_gen_shli_i64(t0, arg, 24);
1629 25c4d9cc Richard Henderson
        tcg_gen_ext32u_i64(t0, t0);
1630 9a5c57fd aurel32
1631 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1632 25c4d9cc Richard Henderson
        tcg_gen_shli_i64(t1, t1, 8);
1633 25c4d9cc Richard Henderson
        tcg_gen_or_i64(t0, t0, t1);
1634 9a5c57fd aurel32
1635 25c4d9cc Richard Henderson
        tcg_gen_shri_i64(t1, arg, 8);
1636 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1637 25c4d9cc Richard Henderson
        tcg_gen_or_i64(t0, t0, t1);
1638 9a5c57fd aurel32
1639 25c4d9cc Richard Henderson
        tcg_gen_shri_i64(t1, arg, 24);
1640 25c4d9cc Richard Henderson
        tcg_gen_or_i64(ret, t0, t1);
1641 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
1642 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t1);
1643 25c4d9cc Richard Henderson
    }
1644 9a5c57fd aurel32
}
1645 9a5c57fd aurel32
1646 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1647 c896fe29 bellard
{
1648 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_bswap64_i64) {
1649 25c4d9cc Richard Henderson
        tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1650 25c4d9cc Richard Henderson
    } else {
1651 25c4d9cc Richard Henderson
        TCGv_i64 t0 = tcg_temp_new_i64();
1652 25c4d9cc Richard Henderson
        TCGv_i64 t1 = tcg_temp_new_i64();
1653 c896fe29 bellard
    
1654 25c4d9cc Richard Henderson
        tcg_gen_shli_i64(t0, arg, 56);
1655 c896fe29 bellard
    
1656 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1657 25c4d9cc Richard Henderson
        tcg_gen_shli_i64(t1, t1, 40);
1658 25c4d9cc Richard Henderson
        tcg_gen_or_i64(t0, t0, t1);
1659 c896fe29 bellard
    
1660 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1661 25c4d9cc Richard Henderson
        tcg_gen_shli_i64(t1, t1, 24);
1662 25c4d9cc Richard Henderson
        tcg_gen_or_i64(t0, t0, t1);
1663 c896fe29 bellard
1664 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(t1, arg, 0xff000000);
1665 25c4d9cc Richard Henderson
        tcg_gen_shli_i64(t1, t1, 8);
1666 25c4d9cc Richard Henderson
        tcg_gen_or_i64(t0, t0, t1);
1667 c896fe29 bellard
1668 25c4d9cc Richard Henderson
        tcg_gen_shri_i64(t1, arg, 8);
1669 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(t1, t1, 0xff000000);
1670 25c4d9cc Richard Henderson
        tcg_gen_or_i64(t0, t0, t1);
1671 c896fe29 bellard
    
1672 25c4d9cc Richard Henderson
        tcg_gen_shri_i64(t1, arg, 24);
1673 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1674 25c4d9cc Richard Henderson
        tcg_gen_or_i64(t0, t0, t1);
1675 c896fe29 bellard
1676 25c4d9cc Richard Henderson
        tcg_gen_shri_i64(t1, arg, 40);
1677 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1678 25c4d9cc Richard Henderson
        tcg_gen_or_i64(t0, t0, t1);
1679 c896fe29 bellard
1680 25c4d9cc Richard Henderson
        tcg_gen_shri_i64(t1, arg, 56);
1681 25c4d9cc Richard Henderson
        tcg_gen_or_i64(ret, t0, t1);
1682 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
1683 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t1);
1684 25c4d9cc Richard Henderson
    }
1685 c896fe29 bellard
}
1686 c896fe29 bellard
1687 c896fe29 bellard
#endif
1688 c896fe29 bellard
1689 a7812ae4 pbrook
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1690 390efc54 pbrook
{
1691 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_neg_i32) {
1692 25c4d9cc Richard Henderson
        tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1693 25c4d9cc Richard Henderson
    } else {
1694 25c4d9cc Richard Henderson
        TCGv_i32 t0 = tcg_const_i32(0);
1695 25c4d9cc Richard Henderson
        tcg_gen_sub_i32(ret, t0, arg);
1696 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t0);
1697 25c4d9cc Richard Henderson
    }
1698 390efc54 pbrook
}
1699 390efc54 pbrook
1700 a7812ae4 pbrook
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1701 390efc54 pbrook
{
1702 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_neg_i64) {
1703 25c4d9cc Richard Henderson
        tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1704 25c4d9cc Richard Henderson
    } else {
1705 25c4d9cc Richard Henderson
        TCGv_i64 t0 = tcg_const_i64(0);
1706 25c4d9cc Richard Henderson
        tcg_gen_sub_i64(ret, t0, arg);
1707 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
1708 25c4d9cc Richard Henderson
    }
1709 390efc54 pbrook
}
1710 390efc54 pbrook
1711 a7812ae4 pbrook
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1712 0b6ce4cf bellard
{
1713 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_not_i32) {
1714 25c4d9cc Richard Henderson
        tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1715 25c4d9cc Richard Henderson
    } else {
1716 25c4d9cc Richard Henderson
        tcg_gen_xori_i32(ret, arg, -1);
1717 25c4d9cc Richard Henderson
    }
1718 0b6ce4cf bellard
}
1719 0b6ce4cf bellard
1720 a7812ae4 pbrook
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1721 0b6ce4cf bellard
{
1722 25c4d9cc Richard Henderson
#if TCG_TARGET_REG_BITS == 64
1723 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_not_i64) {
1724 25c4d9cc Richard Henderson
        tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1725 25c4d9cc Richard Henderson
    } else {
1726 25c4d9cc Richard Henderson
        tcg_gen_xori_i64(ret, arg, -1);
1727 25c4d9cc Richard Henderson
    }
1728 25c4d9cc Richard Henderson
#else
1729 a10f9f4f Richard Henderson
    tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1730 a10f9f4f Richard Henderson
    tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1731 d2604285 aurel32
#endif
1732 0b6ce4cf bellard
}
1733 5ff9d6a4 bellard
1734 a7812ae4 pbrook
static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1735 5ff9d6a4 bellard
{
1736 a7812ae4 pbrook
    tcg_gen_op1_i32(INDEX_op_discard, arg);
1737 5ff9d6a4 bellard
}
1738 5ff9d6a4 bellard
1739 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1740 5ff9d6a4 bellard
{
1741 25c4d9cc Richard Henderson
#if TCG_TARGET_REG_BITS == 32
1742 a7812ae4 pbrook
    tcg_gen_discard_i32(TCGV_LOW(arg));
1743 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1744 5ff9d6a4 bellard
#else
1745 a7812ae4 pbrook
    tcg_gen_op1_i64(INDEX_op_discard, arg);
1746 5ff9d6a4 bellard
#endif
1747 25c4d9cc Richard Henderson
}
1748 5ff9d6a4 bellard
1749 a7812ae4 pbrook
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1750 36aa55dc pbrook
{
1751 36aa55dc pbrook
#if TCG_TARGET_REG_BITS == 32
1752 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(dest), low);
1753 36aa55dc pbrook
    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1754 36aa55dc pbrook
#else
1755 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1756 36aa55dc pbrook
    /* This extension is only needed for type correctness.
1757 36aa55dc pbrook
       We may be able to do better given target specific information.  */
1758 36aa55dc pbrook
    tcg_gen_extu_i32_i64(tmp, high);
1759 36aa55dc pbrook
    tcg_gen_shli_i64(tmp, tmp, 32);
1760 36aa55dc pbrook
    tcg_gen_extu_i32_i64(dest, low);
1761 36aa55dc pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1762 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1763 36aa55dc pbrook
#endif
1764 36aa55dc pbrook
}
1765 36aa55dc pbrook
1766 a7812ae4 pbrook
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1767 945ca823 blueswir1
{
1768 945ca823 blueswir1
#if TCG_TARGET_REG_BITS == 32
1769 a7812ae4 pbrook
    tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1770 945ca823 blueswir1
#else
1771 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1772 88422e2e pbrook
    tcg_gen_ext32u_i64(dest, low);
1773 945ca823 blueswir1
    tcg_gen_shli_i64(tmp, high, 32);
1774 88422e2e pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1775 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1776 945ca823 blueswir1
#endif
1777 945ca823 blueswir1
}
1778 945ca823 blueswir1
1779 a7812ae4 pbrook
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1780 f24cb33e aurel32
{
1781 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_andc_i32) {
1782 25c4d9cc Richard Henderson
        tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
1783 25c4d9cc Richard Henderson
    } else {
1784 25c4d9cc Richard Henderson
        TCGv_i32 t0 = tcg_temp_new_i32();
1785 25c4d9cc Richard Henderson
        tcg_gen_not_i32(t0, arg2);
1786 25c4d9cc Richard Henderson
        tcg_gen_and_i32(ret, arg1, t0);
1787 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t0);
1788 25c4d9cc Richard Henderson
    }
1789 f24cb33e aurel32
}
1790 f24cb33e aurel32
1791 a7812ae4 pbrook
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1792 f24cb33e aurel32
{
1793 25c4d9cc Richard Henderson
#if TCG_TARGET_REG_BITS == 64
1794 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_andc_i64) {
1795 25c4d9cc Richard Henderson
        tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1796 25c4d9cc Richard Henderson
    } else {
1797 25c4d9cc Richard Henderson
        TCGv_i64 t0 = tcg_temp_new_i64();
1798 25c4d9cc Richard Henderson
        tcg_gen_not_i64(t0, arg2);
1799 25c4d9cc Richard Henderson
        tcg_gen_and_i64(ret, arg1, t0);
1800 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
1801 25c4d9cc Richard Henderson
    }
1802 25c4d9cc Richard Henderson
#else
1803 241cbed4 Richard Henderson
    tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1804 241cbed4 Richard Henderson
    tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1805 241cbed4 Richard Henderson
#endif
1806 f24cb33e aurel32
}
1807 f24cb33e aurel32
1808 a7812ae4 pbrook
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1809 f24cb33e aurel32
{
1810 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_eqv_i32) {
1811 25c4d9cc Richard Henderson
        tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
1812 25c4d9cc Richard Henderson
    } else {
1813 25c4d9cc Richard Henderson
        tcg_gen_xor_i32(ret, arg1, arg2);
1814 25c4d9cc Richard Henderson
        tcg_gen_not_i32(ret, ret);
1815 25c4d9cc Richard Henderson
    }
1816 f24cb33e aurel32
}
1817 f24cb33e aurel32
1818 a7812ae4 pbrook
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1819 f24cb33e aurel32
{
1820 25c4d9cc Richard Henderson
#if TCG_TARGET_REG_BITS == 64
1821 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_eqv_i64) {
1822 25c4d9cc Richard Henderson
        tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
1823 25c4d9cc Richard Henderson
    } else {
1824 25c4d9cc Richard Henderson
        tcg_gen_xor_i64(ret, arg1, arg2);
1825 25c4d9cc Richard Henderson
        tcg_gen_not_i64(ret, ret);
1826 25c4d9cc Richard Henderson
    }
1827 25c4d9cc Richard Henderson
#else
1828 8d625cf1 Richard Henderson
    tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1829 8d625cf1 Richard Henderson
    tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1830 8d625cf1 Richard Henderson
#endif
1831 f24cb33e aurel32
}
1832 f24cb33e aurel32
1833 a7812ae4 pbrook
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1834 f24cb33e aurel32
{
1835 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_nand_i32) {
1836 25c4d9cc Richard Henderson
        tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
1837 25c4d9cc Richard Henderson
    } else {
1838 25c4d9cc Richard Henderson
        tcg_gen_and_i32(ret, arg1, arg2);
1839 25c4d9cc Richard Henderson
        tcg_gen_not_i32(ret, ret);
1840 25c4d9cc Richard Henderson
    }
1841 f24cb33e aurel32
}
1842 f24cb33e aurel32
1843 a7812ae4 pbrook
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1844 f24cb33e aurel32
{
1845 25c4d9cc Richard Henderson
#if TCG_TARGET_REG_BITS == 64
1846 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_nand_i64) {
1847 25c4d9cc Richard Henderson
        tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
1848 25c4d9cc Richard Henderson
    } else {
1849 25c4d9cc Richard Henderson
        tcg_gen_and_i64(ret, arg1, arg2);
1850 25c4d9cc Richard Henderson
        tcg_gen_not_i64(ret, ret);
1851 25c4d9cc Richard Henderson
    }
1852 25c4d9cc Richard Henderson
#else
1853 9940a96b Richard Henderson
    tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1854 9940a96b Richard Henderson
    tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1855 9940a96b Richard Henderson
#endif
1856 f24cb33e aurel32
}
1857 f24cb33e aurel32
1858 a7812ae4 pbrook
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1859 f24cb33e aurel32
{
1860 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_nor_i32) {
1861 25c4d9cc Richard Henderson
        tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
1862 25c4d9cc Richard Henderson
    } else {
1863 25c4d9cc Richard Henderson
        tcg_gen_or_i32(ret, arg1, arg2);
1864 25c4d9cc Richard Henderson
        tcg_gen_not_i32(ret, ret);
1865 25c4d9cc Richard Henderson
    }
1866 f24cb33e aurel32
}
1867 f24cb33e aurel32
1868 a7812ae4 pbrook
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1869 f24cb33e aurel32
{
1870 25c4d9cc Richard Henderson
#if TCG_TARGET_REG_BITS == 64
1871 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_nor_i64) {
1872 25c4d9cc Richard Henderson
        tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
1873 25c4d9cc Richard Henderson
    } else {
1874 25c4d9cc Richard Henderson
        tcg_gen_or_i64(ret, arg1, arg2);
1875 25c4d9cc Richard Henderson
        tcg_gen_not_i64(ret, ret);
1876 25c4d9cc Richard Henderson
    }
1877 25c4d9cc Richard Henderson
#else
1878 32d98fbd Richard Henderson
    tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1879 32d98fbd Richard Henderson
    tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1880 32d98fbd Richard Henderson
#endif
1881 f24cb33e aurel32
}
1882 f24cb33e aurel32
1883 a7812ae4 pbrook
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1884 f24cb33e aurel32
{
1885 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_orc_i32) {
1886 25c4d9cc Richard Henderson
        tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
1887 25c4d9cc Richard Henderson
    } else {
1888 25c4d9cc Richard Henderson
        TCGv_i32 t0 = tcg_temp_new_i32();
1889 25c4d9cc Richard Henderson
        tcg_gen_not_i32(t0, arg2);
1890 25c4d9cc Richard Henderson
        tcg_gen_or_i32(ret, arg1, t0);
1891 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t0);
1892 25c4d9cc Richard Henderson
    }
1893 f24cb33e aurel32
}
1894 f24cb33e aurel32
1895 a7812ae4 pbrook
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1896 f24cb33e aurel32
{
1897 25c4d9cc Richard Henderson
#if TCG_TARGET_REG_BITS == 64
1898 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_orc_i64) {
1899 25c4d9cc Richard Henderson
        tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
1900 25c4d9cc Richard Henderson
    } else {
1901 25c4d9cc Richard Henderson
        TCGv_i64 t0 = tcg_temp_new_i64();
1902 25c4d9cc Richard Henderson
        tcg_gen_not_i64(t0, arg2);
1903 25c4d9cc Richard Henderson
        tcg_gen_or_i64(ret, arg1, t0);
1904 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
1905 25c4d9cc Richard Henderson
    }
1906 25c4d9cc Richard Henderson
#else
1907 791d1262 Richard Henderson
    tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1908 791d1262 Richard Henderson
    tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1909 791d1262 Richard Henderson
#endif
1910 f24cb33e aurel32
}
1911 f24cb33e aurel32
1912 a7812ae4 pbrook
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1913 15824571 aurel32
{
1914 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_rot_i32) {
1915 25c4d9cc Richard Henderson
        tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1916 25c4d9cc Richard Henderson
    } else {
1917 25c4d9cc Richard Henderson
        TCGv_i32 t0, t1;
1918 15824571 aurel32
1919 25c4d9cc Richard Henderson
        t0 = tcg_temp_new_i32();
1920 25c4d9cc Richard Henderson
        t1 = tcg_temp_new_i32();
1921 25c4d9cc Richard Henderson
        tcg_gen_shl_i32(t0, arg1, arg2);
1922 25c4d9cc Richard Henderson
        tcg_gen_subfi_i32(t1, 32, arg2);
1923 25c4d9cc Richard Henderson
        tcg_gen_shr_i32(t1, arg1, t1);
1924 25c4d9cc Richard Henderson
        tcg_gen_or_i32(ret, t0, t1);
1925 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t0);
1926 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t1);
1927 25c4d9cc Richard Henderson
    }
1928 15824571 aurel32
}
1929 15824571 aurel32
1930 a7812ae4 pbrook
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1931 15824571 aurel32
{
1932 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_rot_i64) {
1933 25c4d9cc Richard Henderson
        tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1934 25c4d9cc Richard Henderson
    } else {
1935 25c4d9cc Richard Henderson
        TCGv_i64 t0, t1;
1936 25c4d9cc Richard Henderson
        t0 = tcg_temp_new_i64();
1937 25c4d9cc Richard Henderson
        t1 = tcg_temp_new_i64();
1938 25c4d9cc Richard Henderson
        tcg_gen_shl_i64(t0, arg1, arg2);
1939 25c4d9cc Richard Henderson
        tcg_gen_subfi_i64(t1, 64, arg2);
1940 25c4d9cc Richard Henderson
        tcg_gen_shr_i64(t1, arg1, t1);
1941 25c4d9cc Richard Henderson
        tcg_gen_or_i64(ret, t0, t1);
1942 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
1943 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t1);
1944 25c4d9cc Richard Henderson
    }
1945 15824571 aurel32
}
1946 15824571 aurel32
1947 a7812ae4 pbrook
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1948 15824571 aurel32
{
1949 15824571 aurel32
    /* some cases can be optimized here */
1950 15824571 aurel32
    if (arg2 == 0) {
1951 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
1952 25c4d9cc Richard Henderson
    } else if (TCG_TARGET_HAS_rot_i32) {
1953 d42f183c aurel32
        TCGv_i32 t0 = tcg_const_i32(arg2);
1954 d42f183c aurel32
        tcg_gen_rotl_i32(ret, arg1, t0);
1955 d42f183c aurel32
        tcg_temp_free_i32(t0);
1956 25c4d9cc Richard Henderson
    } else {
1957 a7812ae4 pbrook
        TCGv_i32 t0, t1;
1958 a7812ae4 pbrook
        t0 = tcg_temp_new_i32();
1959 a7812ae4 pbrook
        t1 = tcg_temp_new_i32();
1960 15824571 aurel32
        tcg_gen_shli_i32(t0, arg1, arg2);
1961 15824571 aurel32
        tcg_gen_shri_i32(t1, arg1, 32 - arg2);
1962 15824571 aurel32
        tcg_gen_or_i32(ret, t0, t1);
1963 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
1964 a7812ae4 pbrook
        tcg_temp_free_i32(t1);
1965 15824571 aurel32
    }
1966 15824571 aurel32
}
1967 15824571 aurel32
1968 a7812ae4 pbrook
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1969 15824571 aurel32
{
1970 15824571 aurel32
    /* some cases can be optimized here */
1971 15824571 aurel32
    if (arg2 == 0) {
1972 15824571 aurel32
        tcg_gen_mov_i64(ret, arg1);
1973 25c4d9cc Richard Henderson
    } else if (TCG_TARGET_HAS_rot_i64) {
1974 d42f183c aurel32
        TCGv_i64 t0 = tcg_const_i64(arg2);
1975 d42f183c aurel32
        tcg_gen_rotl_i64(ret, arg1, t0);
1976 d42f183c aurel32
        tcg_temp_free_i64(t0);
1977 25c4d9cc Richard Henderson
    } else {
1978 a7812ae4 pbrook
        TCGv_i64 t0, t1;
1979 a7812ae4 pbrook
        t0 = tcg_temp_new_i64();
1980 a7812ae4 pbrook
        t1 = tcg_temp_new_i64();
1981 15824571 aurel32
        tcg_gen_shli_i64(t0, arg1, arg2);
1982 15824571 aurel32
        tcg_gen_shri_i64(t1, arg1, 64 - arg2);
1983 15824571 aurel32
        tcg_gen_or_i64(ret, t0, t1);
1984 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1985 a7812ae4 pbrook
        tcg_temp_free_i64(t1);
1986 15824571 aurel32
    }
1987 15824571 aurel32
}
1988 15824571 aurel32
1989 a7812ae4 pbrook
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1990 15824571 aurel32
{
1991 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_rot_i32) {
1992 25c4d9cc Richard Henderson
        tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
1993 25c4d9cc Richard Henderson
    } else {
1994 25c4d9cc Richard Henderson
        TCGv_i32 t0, t1;
1995 15824571 aurel32
1996 25c4d9cc Richard Henderson
        t0 = tcg_temp_new_i32();
1997 25c4d9cc Richard Henderson
        t1 = tcg_temp_new_i32();
1998 25c4d9cc Richard Henderson
        tcg_gen_shr_i32(t0, arg1, arg2);
1999 25c4d9cc Richard Henderson
        tcg_gen_subfi_i32(t1, 32, arg2);
2000 25c4d9cc Richard Henderson
        tcg_gen_shl_i32(t1, arg1, t1);
2001 25c4d9cc Richard Henderson
        tcg_gen_or_i32(ret, t0, t1);
2002 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t0);
2003 25c4d9cc Richard Henderson
        tcg_temp_free_i32(t1);
2004 25c4d9cc Richard Henderson
    }
2005 15824571 aurel32
}
2006 15824571 aurel32
2007 a7812ae4 pbrook
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2008 15824571 aurel32
{
2009 25c4d9cc Richard Henderson
    if (TCG_TARGET_HAS_rot_i64) {
2010 25c4d9cc Richard Henderson
        tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
2011 25c4d9cc Richard Henderson
    } else {
2012 25c4d9cc Richard Henderson
        TCGv_i64 t0, t1;
2013 25c4d9cc Richard Henderson
        t0 = tcg_temp_new_i64();
2014 25c4d9cc Richard Henderson
        t1 = tcg_temp_new_i64();
2015 25c4d9cc Richard Henderson
        tcg_gen_shr_i64(t0, arg1, arg2);
2016 25c4d9cc Richard Henderson
        tcg_gen_subfi_i64(t1, 64, arg2);
2017 25c4d9cc Richard Henderson
        tcg_gen_shl_i64(t1, arg1, t1);
2018 25c4d9cc Richard Henderson
        tcg_gen_or_i64(ret, t0, t1);
2019 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t0);
2020 25c4d9cc Richard Henderson
        tcg_temp_free_i64(t1);
2021 25c4d9cc Richard Henderson
    }
2022 15824571 aurel32
}
2023 15824571 aurel32
2024 a7812ae4 pbrook
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
2025 15824571 aurel32
{
2026 15824571 aurel32
    /* some cases can be optimized here */
2027 15824571 aurel32
    if (arg2 == 0) {
2028 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
2029 15824571 aurel32
    } else {
2030 15824571 aurel32
        tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
2031 15824571 aurel32
    }
2032 15824571 aurel32
}
2033 15824571 aurel32
2034 a7812ae4 pbrook
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2035 15824571 aurel32
{
2036 15824571 aurel32
    /* some cases can be optimized here */
2037 15824571 aurel32
    if (arg2 == 0) {
2038 de3526b2 pbrook
        tcg_gen_mov_i64(ret, arg1);
2039 15824571 aurel32
    } else {
2040 15824571 aurel32
        tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
2041 15824571 aurel32
    }
2042 15824571 aurel32
}
2043 15824571 aurel32
2044 b7767f0f Richard Henderson
static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
2045 0756e71c Richard Henderson
                                       TCGv_i32 arg2, unsigned int ofs,
2046 0756e71c Richard Henderson
                                       unsigned int len)
2047 b7767f0f Richard Henderson
{
2048 df072774 Richard Henderson
    uint32_t mask;
2049 df072774 Richard Henderson
    TCGv_i32 t1;
2050 df072774 Richard Henderson
2051 df072774 Richard Henderson
    if (ofs == 0 && len == 32) {
2052 df072774 Richard Henderson
        tcg_gen_mov_i32(ret, arg2);
2053 df072774 Richard Henderson
        return;
2054 df072774 Richard Henderson
    }
2055 a4773324 Jan Kiszka
    if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) {
2056 25c4d9cc Richard Henderson
        tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
2057 df072774 Richard Henderson
        return;
2058 df072774 Richard Henderson
    }
2059 df072774 Richard Henderson
2060 df072774 Richard Henderson
    mask = (1u << len) - 1;
2061 df072774 Richard Henderson
    t1 = tcg_temp_new_i32();
2062 b7767f0f Richard Henderson
2063 df072774 Richard Henderson
    if (ofs + len < 32) {
2064 25c4d9cc Richard Henderson
        tcg_gen_andi_i32(t1, arg2, mask);
2065 25c4d9cc Richard Henderson
        tcg_gen_shli_i32(t1, t1, ofs);
2066 df072774 Richard Henderson
    } else {
2067 df072774 Richard Henderson
        tcg_gen_shli_i32(t1, arg2, ofs);
2068 25c4d9cc Richard Henderson
    }
2069 df072774 Richard Henderson
    tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
2070 df072774 Richard Henderson
    tcg_gen_or_i32(ret, ret, t1);
2071 df072774 Richard Henderson
2072 df072774 Richard Henderson
    tcg_temp_free_i32(t1);
2073 b7767f0f Richard Henderson
}
2074 b7767f0f Richard Henderson
2075 b7767f0f Richard Henderson
static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
2076 0756e71c Richard Henderson
                                       TCGv_i64 arg2, unsigned int ofs,
2077 0756e71c Richard Henderson
                                       unsigned int len)
2078 b7767f0f Richard Henderson
{
2079 df072774 Richard Henderson
    uint64_t mask;
2080 df072774 Richard Henderson
    TCGv_i64 t1;
2081 df072774 Richard Henderson
2082 df072774 Richard Henderson
    if (ofs == 0 && len == 64) {
2083 df072774 Richard Henderson
        tcg_gen_mov_i64(ret, arg2);
2084 df072774 Richard Henderson
        return;
2085 df072774 Richard Henderson
    }
2086 a4773324 Jan Kiszka
    if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) {
2087 25c4d9cc Richard Henderson
        tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
2088 df072774 Richard Henderson
        return;
2089 df072774 Richard Henderson
    }
2090 b7767f0f Richard Henderson
2091 df072774 Richard Henderson
#if TCG_TARGET_REG_BITS == 32
2092 df072774 Richard Henderson
    if (ofs >= 32) {
2093 2f98c9db Richard Henderson
        tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
2094 df072774 Richard Henderson
        tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1),
2095 df072774 Richard Henderson
                            TCGV_LOW(arg2), ofs - 32, len);
2096 df072774 Richard Henderson
        return;
2097 df072774 Richard Henderson
    }
2098 df072774 Richard Henderson
    if (ofs + len <= 32) {
2099 df072774 Richard Henderson
        tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1),
2100 df072774 Richard Henderson
                            TCGV_LOW(arg2), ofs, len);
2101 2f98c9db Richard Henderson
        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
2102 df072774 Richard Henderson
        return;
2103 df072774 Richard Henderson
    }
2104 df072774 Richard Henderson
#endif
2105 df072774 Richard Henderson
2106 df072774 Richard Henderson
    mask = (1ull << len) - 1;
2107 df072774 Richard Henderson
    t1 = tcg_temp_new_i64();
2108 df072774 Richard Henderson
2109 df072774 Richard Henderson
    if (ofs + len < 64) {
2110 25c4d9cc Richard Henderson
        tcg_gen_andi_i64(t1, arg2, mask);
2111 25c4d9cc Richard Henderson
        tcg_gen_shli_i64(t1, t1, ofs);
2112 df072774 Richard Henderson
    } else {
2113 df072774 Richard Henderson
        tcg_gen_shli_i64(t1, arg2, ofs);
2114 25c4d9cc Richard Henderson
    }
2115 df072774 Richard Henderson
    tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
2116 df072774 Richard Henderson
    tcg_gen_or_i64(ret, ret, t1);
2117 df072774 Richard Henderson
2118 df072774 Richard Henderson
    tcg_temp_free_i64(t1);
2119 b7767f0f Richard Henderson
}
2120 b7767f0f Richard Henderson
2121 c896fe29 bellard
/***************************************/
2122 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
2123 c896fe29 bellard
   type. */
2124 c896fe29 bellard
#ifndef TARGET_LONG_BITS
2125 c896fe29 bellard
#error must include QEMU headers
2126 c896fe29 bellard
#endif
2127 c896fe29 bellard
2128 a7812ae4 pbrook
#if TARGET_LONG_BITS == 32
2129 a7812ae4 pbrook
#define TCGv TCGv_i32
2130 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i32()
2131 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i32
2132 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i32
2133 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i32()
2134 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i32
2135 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
2136 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
2137 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
2138 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
2139 a7812ae4 pbrook
#else
2140 a7812ae4 pbrook
#define TCGv TCGv_i64
2141 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i64()
2142 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i64
2143 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i64
2144 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i64()
2145 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i64
2146 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
2147 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
2148 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
2149 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
2150 a7812ae4 pbrook
#endif
2151 a7812ae4 pbrook
2152 7e4597d7 bellard
/* debug info: write the PC of the corresponding QEMU CPU instruction */
2153 7e4597d7 bellard
static inline void tcg_gen_debug_insn_start(uint64_t pc)
2154 7e4597d7 bellard
{
2155 7e4597d7 bellard
    /* XXX: must really use a 32 bit size for TCGArg in all cases */
2156 7e4597d7 bellard
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2157 bcb0126f pbrook
    tcg_gen_op2ii(INDEX_op_debug_insn_start, 
2158 bcb0126f pbrook
                  (uint32_t)(pc), (uint32_t)(pc >> 32));
2159 7e4597d7 bellard
#else
2160 7e4597d7 bellard
    tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
2161 7e4597d7 bellard
#endif
2162 7e4597d7 bellard
}
2163 7e4597d7 bellard
2164 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
2165 c896fe29 bellard
{
2166 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
2167 c896fe29 bellard
}
2168 c896fe29 bellard
2169 c896fe29 bellard
static inline void tcg_gen_goto_tb(int idx)
2170 c896fe29 bellard
{
2171 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
2172 c896fe29 bellard
}
2173 c896fe29 bellard
2174 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
2175 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2176 c896fe29 bellard
{
2177 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2178 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2179 c896fe29 bellard
#else
2180 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
2181 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2182 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2183 c896fe29 bellard
#endif
2184 c896fe29 bellard
}
2185 c896fe29 bellard
2186 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2187 c896fe29 bellard
{
2188 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2189 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2190 c896fe29 bellard
#else
2191 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
2192 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2193 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2194 c896fe29 bellard
#endif
2195 c896fe29 bellard
}
2196 c896fe29 bellard
2197 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2198 c896fe29 bellard
{
2199 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2200 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2201 c896fe29 bellard
#else
2202 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
2203 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2204 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2205 c896fe29 bellard
#endif
2206 c896fe29 bellard
}
2207 c896fe29 bellard
2208 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2209 c896fe29 bellard
{
2210 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2211 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2212 c896fe29 bellard
#else
2213 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
2214 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2215 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2216 c896fe29 bellard
#endif
2217 c896fe29 bellard
}
2218 c896fe29 bellard
2219 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2220 c896fe29 bellard
{
2221 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2222 86feb1c8 Richard Henderson
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2223 c896fe29 bellard
#else
2224 86feb1c8 Richard Henderson
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2225 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2226 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2227 c896fe29 bellard
#endif
2228 c896fe29 bellard
}
2229 c896fe29 bellard
2230 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2231 c896fe29 bellard
{
2232 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2233 86feb1c8 Richard Henderson
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2234 c896fe29 bellard
#else
2235 86feb1c8 Richard Henderson
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2236 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2237 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2238 c896fe29 bellard
#endif
2239 c896fe29 bellard
}
2240 c896fe29 bellard
2241 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2242 c896fe29 bellard
{
2243 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2244 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
2245 c896fe29 bellard
#else
2246 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2247 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2248 c896fe29 bellard
#endif
2249 c896fe29 bellard
}
2250 c896fe29 bellard
2251 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2252 c896fe29 bellard
{
2253 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2254 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
2255 c896fe29 bellard
#else
2256 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
2257 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2258 c896fe29 bellard
#endif
2259 c896fe29 bellard
}
2260 c896fe29 bellard
2261 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2262 c896fe29 bellard
{
2263 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2264 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
2265 c896fe29 bellard
#else
2266 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2267 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2268 c896fe29 bellard
#endif
2269 c896fe29 bellard
}
2270 c896fe29 bellard
2271 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2272 c896fe29 bellard
{
2273 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2274 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
2275 c896fe29 bellard
#else
2276 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2277 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2278 c896fe29 bellard
#endif
2279 c896fe29 bellard
}
2280 c896fe29 bellard
2281 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2282 c896fe29 bellard
{
2283 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2284 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2285 a7812ae4 pbrook
                     mem_index);
2286 c896fe29 bellard
#else
2287 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2288 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2289 c896fe29 bellard
#endif
2290 c896fe29 bellard
}
2291 c896fe29 bellard
2292 ebecf363 Peter Maydell
#define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
2293 ebecf363 Peter Maydell
#define tcg_gen_discard_ptr(A) tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
2294 f8422f52 blueswir1
2295 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
2296 c896fe29 bellard
2297 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2298 c896fe29 bellard
{
2299 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2300 c896fe29 bellard
}
2301 c896fe29 bellard
2302 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2303 c896fe29 bellard
{
2304 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2305 c896fe29 bellard
}
2306 c896fe29 bellard
2307 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2308 c896fe29 bellard
{
2309 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2310 c896fe29 bellard
}
2311 c896fe29 bellard
2312 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2313 c896fe29 bellard
{
2314 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2315 c896fe29 bellard
}
2316 c896fe29 bellard
2317 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2318 c896fe29 bellard
{
2319 3e1dbadd Richard Henderson
#if TARGET_LONG_BITS == 32
2320 3e1dbadd Richard Henderson
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2321 3e1dbadd Richard Henderson
#else
2322 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
2323 3e1dbadd Richard Henderson
#endif
2324 c896fe29 bellard
}
2325 c896fe29 bellard
2326 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2327 c896fe29 bellard
{
2328 3e1dbadd Richard Henderson
#if TARGET_LONG_BITS == 32
2329 3e1dbadd Richard Henderson
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2330 3e1dbadd Richard Henderson
#else
2331 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
2332 3e1dbadd Richard Henderson
#endif
2333 c896fe29 bellard
}
2334 c896fe29 bellard
2335 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2336 c896fe29 bellard
{
2337 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
2338 c896fe29 bellard
}
2339 c896fe29 bellard
2340 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2341 c896fe29 bellard
{
2342 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
2343 c896fe29 bellard
}
2344 c896fe29 bellard
2345 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2346 c896fe29 bellard
{
2347 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2348 c896fe29 bellard
}
2349 c896fe29 bellard
2350 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2351 c896fe29 bellard
{
2352 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2353 c896fe29 bellard
}
2354 c896fe29 bellard
2355 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2356 c896fe29 bellard
{
2357 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2358 c896fe29 bellard
}
2359 c896fe29 bellard
2360 ebecf363 Peter Maydell
#define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
2361 ebecf363 Peter Maydell
#define tcg_gen_discard_ptr(A) tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
2362 f8422f52 blueswir1
2363 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */
2364 f8422f52 blueswir1
2365 f8422f52 blueswir1
#if TARGET_LONG_BITS == 64
2366 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i64
2367 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i64
2368 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2369 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2370 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2371 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2372 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2373 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2374 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i64
2375 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i64
2376 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i64
2377 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st32_i64
2378 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i64
2379 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i64
2380 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i64
2381 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i64
2382 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i64
2383 10460c8a pbrook
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
2384 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i64
2385 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i64
2386 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i64
2387 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i64
2388 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i64
2389 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i64
2390 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i64
2391 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i64
2392 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i64
2393 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i64
2394 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i64
2395 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i64
2396 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i64
2397 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i64
2398 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
2399 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2400 be210acb Richard Henderson
#define tcg_gen_setcond_tl tcg_gen_setcond_i64
2401 add1e7ea Aurelien Jarno
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
2402 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i64
2403 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i64
2404 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i64
2405 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i64
2406 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i64
2407 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i64
2408 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i64
2409 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2410 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2411 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2412 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2413 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2414 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2415 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2416 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2417 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2418 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2419 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2420 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2421 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2422 911d79ba aurel32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2423 911d79ba aurel32
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2424 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2425 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i64
2426 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
2427 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i64
2428 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i64
2429 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i64
2430 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
2431 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
2432 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
2433 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
2434 b7767f0f Richard Henderson
#define tcg_gen_deposit_tl tcg_gen_deposit_i64
2435 a98824ac blueswir1
#define tcg_const_tl tcg_const_i64
2436 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i64
2437 f8422f52 blueswir1
#else
2438 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i32
2439 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i32
2440 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2441 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2442 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2443 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2444 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
2445 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
2446 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i32
2447 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i32
2448 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i32
2449 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st_i32
2450 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i32
2451 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i32
2452 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i32
2453 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i32
2454 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i32
2455 0045734a aurel32
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
2456 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i32
2457 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i32
2458 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i32
2459 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i32
2460 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i32
2461 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i32
2462 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i32
2463 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i32
2464 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i32
2465 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i32
2466 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i32
2467 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i32
2468 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i32
2469 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i32
2470 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
2471 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2472 be210acb Richard Henderson
#define tcg_gen_setcond_tl tcg_gen_setcond_i32
2473 add1e7ea Aurelien Jarno
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
2474 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i32
2475 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i32
2476 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i32
2477 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i32
2478 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i32
2479 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i32
2480 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i32
2481 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2482 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2483 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2484 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2485 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2486 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2487 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2488 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2489 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2490 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2491 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
2492 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
2493 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2494 911d79ba aurel32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2495 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2496 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i32
2497 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
2498 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i32
2499 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i32
2500 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i32
2501 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
2502 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
2503 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
2504 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
2505 b7767f0f Richard Henderson
#define tcg_gen_deposit_tl tcg_gen_deposit_i32
2506 a98824ac blueswir1
#define tcg_const_tl tcg_const_i32
2507 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i32
2508 f8422f52 blueswir1
#endif
2509 6ddbc6e4 pbrook
2510 6ddbc6e4 pbrook
#if TCG_TARGET_REG_BITS == 32
2511 ebecf363 Peter Maydell
#define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \
2512 ebecf363 Peter Maydell
                                               TCGV_PTR_TO_NAT(A), \
2513 ebecf363 Peter Maydell
                                               TCGV_PTR_TO_NAT(B))
2514 ebecf363 Peter Maydell
#define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), \
2515 ebecf363 Peter Maydell
                                                 TCGV_PTR_TO_NAT(A), (B))
2516 ebecf363 Peter Maydell
#define tcg_gen_ext_i32_ptr(R, A) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
2517 6ddbc6e4 pbrook
#else /* TCG_TARGET_REG_BITS == 32 */
2518 ebecf363 Peter Maydell
#define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), \
2519 ebecf363 Peter Maydell
                                               TCGV_PTR_TO_NAT(A), \
2520 ebecf363 Peter Maydell
                                               TCGV_PTR_TO_NAT(B))
2521 ebecf363 Peter Maydell
#define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R),   \
2522 ebecf363 Peter Maydell
                                                 TCGV_PTR_TO_NAT(A), (B))
2523 ebecf363 Peter Maydell
#define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
2524 6ddbc6e4 pbrook
#endif /* TCG_TARGET_REG_BITS != 32 */