Revision 18fba28c
b/target-ppc/cpu.h | ||
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26 | 26 |
|
27 | 27 |
//#define USE_OPEN_FIRMWARE |
28 | 28 |
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/*** Sign extend constants ***/ |
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30 |
/* 8 to 32 bits */ |
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static inline int32_t s_ext8 (uint8_t value) |
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32 |
{ |
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int8_t *tmp = &value; |
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return *tmp; |
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} |
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|
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/* 16 to 32 bits */ |
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static inline int32_t s_ext16 (uint16_t value) |
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{ |
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int16_t *tmp = &value; |
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return *tmp; |
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} |
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46 | 29 |
#include "config.h" |
47 | 30 |
#include <setjmp.h> |
48 | 31 |
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b/target-ppc/helper.c | ||
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655 | 655 |
msr_dr = (value >> MSR_DR) & 0x01; |
656 | 656 |
msr_ri = (value >> MSR_RI) & 0x01; |
657 | 657 |
msr_le = (value >> MSR_LE) & 0x01; |
658 |
/* XXX: should enter PM state if msr_pow has been set */ |
|
658 | 659 |
} |
659 | 660 |
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#if defined (CONFIG_USER_ONLY) |
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660 | 662 |
void do_interrupt (CPUState *env) |
661 | 663 |
{ |
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#if defined (CONFIG_USER_ONLY)
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env->exception_index |= 0x100;
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664 |
env->exception_index = -1;
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}
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664 | 666 |
#else |
667 |
void do_interrupt (CPUState *env) |
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{ |
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665 | 669 |
uint32_t msr; |
666 |
int excp = env->exception_index;
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int excp; |
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667 | 671 |
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excp = env->exception_index; |
|
668 | 673 |
msr = _load_msr(env); |
669 | 674 |
#if defined (DEBUG_EXCEPTIONS) |
670 | 675 |
if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) |
... | ... | |
906 | 911 |
#else |
907 | 912 |
T0 = 0; |
908 | 913 |
#endif |
909 |
#endif |
|
910 | 914 |
env->exception_index = -1; |
911 | 915 |
} |
916 |
#endif /* !CONFIG_USER_ONLY */ |
b/target-ppc/op.c | ||
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147 | 147 |
} else { |
148 | 148 |
tmp = 0x02; |
149 | 149 |
} |
150 |
env->crf[0] = tmp; |
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RETURN(); |
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} |
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|
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PPC_OP(set_Rc0_ov) |
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{ |
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uint32_t tmp; |
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if (Ts0 < 0) { |
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tmp = 0x08; |
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} else if (Ts0 > 0) { |
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tmp = 0x04; |
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} else { |
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tmp = 0x02; |
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} |
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165 | 150 |
tmp |= xer_ov; |
166 | 151 |
env->crf[0] = tmp; |
167 | 152 |
RETURN(); |
... | ... | |
1062 | 1047 |
/* extend sign byte */ |
1063 | 1048 |
PPC_OP(extsb) |
1064 | 1049 |
{ |
1065 |
Ts0 = s_ext8(Ts0);
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1050 |
Ts0 = (int8_t)(Ts0);
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1066 | 1051 |
RETURN(); |
1067 | 1052 |
} |
1068 | 1053 |
|
1069 | 1054 |
/* extend sign half word */ |
1070 | 1055 |
PPC_OP(extsh) |
1071 | 1056 |
{ |
1072 |
Ts0 = s_ext16(Ts0);
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Ts0 = (int16_t)(Ts0);
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1073 | 1058 |
RETURN(); |
1074 | 1059 |
} |
1075 | 1060 |
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b/target-ppc/op_helper.c | ||
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377 | 377 |
|
378 | 378 |
void do_check_reservation (void) |
379 | 379 |
{ |
380 |
if ((env->reserve & ~(ICACHE_LINE_SIZE - 1)) == T0)
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|
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if ((env->reserve & ~0x03) == T0)
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381 | 381 |
env->reserve = -1; |
382 | 382 |
} |
383 | 383 |
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b/target-ppc/translate.c | ||
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179 | 179 |
|
180 | 180 |
typedef struct opcode_t { |
181 | 181 |
unsigned char opc1, opc2, opc3; |
182 |
#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */ |
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183 |
unsigned char pad[5]; |
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184 |
#else |
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unsigned char pad[1]; |
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#endif |
|
182 | 187 |
opc_handler_t handler; |
183 | 188 |
} opcode_t; |
184 | 189 |
|
... | ... | |
192 | 197 |
#define EXTRACT_SHELPER(name, shift, nb) \ |
193 | 198 |
static inline int32_t name (uint32_t opcode) \ |
194 | 199 |
{ \ |
195 |
return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \
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return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
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196 | 201 |
} |
197 | 202 |
|
198 | 203 |
/* Opcode part 1 */ |
... | ... | |
285 | 290 |
#endif |
286 | 291 |
|
287 | 292 |
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ |
288 |
OPCODES_SECTION static opcode_t opc_##name = { \
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OPCODES_SECTION opcode_t opc_##name = { \
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289 | 294 |
.opc1 = op1, \ |
290 | 295 |
.opc2 = op2, \ |
291 | 296 |
.opc3 = op3, \ |
297 |
.pad = { 0, }, \ |
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292 | 298 |
.handler = { \ |
293 | 299 |
.inval = invl, \ |
294 | 300 |
.type = _typ, \ |
... | ... | |
297 | 303 |
} |
298 | 304 |
|
299 | 305 |
#define GEN_OPCODE_MARK(name) \ |
300 |
OPCODES_SECTION static opcode_t opc_##name = { \
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306 |
OPCODES_SECTION opcode_t opc_##name = { \
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301 | 307 |
.opc1 = 0xFF, \ |
302 | 308 |
.opc2 = 0xFF, \ |
303 | 309 |
.opc3 = 0xFF, \ |
310 |
.pad = { 0, }, \ |
|
304 | 311 |
.handler = { \ |
305 | 312 |
.inval = 0x00000000, \ |
306 | 313 |
.type = 0x00, \ |
... | ... | |
361 | 368 |
gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
362 | 369 |
gen_op_##name(); \ |
363 | 370 |
if (Rc(ctx->opcode) != 0) \ |
364 |
gen_op_set_Rc0_ov(); \
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371 |
gen_op_set_Rc0(); \
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365 | 372 |
gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
366 | 373 |
} |
367 | 374 |
|
... | ... | |
380 | 387 |
gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
381 | 388 |
gen_op_##name(); \ |
382 | 389 |
if (Rc(ctx->opcode) != 0) \ |
383 |
gen_op_set_Rc0_ov(); \
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390 |
gen_op_set_Rc0(); \
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384 | 391 |
gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
385 | 392 |
} |
386 | 393 |
|
... | ... | |
1558 | 1565 |
gen_op_dec_ctr(); |
1559 | 1566 |
switch(type) { |
1560 | 1567 |
case BCOND_IM: |
1561 |
li = s_ext16(BD(ctx->opcode));
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1568 |
li = (int32_t)((int16_t)(BD(ctx->opcode)));
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1562 | 1569 |
if (AA(ctx->opcode) == 0) { |
1563 | 1570 |
target = ctx->nip + li - 4; |
1564 | 1571 |
} else { |
... | ... | |
2160 | 2167 |
case DECR: |
2161 | 2168 |
gen_op_store_decr(); |
2162 | 2169 |
break; |
2163 |
#if 0 |
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2164 |
case HID0: |
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2165 |
gen_op_store_hid0(); |
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2166 |
break; |
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2167 |
#endif |
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2168 | 2170 |
default: |
2169 | 2171 |
gen_op_store_spr(sprn); |
2170 | 2172 |
break; |
... | ... | |
2894 | 2896 |
|
2895 | 2897 |
static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr) |
2896 | 2898 |
{ |
2897 |
opcode_t *opc; |
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2899 |
opcode_t *opc, *start, *end;
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2898 | 2900 |
int i, flags; |
2899 | 2901 |
|
2900 | 2902 |
fill_new_table(ppc_opcodes, 0x40); |
... | ... | |
2906 | 2908 |
} |
2907 | 2909 |
} |
2908 | 2910 |
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2909 |
for (opc = &opc_start + 1; opc != &opc_end; opc++) { |
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2911 |
if (&opc_start < &opc_end) { |
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2912 |
start = &opc_start; |
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2913 |
end = &opc_end; |
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2914 |
} else { |
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2915 |
start = &opc_end; |
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2916 |
end = &opc_start; |
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2917 |
} |
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2918 |
for (opc = start + 1; opc != end; opc++) { |
|
2910 | 2919 |
if ((opc->handler.type & flags) != 0) |
2911 | 2920 |
if (register_insn(ppc_opcodes, opc) < 0) { |
2912 | 2921 |
printf("*** ERROR initializing PPC instruction " |
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