root / hw / vga_int.h @ 192c7bd9
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1 | 798b0c25 | bellard | /*
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2 | 798b0c25 | bellard | * QEMU internal VGA defines.
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3 | 798b0c25 | bellard | *
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4 | 798b0c25 | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 798b0c25 | bellard | *
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6 | 798b0c25 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 798b0c25 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 798b0c25 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 798b0c25 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 798b0c25 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 798b0c25 | bellard | * furnished to do so, subject to the following conditions:
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12 | 798b0c25 | bellard | *
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13 | 798b0c25 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 798b0c25 | bellard | * all copies or substantial portions of the Software.
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15 | 798b0c25 | bellard | *
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16 | 798b0c25 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 798b0c25 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 798b0c25 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 798b0c25 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 798b0c25 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 798b0c25 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 798b0c25 | bellard | * THE SOFTWARE.
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23 | 798b0c25 | bellard | */
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24 | 798b0c25 | bellard | #define MSR_COLOR_EMULATION 0x01 |
25 | 798b0c25 | bellard | #define MSR_PAGE_SELECT 0x20 |
26 | 798b0c25 | bellard | |
27 | 798b0c25 | bellard | #define ST01_V_RETRACE 0x08 |
28 | 798b0c25 | bellard | #define ST01_DISP_ENABLE 0x01 |
29 | 798b0c25 | bellard | |
30 | 798b0c25 | bellard | /* bochs VBE support */
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31 | 798b0c25 | bellard | #define CONFIG_BOCHS_VBE
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32 | 798b0c25 | bellard | |
33 | 798b0c25 | bellard | #define VBE_DISPI_MAX_XRES 1024 |
34 | 798b0c25 | bellard | #define VBE_DISPI_MAX_YRES 768 |
35 | 798b0c25 | bellard | |
36 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_ID 0x0 |
37 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_XRES 0x1 |
38 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_YRES 0x2 |
39 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_BPP 0x3 |
40 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_ENABLE 0x4 |
41 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_BANK 0x5 |
42 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 |
43 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 |
44 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_X_OFFSET 0x8 |
45 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_Y_OFFSET 0x9 |
46 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_NB 0xa |
47 | 798b0c25 | bellard | |
48 | 798b0c25 | bellard | #define VBE_DISPI_ID0 0xB0C0 |
49 | 798b0c25 | bellard | #define VBE_DISPI_ID1 0xB0C1 |
50 | 798b0c25 | bellard | #define VBE_DISPI_ID2 0xB0C2 |
51 | 798b0c25 | bellard | |
52 | 798b0c25 | bellard | #define VBE_DISPI_DISABLED 0x00 |
53 | 798b0c25 | bellard | #define VBE_DISPI_ENABLED 0x01 |
54 | 798b0c25 | bellard | #define VBE_DISPI_LFB_ENABLED 0x40 |
55 | 798b0c25 | bellard | #define VBE_DISPI_NOCLEARMEM 0x80 |
56 | 798b0c25 | bellard | |
57 | 798b0c25 | bellard | #define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000 |
58 | 798b0c25 | bellard | |
59 | 798b0c25 | bellard | #ifdef CONFIG_BOCHS_VBE
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60 | 4e3e9d0b | bellard | |
61 | 4e3e9d0b | bellard | #define VGA_STATE_COMMON_BOCHS_VBE \
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62 | 4e3e9d0b | bellard | uint16_t vbe_index; \ |
63 | 4e3e9d0b | bellard | uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \ |
64 | 4e3e9d0b | bellard | uint32_t vbe_start_addr; \ |
65 | 4e3e9d0b | bellard | uint32_t vbe_line_offset; \ |
66 | 798b0c25 | bellard | uint32_t vbe_bank_mask; |
67 | 4e3e9d0b | bellard | |
68 | 4e3e9d0b | bellard | #else
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69 | 4e3e9d0b | bellard | |
70 | 4e3e9d0b | bellard | #define VGA_STATE_COMMON_BOCHS_VBE
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71 | 4e3e9d0b | bellard | |
72 | 4e3e9d0b | bellard | #endif /* !CONFIG_BOCHS_VBE */ |
73 | 4e3e9d0b | bellard | |
74 | 798b0c25 | bellard | #define CH_ATTR_SIZE (160 * 100) |
75 | a8aa669b | bellard | #define VGA_MAX_HEIGHT 1024 |
76 | 4e3e9d0b | bellard | |
77 | 4e3e9d0b | bellard | #define VGA_STATE_COMMON \
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78 | 4e3e9d0b | bellard | uint8_t *vram_ptr; \ |
79 | 4e3e9d0b | bellard | unsigned long vram_offset; \ |
80 | 4e3e9d0b | bellard | unsigned int vram_size; \ |
81 | 4e3e9d0b | bellard | uint32_t latch; \ |
82 | 4e3e9d0b | bellard | uint8_t sr_index; \ |
83 | 4e3e9d0b | bellard | uint8_t sr[256]; \
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84 | 4e3e9d0b | bellard | uint8_t gr_index; \ |
85 | 4e3e9d0b | bellard | uint8_t gr[256]; \
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86 | 4e3e9d0b | bellard | uint8_t ar_index; \ |
87 | 4e3e9d0b | bellard | uint8_t ar[21]; \
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88 | 4e3e9d0b | bellard | int ar_flip_flop; \
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89 | 4e3e9d0b | bellard | uint8_t cr_index; \ |
90 | 4e3e9d0b | bellard | uint8_t cr[256]; /* CRT registers */ \ |
91 | 4e3e9d0b | bellard | uint8_t msr; /* Misc Output Register */ \
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92 | 4e3e9d0b | bellard | uint8_t fcr; /* Feature Control Register */ \
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93 | 4e3e9d0b | bellard | uint8_t st00; /* status 0 */ \
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94 | 4e3e9d0b | bellard | uint8_t st01; /* status 1 */ \
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95 | 4e3e9d0b | bellard | uint8_t dac_state; \ |
96 | 4e3e9d0b | bellard | uint8_t dac_sub_index; \ |
97 | 4e3e9d0b | bellard | uint8_t dac_read_index; \ |
98 | 4e3e9d0b | bellard | uint8_t dac_write_index; \ |
99 | 4e3e9d0b | bellard | uint8_t dac_cache[3]; /* used when writing */ \ |
100 | 4e3e9d0b | bellard | uint8_t palette[768]; \
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101 | 4e3e9d0b | bellard | int32_t bank_offset; \ |
102 | 4e3e9d0b | bellard | int (*get_bpp)(struct VGAState *s); \ |
103 | 4e3e9d0b | bellard | void (*get_offsets)(struct VGAState *s, \ |
104 | 4e3e9d0b | bellard | uint32_t *pline_offset, \ |
105 | 4e3e9d0b | bellard | uint32_t *pstart_addr); \ |
106 | a130a41e | bellard | void (*get_resolution)(struct VGAState *s, \ |
107 | a130a41e | bellard | int *pwidth, \
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108 | a130a41e | bellard | int *pheight); \
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109 | 4e3e9d0b | bellard | VGA_STATE_COMMON_BOCHS_VBE \ |
110 | 4e3e9d0b | bellard | /* display refresh support */ \
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111 | 4e3e9d0b | bellard | DisplayState *ds; \ |
112 | 4e3e9d0b | bellard | uint32_t font_offsets[2]; \
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113 | 4e3e9d0b | bellard | int graphic_mode; \
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114 | 4e3e9d0b | bellard | uint8_t shift_control; \ |
115 | 4e3e9d0b | bellard | uint8_t double_scan; \ |
116 | 4e3e9d0b | bellard | uint32_t line_offset; \ |
117 | 4e3e9d0b | bellard | uint32_t line_compare; \ |
118 | 4e3e9d0b | bellard | uint32_t start_addr; \ |
119 | 546fa6ab | bellard | uint32_t plane_updated; \ |
120 | 4e3e9d0b | bellard | uint8_t last_cw, last_ch; \ |
121 | 4e3e9d0b | bellard | uint32_t last_width, last_height; /* in chars or pixels */ \
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122 | 4e3e9d0b | bellard | uint32_t last_scr_width, last_scr_height; /* in pixels */ \
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123 | 4e3e9d0b | bellard | uint8_t cursor_start, cursor_end; \ |
124 | 4e3e9d0b | bellard | uint32_t cursor_offset; \ |
125 | 4e3e9d0b | bellard | unsigned int (*rgb_to_pixel)(unsigned int r, \ |
126 | 4e3e9d0b | bellard | unsigned int g, unsigned b); \ |
127 | a8aa669b | bellard | /* hardware mouse cursor support */ \
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128 | a8aa669b | bellard | uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \
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129 | a8aa669b | bellard | void (*cursor_invalidate)(struct VGAState *s); \ |
130 | a8aa669b | bellard | void (*cursor_draw_line)(struct VGAState *s, uint8_t *d, int y); \ |
131 | 4e3e9d0b | bellard | /* tell for each page if it has been updated since the last time */ \
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132 | 4e3e9d0b | bellard | uint32_t last_palette[256]; \
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133 | 798b0c25 | bellard | uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
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134 | 4e3e9d0b | bellard | |
135 | 4e3e9d0b | bellard | |
136 | 4e3e9d0b | bellard | typedef struct VGAState { |
137 | 4e3e9d0b | bellard | VGA_STATE_COMMON |
138 | 798b0c25 | bellard | } VGAState; |
139 | 798b0c25 | bellard | |
140 | a8aa669b | bellard | static inline int c6_to_8(int v) |
141 | a8aa669b | bellard | { |
142 | a8aa669b | bellard | int b;
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143 | a8aa669b | bellard | v &= 0x3f;
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144 | a8aa669b | bellard | b = v & 1;
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145 | a8aa669b | bellard | return (v << 2) | (b << 1) | b; |
146 | a8aa669b | bellard | } |
147 | a8aa669b | bellard | |
148 | 798b0c25 | bellard | void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
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149 | 798b0c25 | bellard | unsigned long vga_ram_offset, int vga_ram_size); |
150 | 798b0c25 | bellard | uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
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151 | 798b0c25 | bellard | void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val); |
152 | a8aa669b | bellard | void vga_invalidate_scanlines(VGAState *s, int y1, int y2); |
153 | a8aa669b | bellard | |
154 | a8aa669b | bellard | void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1, |
155 | a8aa669b | bellard | int poffset, int w, |
156 | a8aa669b | bellard | unsigned int color0, unsigned int color1, |
157 | a8aa669b | bellard | unsigned int color_xor); |
158 | a8aa669b | bellard | void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1, |
159 | a8aa669b | bellard | int poffset, int w, |
160 | a8aa669b | bellard | unsigned int color0, unsigned int color1, |
161 | a8aa669b | bellard | unsigned int color_xor); |
162 | a8aa669b | bellard | void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1, |
163 | a8aa669b | bellard | int poffset, int w, |
164 | a8aa669b | bellard | unsigned int color0, unsigned int color1, |
165 | a8aa669b | bellard | unsigned int color_xor); |
166 | 798b0c25 | bellard | |
167 | 798b0c25 | bellard | extern const uint8_t sr_mask[8]; |
168 | 798b0c25 | bellard | extern const uint8_t gr_mask[16]; |