Revision 19a77215 gdbstub.c
| b/gdbstub.c | ||
|---|---|---|
| 1295 | 1295 |
switch (n) {
|
| 1296 | 1296 |
case 32: /* PPC */ |
| 1297 | 1297 |
GET_REG32(env->ppc); |
| 1298 |
break; |
|
| 1299 | 1298 |
|
| 1300 | 1299 |
case 33: /* NPC */ |
| 1301 | 1300 |
GET_REG32(env->npc); |
| 1302 |
break; |
|
| 1303 | 1301 |
|
| 1304 | 1302 |
case 34: /* SR */ |
| 1305 | 1303 |
GET_REG32(env->sr); |
| 1306 |
break; |
|
| 1307 | 1304 |
|
| 1308 | 1305 |
default: |
| 1309 | 1306 |
break; |
| ... | ... | |
| 1516 | 1513 |
switch (n) {
|
| 1517 | 1514 |
case 16: |
| 1518 | 1515 |
GET_REG8(env->pregs[n - 16]); |
| 1519 |
break; |
|
| 1520 | 1516 |
case 17: |
| 1521 | 1517 |
GET_REG8(env->pregs[n - 16]); |
| 1522 |
break; |
|
| 1523 | 1518 |
case 20: |
| 1524 | 1519 |
case 21: |
| 1525 | 1520 |
GET_REG16(env->pregs[n - 16]); |
| 1526 |
break; |
|
| 1527 | 1521 |
default: |
| 1528 | 1522 |
if (n >= 23) {
|
| 1529 | 1523 |
GET_REG32(env->pregs[n - 16]); |
| ... | ... | |
| 1693 | 1687 |
cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr); |
| 1694 | 1688 |
val = deposit64(env->psw.mask, 44, 2, cc_op); |
| 1695 | 1689 |
GET_REGL(val); |
| 1696 |
break; |
|
| 1697 | 1690 |
case S390_PSWA_REGNUM: |
| 1698 | 1691 |
GET_REGL(env->psw.addr); |
| 1699 |
break; |
|
| 1700 | 1692 |
case S390_R0_REGNUM ... S390_R15_REGNUM: |
| 1701 | 1693 |
GET_REGL(env->regs[n-S390_R0_REGNUM]); |
| 1702 |
break; |
|
| 1703 | 1694 |
case S390_A0_REGNUM ... S390_A15_REGNUM: |
| 1704 | 1695 |
GET_REG32(env->aregs[n-S390_A0_REGNUM]); |
| 1705 |
break; |
|
| 1706 | 1696 |
case S390_FPC_REGNUM: |
| 1707 | 1697 |
GET_REG32(env->fpc); |
| 1708 |
break; |
|
| 1709 | 1698 |
case S390_F0_REGNUM ... S390_F15_REGNUM: |
| 1710 | 1699 |
GET_REG64(env->fregs[n-S390_F0_REGNUM].ll); |
| 1711 |
break; |
|
| 1712 | 1700 |
} |
| 1713 | 1701 |
|
| 1714 | 1702 |
return 0; |
| ... | ... | |
| 1762 | 1750 |
switch (n) {
|
| 1763 | 1751 |
case 32: |
| 1764 | 1752 |
GET_REG32(env->pc); |
| 1765 |
break; |
|
| 1766 | 1753 |
/* FIXME: put in right exception ID */ |
| 1767 | 1754 |
case 33: |
| 1768 | 1755 |
GET_REG32(0); |
| 1769 |
break; |
|
| 1770 | 1756 |
case 34: |
| 1771 | 1757 |
GET_REG32(env->eba); |
| 1772 |
break; |
|
| 1773 | 1758 |
case 35: |
| 1774 | 1759 |
GET_REG32(env->deba); |
| 1775 |
break; |
|
| 1776 | 1760 |
case 36: |
| 1777 | 1761 |
GET_REG32(env->ie); |
| 1778 |
break; |
|
| 1779 | 1762 |
case 37: |
| 1780 | 1763 |
GET_REG32(lm32_pic_get_im(env->pic_state)); |
| 1781 |
break; |
|
| 1782 | 1764 |
case 38: |
| 1783 | 1765 |
GET_REG32(lm32_pic_get_ip(env->pic_state)); |
| 1784 |
break; |
|
| 1785 | 1766 |
} |
| 1786 | 1767 |
} |
| 1787 | 1768 |
return 0; |
| ... | ... | |
| 1844 | 1825 |
switch (reg->type) {
|
| 1845 | 1826 |
case 9: /*pc*/ |
| 1846 | 1827 |
GET_REG32(env->pc); |
| 1847 |
break; |
|
| 1848 | 1828 |
|
| 1849 | 1829 |
case 1: /*ar*/ |
| 1850 | 1830 |
xtensa_sync_phys_from_window(env); |
| 1851 | 1831 |
GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]); |
| 1852 |
break; |
|
| 1853 | 1832 |
|
| 1854 | 1833 |
case 2: /*SR*/ |
| 1855 | 1834 |
GET_REG32(env->sregs[reg->targno & 0xff]); |
| 1856 |
break; |
|
| 1857 | 1835 |
|
| 1858 | 1836 |
case 3: /*UR*/ |
| 1859 | 1837 |
GET_REG32(env->uregs[reg->targno & 0xff]); |
| 1860 |
break; |
|
| 1861 | 1838 |
|
| 1862 | 1839 |
case 4: /*f*/ |
| 1863 | 1840 |
GET_REG32(float32_val(env->fregs[reg->targno & 0x0f])); |
| 1864 |
break; |
|
| 1865 | 1841 |
|
| 1866 | 1842 |
case 8: /*a*/ |
| 1867 | 1843 |
GET_REG32(env->regs[reg->targno & 0x0f]); |
| 1868 |
break; |
|
| 1869 | 1844 |
|
| 1870 | 1845 |
default: |
| 1871 | 1846 |
qemu_log("%s from reg %d of unsupported type %d\n",
|
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