Revision 19e6c4b8 target-i386/translate.c
| b/target-i386/translate.c | ||
|---|---|---|
| 1288 | 1288 |
#endif |
| 1289 | 1289 |
}; |
| 1290 | 1290 |
|
| 1291 |
static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
|
|
| 1292 |
gen_op_fadd_ST0_FT0,
|
|
| 1293 |
gen_op_fmul_ST0_FT0,
|
|
| 1294 |
gen_op_fcom_ST0_FT0,
|
|
| 1295 |
gen_op_fcom_ST0_FT0,
|
|
| 1296 |
gen_op_fsub_ST0_FT0,
|
|
| 1297 |
gen_op_fsubr_ST0_FT0,
|
|
| 1298 |
gen_op_fdiv_ST0_FT0,
|
|
| 1299 |
gen_op_fdivr_ST0_FT0,
|
|
| 1291 |
static void *helper_fp_arith_ST0_FT0[8] = {
|
|
| 1292 |
helper_fadd_ST0_FT0,
|
|
| 1293 |
helper_fmul_ST0_FT0,
|
|
| 1294 |
helper_fcom_ST0_FT0,
|
|
| 1295 |
helper_fcom_ST0_FT0,
|
|
| 1296 |
helper_fsub_ST0_FT0,
|
|
| 1297 |
helper_fsubr_ST0_FT0,
|
|
| 1298 |
helper_fdiv_ST0_FT0,
|
|
| 1299 |
helper_fdivr_ST0_FT0,
|
|
| 1300 | 1300 |
}; |
| 1301 | 1301 |
|
| 1302 | 1302 |
/* NOTE the exception in "r" op ordering */ |
| 1303 |
static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
|
|
| 1304 |
gen_op_fadd_STN_ST0,
|
|
| 1305 |
gen_op_fmul_STN_ST0,
|
|
| 1303 |
static void *helper_fp_arith_STN_ST0[8] = {
|
|
| 1304 |
helper_fadd_STN_ST0,
|
|
| 1305 |
helper_fmul_STN_ST0,
|
|
| 1306 | 1306 |
NULL, |
| 1307 | 1307 |
NULL, |
| 1308 |
gen_op_fsubr_STN_ST0,
|
|
| 1309 |
gen_op_fsub_STN_ST0,
|
|
| 1310 |
gen_op_fdivr_STN_ST0,
|
|
| 1311 |
gen_op_fdiv_STN_ST0,
|
|
| 1308 |
helper_fsubr_STN_ST0,
|
|
| 1309 |
helper_fsub_STN_ST0,
|
|
| 1310 |
helper_fdivr_STN_ST0,
|
|
| 1311 |
helper_fdiv_STN_ST0,
|
|
| 1312 | 1312 |
}; |
| 1313 | 1313 |
|
| 1314 | 1314 |
/* if d == OR_TMP0, it means memory operand (address in A0) */ |
| ... | ... | |
| 3014 | 3014 |
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
| 3015 | 3015 |
offsetof(CPUX86State,xmm_regs[rm])); |
| 3016 | 3016 |
tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2, cpu_ptr0); |
| 3017 |
tcg_gen_extu_i32_i64(cpu_T[0], cpu_tmp2);
|
|
| 3017 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2);
|
|
| 3018 | 3018 |
gen_op_mov_reg_T0(OT_LONG, reg); |
| 3019 | 3019 |
break; |
| 3020 | 3020 |
case 0x150: /* movmskpd */ |
| ... | ... | |
| 3022 | 3022 |
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
| 3023 | 3023 |
offsetof(CPUX86State,xmm_regs[rm])); |
| 3024 | 3024 |
tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2, cpu_ptr0); |
| 3025 |
tcg_gen_extu_i32_i64(cpu_T[0], cpu_tmp2);
|
|
| 3025 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2);
|
|
| 3026 | 3026 |
gen_op_mov_reg_T0(OT_LONG, reg); |
| 3027 | 3027 |
break; |
| 3028 | 3028 |
case 0x02a: /* cvtpi2ps */ |
| ... | ... | |
| 3113 | 3113 |
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
| 3114 | 3114 |
if (ot == OT_LONG) {
|
| 3115 | 3115 |
tcg_gen_helper_1_1(sse_op2, cpu_tmp2, cpu_ptr0); |
| 3116 |
tcg_gen_extu_i32_i64(cpu_T[0], cpu_tmp2);
|
|
| 3116 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2);
|
|
| 3117 | 3117 |
} else {
|
| 3118 | 3118 |
tcg_gen_helper_1_1(sse_op2, cpu_T[0], cpu_ptr0); |
| 3119 | 3119 |
} |
| ... | ... | |
| 3301 | 3301 |
} |
| 3302 | 3302 |
} |
| 3303 | 3303 |
|
| 3304 |
|
|
| 3305 | 3304 |
/* convert one instruction. s->is_jmp is set if the translation must |
| 3306 | 3305 |
be stopped. Return the next pc value */ |
| 3307 | 3306 |
static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) |
| ... | ... | |
| 4536 | 4535 |
|
| 4537 | 4536 |
switch(op >> 4) {
|
| 4538 | 4537 |
case 0: |
| 4539 |
gen_op_flds_FT0_A0(); |
|
| 4538 |
gen_op_ld_T0_A0(OT_LONG); |
|
| 4539 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4540 |
tcg_gen_helper_0_1(helper_flds_FT0, cpu_tmp2); |
|
| 4540 | 4541 |
break; |
| 4541 | 4542 |
case 1: |
| 4542 |
gen_op_fildl_FT0_A0(); |
|
| 4543 |
gen_op_ld_T0_A0(OT_LONG); |
|
| 4544 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4545 |
tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2); |
|
| 4543 | 4546 |
break; |
| 4544 | 4547 |
case 2: |
| 4545 |
gen_op_fldl_FT0_A0(); |
|
| 4548 |
tcg_gen_qemu_ld64(cpu_tmp1, cpu_A0, |
|
| 4549 |
(s->mem_index >> 2) - 1); |
|
| 4550 |
tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1); |
|
| 4546 | 4551 |
break; |
| 4547 | 4552 |
case 3: |
| 4548 | 4553 |
default: |
| 4549 |
gen_op_fild_FT0_A0(); |
|
| 4554 |
gen_op_ld_T0_A0(OT_WORD); |
|
| 4555 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4556 |
tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2); |
|
| 4550 | 4557 |
break; |
| 4551 | 4558 |
} |
| 4552 | 4559 |
|
| 4553 |
gen_op_fp_arith_ST0_FT0[op1]();
|
|
| 4560 |
tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
|
|
| 4554 | 4561 |
if (op1 == 3) {
|
| 4555 | 4562 |
/* fcomp needs pop */ |
| 4556 |
gen_op_fpop();
|
|
| 4563 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4557 | 4564 |
} |
| 4558 | 4565 |
} |
| 4559 | 4566 |
break; |
| ... | ... | |
| 4567 | 4574 |
case 0: |
| 4568 | 4575 |
switch(op >> 4) {
|
| 4569 | 4576 |
case 0: |
| 4570 |
gen_op_flds_ST0_A0(); |
|
| 4577 |
gen_op_ld_T0_A0(OT_LONG); |
|
| 4578 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4579 |
tcg_gen_helper_0_1(helper_flds_ST0, cpu_tmp2); |
|
| 4571 | 4580 |
break; |
| 4572 | 4581 |
case 1: |
| 4573 |
gen_op_fildl_ST0_A0(); |
|
| 4582 |
gen_op_ld_T0_A0(OT_LONG); |
|
| 4583 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4584 |
tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2); |
|
| 4574 | 4585 |
break; |
| 4575 | 4586 |
case 2: |
| 4576 |
gen_op_fldl_ST0_A0(); |
|
| 4587 |
tcg_gen_qemu_ld64(cpu_tmp1, cpu_A0, |
|
| 4588 |
(s->mem_index >> 2) - 1); |
|
| 4589 |
tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1); |
|
| 4577 | 4590 |
break; |
| 4578 | 4591 |
case 3: |
| 4579 | 4592 |
default: |
| 4580 |
gen_op_fild_ST0_A0(); |
|
| 4593 |
gen_op_ld_T0_A0(OT_WORD); |
|
| 4594 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4595 |
tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2); |
|
| 4581 | 4596 |
break; |
| 4582 | 4597 |
} |
| 4583 | 4598 |
break; |
| 4584 | 4599 |
case 1: |
| 4600 |
/* XXX: the corresponding CPUID bit must be tested ! */ |
|
| 4585 | 4601 |
switch(op >> 4) {
|
| 4586 | 4602 |
case 1: |
| 4587 |
gen_op_fisttl_ST0_A0(); |
|
| 4603 |
tcg_gen_helper_1_0(helper_fisttl_ST0, cpu_tmp2); |
|
| 4604 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4605 |
gen_op_st_T0_A0(OT_LONG); |
|
| 4588 | 4606 |
break; |
| 4589 | 4607 |
case 2: |
| 4590 |
gen_op_fisttll_ST0_A0(); |
|
| 4608 |
tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1); |
|
| 4609 |
tcg_gen_qemu_st64(cpu_tmp1, cpu_A0, |
|
| 4610 |
(s->mem_index >> 2) - 1); |
|
| 4591 | 4611 |
break; |
| 4592 | 4612 |
case 3: |
| 4593 | 4613 |
default: |
| 4594 |
gen_op_fistt_ST0_A0(); |
|
| 4614 |
tcg_gen_helper_1_0(helper_fistt_ST0, cpu_tmp2); |
|
| 4615 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4616 |
gen_op_st_T0_A0(OT_WORD); |
|
| 4617 |
break; |
|
| 4595 | 4618 |
} |
| 4596 |
gen_op_fpop();
|
|
| 4619 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4597 | 4620 |
break; |
| 4598 | 4621 |
default: |
| 4599 | 4622 |
switch(op >> 4) {
|
| 4600 | 4623 |
case 0: |
| 4601 |
gen_op_fsts_ST0_A0(); |
|
| 4624 |
tcg_gen_helper_1_0(helper_fsts_ST0, cpu_tmp2); |
|
| 4625 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4626 |
gen_op_st_T0_A0(OT_LONG); |
|
| 4602 | 4627 |
break; |
| 4603 | 4628 |
case 1: |
| 4604 |
gen_op_fistl_ST0_A0(); |
|
| 4629 |
tcg_gen_helper_1_0(helper_fistl_ST0, cpu_tmp2); |
|
| 4630 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4631 |
gen_op_st_T0_A0(OT_LONG); |
|
| 4605 | 4632 |
break; |
| 4606 | 4633 |
case 2: |
| 4607 |
gen_op_fstl_ST0_A0(); |
|
| 4634 |
tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1); |
|
| 4635 |
tcg_gen_qemu_st64(cpu_tmp1, cpu_A0, |
|
| 4636 |
(s->mem_index >> 2) - 1); |
|
| 4608 | 4637 |
break; |
| 4609 | 4638 |
case 3: |
| 4610 | 4639 |
default: |
| 4611 |
gen_op_fist_ST0_A0(); |
|
| 4640 |
tcg_gen_helper_1_0(helper_fist_ST0, cpu_tmp2); |
|
| 4641 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4642 |
gen_op_st_T0_A0(OT_WORD); |
|
| 4612 | 4643 |
break; |
| 4613 | 4644 |
} |
| 4614 | 4645 |
if ((op & 7) == 3) |
| 4615 |
gen_op_fpop();
|
|
| 4646 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4616 | 4647 |
break; |
| 4617 | 4648 |
} |
| 4618 | 4649 |
break; |
| 4619 | 4650 |
case 0x0c: /* fldenv mem */ |
| 4620 |
gen_op_fldenv_A0(s->dflag); |
|
| 4651 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 4652 |
gen_op_set_cc_op(s->cc_op); |
|
| 4653 |
gen_jmp_im(pc_start - s->cs_base); |
|
| 4654 |
tcg_gen_helper_0_2(helper_fldenv, |
|
| 4655 |
cpu_A0, tcg_const_i32(s->dflag)); |
|
| 4621 | 4656 |
break; |
| 4622 | 4657 |
case 0x0d: /* fldcw mem */ |
| 4623 |
gen_op_fldcw_A0(); |
|
| 4658 |
gen_op_ld_T0_A0(OT_WORD + s->mem_index); |
|
| 4659 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4660 |
tcg_gen_helper_0_1(helper_fldcw, cpu_tmp2); |
|
| 4624 | 4661 |
break; |
| 4625 | 4662 |
case 0x0e: /* fnstenv mem */ |
| 4626 |
gen_op_fnstenv_A0(s->dflag); |
|
| 4663 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 4664 |
gen_op_set_cc_op(s->cc_op); |
|
| 4665 |
gen_jmp_im(pc_start - s->cs_base); |
|
| 4666 |
tcg_gen_helper_0_2(helper_fstenv, |
|
| 4667 |
cpu_A0, tcg_const_i32(s->dflag)); |
|
| 4627 | 4668 |
break; |
| 4628 | 4669 |
case 0x0f: /* fnstcw mem */ |
| 4629 |
gen_op_fnstcw_A0(); |
|
| 4670 |
tcg_gen_helper_1_0(helper_fnstcw, cpu_tmp2); |
|
| 4671 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4672 |
gen_op_st_T0_A0(OT_WORD + s->mem_index); |
|
| 4630 | 4673 |
break; |
| 4631 | 4674 |
case 0x1d: /* fldt mem */ |
| 4632 |
gen_op_fldt_ST0_A0(); |
|
| 4675 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 4676 |
gen_op_set_cc_op(s->cc_op); |
|
| 4677 |
gen_jmp_im(pc_start - s->cs_base); |
|
| 4678 |
tcg_gen_helper_0_1(helper_fldt_ST0, cpu_A0); |
|
| 4633 | 4679 |
break; |
| 4634 | 4680 |
case 0x1f: /* fstpt mem */ |
| 4635 |
gen_op_fstt_ST0_A0(); |
|
| 4636 |
gen_op_fpop(); |
|
| 4681 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 4682 |
gen_op_set_cc_op(s->cc_op); |
|
| 4683 |
gen_jmp_im(pc_start - s->cs_base); |
|
| 4684 |
tcg_gen_helper_0_1(helper_fstt_ST0, cpu_A0); |
|
| 4685 |
tcg_gen_helper_0_0(helper_fpop); |
|
| 4637 | 4686 |
break; |
| 4638 | 4687 |
case 0x2c: /* frstor mem */ |
| 4639 |
gen_op_frstor_A0(s->dflag); |
|
| 4688 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 4689 |
gen_op_set_cc_op(s->cc_op); |
|
| 4690 |
gen_jmp_im(pc_start - s->cs_base); |
|
| 4691 |
tcg_gen_helper_0_2(helper_frstor, |
|
| 4692 |
cpu_A0, tcg_const_i32(s->dflag)); |
|
| 4640 | 4693 |
break; |
| 4641 | 4694 |
case 0x2e: /* fnsave mem */ |
| 4642 |
gen_op_fnsave_A0(s->dflag); |
|
| 4695 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 4696 |
gen_op_set_cc_op(s->cc_op); |
|
| 4697 |
gen_jmp_im(pc_start - s->cs_base); |
|
| 4698 |
tcg_gen_helper_0_2(helper_fsave, |
|
| 4699 |
cpu_A0, tcg_const_i32(s->dflag)); |
|
| 4643 | 4700 |
break; |
| 4644 | 4701 |
case 0x2f: /* fnstsw mem */ |
| 4645 |
gen_op_fnstsw_A0(); |
|
| 4702 |
tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2); |
|
| 4703 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4704 |
gen_op_st_T0_A0(OT_WORD + s->mem_index); |
|
| 4646 | 4705 |
break; |
| 4647 | 4706 |
case 0x3c: /* fbld */ |
| 4648 |
gen_op_fbld_ST0_A0(); |
|
| 4707 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 4708 |
gen_op_set_cc_op(s->cc_op); |
|
| 4709 |
gen_jmp_im(pc_start - s->cs_base); |
|
| 4710 |
tcg_gen_helper_0_1(helper_fbld_ST0, cpu_A0); |
|
| 4649 | 4711 |
break; |
| 4650 | 4712 |
case 0x3e: /* fbstp */ |
| 4651 |
gen_op_fbst_ST0_A0(); |
|
| 4652 |
gen_op_fpop(); |
|
| 4713 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 4714 |
gen_op_set_cc_op(s->cc_op); |
|
| 4715 |
gen_jmp_im(pc_start - s->cs_base); |
|
| 4716 |
tcg_gen_helper_0_1(helper_fbst_ST0, cpu_A0); |
|
| 4717 |
tcg_gen_helper_0_0(helper_fpop); |
|
| 4653 | 4718 |
break; |
| 4654 | 4719 |
case 0x3d: /* fildll */ |
| 4655 |
gen_op_fildll_ST0_A0(); |
|
| 4720 |
tcg_gen_qemu_ld64(cpu_tmp1, cpu_A0, |
|
| 4721 |
(s->mem_index >> 2) - 1); |
|
| 4722 |
tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1); |
|
| 4656 | 4723 |
break; |
| 4657 | 4724 |
case 0x3f: /* fistpll */ |
| 4658 |
gen_op_fistll_ST0_A0(); |
|
| 4659 |
gen_op_fpop(); |
|
| 4725 |
tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1); |
|
| 4726 |
tcg_gen_qemu_st64(cpu_tmp1, cpu_A0, |
|
| 4727 |
(s->mem_index >> 2) - 1); |
|
| 4728 |
tcg_gen_helper_0_0(helper_fpop); |
|
| 4660 | 4729 |
break; |
| 4661 | 4730 |
default: |
| 4662 | 4731 |
goto illegal_op; |
| ... | ... | |
| 4667 | 4736 |
|
| 4668 | 4737 |
switch(op) {
|
| 4669 | 4738 |
case 0x08: /* fld sti */ |
| 4670 |
gen_op_fpush();
|
|
| 4671 |
gen_op_fmov_ST0_STN((opreg + 1) & 7);
|
|
| 4739 |
tcg_gen_helper_0_0(helper_fpush);
|
|
| 4740 |
tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32((opreg + 1) & 7));
|
|
| 4672 | 4741 |
break; |
| 4673 | 4742 |
case 0x09: /* fxchg sti */ |
| 4674 | 4743 |
case 0x29: /* fxchg4 sti, undocumented op */ |
| 4675 | 4744 |
case 0x39: /* fxchg7 sti, undocumented op */ |
| 4676 |
gen_op_fxchg_ST0_STN(opreg);
|
|
| 4745 |
tcg_gen_helper_0_1(helper_fxchg_ST0_STN, tcg_const_i32(opreg));
|
|
| 4677 | 4746 |
break; |
| 4678 | 4747 |
case 0x0a: /* grp d9/2 */ |
| 4679 | 4748 |
switch(rm) {
|
| ... | ... | |
| 4682 | 4751 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 4683 | 4752 |
gen_op_set_cc_op(s->cc_op); |
| 4684 | 4753 |
gen_jmp_im(pc_start - s->cs_base); |
| 4685 |
gen_op_fwait();
|
|
| 4754 |
tcg_gen_helper_0_0(helper_fwait);
|
|
| 4686 | 4755 |
break; |
| 4687 | 4756 |
default: |
| 4688 | 4757 |
goto illegal_op; |
| ... | ... | |
| 4691 | 4760 |
case 0x0c: /* grp d9/4 */ |
| 4692 | 4761 |
switch(rm) {
|
| 4693 | 4762 |
case 0: /* fchs */ |
| 4694 |
gen_op_fchs_ST0();
|
|
| 4763 |
tcg_gen_helper_0_0(helper_fchs_ST0);
|
|
| 4695 | 4764 |
break; |
| 4696 | 4765 |
case 1: /* fabs */ |
| 4697 |
gen_op_fabs_ST0();
|
|
| 4766 |
tcg_gen_helper_0_0(helper_fabs_ST0);
|
|
| 4698 | 4767 |
break; |
| 4699 | 4768 |
case 4: /* ftst */ |
| 4700 |
gen_op_fldz_FT0();
|
|
| 4701 |
gen_op_fcom_ST0_FT0();
|
|
| 4769 |
tcg_gen_helper_0_0(helper_fldz_FT0);
|
|
| 4770 |
tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
|
|
| 4702 | 4771 |
break; |
| 4703 | 4772 |
case 5: /* fxam */ |
| 4704 |
gen_op_fxam_ST0();
|
|
| 4773 |
tcg_gen_helper_0_0(helper_fxam_ST0);
|
|
| 4705 | 4774 |
break; |
| 4706 | 4775 |
default: |
| 4707 | 4776 |
goto illegal_op; |
| ... | ... | |
| 4711 | 4780 |
{
|
| 4712 | 4781 |
switch(rm) {
|
| 4713 | 4782 |
case 0: |
| 4714 |
gen_op_fpush();
|
|
| 4715 |
gen_op_fld1_ST0();
|
|
| 4783 |
tcg_gen_helper_0_0(helper_fpush);
|
|
| 4784 |
tcg_gen_helper_0_0(helper_fld1_ST0);
|
|
| 4716 | 4785 |
break; |
| 4717 | 4786 |
case 1: |
| 4718 |
gen_op_fpush();
|
|
| 4719 |
gen_op_fldl2t_ST0();
|
|
| 4787 |
tcg_gen_helper_0_0(helper_fpush);
|
|
| 4788 |
tcg_gen_helper_0_0(helper_fldl2t_ST0);
|
|
| 4720 | 4789 |
break; |
| 4721 | 4790 |
case 2: |
| 4722 |
gen_op_fpush();
|
|
| 4723 |
gen_op_fldl2e_ST0();
|
|
| 4791 |
tcg_gen_helper_0_0(helper_fpush);
|
|
| 4792 |
tcg_gen_helper_0_0(helper_fldl2e_ST0);
|
|
| 4724 | 4793 |
break; |
| 4725 | 4794 |
case 3: |
| 4726 |
gen_op_fpush();
|
|
| 4727 |
gen_op_fldpi_ST0();
|
|
| 4795 |
tcg_gen_helper_0_0(helper_fpush);
|
|
| 4796 |
tcg_gen_helper_0_0(helper_fldpi_ST0);
|
|
| 4728 | 4797 |
break; |
| 4729 | 4798 |
case 4: |
| 4730 |
gen_op_fpush();
|
|
| 4731 |
gen_op_fldlg2_ST0();
|
|
| 4799 |
tcg_gen_helper_0_0(helper_fpush);
|
|
| 4800 |
tcg_gen_helper_0_0(helper_fldlg2_ST0);
|
|
| 4732 | 4801 |
break; |
| 4733 | 4802 |
case 5: |
| 4734 |
gen_op_fpush();
|
|
| 4735 |
gen_op_fldln2_ST0();
|
|
| 4803 |
tcg_gen_helper_0_0(helper_fpush);
|
|
| 4804 |
tcg_gen_helper_0_0(helper_fldln2_ST0);
|
|
| 4736 | 4805 |
break; |
| 4737 | 4806 |
case 6: |
| 4738 |
gen_op_fpush();
|
|
| 4739 |
gen_op_fldz_ST0();
|
|
| 4807 |
tcg_gen_helper_0_0(helper_fpush);
|
|
| 4808 |
tcg_gen_helper_0_0(helper_fldz_ST0);
|
|
| 4740 | 4809 |
break; |
| 4741 | 4810 |
default: |
| 4742 | 4811 |
goto illegal_op; |
| ... | ... | |
| 4746 | 4815 |
case 0x0e: /* grp d9/6 */ |
| 4747 | 4816 |
switch(rm) {
|
| 4748 | 4817 |
case 0: /* f2xm1 */ |
| 4749 |
gen_op_f2xm1();
|
|
| 4818 |
tcg_gen_helper_0_0(helper_f2xm1);
|
|
| 4750 | 4819 |
break; |
| 4751 | 4820 |
case 1: /* fyl2x */ |
| 4752 |
gen_op_fyl2x();
|
|
| 4821 |
tcg_gen_helper_0_0(helper_fyl2x);
|
|
| 4753 | 4822 |
break; |
| 4754 | 4823 |
case 2: /* fptan */ |
| 4755 |
gen_op_fptan();
|
|
| 4824 |
tcg_gen_helper_0_0(helper_fptan);
|
|
| 4756 | 4825 |
break; |
| 4757 | 4826 |
case 3: /* fpatan */ |
| 4758 |
gen_op_fpatan();
|
|
| 4827 |
tcg_gen_helper_0_0(helper_fpatan);
|
|
| 4759 | 4828 |
break; |
| 4760 | 4829 |
case 4: /* fxtract */ |
| 4761 |
gen_op_fxtract();
|
|
| 4830 |
tcg_gen_helper_0_0(helper_fxtract);
|
|
| 4762 | 4831 |
break; |
| 4763 | 4832 |
case 5: /* fprem1 */ |
| 4764 |
gen_op_fprem1();
|
|
| 4833 |
tcg_gen_helper_0_0(helper_fprem1);
|
|
| 4765 | 4834 |
break; |
| 4766 | 4835 |
case 6: /* fdecstp */ |
| 4767 |
gen_op_fdecstp();
|
|
| 4836 |
tcg_gen_helper_0_0(helper_fdecstp);
|
|
| 4768 | 4837 |
break; |
| 4769 | 4838 |
default: |
| 4770 | 4839 |
case 7: /* fincstp */ |
| 4771 |
gen_op_fincstp();
|
|
| 4840 |
tcg_gen_helper_0_0(helper_fincstp);
|
|
| 4772 | 4841 |
break; |
| 4773 | 4842 |
} |
| 4774 | 4843 |
break; |
| 4775 | 4844 |
case 0x0f: /* grp d9/7 */ |
| 4776 | 4845 |
switch(rm) {
|
| 4777 | 4846 |
case 0: /* fprem */ |
| 4778 |
gen_op_fprem();
|
|
| 4847 |
tcg_gen_helper_0_0(helper_fprem);
|
|
| 4779 | 4848 |
break; |
| 4780 | 4849 |
case 1: /* fyl2xp1 */ |
| 4781 |
gen_op_fyl2xp1();
|
|
| 4850 |
tcg_gen_helper_0_0(helper_fyl2xp1);
|
|
| 4782 | 4851 |
break; |
| 4783 | 4852 |
case 2: /* fsqrt */ |
| 4784 |
gen_op_fsqrt();
|
|
| 4853 |
tcg_gen_helper_0_0(helper_fsqrt);
|
|
| 4785 | 4854 |
break; |
| 4786 | 4855 |
case 3: /* fsincos */ |
| 4787 |
gen_op_fsincos();
|
|
| 4856 |
tcg_gen_helper_0_0(helper_fsincos);
|
|
| 4788 | 4857 |
break; |
| 4789 | 4858 |
case 5: /* fscale */ |
| 4790 |
gen_op_fscale();
|
|
| 4859 |
tcg_gen_helper_0_0(helper_fscale);
|
|
| 4791 | 4860 |
break; |
| 4792 | 4861 |
case 4: /* frndint */ |
| 4793 |
gen_op_frndint();
|
|
| 4862 |
tcg_gen_helper_0_0(helper_frndint);
|
|
| 4794 | 4863 |
break; |
| 4795 | 4864 |
case 6: /* fsin */ |
| 4796 |
gen_op_fsin();
|
|
| 4865 |
tcg_gen_helper_0_0(helper_fsin);
|
|
| 4797 | 4866 |
break; |
| 4798 | 4867 |
default: |
| 4799 | 4868 |
case 7: /* fcos */ |
| 4800 |
gen_op_fcos();
|
|
| 4869 |
tcg_gen_helper_0_0(helper_fcos);
|
|
| 4801 | 4870 |
break; |
| 4802 | 4871 |
} |
| 4803 | 4872 |
break; |
| ... | ... | |
| 4809 | 4878 |
|
| 4810 | 4879 |
op1 = op & 7; |
| 4811 | 4880 |
if (op >= 0x20) {
|
| 4812 |
gen_op_fp_arith_STN_ST0[op1](opreg);
|
|
| 4881 |
tcg_gen_helper_0_1(helper_fp_arith_STN_ST0[op1], tcg_const_i32(opreg));
|
|
| 4813 | 4882 |
if (op >= 0x30) |
| 4814 |
gen_op_fpop();
|
|
| 4883 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4815 | 4884 |
} else {
|
| 4816 |
gen_op_fmov_FT0_STN(opreg);
|
|
| 4817 |
gen_op_fp_arith_ST0_FT0[op1]();
|
|
| 4885 |
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
|
|
| 4886 |
tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
|
|
| 4818 | 4887 |
} |
| 4819 | 4888 |
} |
| 4820 | 4889 |
break; |
| 4821 | 4890 |
case 0x02: /* fcom */ |
| 4822 | 4891 |
case 0x22: /* fcom2, undocumented op */ |
| 4823 |
gen_op_fmov_FT0_STN(opreg);
|
|
| 4824 |
gen_op_fcom_ST0_FT0();
|
|
| 4892 |
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
|
|
| 4893 |
tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
|
|
| 4825 | 4894 |
break; |
| 4826 | 4895 |
case 0x03: /* fcomp */ |
| 4827 | 4896 |
case 0x23: /* fcomp3, undocumented op */ |
| 4828 | 4897 |
case 0x32: /* fcomp5, undocumented op */ |
| 4829 |
gen_op_fmov_FT0_STN(opreg);
|
|
| 4830 |
gen_op_fcom_ST0_FT0();
|
|
| 4831 |
gen_op_fpop();
|
|
| 4898 |
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
|
|
| 4899 |
tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
|
|
| 4900 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4832 | 4901 |
break; |
| 4833 | 4902 |
case 0x15: /* da/5 */ |
| 4834 | 4903 |
switch(rm) {
|
| 4835 | 4904 |
case 1: /* fucompp */ |
| 4836 |
gen_op_fmov_FT0_STN(1);
|
|
| 4837 |
gen_op_fucom_ST0_FT0();
|
|
| 4838 |
gen_op_fpop();
|
|
| 4839 |
gen_op_fpop();
|
|
| 4905 |
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
|
|
| 4906 |
tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
|
|
| 4907 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4908 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4840 | 4909 |
break; |
| 4841 | 4910 |
default: |
| 4842 | 4911 |
goto illegal_op; |
| ... | ... | |
| 4849 | 4918 |
case 1: /* fdisi (287 only, just do nop here) */ |
| 4850 | 4919 |
break; |
| 4851 | 4920 |
case 2: /* fclex */ |
| 4852 |
gen_op_fclex();
|
|
| 4921 |
tcg_gen_helper_0_0(helper_fclex);
|
|
| 4853 | 4922 |
break; |
| 4854 | 4923 |
case 3: /* fninit */ |
| 4855 |
gen_op_fninit();
|
|
| 4924 |
tcg_gen_helper_0_0(helper_fninit);
|
|
| 4856 | 4925 |
break; |
| 4857 | 4926 |
case 4: /* fsetpm (287 only, just do nop here) */ |
| 4858 | 4927 |
break; |
| ... | ... | |
| 4863 | 4932 |
case 0x1d: /* fucomi */ |
| 4864 | 4933 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 4865 | 4934 |
gen_op_set_cc_op(s->cc_op); |
| 4866 |
gen_op_fmov_FT0_STN(opreg); |
|
| 4867 |
gen_op_fucomi_ST0_FT0(); |
|
| 4935 |
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
|
| 4936 |
tcg_gen_helper_0_0(helper_fucomi_ST0_FT0); |
|
| 4937 |
gen_op_fcomi_dummy(); |
|
| 4868 | 4938 |
s->cc_op = CC_OP_EFLAGS; |
| 4869 | 4939 |
break; |
| 4870 | 4940 |
case 0x1e: /* fcomi */ |
| 4871 | 4941 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 4872 | 4942 |
gen_op_set_cc_op(s->cc_op); |
| 4873 |
gen_op_fmov_FT0_STN(opreg); |
|
| 4874 |
gen_op_fcomi_ST0_FT0(); |
|
| 4943 |
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
|
| 4944 |
tcg_gen_helper_0_0(helper_fcomi_ST0_FT0); |
|
| 4945 |
gen_op_fcomi_dummy(); |
|
| 4875 | 4946 |
s->cc_op = CC_OP_EFLAGS; |
| 4876 | 4947 |
break; |
| 4877 | 4948 |
case 0x28: /* ffree sti */ |
| 4878 |
gen_op_ffree_STN(opreg);
|
|
| 4949 |
tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
|
|
| 4879 | 4950 |
break; |
| 4880 | 4951 |
case 0x2a: /* fst sti */ |
| 4881 |
gen_op_fmov_STN_ST0(opreg);
|
|
| 4952 |
tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
|
|
| 4882 | 4953 |
break; |
| 4883 | 4954 |
case 0x2b: /* fstp sti */ |
| 4884 | 4955 |
case 0x0b: /* fstp1 sti, undocumented op */ |
| 4885 | 4956 |
case 0x3a: /* fstp8 sti, undocumented op */ |
| 4886 | 4957 |
case 0x3b: /* fstp9 sti, undocumented op */ |
| 4887 |
gen_op_fmov_STN_ST0(opreg);
|
|
| 4888 |
gen_op_fpop();
|
|
| 4958 |
tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
|
|
| 4959 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4889 | 4960 |
break; |
| 4890 | 4961 |
case 0x2c: /* fucom st(i) */ |
| 4891 |
gen_op_fmov_FT0_STN(opreg);
|
|
| 4892 |
gen_op_fucom_ST0_FT0();
|
|
| 4962 |
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
|
|
| 4963 |
tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
|
|
| 4893 | 4964 |
break; |
| 4894 | 4965 |
case 0x2d: /* fucomp st(i) */ |
| 4895 |
gen_op_fmov_FT0_STN(opreg);
|
|
| 4896 |
gen_op_fucom_ST0_FT0();
|
|
| 4897 |
gen_op_fpop();
|
|
| 4966 |
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
|
|
| 4967 |
tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
|
|
| 4968 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4898 | 4969 |
break; |
| 4899 | 4970 |
case 0x33: /* de/3 */ |
| 4900 | 4971 |
switch(rm) {
|
| 4901 | 4972 |
case 1: /* fcompp */ |
| 4902 |
gen_op_fmov_FT0_STN(1);
|
|
| 4903 |
gen_op_fcom_ST0_FT0();
|
|
| 4904 |
gen_op_fpop();
|
|
| 4905 |
gen_op_fpop();
|
|
| 4973 |
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
|
|
| 4974 |
tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
|
|
| 4975 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4976 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4906 | 4977 |
break; |
| 4907 | 4978 |
default: |
| 4908 | 4979 |
goto illegal_op; |
| 4909 | 4980 |
} |
| 4910 | 4981 |
break; |
| 4911 | 4982 |
case 0x38: /* ffreep sti, undocumented op */ |
| 4912 |
gen_op_ffree_STN(opreg);
|
|
| 4913 |
gen_op_fpop();
|
|
| 4983 |
tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
|
|
| 4984 |
tcg_gen_helper_0_0(helper_fpop);
|
|
| 4914 | 4985 |
break; |
| 4915 | 4986 |
case 0x3c: /* df/4 */ |
| 4916 | 4987 |
switch(rm) {
|
| 4917 | 4988 |
case 0: |
| 4918 |
gen_op_fnstsw_EAX(); |
|
| 4989 |
tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2); |
|
| 4990 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4991 |
gen_op_mov_reg_T0(OT_WORD, R_EAX); |
|
| 4919 | 4992 |
break; |
| 4920 | 4993 |
default: |
| 4921 | 4994 |
goto illegal_op; |
| ... | ... | |
| 4924 | 4997 |
case 0x3d: /* fucomip */ |
| 4925 | 4998 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 4926 | 4999 |
gen_op_set_cc_op(s->cc_op); |
| 4927 |
gen_op_fmov_FT0_STN(opreg); |
|
| 4928 |
gen_op_fucomi_ST0_FT0(); |
|
| 4929 |
gen_op_fpop(); |
|
| 5000 |
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
|
| 5001 |
tcg_gen_helper_0_0(helper_fucomi_ST0_FT0); |
|
| 5002 |
tcg_gen_helper_0_0(helper_fpop); |
|
| 5003 |
gen_op_fcomi_dummy(); |
|
| 4930 | 5004 |
s->cc_op = CC_OP_EFLAGS; |
| 4931 | 5005 |
break; |
| 4932 | 5006 |
case 0x3e: /* fcomip */ |
| 4933 | 5007 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 4934 | 5008 |
gen_op_set_cc_op(s->cc_op); |
| 4935 |
gen_op_fmov_FT0_STN(opreg); |
|
| 4936 |
gen_op_fcomi_ST0_FT0(); |
|
| 4937 |
gen_op_fpop(); |
|
| 5009 |
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
|
| 5010 |
tcg_gen_helper_0_0(helper_fcomi_ST0_FT0); |
|
| 5011 |
tcg_gen_helper_0_0(helper_fpop); |
|
| 5012 |
gen_op_fcomi_dummy(); |
|
| 4938 | 5013 |
s->cc_op = CC_OP_EFLAGS; |
| 4939 | 5014 |
break; |
| 4940 | 5015 |
case 0x10 ... 0x13: /* fcmovxx */ |
| 4941 | 5016 |
case 0x18 ... 0x1b: |
| 4942 | 5017 |
{
|
| 4943 |
int op1; |
|
| 5018 |
int op1, l1;
|
|
| 4944 | 5019 |
const static uint8_t fcmov_cc[8] = {
|
| 4945 | 5020 |
(JCC_B << 1), |
| 4946 | 5021 |
(JCC_Z << 1), |
| ... | ... | |
| 4949 | 5024 |
}; |
| 4950 | 5025 |
op1 = fcmov_cc[op & 3] | ((op >> 3) & 1); |
| 4951 | 5026 |
gen_setcc(s, op1); |
| 4952 |
gen_op_fcmov_ST0_STN_T0(opreg); |
|
| 5027 |
l1 = gen_new_label(); |
|
| 5028 |
tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), l1); |
|
| 5029 |
tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32(opreg)); |
|
| 5030 |
gen_set_label(l1); |
|
| 4953 | 5031 |
} |
| 4954 | 5032 |
break; |
| 4955 | 5033 |
default: |
| ... | ... | |
| 5550 | 5628 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 5551 | 5629 |
gen_op_set_cc_op(s->cc_op); |
| 5552 | 5630 |
gen_jmp_im(pc_start - s->cs_base); |
| 5553 |
gen_op_fwait();
|
|
| 5631 |
tcg_gen_helper_0_0(helper_fwait);
|
|
| 5554 | 5632 |
} |
| 5555 | 5633 |
break; |
| 5556 | 5634 |
case 0xcc: /* int3 */ |
| ... | ... | |
| 6301 | 6379 |
break; |
| 6302 | 6380 |
} |
| 6303 | 6381 |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
| 6304 |
gen_op_fxsave_A0((s->dflag == 2)); |
|
| 6382 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 6383 |
gen_op_set_cc_op(s->cc_op); |
|
| 6384 |
gen_jmp_im(pc_start - s->cs_base); |
|
| 6385 |
tcg_gen_helper_0_2(helper_fxsave, |
|
| 6386 |
cpu_A0, tcg_const_i32((s->dflag == 2))); |
|
| 6305 | 6387 |
break; |
| 6306 | 6388 |
case 1: /* fxrstor */ |
| 6307 | 6389 |
if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
| ... | ... | |
| 6312 | 6394 |
break; |
| 6313 | 6395 |
} |
| 6314 | 6396 |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
| 6315 |
gen_op_fxrstor_A0((s->dflag == 2)); |
|
| 6397 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 6398 |
gen_op_set_cc_op(s->cc_op); |
|
| 6399 |
gen_jmp_im(pc_start - s->cs_base); |
|
| 6400 |
tcg_gen_helper_0_2(helper_fxrstor, |
|
| 6401 |
cpu_A0, tcg_const_i32((s->dflag == 2))); |
|
| 6316 | 6402 |
break; |
| 6317 | 6403 |
case 2: /* ldmxcsr */ |
| 6318 | 6404 |
case 3: /* stmxcsr */ |
| ... | ... | |
| 6615 | 6701 |
[INDEX_op_lsl] = CC_Z, |
| 6616 | 6702 |
[INDEX_op_verr] = CC_Z, |
| 6617 | 6703 |
[INDEX_op_verw] = CC_Z, |
| 6618 |
[INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
|
|
| 6619 |
[INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
|
|
| 6704 |
[INDEX_op_fcomi_dummy] = CC_Z | CC_P | CC_C,
|
|
| 6705 |
[INDEX_op_fcomi_dummy] = CC_Z | CC_P | CC_C,
|
|
| 6620 | 6706 |
|
| 6621 | 6707 |
#define DEF_WRITEF(SUFFIX)\ |
| 6622 | 6708 |
[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\ |
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