Revision 1a072690 hw/omap_spi.c
| b/hw/omap_spi.c | ||
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/* Multichannel SPI */ |
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struct omap_mcspi_s {
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MemoryRegion iomem; |
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qemu_irq irq; |
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int chnum; |
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|
| ... | ... | |
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omap_mcspi_interrupt_update(s); |
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} |
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static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr) |
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static uint64_t omap_mcspi_read(void *opaque, target_phys_addr_t addr, |
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unsigned size) |
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{
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struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
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int ch = 0; |
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uint32_t ret; |
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if (size != 4) {
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return omap_badwidth_read32(opaque, addr); |
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} |
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switch (addr) {
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case 0x00: /* MCSPI_REVISION */ |
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return 0x91; |
| ... | ... | |
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} |
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static void omap_mcspi_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value)
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uint64_t value, unsigned size)
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{
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struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
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int ch = 0; |
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if (size != 4) {
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return omap_badwidth_write32(opaque, addr, value); |
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} |
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switch (addr) {
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case 0x00: /* MCSPI_REVISION */ |
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case 0x14: /* MCSPI_SYSSTATUS */ |
| ... | ... | |
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if (((value >> 12) & 3) == 3) /* TRM */ |
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fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__); |
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if (((value >> 7) & 0x1f) < 3) /* WL */ |
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fprintf(stderr, "%s: invalid WL value (%i)\n",
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fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n",
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__FUNCTION__, (value >> 7) & 0x1f); |
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s->ch[ch].config = value & 0x7fffff; |
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break; |
| ... | ... | |
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} |
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} |
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static CPUReadMemoryFunc * const omap_mcspi_readfn[] = {
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omap_badwidth_read32, |
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omap_badwidth_read32, |
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omap_mcspi_read, |
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}; |
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static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = {
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omap_badwidth_write32, |
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omap_badwidth_write32, |
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omap_mcspi_write, |
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static const MemoryRegionOps omap_mcspi_ops = {
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.read = omap_mcspi_read, |
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.write = omap_mcspi_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
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qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) |
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{
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int iomemtype; |
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struct omap_mcspi_s *s = (struct omap_mcspi_s *) |
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g_malloc0(sizeof(struct omap_mcspi_s)); |
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struct omap_mcspi_ch_s *ch = s->ch; |
| ... | ... | |
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} |
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omap_mcspi_reset(s); |
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iomemtype = cpu_register_io_memory(omap_mcspi_readfn,
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omap_mcspi_writefn, s, DEVICE_NATIVE_ENDIAN);
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omap_l4_attach(ta, 0, iomemtype);
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memory_region_init_io(&s->iomem, &omap_mcspi_ops, s, "omap.mcspi",
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omap_l4_region_size(ta, 0));
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omap_l4_attach_region(ta, 0, &s->iomem);
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return s; |
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} |
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