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1 | 7e7c5e4c | balrog | /*
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2 | 7e7c5e4c | balrog | * CBUS three-pin bus and the Retu / Betty / Tahvo / Vilma / Avilma /
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3 | 7e7c5e4c | balrog | * Hinku / Vinku / Ahne / Pihi chips used in various Nokia platforms.
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4 | 7e7c5e4c | balrog | * Based on reverse-engineering of a linux driver.
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5 | 7e7c5e4c | balrog | *
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6 | 7e7c5e4c | balrog | * Copyright (C) 2008 Nokia Corporation
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7 | 7e7c5e4c | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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8 | 7e7c5e4c | balrog | *
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9 | 7e7c5e4c | balrog | * This program is free software; you can redistribute it and/or
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10 | 7e7c5e4c | balrog | * modify it under the terms of the GNU General Public License as
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11 | 7e7c5e4c | balrog | * published by the Free Software Foundation; either version 2 or
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12 | 7e7c5e4c | balrog | * (at your option) version 3 of the License.
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13 | 7e7c5e4c | balrog | *
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14 | 7e7c5e4c | balrog | * This program is distributed in the hope that it will be useful,
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15 | 7e7c5e4c | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 | 7e7c5e4c | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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17 | 7e7c5e4c | balrog | * GNU General Public License for more details.
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18 | 7e7c5e4c | balrog | *
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19 | 7e7c5e4c | balrog | * You should have received a copy of the GNU General Public License
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20 | 7e7c5e4c | balrog | * along with this program; if not, write to the Free Software
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21 | 7e7c5e4c | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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22 | 7e7c5e4c | balrog | * MA 02111-1307 USA
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23 | 7e7c5e4c | balrog | */
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24 | 7e7c5e4c | balrog | |
25 | 7e7c5e4c | balrog | #include "qemu-common.h" |
26 | 7e7c5e4c | balrog | #include "irq.h" |
27 | 7e7c5e4c | balrog | #include "devices.h" |
28 | 7e7c5e4c | balrog | #include "sysemu.h" |
29 | 7e7c5e4c | balrog | |
30 | 7e7c5e4c | balrog | //#define DEBUG
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31 | 7e7c5e4c | balrog | |
32 | 7e7c5e4c | balrog | struct cbus_slave_s;
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33 | 7e7c5e4c | balrog | struct cbus_priv_s {
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34 | 7e7c5e4c | balrog | struct cbus_s cbus;
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35 | 7e7c5e4c | balrog | |
36 | 7e7c5e4c | balrog | int sel;
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37 | 7e7c5e4c | balrog | int dat;
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38 | 7e7c5e4c | balrog | int clk;
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39 | 7e7c5e4c | balrog | int bit;
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40 | 7e7c5e4c | balrog | int dir;
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41 | 7e7c5e4c | balrog | uint16_t val; |
42 | 7e7c5e4c | balrog | qemu_irq dat_out; |
43 | 7e7c5e4c | balrog | |
44 | 7e7c5e4c | balrog | int addr;
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45 | 7e7c5e4c | balrog | int reg;
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46 | 7e7c5e4c | balrog | int rw;
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47 | 7e7c5e4c | balrog | enum {
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48 | 7e7c5e4c | balrog | cbus_address, |
49 | 7e7c5e4c | balrog | cbus_value, |
50 | 7e7c5e4c | balrog | } cycle; |
51 | 7e7c5e4c | balrog | |
52 | 7e7c5e4c | balrog | struct cbus_slave_s *slave[8]; |
53 | 7e7c5e4c | balrog | }; |
54 | 7e7c5e4c | balrog | |
55 | 7e7c5e4c | balrog | struct cbus_slave_s {
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56 | 7e7c5e4c | balrog | void *opaque;
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57 | 7e7c5e4c | balrog | void (*io)(void *opaque, int rw, int reg, uint16_t *val); |
58 | 7e7c5e4c | balrog | int addr;
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59 | 7e7c5e4c | balrog | }; |
60 | 7e7c5e4c | balrog | |
61 | 7e7c5e4c | balrog | static void cbus_io(struct cbus_priv_s *s) |
62 | 7e7c5e4c | balrog | { |
63 | 7e7c5e4c | balrog | if (s->slave[s->addr])
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64 | 7e7c5e4c | balrog | s->slave[s->addr]->io(s->slave[s->addr]->opaque, |
65 | 7e7c5e4c | balrog | s->rw, s->reg, &s->val); |
66 | 7e7c5e4c | balrog | else
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67 | 7e7c5e4c | balrog | cpu_abort(cpu_single_env, "%s: bad slave address %i\n",
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68 | 7e7c5e4c | balrog | __FUNCTION__, s->addr); |
69 | 7e7c5e4c | balrog | } |
70 | 7e7c5e4c | balrog | |
71 | 7e7c5e4c | balrog | static void cbus_cycle(struct cbus_priv_s *s) |
72 | 7e7c5e4c | balrog | { |
73 | 7e7c5e4c | balrog | switch (s->cycle) {
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74 | 7e7c5e4c | balrog | case cbus_address:
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75 | 7e7c5e4c | balrog | s->addr = (s->val >> 6) & 7; |
76 | 7e7c5e4c | balrog | s->rw = (s->val >> 5) & 1; |
77 | 7e7c5e4c | balrog | s->reg = (s->val >> 0) & 0x1f; |
78 | 7e7c5e4c | balrog | |
79 | 7e7c5e4c | balrog | s->cycle = cbus_value; |
80 | 7e7c5e4c | balrog | s->bit = 15;
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81 | 7e7c5e4c | balrog | s->dir = !s->rw; |
82 | 7e7c5e4c | balrog | s->val = 0;
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83 | 7e7c5e4c | balrog | |
84 | 7e7c5e4c | balrog | if (s->rw)
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85 | 7e7c5e4c | balrog | cbus_io(s); |
86 | 7e7c5e4c | balrog | break;
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87 | 7e7c5e4c | balrog | |
88 | 7e7c5e4c | balrog | case cbus_value:
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89 | 7e7c5e4c | balrog | if (!s->rw)
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90 | 7e7c5e4c | balrog | cbus_io(s); |
91 | 7e7c5e4c | balrog | |
92 | 7e7c5e4c | balrog | s->cycle = cbus_address; |
93 | 7e7c5e4c | balrog | s->bit = 8;
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94 | 7e7c5e4c | balrog | s->dir = 1;
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95 | 7e7c5e4c | balrog | s->val = 0;
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96 | 7e7c5e4c | balrog | break;
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97 | 7e7c5e4c | balrog | } |
98 | 7e7c5e4c | balrog | } |
99 | 7e7c5e4c | balrog | |
100 | 7e7c5e4c | balrog | static void cbus_clk(void *opaque, int line, int level) |
101 | 7e7c5e4c | balrog | { |
102 | 7e7c5e4c | balrog | struct cbus_priv_s *s = (struct cbus_priv_s *) opaque; |
103 | 7e7c5e4c | balrog | |
104 | 7e7c5e4c | balrog | if (!s->sel && level && !s->clk) {
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105 | 7e7c5e4c | balrog | if (s->dir)
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106 | 7e7c5e4c | balrog | s->val |= s->dat << (s->bit --); |
107 | 7e7c5e4c | balrog | else
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108 | 7e7c5e4c | balrog | qemu_set_irq(s->dat_out, (s->val >> (s->bit --)) & 1);
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109 | 7e7c5e4c | balrog | |
110 | 7e7c5e4c | balrog | if (s->bit < 0) |
111 | 7e7c5e4c | balrog | cbus_cycle(s); |
112 | 7e7c5e4c | balrog | } |
113 | 7e7c5e4c | balrog | |
114 | 7e7c5e4c | balrog | s->clk = level; |
115 | 7e7c5e4c | balrog | } |
116 | 7e7c5e4c | balrog | |
117 | 7e7c5e4c | balrog | static void cbus_dat(void *opaque, int line, int level) |
118 | 7e7c5e4c | balrog | { |
119 | 7e7c5e4c | balrog | struct cbus_priv_s *s = (struct cbus_priv_s *) opaque; |
120 | 7e7c5e4c | balrog | |
121 | 7e7c5e4c | balrog | s->dat = level; |
122 | 7e7c5e4c | balrog | } |
123 | 7e7c5e4c | balrog | |
124 | 7e7c5e4c | balrog | static void cbus_sel(void *opaque, int line, int level) |
125 | 7e7c5e4c | balrog | { |
126 | 7e7c5e4c | balrog | struct cbus_priv_s *s = (struct cbus_priv_s *) opaque; |
127 | 7e7c5e4c | balrog | |
128 | 7e7c5e4c | balrog | if (!level) {
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129 | 7e7c5e4c | balrog | s->dir = 1;
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130 | 7e7c5e4c | balrog | s->bit = 8;
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131 | 7e7c5e4c | balrog | s->val = 0;
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132 | 7e7c5e4c | balrog | } |
133 | 7e7c5e4c | balrog | |
134 | 7e7c5e4c | balrog | s->sel = level; |
135 | 7e7c5e4c | balrog | } |
136 | 7e7c5e4c | balrog | |
137 | 7e7c5e4c | balrog | struct cbus_s *cbus_init(qemu_irq dat)
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138 | 7e7c5e4c | balrog | { |
139 | 7e7c5e4c | balrog | struct cbus_priv_s *s = (struct cbus_priv_s *) qemu_mallocz(sizeof(*s)); |
140 | 7e7c5e4c | balrog | |
141 | 7e7c5e4c | balrog | s->dat_out = dat; |
142 | 7e7c5e4c | balrog | s->cbus.clk = qemu_allocate_irqs(cbus_clk, s, 1)[0]; |
143 | 7e7c5e4c | balrog | s->cbus.dat = qemu_allocate_irqs(cbus_dat, s, 1)[0]; |
144 | 7e7c5e4c | balrog | s->cbus.sel = qemu_allocate_irqs(cbus_sel, s, 1)[0]; |
145 | 7e7c5e4c | balrog | |
146 | 7e7c5e4c | balrog | s->sel = 1;
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147 | 7e7c5e4c | balrog | s->clk = 0;
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148 | 7e7c5e4c | balrog | s->dat = 0;
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149 | 7e7c5e4c | balrog | |
150 | 7e7c5e4c | balrog | return &s->cbus;
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151 | 7e7c5e4c | balrog | } |
152 | 7e7c5e4c | balrog | |
153 | 7e7c5e4c | balrog | void cbus_attach(struct cbus_s *bus, void *slave_opaque) |
154 | 7e7c5e4c | balrog | { |
155 | 7e7c5e4c | balrog | struct cbus_slave_s *slave = (struct cbus_slave_s *) slave_opaque; |
156 | 7e7c5e4c | balrog | struct cbus_priv_s *s = (struct cbus_priv_s *) bus; |
157 | 7e7c5e4c | balrog | |
158 | 7e7c5e4c | balrog | s->slave[slave->addr] = slave; |
159 | 7e7c5e4c | balrog | } |
160 | 7e7c5e4c | balrog | |
161 | 7e7c5e4c | balrog | /* Retu/Vilma */
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162 | 7e7c5e4c | balrog | struct cbus_retu_s {
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163 | 7e7c5e4c | balrog | uint16_t irqst; |
164 | 7e7c5e4c | balrog | uint16_t irqen; |
165 | 7e7c5e4c | balrog | uint16_t cc[2];
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166 | 7e7c5e4c | balrog | int channel;
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167 | 7e7c5e4c | balrog | uint16_t result[16];
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168 | 7e7c5e4c | balrog | uint16_t sample; |
169 | 7e7c5e4c | balrog | uint16_t status; |
170 | 7e7c5e4c | balrog | |
171 | 7e7c5e4c | balrog | struct {
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172 | 7e7c5e4c | balrog | uint16_t cal; |
173 | 7e7c5e4c | balrog | } rtc; |
174 | 7e7c5e4c | balrog | |
175 | 7e7c5e4c | balrog | int is_vilma;
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176 | 7e7c5e4c | balrog | qemu_irq irq; |
177 | 7e7c5e4c | balrog | struct cbus_slave_s cbus;
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178 | 7e7c5e4c | balrog | }; |
179 | 7e7c5e4c | balrog | |
180 | 7e7c5e4c | balrog | static void retu_interrupt_update(struct cbus_retu_s *s) |
181 | 7e7c5e4c | balrog | { |
182 | 7e7c5e4c | balrog | qemu_set_irq(s->irq, s->irqst & ~s->irqen); |
183 | 7e7c5e4c | balrog | } |
184 | 7e7c5e4c | balrog | |
185 | 7e7c5e4c | balrog | #define RETU_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ |
186 | 7e7c5e4c | balrog | #define RETU_REG_IDR 0x01 /* (T) Interrupt ID */ |
187 | 7e7c5e4c | balrog | #define RETU_REG_IMR 0x02 /* (RW) Interrupt mask */ |
188 | 7e7c5e4c | balrog | #define RETU_REG_RTCDSR 0x03 /* (RW) RTC seconds register */ |
189 | 7e7c5e4c | balrog | #define RETU_REG_RTCHMR 0x04 /* (RO) RTC hours and minutes reg */ |
190 | 7e7c5e4c | balrog | #define RETU_REG_RTCHMAR 0x05 /* (RW) RTC hours and minutes set reg */ |
191 | 7e7c5e4c | balrog | #define RETU_REG_RTCCALR 0x06 /* (RW) RTC calibration register */ |
192 | 7e7c5e4c | balrog | #define RETU_REG_ADCR 0x08 /* (RW) ADC result register */ |
193 | 7e7c5e4c | balrog | #define RETU_REG_ADCSCR 0x09 /* (RW) ADC sample control register */ |
194 | 7e7c5e4c | balrog | #define RETU_REG_AFCR 0x0a /* (RW) AFC register */ |
195 | 7e7c5e4c | balrog | #define RETU_REG_ANTIFR 0x0b /* (RW) AntiF register */ |
196 | 7e7c5e4c | balrog | #define RETU_REG_CALIBR 0x0c /* (RW) CalibR register*/ |
197 | 7e7c5e4c | balrog | #define RETU_REG_CCR1 0x0d /* (RW) Common control register 1 */ |
198 | 7e7c5e4c | balrog | #define RETU_REG_CCR2 0x0e /* (RW) Common control register 2 */ |
199 | 7e7c5e4c | balrog | #define RETU_REG_RCTRL_CLR 0x0f /* (T) Regulator clear register */ |
200 | 7e7c5e4c | balrog | #define RETU_REG_RCTRL_SET 0x10 /* (T) Regulator set register */ |
201 | 7e7c5e4c | balrog | #define RETU_REG_TXCR 0x11 /* (RW) TxC register */ |
202 | 7e7c5e4c | balrog | #define RETU_REG_STATUS 0x16 /* (RO) Status register */ |
203 | 7e7c5e4c | balrog | #define RETU_REG_WATCHDOG 0x17 /* (RW) Watchdog register */ |
204 | 7e7c5e4c | balrog | #define RETU_REG_AUDTXR 0x18 /* (RW) Audio Codec Tx register */ |
205 | 7e7c5e4c | balrog | #define RETU_REG_AUDPAR 0x19 /* (RW) AudioPA register */ |
206 | 7e7c5e4c | balrog | #define RETU_REG_AUDRXR1 0x1a /* (RW) Audio receive register 1 */ |
207 | 7e7c5e4c | balrog | #define RETU_REG_AUDRXR2 0x1b /* (RW) Audio receive register 2 */ |
208 | 7e7c5e4c | balrog | #define RETU_REG_SGR1 0x1c /* (RW) */ |
209 | 7e7c5e4c | balrog | #define RETU_REG_SCR1 0x1d /* (RW) */ |
210 | 7e7c5e4c | balrog | #define RETU_REG_SGR2 0x1e /* (RW) */ |
211 | 7e7c5e4c | balrog | #define RETU_REG_SCR2 0x1f /* (RW) */ |
212 | 7e7c5e4c | balrog | |
213 | 7e7c5e4c | balrog | /* Retu Interrupt sources */
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214 | 7e7c5e4c | balrog | enum {
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215 | 7e7c5e4c | balrog | retu_int_pwr = 0, /* Power button */ |
216 | 7e7c5e4c | balrog | retu_int_char = 1, /* Charger */ |
217 | 7e7c5e4c | balrog | retu_int_rtcs = 2, /* Seconds */ |
218 | 7e7c5e4c | balrog | retu_int_rtcm = 3, /* Minutes */ |
219 | 7e7c5e4c | balrog | retu_int_rtcd = 4, /* Days */ |
220 | 7e7c5e4c | balrog | retu_int_rtca = 5, /* Alarm */ |
221 | 7e7c5e4c | balrog | retu_int_hook = 6, /* Hook */ |
222 | 7e7c5e4c | balrog | retu_int_head = 7, /* Headset */ |
223 | 7e7c5e4c | balrog | retu_int_adcs = 8, /* ADC sample */ |
224 | 7e7c5e4c | balrog | }; |
225 | 7e7c5e4c | balrog | |
226 | 7e7c5e4c | balrog | /* Retu ADC channel wiring */
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227 | 7e7c5e4c | balrog | enum {
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228 | 7e7c5e4c | balrog | retu_adc_bsi = 1, /* BSI */ |
229 | 7e7c5e4c | balrog | retu_adc_batt_temp = 2, /* Battery temperature */ |
230 | 7e7c5e4c | balrog | retu_adc_chg_volt = 3, /* Charger voltage */ |
231 | 7e7c5e4c | balrog | retu_adc_head_det = 4, /* Headset detection */ |
232 | 7e7c5e4c | balrog | retu_adc_hook_det = 5, /* Hook detection */ |
233 | 7e7c5e4c | balrog | retu_adc_rf_gp = 6, /* RF GP */ |
234 | 7e7c5e4c | balrog | retu_adc_tx_det = 7, /* Wideband Tx detection */ |
235 | 7e7c5e4c | balrog | retu_adc_batt_volt = 8, /* Battery voltage */ |
236 | 7e7c5e4c | balrog | retu_adc_sens = 10, /* Light sensor */ |
237 | 7e7c5e4c | balrog | retu_adc_sens_temp = 11, /* Light sensor temperature */ |
238 | 7e7c5e4c | balrog | retu_adc_bbatt_volt = 12, /* Backup battery voltage */ |
239 | 7e7c5e4c | balrog | retu_adc_self_temp = 13, /* RETU temperature */ |
240 | 7e7c5e4c | balrog | }; |
241 | 7e7c5e4c | balrog | |
242 | 7e7c5e4c | balrog | static inline uint16_t retu_read(struct cbus_retu_s *s, int reg) |
243 | 7e7c5e4c | balrog | { |
244 | 7e7c5e4c | balrog | #ifdef DEBUG
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245 | 7e7c5e4c | balrog | printf("RETU read at %02x\n", reg);
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246 | 7e7c5e4c | balrog | #endif
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247 | 7e7c5e4c | balrog | |
248 | 7e7c5e4c | balrog | switch (reg) {
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249 | 7e7c5e4c | balrog | case RETU_REG_ASICR:
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250 | 7e7c5e4c | balrog | return 0x0215 | (s->is_vilma << 7); |
251 | 7e7c5e4c | balrog | |
252 | 7e7c5e4c | balrog | case RETU_REG_IDR: /* TODO: Or is this ffs(s->irqst)? */ |
253 | 7e7c5e4c | balrog | return s->irqst;
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254 | 7e7c5e4c | balrog | |
255 | 7e7c5e4c | balrog | case RETU_REG_IMR:
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256 | 7e7c5e4c | balrog | return s->irqen;
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257 | 7e7c5e4c | balrog | |
258 | 7e7c5e4c | balrog | case RETU_REG_RTCDSR:
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259 | 7e7c5e4c | balrog | case RETU_REG_RTCHMR:
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260 | 7e7c5e4c | balrog | case RETU_REG_RTCHMAR:
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261 | 7e7c5e4c | balrog | /* TODO */
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262 | 7e7c5e4c | balrog | return 0x0000; |
263 | 7e7c5e4c | balrog | |
264 | 7e7c5e4c | balrog | case RETU_REG_RTCCALR:
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265 | 7e7c5e4c | balrog | return s->rtc.cal;
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266 | 7e7c5e4c | balrog | |
267 | 7e7c5e4c | balrog | case RETU_REG_ADCR:
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268 | 7e7c5e4c | balrog | return (s->channel << 10) | s->result[s->channel]; |
269 | 7e7c5e4c | balrog | case RETU_REG_ADCSCR:
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270 | 7e7c5e4c | balrog | return s->sample;
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271 | 7e7c5e4c | balrog | |
272 | 7e7c5e4c | balrog | case RETU_REG_AFCR:
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273 | 7e7c5e4c | balrog | case RETU_REG_ANTIFR:
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274 | 7e7c5e4c | balrog | case RETU_REG_CALIBR:
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275 | 7e7c5e4c | balrog | /* TODO */
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276 | 7e7c5e4c | balrog | return 0x0000; |
277 | 7e7c5e4c | balrog | |
278 | 7e7c5e4c | balrog | case RETU_REG_CCR1:
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279 | 7e7c5e4c | balrog | return s->cc[0]; |
280 | 7e7c5e4c | balrog | case RETU_REG_CCR2:
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281 | 7e7c5e4c | balrog | return s->cc[1]; |
282 | 7e7c5e4c | balrog | |
283 | 7e7c5e4c | balrog | case RETU_REG_RCTRL_CLR:
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284 | 7e7c5e4c | balrog | case RETU_REG_RCTRL_SET:
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285 | 7e7c5e4c | balrog | case RETU_REG_TXCR:
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286 | 7e7c5e4c | balrog | /* TODO */
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287 | 7e7c5e4c | balrog | return 0x0000; |
288 | 7e7c5e4c | balrog | |
289 | 7e7c5e4c | balrog | case RETU_REG_STATUS:
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290 | 7e7c5e4c | balrog | return s->status;
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291 | 7e7c5e4c | balrog | |
292 | 7e7c5e4c | balrog | case RETU_REG_WATCHDOG:
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293 | 7e7c5e4c | balrog | case RETU_REG_AUDTXR:
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294 | 7e7c5e4c | balrog | case RETU_REG_AUDPAR:
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295 | 7e7c5e4c | balrog | case RETU_REG_AUDRXR1:
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296 | 7e7c5e4c | balrog | case RETU_REG_AUDRXR2:
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297 | 7e7c5e4c | balrog | case RETU_REG_SGR1:
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298 | 7e7c5e4c | balrog | case RETU_REG_SCR1:
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299 | 7e7c5e4c | balrog | case RETU_REG_SGR2:
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300 | 7e7c5e4c | balrog | case RETU_REG_SCR2:
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301 | 7e7c5e4c | balrog | /* TODO */
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302 | 7e7c5e4c | balrog | return 0x0000; |
303 | 7e7c5e4c | balrog | |
304 | 7e7c5e4c | balrog | default:
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305 | 7e7c5e4c | balrog | cpu_abort(cpu_single_env, "%s: bad register %02x\n",
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306 | 7e7c5e4c | balrog | __FUNCTION__, reg); |
307 | 7e7c5e4c | balrog | } |
308 | 7e7c5e4c | balrog | } |
309 | 7e7c5e4c | balrog | |
310 | 7e7c5e4c | balrog | static inline void retu_write(struct cbus_retu_s *s, int reg, uint16_t val) |
311 | 7e7c5e4c | balrog | { |
312 | 7e7c5e4c | balrog | #ifdef DEBUG
|
313 | 7e7c5e4c | balrog | printf("RETU write of %04x at %02x\n", val, reg);
|
314 | 7e7c5e4c | balrog | #endif
|
315 | 7e7c5e4c | balrog | |
316 | 7e7c5e4c | balrog | switch (reg) {
|
317 | 7e7c5e4c | balrog | case RETU_REG_IDR:
|
318 | 7e7c5e4c | balrog | s->irqst ^= val; |
319 | 7e7c5e4c | balrog | retu_interrupt_update(s); |
320 | 7e7c5e4c | balrog | break;
|
321 | 7e7c5e4c | balrog | |
322 | 7e7c5e4c | balrog | case RETU_REG_IMR:
|
323 | 7e7c5e4c | balrog | s->irqen = val; |
324 | 7e7c5e4c | balrog | retu_interrupt_update(s); |
325 | 7e7c5e4c | balrog | break;
|
326 | 7e7c5e4c | balrog | |
327 | 7e7c5e4c | balrog | case RETU_REG_RTCDSR:
|
328 | 7e7c5e4c | balrog | case RETU_REG_RTCHMAR:
|
329 | 7e7c5e4c | balrog | /* TODO */
|
330 | 7e7c5e4c | balrog | break;
|
331 | 7e7c5e4c | balrog | |
332 | 7e7c5e4c | balrog | case RETU_REG_RTCCALR:
|
333 | 7e7c5e4c | balrog | s->rtc.cal = val; |
334 | 7e7c5e4c | balrog | break;
|
335 | 7e7c5e4c | balrog | |
336 | 7e7c5e4c | balrog | case RETU_REG_ADCR:
|
337 | 7e7c5e4c | balrog | s->channel = (val >> 10) & 0xf; |
338 | 7e7c5e4c | balrog | s->irqst |= 1 << retu_int_adcs;
|
339 | 7e7c5e4c | balrog | retu_interrupt_update(s); |
340 | 7e7c5e4c | balrog | break;
|
341 | 7e7c5e4c | balrog | case RETU_REG_ADCSCR:
|
342 | 7e7c5e4c | balrog | s->sample &= ~val; |
343 | 7e7c5e4c | balrog | break;
|
344 | 7e7c5e4c | balrog | |
345 | 7e7c5e4c | balrog | case RETU_REG_AFCR:
|
346 | 7e7c5e4c | balrog | case RETU_REG_ANTIFR:
|
347 | 7e7c5e4c | balrog | case RETU_REG_CALIBR:
|
348 | 7e7c5e4c | balrog | |
349 | 7e7c5e4c | balrog | case RETU_REG_CCR1:
|
350 | 7e7c5e4c | balrog | s->cc[0] = val;
|
351 | 7e7c5e4c | balrog | break;
|
352 | 7e7c5e4c | balrog | case RETU_REG_CCR2:
|
353 | 7e7c5e4c | balrog | s->cc[1] = val;
|
354 | 7e7c5e4c | balrog | break;
|
355 | 7e7c5e4c | balrog | |
356 | 7e7c5e4c | balrog | case RETU_REG_RCTRL_CLR:
|
357 | 7e7c5e4c | balrog | case RETU_REG_RCTRL_SET:
|
358 | 7e7c5e4c | balrog | /* TODO */
|
359 | 7e7c5e4c | balrog | break;
|
360 | 7e7c5e4c | balrog | |
361 | 7e7c5e4c | balrog | case RETU_REG_WATCHDOG:
|
362 | 7e7c5e4c | balrog | if (val == 0 && (s->cc[0] & 2)) |
363 | 7e7c5e4c | balrog | qemu_system_shutdown_request(); |
364 | 7e7c5e4c | balrog | break;
|
365 | 7e7c5e4c | balrog | |
366 | 7e7c5e4c | balrog | case RETU_REG_TXCR:
|
367 | 7e7c5e4c | balrog | case RETU_REG_AUDTXR:
|
368 | 7e7c5e4c | balrog | case RETU_REG_AUDPAR:
|
369 | 7e7c5e4c | balrog | case RETU_REG_AUDRXR1:
|
370 | 7e7c5e4c | balrog | case RETU_REG_AUDRXR2:
|
371 | 7e7c5e4c | balrog | case RETU_REG_SGR1:
|
372 | 7e7c5e4c | balrog | case RETU_REG_SCR1:
|
373 | 7e7c5e4c | balrog | case RETU_REG_SGR2:
|
374 | 7e7c5e4c | balrog | case RETU_REG_SCR2:
|
375 | 7e7c5e4c | balrog | /* TODO */
|
376 | 7e7c5e4c | balrog | break;
|
377 | 7e7c5e4c | balrog | |
378 | 7e7c5e4c | balrog | default:
|
379 | 7e7c5e4c | balrog | cpu_abort(cpu_single_env, "%s: bad register %02x\n",
|
380 | 7e7c5e4c | balrog | __FUNCTION__, reg); |
381 | 7e7c5e4c | balrog | } |
382 | 7e7c5e4c | balrog | } |
383 | 7e7c5e4c | balrog | |
384 | 7e7c5e4c | balrog | static void retu_io(void *opaque, int rw, int reg, uint16_t *val) |
385 | 7e7c5e4c | balrog | { |
386 | 7e7c5e4c | balrog | struct cbus_retu_s *s = (struct cbus_retu_s *) opaque; |
387 | 7e7c5e4c | balrog | |
388 | 7e7c5e4c | balrog | if (rw)
|
389 | 7e7c5e4c | balrog | *val = retu_read(s, reg); |
390 | 7e7c5e4c | balrog | else
|
391 | 7e7c5e4c | balrog | retu_write(s, reg, *val); |
392 | 7e7c5e4c | balrog | } |
393 | 7e7c5e4c | balrog | |
394 | 7e7c5e4c | balrog | void *retu_init(qemu_irq irq, int vilma) |
395 | 7e7c5e4c | balrog | { |
396 | 7e7c5e4c | balrog | struct cbus_retu_s *s = (struct cbus_retu_s *) qemu_mallocz(sizeof(*s)); |
397 | 7e7c5e4c | balrog | |
398 | 7e7c5e4c | balrog | s->irq = irq; |
399 | 7e7c5e4c | balrog | s->irqen = 0xffff;
|
400 | 7e7c5e4c | balrog | s->irqst = 0x0000;
|
401 | 7e7c5e4c | balrog | s->status = 0x0020;
|
402 | 7e7c5e4c | balrog | s->is_vilma = !!vilma; |
403 | 7e7c5e4c | balrog | s->rtc.cal = 0x01;
|
404 | 7e7c5e4c | balrog | s->result[retu_adc_bsi] = 0x3c2;
|
405 | 7e7c5e4c | balrog | s->result[retu_adc_batt_temp] = 0x0fc;
|
406 | 7e7c5e4c | balrog | s->result[retu_adc_chg_volt] = 0x165;
|
407 | 7e7c5e4c | balrog | s->result[retu_adc_head_det] = 123;
|
408 | 7e7c5e4c | balrog | s->result[retu_adc_hook_det] = 1023;
|
409 | 7e7c5e4c | balrog | s->result[retu_adc_rf_gp] = 0x11;
|
410 | 7e7c5e4c | balrog | s->result[retu_adc_tx_det] = 0x11;
|
411 | 7e7c5e4c | balrog | s->result[retu_adc_batt_volt] = 0x250;
|
412 | 7e7c5e4c | balrog | s->result[retu_adc_sens] = 2;
|
413 | 7e7c5e4c | balrog | s->result[retu_adc_sens_temp] = 0x11;
|
414 | 7e7c5e4c | balrog | s->result[retu_adc_bbatt_volt] = 0x3d0;
|
415 | 7e7c5e4c | balrog | s->result[retu_adc_self_temp] = 0x330;
|
416 | 7e7c5e4c | balrog | |
417 | 7e7c5e4c | balrog | s->cbus.opaque = s; |
418 | 7e7c5e4c | balrog | s->cbus.io = retu_io; |
419 | 7e7c5e4c | balrog | s->cbus.addr = 1;
|
420 | 7e7c5e4c | balrog | |
421 | 7e7c5e4c | balrog | return &s->cbus;
|
422 | 7e7c5e4c | balrog | } |
423 | 7e7c5e4c | balrog | |
424 | 7e7c5e4c | balrog | void retu_key_event(void *retu, int state) |
425 | 7e7c5e4c | balrog | { |
426 | 7e7c5e4c | balrog | struct cbus_slave_s *slave = (struct cbus_slave_s *) retu; |
427 | 7e7c5e4c | balrog | struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque; |
428 | 7e7c5e4c | balrog | |
429 | 7e7c5e4c | balrog | s->irqst |= 1 << retu_int_pwr;
|
430 | 7e7c5e4c | balrog | retu_interrupt_update(s); |
431 | 7e7c5e4c | balrog | |
432 | 7e7c5e4c | balrog | if (state)
|
433 | 7e7c5e4c | balrog | s->status &= ~(1 << 5); |
434 | 7e7c5e4c | balrog | else
|
435 | 7e7c5e4c | balrog | s->status |= 1 << 5; |
436 | 7e7c5e4c | balrog | } |
437 | 7e7c5e4c | balrog | |
438 | 7e7c5e4c | balrog | void retu_head_event(void *retu, int state) |
439 | 7e7c5e4c | balrog | { |
440 | 7e7c5e4c | balrog | struct cbus_slave_s *slave = (struct cbus_slave_s *) retu; |
441 | 7e7c5e4c | balrog | struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque; |
442 | 7e7c5e4c | balrog | |
443 | 7e7c5e4c | balrog | if ((s->cc[0] & 0x500) == 0x500) { /* TODO: Which bits? */ |
444 | 7e7c5e4c | balrog | /* TODO: reissue the interrupt every 100ms or so. */
|
445 | 7e7c5e4c | balrog | s->irqst |= 1 << retu_int_head;
|
446 | 7e7c5e4c | balrog | retu_interrupt_update(s); |
447 | 7e7c5e4c | balrog | } |
448 | 7e7c5e4c | balrog | |
449 | 7e7c5e4c | balrog | if (state)
|
450 | 7e7c5e4c | balrog | s->result[retu_adc_head_det] = 50;
|
451 | 7e7c5e4c | balrog | else
|
452 | 7e7c5e4c | balrog | s->result[retu_adc_head_det] = 123;
|
453 | 7e7c5e4c | balrog | } |
454 | 7e7c5e4c | balrog | |
455 | 7e7c5e4c | balrog | void retu_hook_event(void *retu, int state) |
456 | 7e7c5e4c | balrog | { |
457 | 7e7c5e4c | balrog | struct cbus_slave_s *slave = (struct cbus_slave_s *) retu; |
458 | 7e7c5e4c | balrog | struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque; |
459 | 7e7c5e4c | balrog | |
460 | 7e7c5e4c | balrog | if ((s->cc[0] & 0x500) == 0x500) { |
461 | 7e7c5e4c | balrog | /* TODO: reissue the interrupt every 100ms or so. */
|
462 | 7e7c5e4c | balrog | s->irqst |= 1 << retu_int_hook;
|
463 | 7e7c5e4c | balrog | retu_interrupt_update(s); |
464 | 7e7c5e4c | balrog | } |
465 | 7e7c5e4c | balrog | |
466 | 7e7c5e4c | balrog | if (state)
|
467 | 7e7c5e4c | balrog | s->result[retu_adc_hook_det] = 50;
|
468 | 7e7c5e4c | balrog | else
|
469 | 7e7c5e4c | balrog | s->result[retu_adc_hook_det] = 123;
|
470 | 7e7c5e4c | balrog | } |
471 | 7e7c5e4c | balrog | |
472 | 7e7c5e4c | balrog | /* Tahvo/Betty */
|
473 | 7e7c5e4c | balrog | struct cbus_tahvo_s {
|
474 | 7e7c5e4c | balrog | uint16_t irqst; |
475 | 7e7c5e4c | balrog | uint16_t irqen; |
476 | 7e7c5e4c | balrog | uint8_t charger; |
477 | 7e7c5e4c | balrog | uint8_t backlight; |
478 | 7e7c5e4c | balrog | uint16_t usbr; |
479 | 7e7c5e4c | balrog | uint16_t power; |
480 | 7e7c5e4c | balrog | |
481 | 7e7c5e4c | balrog | int is_betty;
|
482 | 7e7c5e4c | balrog | qemu_irq irq; |
483 | 7e7c5e4c | balrog | struct cbus_slave_s cbus;
|
484 | 7e7c5e4c | balrog | }; |
485 | 7e7c5e4c | balrog | |
486 | 7e7c5e4c | balrog | static void tahvo_interrupt_update(struct cbus_tahvo_s *s) |
487 | 7e7c5e4c | balrog | { |
488 | 7e7c5e4c | balrog | qemu_set_irq(s->irq, s->irqst & ~s->irqen); |
489 | 7e7c5e4c | balrog | } |
490 | 7e7c5e4c | balrog | |
491 | 7e7c5e4c | balrog | #define TAHVO_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ |
492 | 7e7c5e4c | balrog | #define TAHVO_REG_IDR 0x01 /* (T) Interrupt ID */ |
493 | 7e7c5e4c | balrog | #define TAHVO_REG_IDSR 0x02 /* (RO) Interrupt status */ |
494 | 7e7c5e4c | balrog | #define TAHVO_REG_IMR 0x03 /* (RW) Interrupt mask */ |
495 | 7e7c5e4c | balrog | #define TAHVO_REG_CHAPWMR 0x04 /* (RW) Charger PWM */ |
496 | 7e7c5e4c | balrog | #define TAHVO_REG_LEDPWMR 0x05 /* (RW) LED PWM */ |
497 | 7e7c5e4c | balrog | #define TAHVO_REG_USBR 0x06 /* (RW) USB control */ |
498 | 7e7c5e4c | balrog | #define TAHVO_REG_RCR 0x07 /* (RW) Some kind of power management */ |
499 | 7e7c5e4c | balrog | #define TAHVO_REG_CCR1 0x08 /* (RW) Common control register 1 */ |
500 | 7e7c5e4c | balrog | #define TAHVO_REG_CCR2 0x09 /* (RW) Common control register 2 */ |
501 | 7e7c5e4c | balrog | #define TAHVO_REG_TESTR1 0x0a /* (RW) Test register 1 */ |
502 | 7e7c5e4c | balrog | #define TAHVO_REG_TESTR2 0x0b /* (RW) Test register 2 */ |
503 | 7e7c5e4c | balrog | #define TAHVO_REG_NOPR 0x0c /* (RW) Number of periods */ |
504 | 7e7c5e4c | balrog | #define TAHVO_REG_FRR 0x0d /* (RO) FR */ |
505 | 7e7c5e4c | balrog | |
506 | 7e7c5e4c | balrog | static inline uint16_t tahvo_read(struct cbus_tahvo_s *s, int reg) |
507 | 7e7c5e4c | balrog | { |
508 | 7e7c5e4c | balrog | #ifdef DEBUG
|
509 | 7e7c5e4c | balrog | printf("TAHVO read at %02x\n", reg);
|
510 | 7e7c5e4c | balrog | #endif
|
511 | 7e7c5e4c | balrog | |
512 | 7e7c5e4c | balrog | switch (reg) {
|
513 | 7e7c5e4c | balrog | case TAHVO_REG_ASICR:
|
514 | 7e7c5e4c | balrog | return 0x0021 | (s->is_betty ? 0x0b00 : 0x0300); /* 22 in N810 */ |
515 | 7e7c5e4c | balrog | |
516 | 7e7c5e4c | balrog | case TAHVO_REG_IDR:
|
517 | 7e7c5e4c | balrog | case TAHVO_REG_IDSR: /* XXX: what does this do? */ |
518 | 7e7c5e4c | balrog | return s->irqst;
|
519 | 7e7c5e4c | balrog | |
520 | 7e7c5e4c | balrog | case TAHVO_REG_IMR:
|
521 | 7e7c5e4c | balrog | return s->irqen;
|
522 | 7e7c5e4c | balrog | |
523 | 7e7c5e4c | balrog | case TAHVO_REG_CHAPWMR:
|
524 | 7e7c5e4c | balrog | return s->charger;
|
525 | 7e7c5e4c | balrog | |
526 | 7e7c5e4c | balrog | case TAHVO_REG_LEDPWMR:
|
527 | 7e7c5e4c | balrog | return s->backlight;
|
528 | 7e7c5e4c | balrog | |
529 | 7e7c5e4c | balrog | case TAHVO_REG_USBR:
|
530 | 7e7c5e4c | balrog | return s->usbr;
|
531 | 7e7c5e4c | balrog | |
532 | 7e7c5e4c | balrog | case TAHVO_REG_RCR:
|
533 | 7e7c5e4c | balrog | return s->power;
|
534 | 7e7c5e4c | balrog | |
535 | 7e7c5e4c | balrog | case TAHVO_REG_CCR1:
|
536 | 7e7c5e4c | balrog | case TAHVO_REG_CCR2:
|
537 | 7e7c5e4c | balrog | case TAHVO_REG_TESTR1:
|
538 | 7e7c5e4c | balrog | case TAHVO_REG_TESTR2:
|
539 | 7e7c5e4c | balrog | case TAHVO_REG_NOPR:
|
540 | 7e7c5e4c | balrog | case TAHVO_REG_FRR:
|
541 | 7e7c5e4c | balrog | return 0x0000; |
542 | 7e7c5e4c | balrog | |
543 | 7e7c5e4c | balrog | default:
|
544 | 7e7c5e4c | balrog | cpu_abort(cpu_single_env, "%s: bad register %02x\n",
|
545 | 7e7c5e4c | balrog | __FUNCTION__, reg); |
546 | 7e7c5e4c | balrog | } |
547 | 7e7c5e4c | balrog | } |
548 | 7e7c5e4c | balrog | |
549 | 7e7c5e4c | balrog | static inline void tahvo_write(struct cbus_tahvo_s *s, int reg, uint16_t val) |
550 | 7e7c5e4c | balrog | { |
551 | 7e7c5e4c | balrog | #ifdef DEBUG
|
552 | 7e7c5e4c | balrog | printf("TAHVO write of %04x at %02x\n", val, reg);
|
553 | 7e7c5e4c | balrog | #endif
|
554 | 7e7c5e4c | balrog | |
555 | 7e7c5e4c | balrog | switch (reg) {
|
556 | 7e7c5e4c | balrog | case TAHVO_REG_IDR:
|
557 | 7e7c5e4c | balrog | s->irqst ^= val; |
558 | 7e7c5e4c | balrog | tahvo_interrupt_update(s); |
559 | 7e7c5e4c | balrog | break;
|
560 | 7e7c5e4c | balrog | |
561 | 7e7c5e4c | balrog | case TAHVO_REG_IMR:
|
562 | 7e7c5e4c | balrog | s->irqen = val; |
563 | 7e7c5e4c | balrog | tahvo_interrupt_update(s); |
564 | 7e7c5e4c | balrog | break;
|
565 | 7e7c5e4c | balrog | |
566 | 7e7c5e4c | balrog | case TAHVO_REG_CHAPWMR:
|
567 | 7e7c5e4c | balrog | s->charger = val; |
568 | 7e7c5e4c | balrog | break;
|
569 | 7e7c5e4c | balrog | |
570 | 7e7c5e4c | balrog | case TAHVO_REG_LEDPWMR:
|
571 | 7e7c5e4c | balrog | if (s->backlight != (val & 0x7f)) { |
572 | 7e7c5e4c | balrog | s->backlight = val & 0x7f;
|
573 | 7e7c5e4c | balrog | printf("%s: LCD backlight now at %i / 127\n",
|
574 | 7e7c5e4c | balrog | __FUNCTION__, s->backlight); |
575 | 7e7c5e4c | balrog | } |
576 | 7e7c5e4c | balrog | break;
|
577 | 7e7c5e4c | balrog | |
578 | 7e7c5e4c | balrog | case TAHVO_REG_USBR:
|
579 | 7e7c5e4c | balrog | s->usbr = val; |
580 | 7e7c5e4c | balrog | break;
|
581 | 7e7c5e4c | balrog | |
582 | 7e7c5e4c | balrog | case TAHVO_REG_RCR:
|
583 | 7e7c5e4c | balrog | s->power = val; |
584 | 7e7c5e4c | balrog | break;
|
585 | 7e7c5e4c | balrog | |
586 | 7e7c5e4c | balrog | case TAHVO_REG_CCR1:
|
587 | 7e7c5e4c | balrog | case TAHVO_REG_CCR2:
|
588 | 7e7c5e4c | balrog | case TAHVO_REG_TESTR1:
|
589 | 7e7c5e4c | balrog | case TAHVO_REG_TESTR2:
|
590 | 7e7c5e4c | balrog | case TAHVO_REG_NOPR:
|
591 | 7e7c5e4c | balrog | case TAHVO_REG_FRR:
|
592 | 7e7c5e4c | balrog | break;
|
593 | 7e7c5e4c | balrog | |
594 | 7e7c5e4c | balrog | default:
|
595 | 7e7c5e4c | balrog | cpu_abort(cpu_single_env, "%s: bad register %02x\n",
|
596 | 7e7c5e4c | balrog | __FUNCTION__, reg); |
597 | 7e7c5e4c | balrog | } |
598 | 7e7c5e4c | balrog | } |
599 | 7e7c5e4c | balrog | |
600 | 7e7c5e4c | balrog | static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val) |
601 | 7e7c5e4c | balrog | { |
602 | 7e7c5e4c | balrog | struct cbus_tahvo_s *s = (struct cbus_tahvo_s *) opaque; |
603 | 7e7c5e4c | balrog | |
604 | 7e7c5e4c | balrog | if (rw)
|
605 | 7e7c5e4c | balrog | *val = tahvo_read(s, reg); |
606 | 7e7c5e4c | balrog | else
|
607 | 7e7c5e4c | balrog | tahvo_write(s, reg, *val); |
608 | 7e7c5e4c | balrog | } |
609 | 7e7c5e4c | balrog | |
610 | 7e7c5e4c | balrog | void *tahvo_init(qemu_irq irq, int betty) |
611 | 7e7c5e4c | balrog | { |
612 | 7e7c5e4c | balrog | struct cbus_tahvo_s *s = (struct cbus_tahvo_s *) qemu_mallocz(sizeof(*s)); |
613 | 7e7c5e4c | balrog | |
614 | 7e7c5e4c | balrog | s->irq = irq; |
615 | 7e7c5e4c | balrog | s->irqen = 0xffff;
|
616 | 7e7c5e4c | balrog | s->irqst = 0x0000;
|
617 | 7e7c5e4c | balrog | s->is_betty = !!betty; |
618 | 7e7c5e4c | balrog | |
619 | 7e7c5e4c | balrog | s->cbus.opaque = s; |
620 | 7e7c5e4c | balrog | s->cbus.io = tahvo_io; |
621 | 7e7c5e4c | balrog | s->cbus.addr = 2;
|
622 | 7e7c5e4c | balrog | |
623 | 7e7c5e4c | balrog | return &s->cbus;
|
624 | 7e7c5e4c | balrog | } |