root / hw / sparc32_dma.c @ 1a4f5971
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1 | 67e999be | bellard | /*
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2 | 67e999be | bellard | * QEMU Sparc32 DMA controller emulation
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3 | 67e999be | bellard | *
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4 | 67e999be | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | 67e999be | bellard | *
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6 | 6f57bbf4 | Artyom Tarasenko | * Modifications:
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7 | 6f57bbf4 | Artyom Tarasenko | * 2010-Feb-14 Artyom Tarasenko : reworked irq generation
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8 | 6f57bbf4 | Artyom Tarasenko | *
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9 | 67e999be | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | 67e999be | bellard | * of this software and associated documentation files (the "Software"), to deal
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11 | 67e999be | bellard | * in the Software without restriction, including without limitation the rights
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12 | 67e999be | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | 67e999be | bellard | * copies of the Software, and to permit persons to whom the Software is
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14 | 67e999be | bellard | * furnished to do so, subject to the following conditions:
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15 | 67e999be | bellard | *
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16 | 67e999be | bellard | * The above copyright notice and this permission notice shall be included in
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17 | 67e999be | bellard | * all copies or substantial portions of the Software.
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18 | 67e999be | bellard | *
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19 | 67e999be | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | 67e999be | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | 67e999be | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | 67e999be | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | 67e999be | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | 67e999be | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | 67e999be | bellard | * THE SOFTWARE.
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26 | 67e999be | bellard | */
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27 | 6f6260c7 | Blue Swirl | |
28 | 87ecb68b | pbrook | #include "hw.h" |
29 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
30 | 87ecb68b | pbrook | #include "sun4m.h" |
31 | 6f6260c7 | Blue Swirl | #include "sysbus.h" |
32 | 67e999be | bellard | |
33 | 67e999be | bellard | /* debug DMA */
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34 | 67e999be | bellard | //#define DEBUG_DMA
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35 | 67e999be | bellard | |
36 | 67e999be | bellard | /*
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37 | 67e999be | bellard | * This is the DMA controller part of chip STP2000 (Master I/O), also
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38 | 67e999be | bellard | * produced as NCR89C100. See
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39 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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40 | 67e999be | bellard | * and
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41 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
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42 | 67e999be | bellard | */
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43 | 67e999be | bellard | |
44 | 67e999be | bellard | #ifdef DEBUG_DMA
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45 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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46 | 001faf32 | Blue Swirl | do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0) |
47 | 67e999be | bellard | #else
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48 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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49 | 67e999be | bellard | #endif
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50 | 67e999be | bellard | |
51 | 5aca8c3b | blueswir1 | #define DMA_REGS 4 |
52 | 5aca8c3b | blueswir1 | #define DMA_SIZE (4 * sizeof(uint32_t)) |
53 | 09723aa1 | blueswir1 | /* We need the mask, because one instance of the device is not page
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54 | 09723aa1 | blueswir1 | aligned (ledma, start address 0x0010) */
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55 | 09723aa1 | blueswir1 | #define DMA_MASK (DMA_SIZE - 1) |
56 | 67e999be | bellard | |
57 | 67e999be | bellard | #define DMA_VER 0xa0000000 |
58 | 67e999be | bellard | #define DMA_INTR 1 |
59 | 67e999be | bellard | #define DMA_INTREN 0x10 |
60 | 67e999be | bellard | #define DMA_WRITE_MEM 0x100 |
61 | 67e999be | bellard | #define DMA_LOADED 0x04000000 |
62 | 5aca8c3b | blueswir1 | #define DMA_DRAIN_FIFO 0x40 |
63 | 67e999be | bellard | #define DMA_RESET 0x80 |
64 | 67e999be | bellard | |
65 | 65899fe3 | Artyom Tarasenko | /* XXX SCSI and ethernet should have different read-only bit masks */
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66 | 65899fe3 | Artyom Tarasenko | #define DMA_CSR_RO_MASK 0xfe000007 |
67 | 65899fe3 | Artyom Tarasenko | |
68 | 67e999be | bellard | typedef struct DMAState DMAState; |
69 | 67e999be | bellard | |
70 | 67e999be | bellard | struct DMAState {
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71 | 6f6260c7 | Blue Swirl | SysBusDevice busdev; |
72 | 67e999be | bellard | uint32_t dmaregs[DMA_REGS]; |
73 | 5aca8c3b | blueswir1 | qemu_irq irq; |
74 | 2d069bab | blueswir1 | void *iommu;
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75 | 2d069bab | blueswir1 | qemu_irq dev_reset; |
76 | 67e999be | bellard | }; |
77 | 67e999be | bellard | |
78 | 9b94dc32 | bellard | /* Note: on sparc, the lance 16 bit bus is swapped */
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79 | c227f099 | Anthony Liguori | void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
80 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
81 | 67e999be | bellard | { |
82 | 67e999be | bellard | DMAState *s = opaque; |
83 | 9b94dc32 | bellard | int i;
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84 | 67e999be | bellard | |
85 | 67e999be | bellard | DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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86 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
87 | 5aca8c3b | blueswir1 | addr |= s->dmaregs[3];
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88 | 9b94dc32 | bellard | if (do_bswap) {
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89 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
90 | 9b94dc32 | bellard | } else {
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91 | 9b94dc32 | bellard | addr &= ~1;
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92 | 9b94dc32 | bellard | len &= ~1;
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93 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
94 | 9b94dc32 | bellard | for(i = 0; i < len; i += 2) { |
95 | 9b94dc32 | bellard | bswap16s((uint16_t *)(buf + i)); |
96 | 9b94dc32 | bellard | } |
97 | 9b94dc32 | bellard | } |
98 | 67e999be | bellard | } |
99 | 67e999be | bellard | |
100 | c227f099 | Anthony Liguori | void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
101 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
102 | 67e999be | bellard | { |
103 | 67e999be | bellard | DMAState *s = opaque; |
104 | 9b94dc32 | bellard | int l, i;
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105 | 9b94dc32 | bellard | uint16_t tmp_buf[32];
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106 | 67e999be | bellard | |
107 | 67e999be | bellard | DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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108 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
109 | 5aca8c3b | blueswir1 | addr |= s->dmaregs[3];
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110 | 9b94dc32 | bellard | if (do_bswap) {
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111 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, buf, len); |
112 | 9b94dc32 | bellard | } else {
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113 | 9b94dc32 | bellard | addr &= ~1;
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114 | 9b94dc32 | bellard | len &= ~1;
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115 | 9b94dc32 | bellard | while (len > 0) { |
116 | 9b94dc32 | bellard | l = len; |
117 | 9b94dc32 | bellard | if (l > sizeof(tmp_buf)) |
118 | 9b94dc32 | bellard | l = sizeof(tmp_buf);
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119 | 9b94dc32 | bellard | for(i = 0; i < l; i += 2) { |
120 | 9b94dc32 | bellard | tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
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121 | 9b94dc32 | bellard | } |
122 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l); |
123 | 9b94dc32 | bellard | len -= l; |
124 | 9b94dc32 | bellard | buf += l; |
125 | 9b94dc32 | bellard | addr += l; |
126 | 9b94dc32 | bellard | } |
127 | 9b94dc32 | bellard | } |
128 | 67e999be | bellard | } |
129 | 67e999be | bellard | |
130 | 70c0de96 | blueswir1 | static void dma_set_irq(void *opaque, int irq, int level) |
131 | 67e999be | bellard | { |
132 | 67e999be | bellard | DMAState *s = opaque; |
133 | 70c0de96 | blueswir1 | if (level) {
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134 | 70c0de96 | blueswir1 | s->dmaregs[0] |= DMA_INTR;
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135 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTREN) { |
136 | 6f57bbf4 | Artyom Tarasenko | DPRINTF("Raise IRQ\n");
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137 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_raise(s->irq); |
138 | 6f57bbf4 | Artyom Tarasenko | } |
139 | 70c0de96 | blueswir1 | } else {
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140 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTR) { |
141 | 6f57bbf4 | Artyom Tarasenko | s->dmaregs[0] &= ~DMA_INTR;
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142 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTREN) { |
143 | 6f57bbf4 | Artyom Tarasenko | DPRINTF("Lower IRQ\n");
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144 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_lower(s->irq); |
145 | 6f57bbf4 | Artyom Tarasenko | } |
146 | 6f57bbf4 | Artyom Tarasenko | } |
147 | 70c0de96 | blueswir1 | } |
148 | 67e999be | bellard | } |
149 | 67e999be | bellard | |
150 | 67e999be | bellard | void espdma_memory_read(void *opaque, uint8_t *buf, int len) |
151 | 67e999be | bellard | { |
152 | 67e999be | bellard | DMAState *s = opaque; |
153 | 67e999be | bellard | |
154 | 67e999be | bellard | DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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155 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
156 | 67e999be | bellard | sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
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157 | 67e999be | bellard | s->dmaregs[1] += len;
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158 | 67e999be | bellard | } |
159 | 67e999be | bellard | |
160 | 67e999be | bellard | void espdma_memory_write(void *opaque, uint8_t *buf, int len) |
161 | 67e999be | bellard | { |
162 | 67e999be | bellard | DMAState *s = opaque; |
163 | 67e999be | bellard | |
164 | 67e999be | bellard | DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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165 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
166 | 67e999be | bellard | sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
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167 | 67e999be | bellard | s->dmaregs[1] += len;
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168 | 67e999be | bellard | } |
169 | 67e999be | bellard | |
170 | c227f099 | Anthony Liguori | static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr) |
171 | 67e999be | bellard | { |
172 | 67e999be | bellard | DMAState *s = opaque; |
173 | 67e999be | bellard | uint32_t saddr; |
174 | 67e999be | bellard | |
175 | 09723aa1 | blueswir1 | saddr = (addr & DMA_MASK) >> 2;
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176 | 5aca8c3b | blueswir1 | DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr, |
177 | 5aca8c3b | blueswir1 | s->dmaregs[saddr]); |
178 | 67e999be | bellard | |
179 | 67e999be | bellard | return s->dmaregs[saddr];
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180 | 67e999be | bellard | } |
181 | 67e999be | bellard | |
182 | c227f099 | Anthony Liguori | static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
183 | 67e999be | bellard | { |
184 | 67e999be | bellard | DMAState *s = opaque; |
185 | 67e999be | bellard | uint32_t saddr; |
186 | 67e999be | bellard | |
187 | 09723aa1 | blueswir1 | saddr = (addr & DMA_MASK) >> 2;
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188 | 5aca8c3b | blueswir1 | DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr, |
189 | 5aca8c3b | blueswir1 | s->dmaregs[saddr], val); |
190 | 67e999be | bellard | switch (saddr) {
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191 | 67e999be | bellard | case 0: |
192 | 6f57bbf4 | Artyom Tarasenko | if (val & DMA_INTREN) {
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193 | 65899fe3 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTR) { |
194 | 6f57bbf4 | Artyom Tarasenko | DPRINTF("Raise IRQ\n");
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195 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_raise(s->irq); |
196 | 6f57bbf4 | Artyom Tarasenko | } |
197 | 6f57bbf4 | Artyom Tarasenko | } else {
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198 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) { |
199 | 6f57bbf4 | Artyom Tarasenko | DPRINTF("Lower IRQ\n");
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200 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_lower(s->irq); |
201 | 6f57bbf4 | Artyom Tarasenko | } |
202 | d537cf6c | pbrook | } |
203 | 67e999be | bellard | if (val & DMA_RESET) {
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204 | 2d069bab | blueswir1 | qemu_irq_raise(s->dev_reset); |
205 | 2d069bab | blueswir1 | qemu_irq_lower(s->dev_reset); |
206 | 5aca8c3b | blueswir1 | } else if (val & DMA_DRAIN_FIFO) { |
207 | 5aca8c3b | blueswir1 | val &= ~DMA_DRAIN_FIFO; |
208 | 67e999be | bellard | } else if (val == 0) |
209 | 5aca8c3b | blueswir1 | val = DMA_DRAIN_FIFO; |
210 | 65899fe3 | Artyom Tarasenko | val &= ~DMA_CSR_RO_MASK; |
211 | 67e999be | bellard | val |= DMA_VER; |
212 | 65899fe3 | Artyom Tarasenko | s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val; |
213 | 67e999be | bellard | break;
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214 | 67e999be | bellard | case 1: |
215 | 67e999be | bellard | s->dmaregs[0] |= DMA_LOADED;
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216 | 65899fe3 | Artyom Tarasenko | /* fall through */
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217 | 67e999be | bellard | default:
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218 | 65899fe3 | Artyom Tarasenko | s->dmaregs[saddr] = val; |
219 | 67e999be | bellard | break;
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220 | 67e999be | bellard | } |
221 | 67e999be | bellard | } |
222 | 67e999be | bellard | |
223 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const dma_mem_read[3] = { |
224 | 7c560456 | blueswir1 | NULL,
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225 | 7c560456 | blueswir1 | NULL,
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226 | 67e999be | bellard | dma_mem_readl, |
227 | 67e999be | bellard | }; |
228 | 67e999be | bellard | |
229 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const dma_mem_write[3] = { |
230 | 7c560456 | blueswir1 | NULL,
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231 | 7c560456 | blueswir1 | NULL,
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232 | 67e999be | bellard | dma_mem_writel, |
233 | 67e999be | bellard | }; |
234 | 67e999be | bellard | |
235 | 49ef6c90 | Blue Swirl | static void dma_reset(DeviceState *d) |
236 | 67e999be | bellard | { |
237 | 49ef6c90 | Blue Swirl | DMAState *s = container_of(d, DMAState, busdev.qdev); |
238 | 67e999be | bellard | |
239 | 5aca8c3b | blueswir1 | memset(s->dmaregs, 0, DMA_SIZE);
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240 | 67e999be | bellard | s->dmaregs[0] = DMA_VER;
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241 | 67e999be | bellard | } |
242 | 67e999be | bellard | |
243 | 75c497dc | Blue Swirl | static const VMStateDescription vmstate_dma = { |
244 | 75c497dc | Blue Swirl | .name ="sparc32_dma",
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245 | 75c497dc | Blue Swirl | .version_id = 2,
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246 | 75c497dc | Blue Swirl | .minimum_version_id = 2,
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247 | 75c497dc | Blue Swirl | .minimum_version_id_old = 2,
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248 | 75c497dc | Blue Swirl | .fields = (VMStateField []) { |
249 | 75c497dc | Blue Swirl | VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS), |
250 | 75c497dc | Blue Swirl | VMSTATE_END_OF_LIST() |
251 | 75c497dc | Blue Swirl | } |
252 | 75c497dc | Blue Swirl | }; |
253 | 67e999be | bellard | |
254 | 81a322d4 | Gerd Hoffmann | static int sparc32_dma_init1(SysBusDevice *dev) |
255 | 6f6260c7 | Blue Swirl | { |
256 | 6f6260c7 | Blue Swirl | DMAState *s = FROM_SYSBUS(DMAState, dev); |
257 | 6f6260c7 | Blue Swirl | int dma_io_memory;
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258 | 67e999be | bellard | |
259 | 6f6260c7 | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
260 | 67e999be | bellard | |
261 | 1eed09cb | Avi Kivity | dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s); |
262 | 6f6260c7 | Blue Swirl | sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory); |
263 | 67e999be | bellard | |
264 | 6f6260c7 | Blue Swirl | qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
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265 | 74ff8d90 | Blue Swirl | qdev_init_gpio_out(&dev->qdev, &s->dev_reset, 1);
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266 | 49ef6c90 | Blue Swirl | |
267 | 81a322d4 | Gerd Hoffmann | return 0; |
268 | 6f6260c7 | Blue Swirl | } |
269 | 67e999be | bellard | |
270 | 6f6260c7 | Blue Swirl | static SysBusDeviceInfo sparc32_dma_info = {
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271 | 6f6260c7 | Blue Swirl | .init = sparc32_dma_init1, |
272 | 6f6260c7 | Blue Swirl | .qdev.name = "sparc32_dma",
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273 | 6f6260c7 | Blue Swirl | .qdev.size = sizeof(DMAState),
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274 | 49ef6c90 | Blue Swirl | .qdev.vmsd = &vmstate_dma, |
275 | 49ef6c90 | Blue Swirl | .qdev.reset = dma_reset, |
276 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
277 | 3180d772 | Gerd Hoffmann | DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu),
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278 | 3180d772 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
279 | 6f6260c7 | Blue Swirl | } |
280 | 6f6260c7 | Blue Swirl | }; |
281 | 6f6260c7 | Blue Swirl | |
282 | 6f6260c7 | Blue Swirl | static void sparc32_dma_register_devices(void) |
283 | 6f6260c7 | Blue Swirl | { |
284 | 6f6260c7 | Blue Swirl | sysbus_register_withprop(&sparc32_dma_info); |
285 | 67e999be | bellard | } |
286 | 6f6260c7 | Blue Swirl | |
287 | 6f6260c7 | Blue Swirl | device_init(sparc32_dma_register_devices) |