root / hw / omap_dss.c @ 1ae26a18
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1 | 827df9f3 | balrog | /*
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2 | 827df9f3 | balrog | * OMAP2 Display Subsystem.
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3 | 827df9f3 | balrog | *
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4 | 827df9f3 | balrog | * Copyright (C) 2008 Nokia Corporation
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5 | 827df9f3 | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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6 | 827df9f3 | balrog | *
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7 | 827df9f3 | balrog | * This program is free software; you can redistribute it and/or
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8 | 827df9f3 | balrog | * modify it under the terms of the GNU General Public License as
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9 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
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10 | 827df9f3 | balrog | * (at your option) version 3 of the License.
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11 | 827df9f3 | balrog | *
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12 | 827df9f3 | balrog | * This program is distributed in the hope that it will be useful,
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13 | 827df9f3 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 827df9f3 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 827df9f3 | balrog | * GNU General Public License for more details.
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16 | 827df9f3 | balrog | *
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17 | 827df9f3 | balrog | * You should have received a copy of the GNU General Public License
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18 | 827df9f3 | balrog | * along with this program; if not, write to the Free Software
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19 | 827df9f3 | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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20 | 827df9f3 | balrog | * MA 02111-1307 USA
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21 | 827df9f3 | balrog | */
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22 | 827df9f3 | balrog | #include "hw.h" |
23 | 827df9f3 | balrog | #include "console.h" |
24 | 827df9f3 | balrog | #include "omap.h" |
25 | 827df9f3 | balrog | |
26 | 827df9f3 | balrog | struct omap_dss_s {
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27 | 827df9f3 | balrog | target_phys_addr_t diss_base; |
28 | 827df9f3 | balrog | target_phys_addr_t disc_base; |
29 | 827df9f3 | balrog | target_phys_addr_t rfbi_base; |
30 | 827df9f3 | balrog | target_phys_addr_t venc_base; |
31 | 827df9f3 | balrog | target_phys_addr_t im3_base; |
32 | 827df9f3 | balrog | qemu_irq irq; |
33 | 827df9f3 | balrog | qemu_irq drq; |
34 | 827df9f3 | balrog | DisplayState *state; |
35 | 827df9f3 | balrog | |
36 | 827df9f3 | balrog | int autoidle;
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37 | 827df9f3 | balrog | int control;
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38 | 827df9f3 | balrog | int enable;
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39 | 827df9f3 | balrog | |
40 | 827df9f3 | balrog | struct omap_dss_panel_s {
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41 | 827df9f3 | balrog | int enable;
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42 | 827df9f3 | balrog | int nx;
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43 | 827df9f3 | balrog | int ny;
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44 | 827df9f3 | balrog | |
45 | 827df9f3 | balrog | int x;
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46 | 827df9f3 | balrog | int y;
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47 | 827df9f3 | balrog | } dig, lcd; |
48 | 827df9f3 | balrog | |
49 | 827df9f3 | balrog | struct {
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50 | 827df9f3 | balrog | uint32_t idlemode; |
51 | 827df9f3 | balrog | uint32_t irqst; |
52 | 827df9f3 | balrog | uint32_t irqen; |
53 | 827df9f3 | balrog | uint32_t control; |
54 | 827df9f3 | balrog | uint32_t config; |
55 | 827df9f3 | balrog | uint32_t capable; |
56 | f3d8b1eb | aurel32 | uint32_t timing[4];
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57 | 827df9f3 | balrog | int line;
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58 | 827df9f3 | balrog | uint32_t bg[2];
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59 | 827df9f3 | balrog | uint32_t trans[2];
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60 | 827df9f3 | balrog | |
61 | 827df9f3 | balrog | struct omap_dss_plane_s {
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62 | 827df9f3 | balrog | int enable;
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63 | 827df9f3 | balrog | int bpp;
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64 | 827df9f3 | balrog | int posx;
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65 | 827df9f3 | balrog | int posy;
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66 | 827df9f3 | balrog | int nx;
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67 | 827df9f3 | balrog | int ny;
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68 | 827df9f3 | balrog | |
69 | 827df9f3 | balrog | target_phys_addr_t addr[3];
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70 | 827df9f3 | balrog | |
71 | 827df9f3 | balrog | uint32_t attr; |
72 | 827df9f3 | balrog | uint32_t tresh; |
73 | 827df9f3 | balrog | int rowinc;
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74 | 827df9f3 | balrog | int colinc;
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75 | 827df9f3 | balrog | int wininc;
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76 | 827df9f3 | balrog | } l[3];
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77 | 827df9f3 | balrog | |
78 | 827df9f3 | balrog | int invalidate;
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79 | 827df9f3 | balrog | uint16_t palette[256];
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80 | 827df9f3 | balrog | } dispc; |
81 | 827df9f3 | balrog | |
82 | 827df9f3 | balrog | struct {
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83 | 827df9f3 | balrog | int idlemode;
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84 | 827df9f3 | balrog | uint32_t control; |
85 | 827df9f3 | balrog | int enable;
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86 | 827df9f3 | balrog | int pixels;
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87 | 827df9f3 | balrog | int busy;
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88 | 827df9f3 | balrog | int skiplines;
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89 | 827df9f3 | balrog | uint16_t rxbuf; |
90 | 827df9f3 | balrog | uint32_t config[2];
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91 | 827df9f3 | balrog | uint32_t time[4];
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92 | 827df9f3 | balrog | uint32_t data[6];
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93 | 827df9f3 | balrog | uint16_t vsync; |
94 | 827df9f3 | balrog | uint16_t hsync; |
95 | 827df9f3 | balrog | struct rfbi_chip_s *chip[2]; |
96 | 827df9f3 | balrog | } rfbi; |
97 | 827df9f3 | balrog | }; |
98 | 827df9f3 | balrog | |
99 | 827df9f3 | balrog | static void omap_dispc_interrupt_update(struct omap_dss_s *s) |
100 | 827df9f3 | balrog | { |
101 | 827df9f3 | balrog | qemu_set_irq(s->irq, s->dispc.irqst & s->dispc.irqen); |
102 | 827df9f3 | balrog | } |
103 | 827df9f3 | balrog | |
104 | 827df9f3 | balrog | static void omap_rfbi_reset(struct omap_dss_s *s) |
105 | 827df9f3 | balrog | { |
106 | 827df9f3 | balrog | s->rfbi.idlemode = 0;
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107 | 827df9f3 | balrog | s->rfbi.control = 2;
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108 | 827df9f3 | balrog | s->rfbi.enable = 0;
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109 | 827df9f3 | balrog | s->rfbi.pixels = 0;
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110 | 827df9f3 | balrog | s->rfbi.skiplines = 0;
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111 | 827df9f3 | balrog | s->rfbi.busy = 0;
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112 | 827df9f3 | balrog | s->rfbi.config[0] = 0x00310000; |
113 | 827df9f3 | balrog | s->rfbi.config[1] = 0x00310000; |
114 | 827df9f3 | balrog | s->rfbi.time[0] = 0; |
115 | 827df9f3 | balrog | s->rfbi.time[1] = 0; |
116 | 827df9f3 | balrog | s->rfbi.time[2] = 0; |
117 | 827df9f3 | balrog | s->rfbi.time[3] = 0; |
118 | 827df9f3 | balrog | s->rfbi.data[0] = 0; |
119 | 827df9f3 | balrog | s->rfbi.data[1] = 0; |
120 | 827df9f3 | balrog | s->rfbi.data[2] = 0; |
121 | 827df9f3 | balrog | s->rfbi.data[3] = 0; |
122 | 827df9f3 | balrog | s->rfbi.data[4] = 0; |
123 | 827df9f3 | balrog | s->rfbi.data[5] = 0; |
124 | 827df9f3 | balrog | s->rfbi.vsync = 0;
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125 | 827df9f3 | balrog | s->rfbi.hsync = 0;
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126 | 827df9f3 | balrog | } |
127 | 827df9f3 | balrog | |
128 | 827df9f3 | balrog | void omap_dss_reset(struct omap_dss_s *s) |
129 | 827df9f3 | balrog | { |
130 | 827df9f3 | balrog | s->autoidle = 0;
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131 | 827df9f3 | balrog | s->control = 0;
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132 | 827df9f3 | balrog | s->enable = 0;
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133 | 827df9f3 | balrog | |
134 | 827df9f3 | balrog | s->dig.enable = 0;
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135 | 827df9f3 | balrog | s->dig.nx = 1;
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136 | 827df9f3 | balrog | s->dig.ny = 1;
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137 | 827df9f3 | balrog | |
138 | 827df9f3 | balrog | s->lcd.enable = 0;
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139 | 827df9f3 | balrog | s->lcd.nx = 1;
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140 | 827df9f3 | balrog | s->lcd.ny = 1;
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141 | 827df9f3 | balrog | |
142 | 827df9f3 | balrog | s->dispc.idlemode = 0;
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143 | 827df9f3 | balrog | s->dispc.irqst = 0;
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144 | 827df9f3 | balrog | s->dispc.irqen = 0;
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145 | 827df9f3 | balrog | s->dispc.control = 0;
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146 | 827df9f3 | balrog | s->dispc.config = 0;
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147 | 827df9f3 | balrog | s->dispc.capable = 0x161;
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148 | 827df9f3 | balrog | s->dispc.timing[0] = 0; |
149 | 827df9f3 | balrog | s->dispc.timing[1] = 0; |
150 | 827df9f3 | balrog | s->dispc.timing[2] = 0; |
151 | f3d8b1eb | aurel32 | s->dispc.timing[3] = 0; |
152 | 827df9f3 | balrog | s->dispc.line = 0;
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153 | 827df9f3 | balrog | s->dispc.bg[0] = 0; |
154 | 827df9f3 | balrog | s->dispc.bg[1] = 0; |
155 | 827df9f3 | balrog | s->dispc.trans[0] = 0; |
156 | 827df9f3 | balrog | s->dispc.trans[1] = 0; |
157 | 827df9f3 | balrog | |
158 | 827df9f3 | balrog | s->dispc.l[0].enable = 0; |
159 | 827df9f3 | balrog | s->dispc.l[0].bpp = 0; |
160 | 827df9f3 | balrog | s->dispc.l[0].addr[0] = 0; |
161 | 827df9f3 | balrog | s->dispc.l[0].addr[1] = 0; |
162 | 827df9f3 | balrog | s->dispc.l[0].addr[2] = 0; |
163 | 827df9f3 | balrog | s->dispc.l[0].posx = 0; |
164 | 827df9f3 | balrog | s->dispc.l[0].posy = 0; |
165 | 827df9f3 | balrog | s->dispc.l[0].nx = 1; |
166 | 827df9f3 | balrog | s->dispc.l[0].ny = 1; |
167 | 827df9f3 | balrog | s->dispc.l[0].attr = 0; |
168 | 827df9f3 | balrog | s->dispc.l[0].tresh = 0; |
169 | 827df9f3 | balrog | s->dispc.l[0].rowinc = 1; |
170 | 827df9f3 | balrog | s->dispc.l[0].colinc = 1; |
171 | 827df9f3 | balrog | s->dispc.l[0].wininc = 0; |
172 | 827df9f3 | balrog | |
173 | 827df9f3 | balrog | omap_rfbi_reset(s); |
174 | 827df9f3 | balrog | omap_dispc_interrupt_update(s); |
175 | 827df9f3 | balrog | } |
176 | 827df9f3 | balrog | |
177 | 827df9f3 | balrog | static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr) |
178 | 827df9f3 | balrog | { |
179 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
180 | 827df9f3 | balrog | int offset = addr - s->diss_base;
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181 | 827df9f3 | balrog | |
182 | 827df9f3 | balrog | switch (offset) {
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183 | 827df9f3 | balrog | case 0x00: /* DSS_REVISIONNUMBER */ |
184 | 827df9f3 | balrog | return 0x20; |
185 | 827df9f3 | balrog | |
186 | 827df9f3 | balrog | case 0x10: /* DSS_SYSCONFIG */ |
187 | 827df9f3 | balrog | return s->autoidle;
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188 | 827df9f3 | balrog | |
189 | 827df9f3 | balrog | case 0x14: /* DSS_SYSSTATUS */ |
190 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
191 | 827df9f3 | balrog | |
192 | 827df9f3 | balrog | case 0x40: /* DSS_CONTROL */ |
193 | 827df9f3 | balrog | return s->control;
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194 | 827df9f3 | balrog | |
195 | 827df9f3 | balrog | case 0x50: /* DSS_PSA_LCD_REG_1 */ |
196 | 827df9f3 | balrog | case 0x54: /* DSS_PSA_LCD_REG_2 */ |
197 | 827df9f3 | balrog | case 0x58: /* DSS_PSA_VIDEO_REG */ |
198 | 827df9f3 | balrog | /* TODO: fake some values when appropriate s->control bits are set */
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199 | 827df9f3 | balrog | return 0; |
200 | 827df9f3 | balrog | |
201 | 827df9f3 | balrog | case 0x5c: /* DSS_STATUS */ |
202 | 827df9f3 | balrog | return 1 + (s->control & 1); |
203 | 827df9f3 | balrog | |
204 | 827df9f3 | balrog | default:
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205 | 827df9f3 | balrog | break;
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206 | 827df9f3 | balrog | } |
207 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
208 | 827df9f3 | balrog | return 0; |
209 | 827df9f3 | balrog | } |
210 | 827df9f3 | balrog | |
211 | 827df9f3 | balrog | static void omap_diss_write(void *opaque, target_phys_addr_t addr, |
212 | 827df9f3 | balrog | uint32_t value) |
213 | 827df9f3 | balrog | { |
214 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
215 | 827df9f3 | balrog | int offset = addr - s->diss_base;
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216 | 827df9f3 | balrog | |
217 | 827df9f3 | balrog | switch (offset) {
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218 | 827df9f3 | balrog | case 0x00: /* DSS_REVISIONNUMBER */ |
219 | 827df9f3 | balrog | case 0x14: /* DSS_SYSSTATUS */ |
220 | 827df9f3 | balrog | case 0x50: /* DSS_PSA_LCD_REG_1 */ |
221 | 827df9f3 | balrog | case 0x54: /* DSS_PSA_LCD_REG_2 */ |
222 | 827df9f3 | balrog | case 0x58: /* DSS_PSA_VIDEO_REG */ |
223 | 827df9f3 | balrog | case 0x5c: /* DSS_STATUS */ |
224 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
225 | 827df9f3 | balrog | break;
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226 | 827df9f3 | balrog | |
227 | 827df9f3 | balrog | case 0x10: /* DSS_SYSCONFIG */ |
228 | 827df9f3 | balrog | if (value & 2) /* SOFTRESET */ |
229 | 827df9f3 | balrog | omap_dss_reset(s); |
230 | 827df9f3 | balrog | s->autoidle = value & 1;
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231 | 827df9f3 | balrog | break;
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232 | 827df9f3 | balrog | |
233 | 827df9f3 | balrog | case 0x40: /* DSS_CONTROL */ |
234 | 827df9f3 | balrog | s->control = value & 0x3dd;
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235 | 827df9f3 | balrog | break;
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236 | 827df9f3 | balrog | |
237 | 827df9f3 | balrog | default:
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238 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
239 | 827df9f3 | balrog | } |
240 | 827df9f3 | balrog | } |
241 | 827df9f3 | balrog | |
242 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_diss1_readfn[] = {
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243 | 827df9f3 | balrog | omap_badwidth_read32, |
244 | 827df9f3 | balrog | omap_badwidth_read32, |
245 | 827df9f3 | balrog | omap_diss_read, |
246 | 827df9f3 | balrog | }; |
247 | 827df9f3 | balrog | |
248 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_diss1_writefn[] = {
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249 | 827df9f3 | balrog | omap_badwidth_write32, |
250 | 827df9f3 | balrog | omap_badwidth_write32, |
251 | 827df9f3 | balrog | omap_diss_write, |
252 | 827df9f3 | balrog | }; |
253 | 827df9f3 | balrog | |
254 | 827df9f3 | balrog | static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr) |
255 | 827df9f3 | balrog | { |
256 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
257 | 827df9f3 | balrog | int offset = addr - s->disc_base;
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258 | 827df9f3 | balrog | |
259 | 827df9f3 | balrog | switch (offset) {
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260 | 827df9f3 | balrog | case 0x000: /* DISPC_REVISION */ |
261 | 827df9f3 | balrog | return 0x20; |
262 | 827df9f3 | balrog | |
263 | 827df9f3 | balrog | case 0x010: /* DISPC_SYSCONFIG */ |
264 | 827df9f3 | balrog | return s->dispc.idlemode;
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265 | 827df9f3 | balrog | |
266 | 827df9f3 | balrog | case 0x014: /* DISPC_SYSSTATUS */ |
267 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
268 | 827df9f3 | balrog | |
269 | 827df9f3 | balrog | case 0x018: /* DISPC_IRQSTATUS */ |
270 | 827df9f3 | balrog | return s->dispc.irqst;
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271 | 827df9f3 | balrog | |
272 | 827df9f3 | balrog | case 0x01c: /* DISPC_IRQENABLE */ |
273 | 827df9f3 | balrog | return s->dispc.irqen;
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274 | 827df9f3 | balrog | |
275 | 827df9f3 | balrog | case 0x040: /* DISPC_CONTROL */ |
276 | 827df9f3 | balrog | return s->dispc.control;
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277 | 827df9f3 | balrog | |
278 | 827df9f3 | balrog | case 0x044: /* DISPC_CONFIG */ |
279 | 827df9f3 | balrog | return s->dispc.config;
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280 | 827df9f3 | balrog | |
281 | 827df9f3 | balrog | case 0x048: /* DISPC_CAPABLE */ |
282 | 827df9f3 | balrog | return s->dispc.capable;
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283 | 827df9f3 | balrog | |
284 | 827df9f3 | balrog | case 0x04c: /* DISPC_DEFAULT_COLOR0 */ |
285 | 827df9f3 | balrog | return s->dispc.bg[0]; |
286 | 827df9f3 | balrog | case 0x050: /* DISPC_DEFAULT_COLOR1 */ |
287 | 827df9f3 | balrog | return s->dispc.bg[1]; |
288 | 827df9f3 | balrog | case 0x054: /* DISPC_TRANS_COLOR0 */ |
289 | 827df9f3 | balrog | return s->dispc.trans[0]; |
290 | 827df9f3 | balrog | case 0x058: /* DISPC_TRANS_COLOR1 */ |
291 | 827df9f3 | balrog | return s->dispc.trans[1]; |
292 | 827df9f3 | balrog | |
293 | 827df9f3 | balrog | case 0x05c: /* DISPC_LINE_STATUS */ |
294 | 827df9f3 | balrog | return 0x7ff; |
295 | 827df9f3 | balrog | case 0x060: /* DISPC_LINE_NUMBER */ |
296 | 827df9f3 | balrog | return s->dispc.line;
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297 | 827df9f3 | balrog | |
298 | 827df9f3 | balrog | case 0x064: /* DISPC_TIMING_H */ |
299 | 827df9f3 | balrog | return s->dispc.timing[0]; |
300 | 827df9f3 | balrog | case 0x068: /* DISPC_TIMING_V */ |
301 | 827df9f3 | balrog | return s->dispc.timing[1]; |
302 | 827df9f3 | balrog | case 0x06c: /* DISPC_POL_FREQ */ |
303 | 827df9f3 | balrog | return s->dispc.timing[2]; |
304 | 827df9f3 | balrog | case 0x070: /* DISPC_DIVISOR */ |
305 | 827df9f3 | balrog | return s->dispc.timing[3]; |
306 | 827df9f3 | balrog | |
307 | 827df9f3 | balrog | case 0x078: /* DISPC_SIZE_DIG */ |
308 | 827df9f3 | balrog | return ((s->dig.ny - 1) << 16) | (s->dig.nx - 1); |
309 | 827df9f3 | balrog | case 0x07c: /* DISPC_SIZE_LCD */ |
310 | 827df9f3 | balrog | return ((s->lcd.ny - 1) << 16) | (s->lcd.nx - 1); |
311 | 827df9f3 | balrog | |
312 | 827df9f3 | balrog | case 0x080: /* DISPC_GFX_BA0 */ |
313 | 827df9f3 | balrog | return s->dispc.l[0].addr[0]; |
314 | 827df9f3 | balrog | case 0x084: /* DISPC_GFX_BA1 */ |
315 | 827df9f3 | balrog | return s->dispc.l[0].addr[1]; |
316 | 827df9f3 | balrog | case 0x088: /* DISPC_GFX_POSITION */ |
317 | 827df9f3 | balrog | return (s->dispc.l[0].posy << 16) | s->dispc.l[0].posx; |
318 | 827df9f3 | balrog | case 0x08c: /* DISPC_GFX_SIZE */ |
319 | 827df9f3 | balrog | return ((s->dispc.l[0].ny - 1) << 16) | (s->dispc.l[0].nx - 1); |
320 | 827df9f3 | balrog | case 0x0a0: /* DISPC_GFX_ATTRIBUTES */ |
321 | 827df9f3 | balrog | return s->dispc.l[0].attr; |
322 | 827df9f3 | balrog | case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */ |
323 | 827df9f3 | balrog | return s->dispc.l[0].tresh; |
324 | 827df9f3 | balrog | case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */ |
325 | 827df9f3 | balrog | return 256; |
326 | 827df9f3 | balrog | case 0x0ac: /* DISPC_GFX_ROW_INC */ |
327 | 827df9f3 | balrog | return s->dispc.l[0].rowinc; |
328 | 827df9f3 | balrog | case 0x0b0: /* DISPC_GFX_PIXEL_INC */ |
329 | 827df9f3 | balrog | return s->dispc.l[0].colinc; |
330 | 827df9f3 | balrog | case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */ |
331 | 827df9f3 | balrog | return s->dispc.l[0].wininc; |
332 | 827df9f3 | balrog | case 0x0b8: /* DISPC_GFX_TABLE_BA */ |
333 | 827df9f3 | balrog | return s->dispc.l[0].addr[2]; |
334 | 827df9f3 | balrog | |
335 | 827df9f3 | balrog | case 0x0bc: /* DISPC_VID1_BA0 */ |
336 | 827df9f3 | balrog | case 0x0c0: /* DISPC_VID1_BA1 */ |
337 | 827df9f3 | balrog | case 0x0c4: /* DISPC_VID1_POSITION */ |
338 | 827df9f3 | balrog | case 0x0c8: /* DISPC_VID1_SIZE */ |
339 | 827df9f3 | balrog | case 0x0cc: /* DISPC_VID1_ATTRIBUTES */ |
340 | 827df9f3 | balrog | case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */ |
341 | 827df9f3 | balrog | case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */ |
342 | 827df9f3 | balrog | case 0x0d8: /* DISPC_VID1_ROW_INC */ |
343 | 827df9f3 | balrog | case 0x0dc: /* DISPC_VID1_PIXEL_INC */ |
344 | 827df9f3 | balrog | case 0x0e0: /* DISPC_VID1_FIR */ |
345 | 827df9f3 | balrog | case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */ |
346 | 827df9f3 | balrog | case 0x0e8: /* DISPC_VID1_ACCU0 */ |
347 | 827df9f3 | balrog | case 0x0ec: /* DISPC_VID1_ACCU1 */ |
348 | 827df9f3 | balrog | case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */ |
349 | 827df9f3 | balrog | case 0x14c: /* DISPC_VID2_BA0 */ |
350 | 827df9f3 | balrog | case 0x150: /* DISPC_VID2_BA1 */ |
351 | 827df9f3 | balrog | case 0x154: /* DISPC_VID2_POSITION */ |
352 | 827df9f3 | balrog | case 0x158: /* DISPC_VID2_SIZE */ |
353 | 827df9f3 | balrog | case 0x15c: /* DISPC_VID2_ATTRIBUTES */ |
354 | 827df9f3 | balrog | case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */ |
355 | 827df9f3 | balrog | case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */ |
356 | 827df9f3 | balrog | case 0x168: /* DISPC_VID2_ROW_INC */ |
357 | 827df9f3 | balrog | case 0x16c: /* DISPC_VID2_PIXEL_INC */ |
358 | 827df9f3 | balrog | case 0x170: /* DISPC_VID2_FIR */ |
359 | 827df9f3 | balrog | case 0x174: /* DISPC_VID2_PICTURE_SIZE */ |
360 | 827df9f3 | balrog | case 0x178: /* DISPC_VID2_ACCU0 */ |
361 | 827df9f3 | balrog | case 0x17c: /* DISPC_VID2_ACCU1 */ |
362 | 827df9f3 | balrog | case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */ |
363 | 827df9f3 | balrog | case 0x1d4: /* DISPC_DATA_CYCLE1 */ |
364 | 827df9f3 | balrog | case 0x1d8: /* DISPC_DATA_CYCLE2 */ |
365 | 827df9f3 | balrog | case 0x1dc: /* DISPC_DATA_CYCLE3 */ |
366 | 827df9f3 | balrog | return 0; |
367 | 827df9f3 | balrog | |
368 | 827df9f3 | balrog | default:
|
369 | 827df9f3 | balrog | break;
|
370 | 827df9f3 | balrog | } |
371 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
372 | 827df9f3 | balrog | return 0; |
373 | 827df9f3 | balrog | } |
374 | 827df9f3 | balrog | |
375 | 827df9f3 | balrog | static void omap_disc_write(void *opaque, target_phys_addr_t addr, |
376 | 827df9f3 | balrog | uint32_t value) |
377 | 827df9f3 | balrog | { |
378 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
379 | 827df9f3 | balrog | int offset = addr - s->disc_base;
|
380 | 827df9f3 | balrog | |
381 | 827df9f3 | balrog | switch (offset) {
|
382 | 827df9f3 | balrog | case 0x010: /* DISPC_SYSCONFIG */ |
383 | 827df9f3 | balrog | if (value & 2) /* SOFTRESET */ |
384 | 827df9f3 | balrog | omap_dss_reset(s); |
385 | 827df9f3 | balrog | s->dispc.idlemode = value & 0x301b;
|
386 | 827df9f3 | balrog | break;
|
387 | 827df9f3 | balrog | |
388 | 827df9f3 | balrog | case 0x018: /* DISPC_IRQSTATUS */ |
389 | 827df9f3 | balrog | s->dispc.irqst &= ~value; |
390 | 827df9f3 | balrog | omap_dispc_interrupt_update(s); |
391 | 827df9f3 | balrog | break;
|
392 | 827df9f3 | balrog | |
393 | 827df9f3 | balrog | case 0x01c: /* DISPC_IRQENABLE */ |
394 | 827df9f3 | balrog | s->dispc.irqen = value & 0xffff;
|
395 | 827df9f3 | balrog | omap_dispc_interrupt_update(s); |
396 | 827df9f3 | balrog | break;
|
397 | 827df9f3 | balrog | |
398 | 827df9f3 | balrog | case 0x040: /* DISPC_CONTROL */ |
399 | 827df9f3 | balrog | s->dispc.control = value & 0x07ff9fff;
|
400 | 827df9f3 | balrog | s->dig.enable = (value >> 1) & 1; |
401 | 827df9f3 | balrog | s->lcd.enable = (value >> 0) & 1; |
402 | 827df9f3 | balrog | if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */ |
403 | 827df9f3 | balrog | if (~((s->dispc.l[1].attr | s->dispc.l[2].attr) & 1)) |
404 | 827df9f3 | balrog | fprintf(stderr, "%s: Overlay Optimization when no overlay "
|
405 | 827df9f3 | balrog | "region effectively exists leads to "
|
406 | 827df9f3 | balrog | "unpredictable behaviour!\n", __FUNCTION__);
|
407 | 827df9f3 | balrog | if (value & (1 << 6)) { /* GODIGITAL */ |
408 | 827df9f3 | balrog | /* XXX: Shadowed fields are:
|
409 | 827df9f3 | balrog | * s->dispc.config
|
410 | 827df9f3 | balrog | * s->dispc.capable
|
411 | 827df9f3 | balrog | * s->dispc.bg[0]
|
412 | 827df9f3 | balrog | * s->dispc.bg[1]
|
413 | 827df9f3 | balrog | * s->dispc.trans[0]
|
414 | 827df9f3 | balrog | * s->dispc.trans[1]
|
415 | 827df9f3 | balrog | * s->dispc.line
|
416 | 827df9f3 | balrog | * s->dispc.timing[0]
|
417 | 827df9f3 | balrog | * s->dispc.timing[1]
|
418 | 827df9f3 | balrog | * s->dispc.timing[2]
|
419 | 827df9f3 | balrog | * s->dispc.timing[3]
|
420 | 827df9f3 | balrog | * s->lcd.nx
|
421 | 827df9f3 | balrog | * s->lcd.ny
|
422 | 827df9f3 | balrog | * s->dig.nx
|
423 | 827df9f3 | balrog | * s->dig.ny
|
424 | 827df9f3 | balrog | * s->dispc.l[0].addr[0]
|
425 | 827df9f3 | balrog | * s->dispc.l[0].addr[1]
|
426 | 827df9f3 | balrog | * s->dispc.l[0].addr[2]
|
427 | 827df9f3 | balrog | * s->dispc.l[0].posx
|
428 | 827df9f3 | balrog | * s->dispc.l[0].posy
|
429 | 827df9f3 | balrog | * s->dispc.l[0].nx
|
430 | 827df9f3 | balrog | * s->dispc.l[0].ny
|
431 | 827df9f3 | balrog | * s->dispc.l[0].tresh
|
432 | 827df9f3 | balrog | * s->dispc.l[0].rowinc
|
433 | 827df9f3 | balrog | * s->dispc.l[0].colinc
|
434 | 827df9f3 | balrog | * s->dispc.l[0].wininc
|
435 | 827df9f3 | balrog | * All they need to be loaded here from their shadow registers.
|
436 | 827df9f3 | balrog | */
|
437 | 827df9f3 | balrog | } |
438 | 827df9f3 | balrog | if (value & (1 << 5)) { /* GOLCD */ |
439 | 827df9f3 | balrog | /* XXX: Likewise for LCD here. */
|
440 | 827df9f3 | balrog | } |
441 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
442 | 827df9f3 | balrog | break;
|
443 | 827df9f3 | balrog | |
444 | 827df9f3 | balrog | case 0x044: /* DISPC_CONFIG */ |
445 | 827df9f3 | balrog | s->dispc.config = value & 0x3fff;
|
446 | 827df9f3 | balrog | /* XXX:
|
447 | 827df9f3 | balrog | * bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded
|
448 | 827df9f3 | balrog | * bits 2:1 (LOADMODE) reset to 2 after set to 3 and palette loaded
|
449 | 827df9f3 | balrog | */
|
450 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
451 | 827df9f3 | balrog | break;
|
452 | 827df9f3 | balrog | |
453 | 827df9f3 | balrog | case 0x048: /* DISPC_CAPABLE */ |
454 | 827df9f3 | balrog | s->dispc.capable = value & 0x3ff;
|
455 | 827df9f3 | balrog | break;
|
456 | 827df9f3 | balrog | |
457 | 827df9f3 | balrog | case 0x04c: /* DISPC_DEFAULT_COLOR0 */ |
458 | 827df9f3 | balrog | s->dispc.bg[0] = value & 0xffffff; |
459 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
460 | 827df9f3 | balrog | break;
|
461 | 827df9f3 | balrog | case 0x050: /* DISPC_DEFAULT_COLOR1 */ |
462 | 827df9f3 | balrog | s->dispc.bg[1] = value & 0xffffff; |
463 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
464 | 827df9f3 | balrog | break;
|
465 | 827df9f3 | balrog | case 0x054: /* DISPC_TRANS_COLOR0 */ |
466 | 827df9f3 | balrog | s->dispc.trans[0] = value & 0xffffff; |
467 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
468 | 827df9f3 | balrog | break;
|
469 | 827df9f3 | balrog | case 0x058: /* DISPC_TRANS_COLOR1 */ |
470 | 827df9f3 | balrog | s->dispc.trans[1] = value & 0xffffff; |
471 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
472 | 827df9f3 | balrog | break;
|
473 | 827df9f3 | balrog | |
474 | 827df9f3 | balrog | case 0x060: /* DISPC_LINE_NUMBER */ |
475 | 827df9f3 | balrog | s->dispc.line = value & 0x7ff;
|
476 | 827df9f3 | balrog | break;
|
477 | 827df9f3 | balrog | |
478 | 827df9f3 | balrog | case 0x064: /* DISPC_TIMING_H */ |
479 | 827df9f3 | balrog | s->dispc.timing[0] = value & 0x0ff0ff3f; |
480 | 827df9f3 | balrog | break;
|
481 | 827df9f3 | balrog | case 0x068: /* DISPC_TIMING_V */ |
482 | 827df9f3 | balrog | s->dispc.timing[1] = value & 0x0ff0ff3f; |
483 | 827df9f3 | balrog | break;
|
484 | 827df9f3 | balrog | case 0x06c: /* DISPC_POL_FREQ */ |
485 | 827df9f3 | balrog | s->dispc.timing[2] = value & 0x0003ffff; |
486 | 827df9f3 | balrog | break;
|
487 | 827df9f3 | balrog | case 0x070: /* DISPC_DIVISOR */ |
488 | 827df9f3 | balrog | s->dispc.timing[3] = value & 0x00ff00ff; |
489 | 827df9f3 | balrog | break;
|
490 | 827df9f3 | balrog | |
491 | 827df9f3 | balrog | case 0x078: /* DISPC_SIZE_DIG */ |
492 | 827df9f3 | balrog | s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */ |
493 | 827df9f3 | balrog | s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */ |
494 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
495 | 827df9f3 | balrog | break;
|
496 | 827df9f3 | balrog | case 0x07c: /* DISPC_SIZE_LCD */ |
497 | 827df9f3 | balrog | s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */ |
498 | 827df9f3 | balrog | s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */ |
499 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
500 | 827df9f3 | balrog | break;
|
501 | 827df9f3 | balrog | case 0x080: /* DISPC_GFX_BA0 */ |
502 | 827df9f3 | balrog | s->dispc.l[0].addr[0] = (target_phys_addr_t) value; |
503 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
504 | 827df9f3 | balrog | break;
|
505 | 827df9f3 | balrog | case 0x084: /* DISPC_GFX_BA1 */ |
506 | 827df9f3 | balrog | s->dispc.l[0].addr[1] = (target_phys_addr_t) value; |
507 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
508 | 827df9f3 | balrog | break;
|
509 | 827df9f3 | balrog | case 0x088: /* DISPC_GFX_POSITION */ |
510 | 827df9f3 | balrog | s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */ |
511 | 827df9f3 | balrog | s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */ |
512 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
513 | 827df9f3 | balrog | break;
|
514 | 827df9f3 | balrog | case 0x08c: /* DISPC_GFX_SIZE */ |
515 | 827df9f3 | balrog | s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */ |
516 | 827df9f3 | balrog | s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */ |
517 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
518 | 827df9f3 | balrog | break;
|
519 | 827df9f3 | balrog | case 0x0a0: /* DISPC_GFX_ATTRIBUTES */ |
520 | 827df9f3 | balrog | s->dispc.l[0].attr = value & 0x7ff; |
521 | 827df9f3 | balrog | if (value & (3 << 9)) |
522 | 827df9f3 | balrog | fprintf(stderr, "%s: Big-endian pixel format not supported\n",
|
523 | 827df9f3 | balrog | __FUNCTION__); |
524 | 827df9f3 | balrog | s->dispc.l[0].enable = value & 1; |
525 | 827df9f3 | balrog | s->dispc.l[0].bpp = (value >> 1) & 0xf; |
526 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
527 | 827df9f3 | balrog | break;
|
528 | 827df9f3 | balrog | case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */ |
529 | 827df9f3 | balrog | s->dispc.l[0].tresh = value & 0x01ff01ff; |
530 | 827df9f3 | balrog | break;
|
531 | 827df9f3 | balrog | case 0x0ac: /* DISPC_GFX_ROW_INC */ |
532 | 827df9f3 | balrog | s->dispc.l[0].rowinc = value;
|
533 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
534 | 827df9f3 | balrog | break;
|
535 | 827df9f3 | balrog | case 0x0b0: /* DISPC_GFX_PIXEL_INC */ |
536 | 827df9f3 | balrog | s->dispc.l[0].colinc = value;
|
537 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
538 | 827df9f3 | balrog | break;
|
539 | 827df9f3 | balrog | case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */ |
540 | 827df9f3 | balrog | s->dispc.l[0].wininc = value;
|
541 | 827df9f3 | balrog | break;
|
542 | 827df9f3 | balrog | case 0x0b8: /* DISPC_GFX_TABLE_BA */ |
543 | 827df9f3 | balrog | s->dispc.l[0].addr[2] = (target_phys_addr_t) value; |
544 | 827df9f3 | balrog | s->dispc.invalidate = 1;
|
545 | 827df9f3 | balrog | break;
|
546 | 827df9f3 | balrog | |
547 | 827df9f3 | balrog | case 0x0bc: /* DISPC_VID1_BA0 */ |
548 | 827df9f3 | balrog | case 0x0c0: /* DISPC_VID1_BA1 */ |
549 | 827df9f3 | balrog | case 0x0c4: /* DISPC_VID1_POSITION */ |
550 | 827df9f3 | balrog | case 0x0c8: /* DISPC_VID1_SIZE */ |
551 | 827df9f3 | balrog | case 0x0cc: /* DISPC_VID1_ATTRIBUTES */ |
552 | 827df9f3 | balrog | case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */ |
553 | 827df9f3 | balrog | case 0x0d8: /* DISPC_VID1_ROW_INC */ |
554 | 827df9f3 | balrog | case 0x0dc: /* DISPC_VID1_PIXEL_INC */ |
555 | 827df9f3 | balrog | case 0x0e0: /* DISPC_VID1_FIR */ |
556 | 827df9f3 | balrog | case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */ |
557 | 827df9f3 | balrog | case 0x0e8: /* DISPC_VID1_ACCU0 */ |
558 | 827df9f3 | balrog | case 0x0ec: /* DISPC_VID1_ACCU1 */ |
559 | 827df9f3 | balrog | case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */ |
560 | 827df9f3 | balrog | case 0x14c: /* DISPC_VID2_BA0 */ |
561 | 827df9f3 | balrog | case 0x150: /* DISPC_VID2_BA1 */ |
562 | 827df9f3 | balrog | case 0x154: /* DISPC_VID2_POSITION */ |
563 | 827df9f3 | balrog | case 0x158: /* DISPC_VID2_SIZE */ |
564 | 827df9f3 | balrog | case 0x15c: /* DISPC_VID2_ATTRIBUTES */ |
565 | 827df9f3 | balrog | case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */ |
566 | 827df9f3 | balrog | case 0x168: /* DISPC_VID2_ROW_INC */ |
567 | 827df9f3 | balrog | case 0x16c: /* DISPC_VID2_PIXEL_INC */ |
568 | 827df9f3 | balrog | case 0x170: /* DISPC_VID2_FIR */ |
569 | 827df9f3 | balrog | case 0x174: /* DISPC_VID2_PICTURE_SIZE */ |
570 | 827df9f3 | balrog | case 0x178: /* DISPC_VID2_ACCU0 */ |
571 | 827df9f3 | balrog | case 0x17c: /* DISPC_VID2_ACCU1 */ |
572 | 827df9f3 | balrog | case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */ |
573 | 827df9f3 | balrog | case 0x1d4: /* DISPC_DATA_CYCLE1 */ |
574 | 827df9f3 | balrog | case 0x1d8: /* DISPC_DATA_CYCLE2 */ |
575 | 827df9f3 | balrog | case 0x1dc: /* DISPC_DATA_CYCLE3 */ |
576 | 827df9f3 | balrog | break;
|
577 | 827df9f3 | balrog | |
578 | 827df9f3 | balrog | default:
|
579 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
580 | 827df9f3 | balrog | } |
581 | 827df9f3 | balrog | } |
582 | 827df9f3 | balrog | |
583 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_disc1_readfn[] = {
|
584 | 827df9f3 | balrog | omap_badwidth_read32, |
585 | 827df9f3 | balrog | omap_badwidth_read32, |
586 | 827df9f3 | balrog | omap_disc_read, |
587 | 827df9f3 | balrog | }; |
588 | 827df9f3 | balrog | |
589 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_disc1_writefn[] = {
|
590 | 827df9f3 | balrog | omap_badwidth_write32, |
591 | 827df9f3 | balrog | omap_badwidth_write32, |
592 | 827df9f3 | balrog | omap_disc_write, |
593 | 827df9f3 | balrog | }; |
594 | 827df9f3 | balrog | |
595 | 827df9f3 | balrog | static void *omap_rfbi_get_buffer(struct omap_dss_s *s) |
596 | 827df9f3 | balrog | { |
597 | 827df9f3 | balrog | target_phys_addr_t fb; |
598 | 827df9f3 | balrog | uint32_t pd; |
599 | 827df9f3 | balrog | |
600 | 827df9f3 | balrog | /* TODO */
|
601 | 827df9f3 | balrog | fb = s->dispc.l[0].addr[0]; |
602 | 827df9f3 | balrog | |
603 | 827df9f3 | balrog | pd = cpu_get_physical_page_desc(fb); |
604 | 827df9f3 | balrog | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
|
605 | 827df9f3 | balrog | /* TODO */
|
606 | 827df9f3 | balrog | cpu_abort(cpu_single_env, "%s: framebuffer outside RAM!\n",
|
607 | 827df9f3 | balrog | __FUNCTION__); |
608 | 827df9f3 | balrog | else
|
609 | 827df9f3 | balrog | return phys_ram_base +
|
610 | 827df9f3 | balrog | (pd & TARGET_PAGE_MASK) + |
611 | 827df9f3 | balrog | (fb & ~TARGET_PAGE_MASK); |
612 | 827df9f3 | balrog | } |
613 | 827df9f3 | balrog | |
614 | 827df9f3 | balrog | static void omap_rfbi_transfer_stop(struct omap_dss_s *s) |
615 | 827df9f3 | balrog | { |
616 | 827df9f3 | balrog | if (!s->rfbi.busy)
|
617 | 827df9f3 | balrog | return;
|
618 | 827df9f3 | balrog | |
619 | 827df9f3 | balrog | /* TODO: in non-Bypass mode we probably need to just deassert the DRQ. */
|
620 | 827df9f3 | balrog | |
621 | 827df9f3 | balrog | s->rfbi.busy = 0;
|
622 | 827df9f3 | balrog | } |
623 | 827df9f3 | balrog | |
624 | 827df9f3 | balrog | static void omap_rfbi_transfer_start(struct omap_dss_s *s) |
625 | 827df9f3 | balrog | { |
626 | 827df9f3 | balrog | void *data;
|
627 | 827df9f3 | balrog | size_t len; |
628 | 827df9f3 | balrog | int pitch;
|
629 | 827df9f3 | balrog | |
630 | 827df9f3 | balrog | if (!s->rfbi.enable || s->rfbi.busy)
|
631 | 827df9f3 | balrog | return;
|
632 | 827df9f3 | balrog | |
633 | 827df9f3 | balrog | if (s->rfbi.control & (1 << 1)) { /* BYPASS */ |
634 | 827df9f3 | balrog | /* TODO: in non-Bypass mode we probably need to just assert the
|
635 | 827df9f3 | balrog | * DRQ and wait for DMA to write the pixels. */
|
636 | 827df9f3 | balrog | fprintf(stderr, "%s: Bypass mode unimplemented\n", __FUNCTION__);
|
637 | 827df9f3 | balrog | return;
|
638 | 827df9f3 | balrog | } |
639 | 827df9f3 | balrog | |
640 | 827df9f3 | balrog | if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */ |
641 | 827df9f3 | balrog | return;
|
642 | 827df9f3 | balrog | /* TODO: check that LCD output is enabled in DISPC. */
|
643 | 827df9f3 | balrog | |
644 | 827df9f3 | balrog | s->rfbi.busy = 1;
|
645 | 827df9f3 | balrog | |
646 | 827df9f3 | balrog | data = omap_rfbi_get_buffer(s); |
647 | 827df9f3 | balrog | |
648 | 827df9f3 | balrog | /* TODO bpp */
|
649 | 827df9f3 | balrog | len = s->rfbi.pixels * 2;
|
650 | 827df9f3 | balrog | s->rfbi.pixels = 0;
|
651 | 827df9f3 | balrog | |
652 | 827df9f3 | balrog | /* TODO: negative values */
|
653 | 827df9f3 | balrog | pitch = s->dispc.l[0].nx + (s->dispc.l[0].rowinc - 1) / 2; |
654 | 827df9f3 | balrog | |
655 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
656 | 827df9f3 | balrog | s->rfbi.chip[0]->block(s->rfbi.chip[0]->opaque, 1, data, len, pitch); |
657 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
658 | 827df9f3 | balrog | s->rfbi.chip[1]->block(s->rfbi.chip[1]->opaque, 1, data, len, pitch); |
659 | 827df9f3 | balrog | |
660 | 827df9f3 | balrog | omap_rfbi_transfer_stop(s); |
661 | 827df9f3 | balrog | |
662 | 827df9f3 | balrog | /* TODO */
|
663 | 827df9f3 | balrog | s->dispc.irqst |= 1; /* FRAMEDONE */ |
664 | 827df9f3 | balrog | omap_dispc_interrupt_update(s); |
665 | 827df9f3 | balrog | } |
666 | 827df9f3 | balrog | |
667 | 827df9f3 | balrog | static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr) |
668 | 827df9f3 | balrog | { |
669 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
670 | 827df9f3 | balrog | int offset = addr - s->rfbi_base;
|
671 | 827df9f3 | balrog | |
672 | 827df9f3 | balrog | switch (offset) {
|
673 | 827df9f3 | balrog | case 0x00: /* RFBI_REVISION */ |
674 | 827df9f3 | balrog | return 0x10; |
675 | 827df9f3 | balrog | |
676 | 827df9f3 | balrog | case 0x10: /* RFBI_SYSCONFIG */ |
677 | 827df9f3 | balrog | return s->rfbi.idlemode;
|
678 | 827df9f3 | balrog | |
679 | 827df9f3 | balrog | case 0x14: /* RFBI_SYSSTATUS */ |
680 | 827df9f3 | balrog | return 1 | (s->rfbi.busy << 8); /* RESETDONE */ |
681 | 827df9f3 | balrog | |
682 | 827df9f3 | balrog | case 0x40: /* RFBI_CONTROL */ |
683 | 827df9f3 | balrog | return s->rfbi.control;
|
684 | 827df9f3 | balrog | |
685 | 827df9f3 | balrog | case 0x44: /* RFBI_PIXELCNT */ |
686 | 827df9f3 | balrog | return s->rfbi.pixels;
|
687 | 827df9f3 | balrog | |
688 | 827df9f3 | balrog | case 0x48: /* RFBI_LINE_NUMBER */ |
689 | 827df9f3 | balrog | return s->rfbi.skiplines;
|
690 | 827df9f3 | balrog | |
691 | 827df9f3 | balrog | case 0x58: /* RFBI_READ */ |
692 | 827df9f3 | balrog | case 0x5c: /* RFBI_STATUS */ |
693 | 827df9f3 | balrog | return s->rfbi.rxbuf;
|
694 | 827df9f3 | balrog | |
695 | 827df9f3 | balrog | case 0x60: /* RFBI_CONFIG0 */ |
696 | 827df9f3 | balrog | return s->rfbi.config[0]; |
697 | 827df9f3 | balrog | case 0x64: /* RFBI_ONOFF_TIME0 */ |
698 | 827df9f3 | balrog | return s->rfbi.time[0]; |
699 | 827df9f3 | balrog | case 0x68: /* RFBI_CYCLE_TIME0 */ |
700 | 827df9f3 | balrog | return s->rfbi.time[1]; |
701 | 827df9f3 | balrog | case 0x6c: /* RFBI_DATA_CYCLE1_0 */ |
702 | 827df9f3 | balrog | return s->rfbi.data[0]; |
703 | 827df9f3 | balrog | case 0x70: /* RFBI_DATA_CYCLE2_0 */ |
704 | 827df9f3 | balrog | return s->rfbi.data[1]; |
705 | 827df9f3 | balrog | case 0x74: /* RFBI_DATA_CYCLE3_0 */ |
706 | 827df9f3 | balrog | return s->rfbi.data[2]; |
707 | 827df9f3 | balrog | |
708 | 827df9f3 | balrog | case 0x78: /* RFBI_CONFIG1 */ |
709 | 827df9f3 | balrog | return s->rfbi.config[1]; |
710 | 827df9f3 | balrog | case 0x7c: /* RFBI_ONOFF_TIME1 */ |
711 | 827df9f3 | balrog | return s->rfbi.time[2]; |
712 | 827df9f3 | balrog | case 0x80: /* RFBI_CYCLE_TIME1 */ |
713 | 827df9f3 | balrog | return s->rfbi.time[3]; |
714 | 827df9f3 | balrog | case 0x84: /* RFBI_DATA_CYCLE1_1 */ |
715 | 827df9f3 | balrog | return s->rfbi.data[3]; |
716 | 827df9f3 | balrog | case 0x88: /* RFBI_DATA_CYCLE2_1 */ |
717 | 827df9f3 | balrog | return s->rfbi.data[4]; |
718 | 827df9f3 | balrog | case 0x8c: /* RFBI_DATA_CYCLE3_1 */ |
719 | 827df9f3 | balrog | return s->rfbi.data[5]; |
720 | 827df9f3 | balrog | |
721 | 827df9f3 | balrog | case 0x90: /* RFBI_VSYNC_WIDTH */ |
722 | 827df9f3 | balrog | return s->rfbi.vsync;
|
723 | 827df9f3 | balrog | case 0x94: /* RFBI_HSYNC_WIDTH */ |
724 | 827df9f3 | balrog | return s->rfbi.hsync;
|
725 | 827df9f3 | balrog | } |
726 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
727 | 827df9f3 | balrog | return 0; |
728 | 827df9f3 | balrog | } |
729 | 827df9f3 | balrog | |
730 | 827df9f3 | balrog | static void omap_rfbi_write(void *opaque, target_phys_addr_t addr, |
731 | 827df9f3 | balrog | uint32_t value) |
732 | 827df9f3 | balrog | { |
733 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
734 | 827df9f3 | balrog | int offset = addr - s->rfbi_base;
|
735 | 827df9f3 | balrog | |
736 | 827df9f3 | balrog | switch (offset) {
|
737 | 827df9f3 | balrog | case 0x10: /* RFBI_SYSCONFIG */ |
738 | 827df9f3 | balrog | if (value & 2) /* SOFTRESET */ |
739 | 827df9f3 | balrog | omap_rfbi_reset(s); |
740 | 827df9f3 | balrog | s->rfbi.idlemode = value & 0x19;
|
741 | 827df9f3 | balrog | break;
|
742 | 827df9f3 | balrog | |
743 | 827df9f3 | balrog | case 0x40: /* RFBI_CONTROL */ |
744 | 827df9f3 | balrog | s->rfbi.control = value & 0xf;
|
745 | 827df9f3 | balrog | s->rfbi.enable = value & 1;
|
746 | 827df9f3 | balrog | if (value & (1 << 4) && /* ITE */ |
747 | 827df9f3 | balrog | !(s->rfbi.config[0] & s->rfbi.config[1] & 0xc)) |
748 | 827df9f3 | balrog | omap_rfbi_transfer_start(s); |
749 | 827df9f3 | balrog | break;
|
750 | 827df9f3 | balrog | |
751 | 827df9f3 | balrog | case 0x44: /* RFBI_PIXELCNT */ |
752 | 827df9f3 | balrog | s->rfbi.pixels = value; |
753 | 827df9f3 | balrog | break;
|
754 | 827df9f3 | balrog | |
755 | 827df9f3 | balrog | case 0x48: /* RFBI_LINE_NUMBER */ |
756 | 827df9f3 | balrog | s->rfbi.skiplines = value & 0x7ff;
|
757 | 827df9f3 | balrog | break;
|
758 | 827df9f3 | balrog | |
759 | 827df9f3 | balrog | case 0x4c: /* RFBI_CMD */ |
760 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
761 | 827df9f3 | balrog | s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 0, value & 0xffff); |
762 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
763 | 827df9f3 | balrog | s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 0, value & 0xffff); |
764 | 827df9f3 | balrog | break;
|
765 | 827df9f3 | balrog | case 0x50: /* RFBI_PARAM */ |
766 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
767 | 827df9f3 | balrog | s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff); |
768 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
769 | 827df9f3 | balrog | s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff); |
770 | 827df9f3 | balrog | break;
|
771 | 827df9f3 | balrog | case 0x54: /* RFBI_DATA */ |
772 | 827df9f3 | balrog | /* TODO: take into account the format set up in s->rfbi.config[?] and
|
773 | 827df9f3 | balrog | * s->rfbi.data[?], but special-case the most usual scenario so that
|
774 | 827df9f3 | balrog | * speed doesn't suffer. */
|
775 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) { |
776 | 827df9f3 | balrog | s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff); |
777 | 827df9f3 | balrog | s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value >> 16); |
778 | 827df9f3 | balrog | } |
779 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) { |
780 | 827df9f3 | balrog | s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff); |
781 | 827df9f3 | balrog | s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value >> 16); |
782 | 827df9f3 | balrog | } |
783 | 827df9f3 | balrog | if (!-- s->rfbi.pixels)
|
784 | 827df9f3 | balrog | omap_rfbi_transfer_stop(s); |
785 | 827df9f3 | balrog | break;
|
786 | 827df9f3 | balrog | case 0x58: /* RFBI_READ */ |
787 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
788 | 827df9f3 | balrog | s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1); |
789 | 827df9f3 | balrog | else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
790 | 827df9f3 | balrog | s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1); |
791 | 827df9f3 | balrog | if (!-- s->rfbi.pixels)
|
792 | 827df9f3 | balrog | omap_rfbi_transfer_stop(s); |
793 | 827df9f3 | balrog | break;
|
794 | 827df9f3 | balrog | |
795 | 827df9f3 | balrog | case 0x5c: /* RFBI_STATUS */ |
796 | 827df9f3 | balrog | if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
797 | 827df9f3 | balrog | s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0); |
798 | 827df9f3 | balrog | else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
799 | 827df9f3 | balrog | s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0); |
800 | 827df9f3 | balrog | if (!-- s->rfbi.pixels)
|
801 | 827df9f3 | balrog | omap_rfbi_transfer_stop(s); |
802 | 827df9f3 | balrog | break;
|
803 | 827df9f3 | balrog | |
804 | 827df9f3 | balrog | case 0x60: /* RFBI_CONFIG0 */ |
805 | 827df9f3 | balrog | s->rfbi.config[0] = value & 0x003f1fff; |
806 | 827df9f3 | balrog | break;
|
807 | 827df9f3 | balrog | |
808 | 827df9f3 | balrog | case 0x64: /* RFBI_ONOFF_TIME0 */ |
809 | 827df9f3 | balrog | s->rfbi.time[0] = value & 0x3fffffff; |
810 | 827df9f3 | balrog | break;
|
811 | 827df9f3 | balrog | case 0x68: /* RFBI_CYCLE_TIME0 */ |
812 | 827df9f3 | balrog | s->rfbi.time[1] = value & 0x0fffffff; |
813 | 827df9f3 | balrog | break;
|
814 | 827df9f3 | balrog | case 0x6c: /* RFBI_DATA_CYCLE1_0 */ |
815 | 827df9f3 | balrog | s->rfbi.data[0] = value & 0x0f1f0f1f; |
816 | 827df9f3 | balrog | break;
|
817 | 827df9f3 | balrog | case 0x70: /* RFBI_DATA_CYCLE2_0 */ |
818 | 827df9f3 | balrog | s->rfbi.data[1] = value & 0x0f1f0f1f; |
819 | 827df9f3 | balrog | break;
|
820 | 827df9f3 | balrog | case 0x74: /* RFBI_DATA_CYCLE3_0 */ |
821 | 827df9f3 | balrog | s->rfbi.data[2] = value & 0x0f1f0f1f; |
822 | 827df9f3 | balrog | break;
|
823 | 827df9f3 | balrog | case 0x78: /* RFBI_CONFIG1 */ |
824 | 827df9f3 | balrog | s->rfbi.config[1] = value & 0x003f1fff; |
825 | 827df9f3 | balrog | break;
|
826 | 827df9f3 | balrog | |
827 | 827df9f3 | balrog | case 0x7c: /* RFBI_ONOFF_TIME1 */ |
828 | 827df9f3 | balrog | s->rfbi.time[2] = value & 0x3fffffff; |
829 | 827df9f3 | balrog | break;
|
830 | 827df9f3 | balrog | case 0x80: /* RFBI_CYCLE_TIME1 */ |
831 | 827df9f3 | balrog | s->rfbi.time[3] = value & 0x0fffffff; |
832 | 827df9f3 | balrog | break;
|
833 | 827df9f3 | balrog | case 0x84: /* RFBI_DATA_CYCLE1_1 */ |
834 | 827df9f3 | balrog | s->rfbi.data[3] = value & 0x0f1f0f1f; |
835 | 827df9f3 | balrog | break;
|
836 | 827df9f3 | balrog | case 0x88: /* RFBI_DATA_CYCLE2_1 */ |
837 | 827df9f3 | balrog | s->rfbi.data[4] = value & 0x0f1f0f1f; |
838 | 827df9f3 | balrog | break;
|
839 | 827df9f3 | balrog | case 0x8c: /* RFBI_DATA_CYCLE3_1 */ |
840 | 827df9f3 | balrog | s->rfbi.data[5] = value & 0x0f1f0f1f; |
841 | 827df9f3 | balrog | break;
|
842 | 827df9f3 | balrog | |
843 | 827df9f3 | balrog | case 0x90: /* RFBI_VSYNC_WIDTH */ |
844 | 827df9f3 | balrog | s->rfbi.vsync = value & 0xffff;
|
845 | 827df9f3 | balrog | break;
|
846 | 827df9f3 | balrog | case 0x94: /* RFBI_HSYNC_WIDTH */ |
847 | 827df9f3 | balrog | s->rfbi.hsync = value & 0xffff;
|
848 | 827df9f3 | balrog | break;
|
849 | 827df9f3 | balrog | |
850 | 827df9f3 | balrog | default:
|
851 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
852 | 827df9f3 | balrog | } |
853 | 827df9f3 | balrog | } |
854 | 827df9f3 | balrog | |
855 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_rfbi1_readfn[] = {
|
856 | 827df9f3 | balrog | omap_badwidth_read32, |
857 | 827df9f3 | balrog | omap_badwidth_read32, |
858 | 827df9f3 | balrog | omap_rfbi_read, |
859 | 827df9f3 | balrog | }; |
860 | 827df9f3 | balrog | |
861 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_rfbi1_writefn[] = {
|
862 | 827df9f3 | balrog | omap_badwidth_write32, |
863 | 827df9f3 | balrog | omap_badwidth_write32, |
864 | 827df9f3 | balrog | omap_rfbi_write, |
865 | 827df9f3 | balrog | }; |
866 | 827df9f3 | balrog | |
867 | 827df9f3 | balrog | static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr) |
868 | 827df9f3 | balrog | { |
869 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
870 | 827df9f3 | balrog | int offset = addr - s->venc_base;
|
871 | 827df9f3 | balrog | |
872 | 827df9f3 | balrog | switch (offset) {
|
873 | 827df9f3 | balrog | case 0x00: /* REV_ID */ |
874 | 827df9f3 | balrog | case 0x04: /* STATUS */ |
875 | 827df9f3 | balrog | case 0x08: /* F_CONTROL */ |
876 | 827df9f3 | balrog | case 0x10: /* VIDOUT_CTRL */ |
877 | 827df9f3 | balrog | case 0x14: /* SYNC_CTRL */ |
878 | 827df9f3 | balrog | case 0x1c: /* LLEN */ |
879 | 827df9f3 | balrog | case 0x20: /* FLENS */ |
880 | 827df9f3 | balrog | case 0x24: /* HFLTR_CTRL */ |
881 | 827df9f3 | balrog | case 0x28: /* CC_CARR_WSS_CARR */ |
882 | 827df9f3 | balrog | case 0x2c: /* C_PHASE */ |
883 | 827df9f3 | balrog | case 0x30: /* GAIN_U */ |
884 | 827df9f3 | balrog | case 0x34: /* GAIN_V */ |
885 | 827df9f3 | balrog | case 0x38: /* GAIN_Y */ |
886 | 827df9f3 | balrog | case 0x3c: /* BLACK_LEVEL */ |
887 | 827df9f3 | balrog | case 0x40: /* BLANK_LEVEL */ |
888 | 827df9f3 | balrog | case 0x44: /* X_COLOR */ |
889 | 827df9f3 | balrog | case 0x48: /* M_CONTROL */ |
890 | 827df9f3 | balrog | case 0x4c: /* BSTAMP_WSS_DATA */ |
891 | 827df9f3 | balrog | case 0x50: /* S_CARR */ |
892 | 827df9f3 | balrog | case 0x54: /* LINE21 */ |
893 | 827df9f3 | balrog | case 0x58: /* LN_SEL */ |
894 | 827df9f3 | balrog | case 0x5c: /* L21__WC_CTL */ |
895 | 827df9f3 | balrog | case 0x60: /* HTRIGGER_VTRIGGER */ |
896 | 827df9f3 | balrog | case 0x64: /* SAVID__EAVID */ |
897 | 827df9f3 | balrog | case 0x68: /* FLEN__FAL */ |
898 | 827df9f3 | balrog | case 0x6c: /* LAL__PHASE_RESET */ |
899 | 827df9f3 | balrog | case 0x70: /* HS_INT_START_STOP_X */ |
900 | 827df9f3 | balrog | case 0x74: /* HS_EXT_START_STOP_X */ |
901 | 827df9f3 | balrog | case 0x78: /* VS_INT_START_X */ |
902 | 827df9f3 | balrog | case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */ |
903 | 827df9f3 | balrog | case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */ |
904 | 827df9f3 | balrog | case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */ |
905 | 827df9f3 | balrog | case 0x88: /* VS_EXT_STOP_Y */ |
906 | 827df9f3 | balrog | case 0x90: /* AVID_START_STOP_X */ |
907 | 827df9f3 | balrog | case 0x94: /* AVID_START_STOP_Y */ |
908 | 827df9f3 | balrog | case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */ |
909 | 827df9f3 | balrog | case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */ |
910 | 827df9f3 | balrog | case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */ |
911 | 827df9f3 | balrog | case 0xb0: /* TVDETGP_INT_START_STOP_X */ |
912 | 827df9f3 | balrog | case 0xb4: /* TVDETGP_INT_START_STOP_Y */ |
913 | 827df9f3 | balrog | case 0xb8: /* GEN_CTRL */ |
914 | 827df9f3 | balrog | case 0xc4: /* DAC_TST__DAC_A */ |
915 | 827df9f3 | balrog | case 0xc8: /* DAC_B__DAC_C */ |
916 | 827df9f3 | balrog | return 0; |
917 | 827df9f3 | balrog | |
918 | 827df9f3 | balrog | default:
|
919 | 827df9f3 | balrog | break;
|
920 | 827df9f3 | balrog | } |
921 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
922 | 827df9f3 | balrog | return 0; |
923 | 827df9f3 | balrog | } |
924 | 827df9f3 | balrog | |
925 | 827df9f3 | balrog | static void omap_venc_write(void *opaque, target_phys_addr_t addr, |
926 | 827df9f3 | balrog | uint32_t value) |
927 | 827df9f3 | balrog | { |
928 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
929 | 827df9f3 | balrog | int offset = addr - s->venc_base;
|
930 | 827df9f3 | balrog | |
931 | 827df9f3 | balrog | switch (offset) {
|
932 | 827df9f3 | balrog | case 0x08: /* F_CONTROL */ |
933 | 827df9f3 | balrog | case 0x10: /* VIDOUT_CTRL */ |
934 | 827df9f3 | balrog | case 0x14: /* SYNC_CTRL */ |
935 | 827df9f3 | balrog | case 0x1c: /* LLEN */ |
936 | 827df9f3 | balrog | case 0x20: /* FLENS */ |
937 | 827df9f3 | balrog | case 0x24: /* HFLTR_CTRL */ |
938 | 827df9f3 | balrog | case 0x28: /* CC_CARR_WSS_CARR */ |
939 | 827df9f3 | balrog | case 0x2c: /* C_PHASE */ |
940 | 827df9f3 | balrog | case 0x30: /* GAIN_U */ |
941 | 827df9f3 | balrog | case 0x34: /* GAIN_V */ |
942 | 827df9f3 | balrog | case 0x38: /* GAIN_Y */ |
943 | 827df9f3 | balrog | case 0x3c: /* BLACK_LEVEL */ |
944 | 827df9f3 | balrog | case 0x40: /* BLANK_LEVEL */ |
945 | 827df9f3 | balrog | case 0x44: /* X_COLOR */ |
946 | 827df9f3 | balrog | case 0x48: /* M_CONTROL */ |
947 | 827df9f3 | balrog | case 0x4c: /* BSTAMP_WSS_DATA */ |
948 | 827df9f3 | balrog | case 0x50: /* S_CARR */ |
949 | 827df9f3 | balrog | case 0x54: /* LINE21 */ |
950 | 827df9f3 | balrog | case 0x58: /* LN_SEL */ |
951 | 827df9f3 | balrog | case 0x5c: /* L21__WC_CTL */ |
952 | 827df9f3 | balrog | case 0x60: /* HTRIGGER_VTRIGGER */ |
953 | 827df9f3 | balrog | case 0x64: /* SAVID__EAVID */ |
954 | 827df9f3 | balrog | case 0x68: /* FLEN__FAL */ |
955 | 827df9f3 | balrog | case 0x6c: /* LAL__PHASE_RESET */ |
956 | 827df9f3 | balrog | case 0x70: /* HS_INT_START_STOP_X */ |
957 | 827df9f3 | balrog | case 0x74: /* HS_EXT_START_STOP_X */ |
958 | 827df9f3 | balrog | case 0x78: /* VS_INT_START_X */ |
959 | 827df9f3 | balrog | case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */ |
960 | 827df9f3 | balrog | case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */ |
961 | 827df9f3 | balrog | case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */ |
962 | 827df9f3 | balrog | case 0x88: /* VS_EXT_STOP_Y */ |
963 | 827df9f3 | balrog | case 0x90: /* AVID_START_STOP_X */ |
964 | 827df9f3 | balrog | case 0x94: /* AVID_START_STOP_Y */ |
965 | 827df9f3 | balrog | case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */ |
966 | 827df9f3 | balrog | case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */ |
967 | 827df9f3 | balrog | case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */ |
968 | 827df9f3 | balrog | case 0xb0: /* TVDETGP_INT_START_STOP_X */ |
969 | 827df9f3 | balrog | case 0xb4: /* TVDETGP_INT_START_STOP_Y */ |
970 | 827df9f3 | balrog | case 0xb8: /* GEN_CTRL */ |
971 | 827df9f3 | balrog | case 0xc4: /* DAC_TST__DAC_A */ |
972 | 827df9f3 | balrog | case 0xc8: /* DAC_B__DAC_C */ |
973 | 827df9f3 | balrog | break;
|
974 | 827df9f3 | balrog | |
975 | 827df9f3 | balrog | default:
|
976 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
977 | 827df9f3 | balrog | } |
978 | 827df9f3 | balrog | } |
979 | 827df9f3 | balrog | |
980 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_venc1_readfn[] = {
|
981 | 827df9f3 | balrog | omap_badwidth_read32, |
982 | 827df9f3 | balrog | omap_badwidth_read32, |
983 | 827df9f3 | balrog | omap_venc_read, |
984 | 827df9f3 | balrog | }; |
985 | 827df9f3 | balrog | |
986 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_venc1_writefn[] = {
|
987 | 827df9f3 | balrog | omap_badwidth_write32, |
988 | 827df9f3 | balrog | omap_badwidth_write32, |
989 | 827df9f3 | balrog | omap_venc_write, |
990 | 827df9f3 | balrog | }; |
991 | 827df9f3 | balrog | |
992 | 827df9f3 | balrog | static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr) |
993 | 827df9f3 | balrog | { |
994 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
995 | 827df9f3 | balrog | int offset = addr - s->im3_base;
|
996 | 827df9f3 | balrog | |
997 | 827df9f3 | balrog | switch (offset) {
|
998 | 827df9f3 | balrog | case 0x0a8: /* SBIMERRLOGA */ |
999 | 827df9f3 | balrog | case 0x0b0: /* SBIMERRLOG */ |
1000 | 827df9f3 | balrog | case 0x190: /* SBIMSTATE */ |
1001 | 827df9f3 | balrog | case 0x198: /* SBTMSTATE_L */ |
1002 | 827df9f3 | balrog | case 0x19c: /* SBTMSTATE_H */ |
1003 | 827df9f3 | balrog | case 0x1a8: /* SBIMCONFIG_L */ |
1004 | 827df9f3 | balrog | case 0x1ac: /* SBIMCONFIG_H */ |
1005 | 827df9f3 | balrog | case 0x1f8: /* SBID_L */ |
1006 | 827df9f3 | balrog | case 0x1fc: /* SBID_H */ |
1007 | 827df9f3 | balrog | return 0; |
1008 | 827df9f3 | balrog | |
1009 | 827df9f3 | balrog | default:
|
1010 | 827df9f3 | balrog | break;
|
1011 | 827df9f3 | balrog | } |
1012 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1013 | 827df9f3 | balrog | return 0; |
1014 | 827df9f3 | balrog | } |
1015 | 827df9f3 | balrog | |
1016 | 827df9f3 | balrog | static void omap_im3_write(void *opaque, target_phys_addr_t addr, |
1017 | 827df9f3 | balrog | uint32_t value) |
1018 | 827df9f3 | balrog | { |
1019 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
1020 | 827df9f3 | balrog | int offset = addr - s->im3_base;
|
1021 | 827df9f3 | balrog | |
1022 | 827df9f3 | balrog | switch (offset) {
|
1023 | 827df9f3 | balrog | case 0x0b0: /* SBIMERRLOG */ |
1024 | 827df9f3 | balrog | case 0x190: /* SBIMSTATE */ |
1025 | 827df9f3 | balrog | case 0x198: /* SBTMSTATE_L */ |
1026 | 827df9f3 | balrog | case 0x19c: /* SBTMSTATE_H */ |
1027 | 827df9f3 | balrog | case 0x1a8: /* SBIMCONFIG_L */ |
1028 | 827df9f3 | balrog | case 0x1ac: /* SBIMCONFIG_H */ |
1029 | 827df9f3 | balrog | break;
|
1030 | 827df9f3 | balrog | |
1031 | 827df9f3 | balrog | default:
|
1032 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
1033 | 827df9f3 | balrog | } |
1034 | 827df9f3 | balrog | } |
1035 | 827df9f3 | balrog | |
1036 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_im3_readfn[] = {
|
1037 | 827df9f3 | balrog | omap_badwidth_read32, |
1038 | 827df9f3 | balrog | omap_badwidth_read32, |
1039 | 827df9f3 | balrog | omap_im3_read, |
1040 | 827df9f3 | balrog | }; |
1041 | 827df9f3 | balrog | |
1042 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_im3_writefn[] = {
|
1043 | 827df9f3 | balrog | omap_badwidth_write32, |
1044 | 827df9f3 | balrog | omap_badwidth_write32, |
1045 | 827df9f3 | balrog | omap_im3_write, |
1046 | 827df9f3 | balrog | }; |
1047 | 827df9f3 | balrog | |
1048 | 827df9f3 | balrog | struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
1049 | 827df9f3 | balrog | target_phys_addr_t l3_base, DisplayState *ds, |
1050 | 827df9f3 | balrog | qemu_irq irq, qemu_irq drq, |
1051 | 827df9f3 | balrog | omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
1052 | 827df9f3 | balrog | omap_clk ick1, omap_clk ick2) |
1053 | 827df9f3 | balrog | { |
1054 | 827df9f3 | balrog | int iomemtype[5]; |
1055 | 827df9f3 | balrog | struct omap_dss_s *s = (struct omap_dss_s *) |
1056 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_dss_s)); |
1057 | 827df9f3 | balrog | |
1058 | 827df9f3 | balrog | s->irq = irq; |
1059 | 827df9f3 | balrog | s->drq = drq; |
1060 | 827df9f3 | balrog | s->state = ds; |
1061 | 827df9f3 | balrog | omap_dss_reset(s); |
1062 | 827df9f3 | balrog | |
1063 | c66fb5bc | balrog | iomemtype[0] = l4_register_io_memory(0, omap_diss1_readfn, |
1064 | 827df9f3 | balrog | omap_diss1_writefn, s); |
1065 | c66fb5bc | balrog | iomemtype[1] = l4_register_io_memory(0, omap_disc1_readfn, |
1066 | 827df9f3 | balrog | omap_disc1_writefn, s); |
1067 | c66fb5bc | balrog | iomemtype[2] = l4_register_io_memory(0, omap_rfbi1_readfn, |
1068 | 827df9f3 | balrog | omap_rfbi1_writefn, s); |
1069 | c66fb5bc | balrog | iomemtype[3] = l4_register_io_memory(0, omap_venc1_readfn, |
1070 | 827df9f3 | balrog | omap_venc1_writefn, s); |
1071 | 827df9f3 | balrog | iomemtype[4] = cpu_register_io_memory(0, omap_im3_readfn, |
1072 | 827df9f3 | balrog | omap_im3_writefn, s); |
1073 | 827df9f3 | balrog | s->diss_base = omap_l4_attach(ta, 0, iomemtype[0]); |
1074 | 827df9f3 | balrog | s->disc_base = omap_l4_attach(ta, 1, iomemtype[1]); |
1075 | 827df9f3 | balrog | s->rfbi_base = omap_l4_attach(ta, 2, iomemtype[2]); |
1076 | 827df9f3 | balrog | s->venc_base = omap_l4_attach(ta, 3, iomemtype[3]); |
1077 | 827df9f3 | balrog | s->im3_base = l3_base; |
1078 | 827df9f3 | balrog | cpu_register_physical_memory(s->im3_base, 0x1000, iomemtype[4]); |
1079 | 827df9f3 | balrog | |
1080 | 827df9f3 | balrog | #if 0
|
1081 | 827df9f3 | balrog | if (ds)
|
1082 | 827df9f3 | balrog | graphic_console_init(ds, omap_update_display,
|
1083 | 827df9f3 | balrog | omap_invalidate_display, omap_screen_dump, s);
|
1084 | 827df9f3 | balrog | #endif
|
1085 | 827df9f3 | balrog | |
1086 | 827df9f3 | balrog | return s;
|
1087 | 827df9f3 | balrog | } |
1088 | 827df9f3 | balrog | |
1089 | 827df9f3 | balrog | void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip) |
1090 | 827df9f3 | balrog | { |
1091 | 827df9f3 | balrog | if (cs < 0 || cs > 1) |
1092 | 827df9f3 | balrog | cpu_abort(cpu_single_env, "%s: wrong CS %i\n", __FUNCTION__, cs);
|
1093 | 827df9f3 | balrog | s->rfbi.chip[cs] = chip; |
1094 | 827df9f3 | balrog | } |