root / hw / sun4m.c @ 1ae26a18
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1 | 420557e8 | bellard | /*
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2 | ee76f82e | blueswir1 | * QEMU Sun4m & Sun4d & Sun4c System Emulator
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3 | 5fafdf24 | ths | *
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4 | b81b3b10 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sun4m.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "sysemu.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 8b17de88 | blueswir1 | #include "scsi.h" |
35 | 22548760 | blueswir1 | #include "pc.h" |
36 | 22548760 | blueswir1 | #include "isa.h" |
37 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
38 | d2c63fc1 | blueswir1 | |
39 | b3a23197 | blueswir1 | //#define DEBUG_IRQ
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40 | 420557e8 | bellard | |
41 | 36cd9210 | blueswir1 | /*
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42 | 36cd9210 | blueswir1 | * Sun4m architecture was used in the following machines:
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43 | 36cd9210 | blueswir1 | *
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44 | 36cd9210 | blueswir1 | * SPARCserver 6xxMP/xx
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45 | 77f193da | blueswir1 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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46 | 77f193da | blueswir1 | * SPARCclassic X (4/10)
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47 | 36cd9210 | blueswir1 | * SPARCstation LX/ZX (4/30)
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48 | 36cd9210 | blueswir1 | * SPARCstation Voyager
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49 | 36cd9210 | blueswir1 | * SPARCstation 10/xx, SPARCserver 10/xx
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50 | 36cd9210 | blueswir1 | * SPARCstation 5, SPARCserver 5
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51 | 36cd9210 | blueswir1 | * SPARCstation 20/xx, SPARCserver 20
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52 | 36cd9210 | blueswir1 | * SPARCstation 4
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53 | 36cd9210 | blueswir1 | *
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54 | 7d85892b | blueswir1 | * Sun4d architecture was used in the following machines:
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55 | 7d85892b | blueswir1 | *
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56 | 7d85892b | blueswir1 | * SPARCcenter 2000
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57 | 7d85892b | blueswir1 | * SPARCserver 1000
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58 | 7d85892b | blueswir1 | *
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59 | ee76f82e | blueswir1 | * Sun4c architecture was used in the following machines:
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60 | ee76f82e | blueswir1 | * SPARCstation 1/1+, SPARCserver 1/1+
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61 | ee76f82e | blueswir1 | * SPARCstation SLC
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62 | ee76f82e | blueswir1 | * SPARCstation IPC
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63 | ee76f82e | blueswir1 | * SPARCstation ELC
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64 | ee76f82e | blueswir1 | * SPARCstation IPX
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65 | ee76f82e | blueswir1 | *
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66 | 36cd9210 | blueswir1 | * See for example: http://www.sunhelp.org/faq/sunref1.html
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67 | 36cd9210 | blueswir1 | */
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68 | 36cd9210 | blueswir1 | |
69 | b3a23197 | blueswir1 | #ifdef DEBUG_IRQ
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70 | b3a23197 | blueswir1 | #define DPRINTF(fmt, args...) \
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71 | b3a23197 | blueswir1 | do { printf("CPUIRQ: " fmt , ##args); } while (0) |
72 | b3a23197 | blueswir1 | #else
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73 | b3a23197 | blueswir1 | #define DPRINTF(fmt, args...)
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74 | b3a23197 | blueswir1 | #endif
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75 | b3a23197 | blueswir1 | |
76 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
77 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
78 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
79 | aa6ad6fe | blueswir1 | #define PROM_SIZE_MAX (512 * 1024) |
80 | 40ce0a9a | blueswir1 | #define PROM_VADDR 0xffd00000 |
81 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc32" |
82 | 3cce6243 | blueswir1 | #define CFG_ADDR 0xd00000510ULL |
83 | fbfcf955 | blueswir1 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
84 | b8174937 | bellard | |
85 | ac2e9d66 | blueswir1 | // Control plane, 8-bit and 24-bit planes
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86 | ac2e9d66 | blueswir1 | #define TCX_SIZE (9 * 1024 * 1024) |
87 | ac2e9d66 | blueswir1 | |
88 | ba3c64fb | bellard | #define MAX_CPUS 16 |
89 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
90 | 420557e8 | bellard | |
91 | 36cd9210 | blueswir1 | struct hwdef {
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92 | 5dcb6b91 | blueswir1 | target_phys_addr_t iommu_base, slavio_base; |
93 | 5dcb6b91 | blueswir1 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
94 | 5dcb6b91 | blueswir1 | target_phys_addr_t serial_base, fd_base; |
95 | 4c2485de | blueswir1 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
96 | 0019ad53 | blueswir1 | target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
97 | 7eb0c8e8 | blueswir1 | target_phys_addr_t ecc_base; |
98 | 7eb0c8e8 | blueswir1 | uint32_t ecc_version; |
99 | ee76f82e | blueswir1 | target_phys_addr_t sun4c_intctl_base, sun4c_counter_base; |
100 | 36cd9210 | blueswir1 | long vram_size, nvram_size;
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101 | 6341fdcb | blueswir1 | // IRQ numbers are not PIL ones, but master interrupt controller
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102 | e3a79bca | blueswir1 | // register bit numbers
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103 | d7edfd27 | blueswir1 | int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
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104 | e42c20b4 | blueswir1 | int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
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105 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
106 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
107 | 7fbfb139 | blueswir1 | uint32_t iommu_version; |
108 | e0353fe2 | blueswir1 | uint32_t intbit_to_level[32];
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109 | 3ebf5aaf | blueswir1 | uint64_t max_mem; |
110 | 3ebf5aaf | blueswir1 | const char * const default_cpu_model; |
111 | 36cd9210 | blueswir1 | }; |
112 | 36cd9210 | blueswir1 | |
113 | 7d85892b | blueswir1 | #define MAX_IOUNITS 5 |
114 | 7d85892b | blueswir1 | |
115 | 7d85892b | blueswir1 | struct sun4d_hwdef {
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116 | 7d85892b | blueswir1 | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
117 | 7d85892b | blueswir1 | target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
118 | 7d85892b | blueswir1 | target_phys_addr_t serial_base; |
119 | 7d85892b | blueswir1 | target_phys_addr_t espdma_base, esp_base; |
120 | 7d85892b | blueswir1 | target_phys_addr_t ledma_base, le_base; |
121 | 7d85892b | blueswir1 | target_phys_addr_t tcx_base; |
122 | 7d85892b | blueswir1 | target_phys_addr_t sbi_base; |
123 | 7d85892b | blueswir1 | unsigned long vram_size, nvram_size; |
124 | 7d85892b | blueswir1 | // IRQ numbers are not PIL ones, but SBI register bit numbers
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125 | 7d85892b | blueswir1 | int esp_irq, le_irq, clock_irq, clock1_irq;
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126 | 7d85892b | blueswir1 | int ser_irq, ms_kb_irq, me_irq;
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127 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
128 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
129 | 7d85892b | blueswir1 | uint32_t iounit_version; |
130 | 7d85892b | blueswir1 | uint64_t max_mem; |
131 | 7d85892b | blueswir1 | const char * const default_cpu_model; |
132 | 7d85892b | blueswir1 | }; |
133 | 7d85892b | blueswir1 | |
134 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
135 | 6f7e9aec | bellard | { |
136 | 6f7e9aec | bellard | return 0; |
137 | 6f7e9aec | bellard | } |
138 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
139 | 6f7e9aec | bellard | { |
140 | 6f7e9aec | bellard | return 0; |
141 | 6f7e9aec | bellard | } |
142 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
143 | 6f7e9aec | bellard | { |
144 | 6f7e9aec | bellard | return 0; |
145 | 6f7e9aec | bellard | } |
146 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
147 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
148 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
149 | 6f7e9aec | bellard | void DMA_run (void) {} |
150 | 6f7e9aec | bellard | void DMA_init (int high_page_enable) {} |
151 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
152 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
153 | 6f7e9aec | bellard | void *opaque)
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154 | 6f7e9aec | bellard | { |
155 | 6f7e9aec | bellard | } |
156 | 6f7e9aec | bellard | |
157 | 81864572 | blueswir1 | static int nvram_boot_set(void *opaque, const char *boot_device) |
158 | 81864572 | blueswir1 | { |
159 | 81864572 | blueswir1 | unsigned int i; |
160 | 81864572 | blueswir1 | uint8_t image[sizeof(ohwcfg_v3_t)];
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161 | 81864572 | blueswir1 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
162 | 81864572 | blueswir1 | m48t59_t *nvram = (m48t59_t *)opaque; |
163 | 81864572 | blueswir1 | |
164 | 81864572 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
165 | 81864572 | blueswir1 | image[i] = m48t59_read(nvram, i) & 0xff;
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166 | 81864572 | blueswir1 | |
167 | 363a37d5 | blueswir1 | pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
168 | 363a37d5 | blueswir1 | boot_device); |
169 | 81864572 | blueswir1 | header->nboot_devices = strlen(boot_device) & 0xff;
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170 | 81864572 | blueswir1 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
171 | 81864572 | blueswir1 | |
172 | 81864572 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
173 | 81864572 | blueswir1 | m48t59_write(nvram, i, image[i]); |
174 | 81864572 | blueswir1 | |
175 | 81864572 | blueswir1 | return 0; |
176 | 81864572 | blueswir1 | } |
177 | 81864572 | blueswir1 | |
178 | 6f7e9aec | bellard | extern int nographic; |
179 | 6f7e9aec | bellard | |
180 | 819385c5 | bellard | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
181 | 6ef05b95 | blueswir1 | const char *boot_devices, ram_addr_t RAM_size, |
182 | f930d07e | blueswir1 | uint32_t kernel_size, |
183 | f930d07e | blueswir1 | int width, int height, int depth, |
184 | 905fdcb5 | blueswir1 | int nvram_machine_id, const char *arch) |
185 | e80cfcfc | bellard | { |
186 | d2c63fc1 | blueswir1 | unsigned int i; |
187 | 66508601 | blueswir1 | uint32_t start, end; |
188 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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189 | d2c63fc1 | blueswir1 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
190 | d2c63fc1 | blueswir1 | struct sparc_arch_cfg *sparc_header;
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191 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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192 | d2c63fc1 | blueswir1 | |
193 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
194 | e80cfcfc | bellard | |
195 | 6f7e9aec | bellard | // Try to match PPC NVRAM
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196 | 363a37d5 | blueswir1 | pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident), |
197 | 363a37d5 | blueswir1 | "QEMU_BIOS");
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198 | d2c63fc1 | blueswir1 | header->struct_version = cpu_to_be32(3); /* structure v3 */ |
199 | d2c63fc1 | blueswir1 | |
200 | d2c63fc1 | blueswir1 | header->nvram_size = cpu_to_be16(0x2000);
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201 | d2c63fc1 | blueswir1 | header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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202 | d2c63fc1 | blueswir1 | header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); |
203 | 363a37d5 | blueswir1 | pstrcpy((char *)header->arch, sizeof(header->arch), arch); |
204 | d2c63fc1 | blueswir1 | header->nb_cpus = smp_cpus & 0xff;
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205 | d2c63fc1 | blueswir1 | header->RAM0_base = 0;
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206 | d2c63fc1 | blueswir1 | header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); |
207 | 363a37d5 | blueswir1 | pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
208 | 363a37d5 | blueswir1 | boot_devices); |
209 | d2c63fc1 | blueswir1 | header->nboot_devices = strlen(boot_devices) & 0xff;
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210 | d2c63fc1 | blueswir1 | header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR); |
211 | d2c63fc1 | blueswir1 | header->kernel_size = cpu_to_be64((uint64_t)kernel_size); |
212 | b6f479d3 | bellard | if (cmdline) {
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213 | 293f78bc | blueswir1 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline); |
214 | d2c63fc1 | blueswir1 | header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
215 | d2c63fc1 | blueswir1 | header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); |
216 | b6f479d3 | bellard | } |
217 | d2c63fc1 | blueswir1 | // XXX add initrd_image, initrd_size
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218 | d2c63fc1 | blueswir1 | header->width = cpu_to_be16(width); |
219 | d2c63fc1 | blueswir1 | header->height = cpu_to_be16(height); |
220 | d2c63fc1 | blueswir1 | header->depth = cpu_to_be16(depth); |
221 | d2c63fc1 | blueswir1 | if (nographic)
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222 | d2c63fc1 | blueswir1 | header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); |
223 | d2c63fc1 | blueswir1 | |
224 | d2c63fc1 | blueswir1 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
225 | d2c63fc1 | blueswir1 | |
226 | d2c63fc1 | blueswir1 | // Architecture specific header
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227 | d2c63fc1 | blueswir1 | start = sizeof(ohwcfg_v3_t);
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228 | d2c63fc1 | blueswir1 | sparc_header = (struct sparc_arch_cfg *)&image[start];
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229 | d2c63fc1 | blueswir1 | sparc_header->valid = 0;
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230 | d2c63fc1 | blueswir1 | start += sizeof(struct sparc_arch_cfg); |
231 | b6f479d3 | bellard | |
232 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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233 | 66508601 | blueswir1 | // Variable partition
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234 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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235 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
236 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
237 | 66508601 | blueswir1 | |
238 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
239 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
240 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
241 | d2c63fc1 | blueswir1 | |
242 | d2c63fc1 | blueswir1 | // End marker
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243 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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244 | 66508601 | blueswir1 | |
245 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
246 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
247 | 66508601 | blueswir1 | |
248 | 66508601 | blueswir1 | // free partition
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249 | 66508601 | blueswir1 | start = end; |
250 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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251 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
252 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
253 | 66508601 | blueswir1 | |
254 | 66508601 | blueswir1 | end = 0x1fd0;
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255 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
256 | d2c63fc1 | blueswir1 | |
257 | 905fdcb5 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
258 | 905fdcb5 | blueswir1 | nvram_machine_id); |
259 | d2c63fc1 | blueswir1 | |
260 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
261 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
262 | 81864572 | blueswir1 | |
263 | 81864572 | blueswir1 | qemu_register_boot_set(nvram_boot_set, nvram); |
264 | e80cfcfc | bellard | } |
265 | e80cfcfc | bellard | |
266 | e80cfcfc | bellard | static void *slavio_intctl; |
267 | e80cfcfc | bellard | |
268 | 22548760 | blueswir1 | void pic_info(void) |
269 | e80cfcfc | bellard | { |
270 | 7d85892b | blueswir1 | if (slavio_intctl)
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271 | 7d85892b | blueswir1 | slavio_pic_info(slavio_intctl); |
272 | e80cfcfc | bellard | } |
273 | e80cfcfc | bellard | |
274 | 22548760 | blueswir1 | void irq_info(void) |
275 | e80cfcfc | bellard | { |
276 | 7d85892b | blueswir1 | if (slavio_intctl)
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277 | 7d85892b | blueswir1 | slavio_irq_info(slavio_intctl); |
278 | e80cfcfc | bellard | } |
279 | e80cfcfc | bellard | |
280 | 327ac2e7 | blueswir1 | void cpu_check_irqs(CPUState *env)
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281 | 327ac2e7 | blueswir1 | { |
282 | 327ac2e7 | blueswir1 | if (env->pil_in && (env->interrupt_index == 0 || |
283 | 327ac2e7 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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284 | 327ac2e7 | blueswir1 | unsigned int i; |
285 | 327ac2e7 | blueswir1 | |
286 | 327ac2e7 | blueswir1 | for (i = 15; i > 0; i--) { |
287 | 327ac2e7 | blueswir1 | if (env->pil_in & (1 << i)) { |
288 | 327ac2e7 | blueswir1 | int old_interrupt = env->interrupt_index;
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289 | 327ac2e7 | blueswir1 | |
290 | 327ac2e7 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
291 | f32d7ec5 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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292 | f32d7ec5 | blueswir1 | DPRINTF("Set CPU IRQ %d\n", i);
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293 | 327ac2e7 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
294 | f32d7ec5 | blueswir1 | } |
295 | 327ac2e7 | blueswir1 | break;
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296 | 327ac2e7 | blueswir1 | } |
297 | 327ac2e7 | blueswir1 | } |
298 | 327ac2e7 | blueswir1 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
299 | f32d7ec5 | blueswir1 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
300 | 327ac2e7 | blueswir1 | env->interrupt_index = 0;
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301 | 327ac2e7 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
302 | 327ac2e7 | blueswir1 | } |
303 | 327ac2e7 | blueswir1 | } |
304 | 327ac2e7 | blueswir1 | |
305 | b3a23197 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
306 | b3a23197 | blueswir1 | { |
307 | b3a23197 | blueswir1 | CPUState *env = opaque; |
308 | b3a23197 | blueswir1 | |
309 | b3a23197 | blueswir1 | if (level) {
|
310 | b3a23197 | blueswir1 | DPRINTF("Raise CPU IRQ %d\n", irq);
|
311 | b3a23197 | blueswir1 | env->halted = 0;
|
312 | 327ac2e7 | blueswir1 | env->pil_in |= 1 << irq;
|
313 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
314 | b3a23197 | blueswir1 | } else {
|
315 | b3a23197 | blueswir1 | DPRINTF("Lower CPU IRQ %d\n", irq);
|
316 | 327ac2e7 | blueswir1 | env->pil_in &= ~(1 << irq);
|
317 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
318 | b3a23197 | blueswir1 | } |
319 | b3a23197 | blueswir1 | } |
320 | b3a23197 | blueswir1 | |
321 | b3a23197 | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
322 | b3a23197 | blueswir1 | { |
323 | b3a23197 | blueswir1 | } |
324 | b3a23197 | blueswir1 | |
325 | 3475187d | bellard | static void *slavio_misc; |
326 | 3475187d | bellard | |
327 | 3475187d | bellard | void qemu_system_powerdown(void) |
328 | 3475187d | bellard | { |
329 | 3475187d | bellard | slavio_set_power_fail(slavio_misc, 1);
|
330 | 3475187d | bellard | } |
331 | 3475187d | bellard | |
332 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
333 | c68ea704 | bellard | { |
334 | c68ea704 | bellard | CPUState *env = opaque; |
335 | 3d29fbef | blueswir1 | |
336 | 3d29fbef | blueswir1 | cpu_reset(env); |
337 | 3d29fbef | blueswir1 | env->halted = 0;
|
338 | 3d29fbef | blueswir1 | } |
339 | 3d29fbef | blueswir1 | |
340 | 3d29fbef | blueswir1 | static void secondary_cpu_reset(void *opaque) |
341 | 3d29fbef | blueswir1 | { |
342 | 3d29fbef | blueswir1 | CPUState *env = opaque; |
343 | 3d29fbef | blueswir1 | |
344 | c68ea704 | bellard | cpu_reset(env); |
345 | 3d29fbef | blueswir1 | env->halted = 1;
|
346 | c68ea704 | bellard | } |
347 | c68ea704 | bellard | |
348 | 3ebf5aaf | blueswir1 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
349 | 293f78bc | blueswir1 | const char *initrd_filename, |
350 | 293f78bc | blueswir1 | ram_addr_t RAM_size) |
351 | 3ebf5aaf | blueswir1 | { |
352 | 3ebf5aaf | blueswir1 | int linux_boot;
|
353 | 3ebf5aaf | blueswir1 | unsigned int i; |
354 | 3ebf5aaf | blueswir1 | long initrd_size, kernel_size;
|
355 | 3ebf5aaf | blueswir1 | |
356 | 3ebf5aaf | blueswir1 | linux_boot = (kernel_filename != NULL);
|
357 | 3ebf5aaf | blueswir1 | |
358 | 3ebf5aaf | blueswir1 | kernel_size = 0;
|
359 | 3ebf5aaf | blueswir1 | if (linux_boot) {
|
360 | 3ebf5aaf | blueswir1 | kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
361 | 3ebf5aaf | blueswir1 | NULL);
|
362 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
363 | 293f78bc | blueswir1 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
364 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
365 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
366 | 293f78bc | blueswir1 | kernel_size = load_image_targphys(kernel_filename, |
367 | 293f78bc | blueswir1 | KERNEL_LOAD_ADDR, |
368 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
369 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) { |
370 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
371 | 3ebf5aaf | blueswir1 | kernel_filename); |
372 | 3ebf5aaf | blueswir1 | exit(1);
|
373 | 3ebf5aaf | blueswir1 | } |
374 | 3ebf5aaf | blueswir1 | |
375 | 3ebf5aaf | blueswir1 | /* load initrd */
|
376 | 3ebf5aaf | blueswir1 | initrd_size = 0;
|
377 | 3ebf5aaf | blueswir1 | if (initrd_filename) {
|
378 | 293f78bc | blueswir1 | initrd_size = load_image_targphys(initrd_filename, |
379 | 293f78bc | blueswir1 | INITRD_LOAD_ADDR, |
380 | 293f78bc | blueswir1 | RAM_size - INITRD_LOAD_ADDR); |
381 | 3ebf5aaf | blueswir1 | if (initrd_size < 0) { |
382 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
383 | 3ebf5aaf | blueswir1 | initrd_filename); |
384 | 3ebf5aaf | blueswir1 | exit(1);
|
385 | 3ebf5aaf | blueswir1 | } |
386 | 3ebf5aaf | blueswir1 | } |
387 | 3ebf5aaf | blueswir1 | if (initrd_size > 0) { |
388 | 3ebf5aaf | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
389 | 293f78bc | blueswir1 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
390 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
391 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
392 | 3ebf5aaf | blueswir1 | break;
|
393 | 3ebf5aaf | blueswir1 | } |
394 | 3ebf5aaf | blueswir1 | } |
395 | 3ebf5aaf | blueswir1 | } |
396 | 3ebf5aaf | blueswir1 | } |
397 | 3ebf5aaf | blueswir1 | return kernel_size;
|
398 | 3ebf5aaf | blueswir1 | } |
399 | 3ebf5aaf | blueswir1 | |
400 | 6ef05b95 | blueswir1 | static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, |
401 | 3ebf5aaf | blueswir1 | const char *boot_device, |
402 | 3ebf5aaf | blueswir1 | DisplayState *ds, const char *kernel_filename, |
403 | 3ebf5aaf | blueswir1 | const char *kernel_cmdline, |
404 | 3ebf5aaf | blueswir1 | const char *initrd_filename, const char *cpu_model) |
405 | 36cd9210 | blueswir1 | |
406 | 420557e8 | bellard | { |
407 | ba3c64fb | bellard | CPUState *env, *envs[MAX_CPUS]; |
408 | 713c45fa | bellard | unsigned int i; |
409 | b3ceef24 | blueswir1 | void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
410 | b3a23197 | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
411 | d7edfd27 | blueswir1 | *espdma_irq, *ledma_irq; |
412 | 2d069bab | blueswir1 | qemu_irq *esp_reset, *le_reset; |
413 | 2be17ebd | blueswir1 | qemu_irq *fdc_tc; |
414 | 3ebf5aaf | blueswir1 | unsigned long prom_offset, kernel_size; |
415 | 3ebf5aaf | blueswir1 | int ret;
|
416 | 3ebf5aaf | blueswir1 | char buf[1024]; |
417 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
418 | 22548760 | blueswir1 | int drive_index;
|
419 | 3cce6243 | blueswir1 | void *fw_cfg;
|
420 | 420557e8 | bellard | |
421 | ba3c64fb | bellard | /* init CPUs */
|
422 | 3ebf5aaf | blueswir1 | if (!cpu_model)
|
423 | 3ebf5aaf | blueswir1 | cpu_model = hwdef->default_cpu_model; |
424 | b3a23197 | blueswir1 | |
425 | ba3c64fb | bellard | for(i = 0; i < smp_cpus; i++) { |
426 | aaed909a | bellard | env = cpu_init(cpu_model); |
427 | aaed909a | bellard | if (!env) {
|
428 | 8e82c6a8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
429 | aaed909a | bellard | exit(1);
|
430 | aaed909a | bellard | } |
431 | aaed909a | bellard | cpu_sparc_set_id(env, i); |
432 | ba3c64fb | bellard | envs[i] = env; |
433 | 3d29fbef | blueswir1 | if (i == 0) { |
434 | 3d29fbef | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
435 | 3d29fbef | blueswir1 | } else {
|
436 | 3d29fbef | blueswir1 | qemu_register_reset(secondary_cpu_reset, env); |
437 | ba3c64fb | bellard | env->halted = 1;
|
438 | 3d29fbef | blueswir1 | } |
439 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
440 | 3ebf5aaf | blueswir1 | env->prom_addr = hwdef->slavio_base; |
441 | ba3c64fb | bellard | } |
442 | b3a23197 | blueswir1 | |
443 | b3a23197 | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
444 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
445 | b3a23197 | blueswir1 | |
446 | 3ebf5aaf | blueswir1 | |
447 | 420557e8 | bellard | /* allocate RAM */
|
448 | 3ebf5aaf | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
449 | 77f193da | blueswir1 | fprintf(stderr, |
450 | 77f193da | blueswir1 | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
451 | 6ef05b95 | blueswir1 | (unsigned int)(RAM_size / (1024 * 1024)), |
452 | 3ebf5aaf | blueswir1 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
453 | 3ebf5aaf | blueswir1 | exit(1);
|
454 | 3ebf5aaf | blueswir1 | } |
455 | b3ceef24 | blueswir1 | cpu_register_physical_memory(0, RAM_size, 0); |
456 | 420557e8 | bellard | |
457 | 3ebf5aaf | blueswir1 | /* load boot prom */
|
458 | 3ebf5aaf | blueswir1 | prom_offset = RAM_size + hwdef->vram_size; |
459 | 3ebf5aaf | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
460 | 3ebf5aaf | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
461 | 3ebf5aaf | blueswir1 | TARGET_PAGE_MASK, |
462 | 3ebf5aaf | blueswir1 | prom_offset | IO_MEM_ROM); |
463 | 3ebf5aaf | blueswir1 | |
464 | 3ebf5aaf | blueswir1 | if (bios_name == NULL) |
465 | 3ebf5aaf | blueswir1 | bios_name = PROM_FILENAME; |
466 | 3ebf5aaf | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
467 | 3ebf5aaf | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
468 | 3ebf5aaf | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
469 | e01f4a1c | blueswir1 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
470 | 3ebf5aaf | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
471 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
472 | 3ebf5aaf | blueswir1 | buf); |
473 | 3ebf5aaf | blueswir1 | exit(1);
|
474 | 3ebf5aaf | blueswir1 | } |
475 | 4c2485de | blueswir1 | prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
476 | 3ebf5aaf | blueswir1 | |
477 | 3ebf5aaf | blueswir1 | /* set up devices */
|
478 | 36cd9210 | blueswir1 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
479 | 5dcb6b91 | blueswir1 | hwdef->intctl_base + 0x10000ULL,
|
480 | d537cf6c | pbrook | &hwdef->intbit_to_level[0],
|
481 | d7edfd27 | blueswir1 | &slavio_irq, &slavio_cpu_irq, |
482 | b3a23197 | blueswir1 | cpu_irqs, |
483 | d7edfd27 | blueswir1 | hwdef->clock_irq); |
484 | b3a23197 | blueswir1 | |
485 | 4c2485de | blueswir1 | if (hwdef->idreg_base != (target_phys_addr_t)-1) { |
486 | 293f78bc | blueswir1 | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
487 | 4c2485de | blueswir1 | |
488 | 293f78bc | blueswir1 | cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
|
489 | 4c2485de | blueswir1 | prom_offset | IO_MEM_ROM); |
490 | 293f78bc | blueswir1 | cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data, |
491 | 293f78bc | blueswir1 | sizeof(idreg_data));
|
492 | 4c2485de | blueswir1 | } |
493 | 4c2485de | blueswir1 | |
494 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
495 | ff403da6 | blueswir1 | slavio_irq[hwdef->me_irq]); |
496 | ff403da6 | blueswir1 | |
497 | 5aca8c3b | blueswir1 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
498 | 2d069bab | blueswir1 | iommu, &espdma_irq, &esp_reset); |
499 | 2d069bab | blueswir1 | |
500 | 5aca8c3b | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
501 | 2d069bab | blueswir1 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
502 | 2d069bab | blueswir1 | &le_reset); |
503 | ba3c64fb | bellard | |
504 | eee0b836 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
505 | eee0b836 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
506 | eee0b836 | blueswir1 | exit (1);
|
507 | eee0b836 | blueswir1 | } |
508 | b3ceef24 | blueswir1 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
509 | eee0b836 | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
510 | dbe06e18 | blueswir1 | |
511 | dbe06e18 | blueswir1 | if (nd_table[0].model == NULL |
512 | dbe06e18 | blueswir1 | || strcmp(nd_table[0].model, "lance") == 0) { |
513 | 2d069bab | blueswir1 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
514 | c4a7060c | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
515 | c4a7060c | blueswir1 | fprintf(stderr, "qemu: Supported NICs: lance\n");
|
516 | c4a7060c | blueswir1 | exit (1);
|
517 | dbe06e18 | blueswir1 | } else {
|
518 | dbe06e18 | blueswir1 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
519 | dbe06e18 | blueswir1 | exit (1);
|
520 | a41b2ff2 | pbrook | } |
521 | dbe06e18 | blueswir1 | |
522 | d537cf6c | pbrook | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
523 | d537cf6c | pbrook | hwdef->nvram_size, 8);
|
524 | 81732d19 | blueswir1 | |
525 | 81732d19 | blueswir1 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq], |
526 | 19f8e5dd | blueswir1 | slavio_cpu_irq, smp_cpus); |
527 | 81732d19 | blueswir1 | |
528 | 577390ff | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
529 | 577390ff | blueswir1 | nographic); |
530 | b81b3b10 | bellard | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
531 | b81b3b10 | bellard | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
532 | d537cf6c | pbrook | slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
533 | d537cf6c | pbrook | serial_hds[1], serial_hds[0]); |
534 | 741402f9 | blueswir1 | |
535 | 2be17ebd | blueswir1 | slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base, |
536 | 2be17ebd | blueswir1 | hwdef->aux1_base, hwdef->aux2_base, |
537 | 2be17ebd | blueswir1 | slavio_irq[hwdef->me_irq], envs[0],
|
538 | 2be17ebd | blueswir1 | &fdc_tc); |
539 | 2be17ebd | blueswir1 | |
540 | e4bcb14c | ths | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
541 | e4bcb14c | ths | /* there is zero or one floppy drive */
|
542 | 309e60bd | blueswir1 | memset(fd, 0, sizeof(fd)); |
543 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
544 | 22548760 | blueswir1 | if (drive_index != -1) |
545 | 22548760 | blueswir1 | fd[0] = drives_table[drive_index].bdrv;
|
546 | 2d069bab | blueswir1 | |
547 | 2be17ebd | blueswir1 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
548 | 2be17ebd | blueswir1 | fdc_tc); |
549 | e4bcb14c | ths | } |
550 | e4bcb14c | ths | |
551 | e4bcb14c | ths | if (drive_get_max_bus(IF_SCSI) > 0) { |
552 | e4bcb14c | ths | fprintf(stderr, "qemu: too many SCSI bus\n");
|
553 | e4bcb14c | ths | exit(1);
|
554 | e4bcb14c | ths | } |
555 | e4bcb14c | ths | |
556 | 5d20fa6b | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
557 | 8b17de88 | blueswir1 | espdma_memory_read, espdma_memory_write, |
558 | 8b17de88 | blueswir1 | espdma, *espdma_irq, esp_reset); |
559 | f1587550 | ths | |
560 | e4bcb14c | ths | for (i = 0; i < ESP_MAX_DEVS; i++) { |
561 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_SCSI, 0, i);
|
562 | 22548760 | blueswir1 | if (drive_index == -1) |
563 | e4bcb14c | ths | continue;
|
564 | 22548760 | blueswir1 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
565 | f1587550 | ths | } |
566 | f1587550 | ths | |
567 | 5dcb6b91 | blueswir1 | if (hwdef->cs_base != (target_phys_addr_t)-1) |
568 | 803b3c7b | blueswir1 | cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
569 | b3ceef24 | blueswir1 | |
570 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
571 | 293f78bc | blueswir1 | RAM_size); |
572 | 36cd9210 | blueswir1 | |
573 | 36cd9210 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
574 | b3ceef24 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
575 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
576 | 905fdcb5 | blueswir1 | "Sun4m");
|
577 | 7eb0c8e8 | blueswir1 | |
578 | 7eb0c8e8 | blueswir1 | if (hwdef->ecc_base != (target_phys_addr_t)-1) |
579 | e42c20b4 | blueswir1 | ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq], |
580 | e42c20b4 | blueswir1 | hwdef->ecc_version); |
581 | 3cce6243 | blueswir1 | |
582 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
583 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
584 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
585 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
586 | fbfcf955 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
587 | 36cd9210 | blueswir1 | } |
588 | 36cd9210 | blueswir1 | |
589 | 6ef05b95 | blueswir1 | static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, |
590 | ee76f82e | blueswir1 | const char *boot_device, |
591 | ee76f82e | blueswir1 | DisplayState *ds, const char *kernel_filename, |
592 | ee76f82e | blueswir1 | const char *kernel_cmdline, |
593 | ee76f82e | blueswir1 | const char *initrd_filename, const char *cpu_model) |
594 | ee76f82e | blueswir1 | { |
595 | ee76f82e | blueswir1 | CPUState *env; |
596 | ee76f82e | blueswir1 | unsigned int i; |
597 | ee76f82e | blueswir1 | void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
598 | ee76f82e | blueswir1 | qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; |
599 | ee76f82e | blueswir1 | qemu_irq *esp_reset, *le_reset; |
600 | 2be17ebd | blueswir1 | qemu_irq *fdc_tc; |
601 | ee76f82e | blueswir1 | unsigned long prom_offset, kernel_size; |
602 | ee76f82e | blueswir1 | int ret;
|
603 | ee76f82e | blueswir1 | char buf[1024]; |
604 | ee76f82e | blueswir1 | BlockDriverState *fd[MAX_FD]; |
605 | 22548760 | blueswir1 | int drive_index;
|
606 | 3cce6243 | blueswir1 | void *fw_cfg;
|
607 | ee76f82e | blueswir1 | |
608 | ee76f82e | blueswir1 | /* init CPU */
|
609 | ee76f82e | blueswir1 | if (!cpu_model)
|
610 | ee76f82e | blueswir1 | cpu_model = hwdef->default_cpu_model; |
611 | ee76f82e | blueswir1 | |
612 | ee76f82e | blueswir1 | env = cpu_init(cpu_model); |
613 | ee76f82e | blueswir1 | if (!env) {
|
614 | 8e82c6a8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
615 | ee76f82e | blueswir1 | exit(1);
|
616 | ee76f82e | blueswir1 | } |
617 | ee76f82e | blueswir1 | |
618 | ee76f82e | blueswir1 | cpu_sparc_set_id(env, 0);
|
619 | ee76f82e | blueswir1 | |
620 | ee76f82e | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
621 | ee76f82e | blueswir1 | cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
622 | cebb73aa | blueswir1 | env->prom_addr = hwdef->slavio_base; |
623 | ee76f82e | blueswir1 | |
624 | ee76f82e | blueswir1 | /* allocate RAM */
|
625 | ee76f82e | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
626 | 77f193da | blueswir1 | fprintf(stderr, |
627 | 77f193da | blueswir1 | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
628 | 6ef05b95 | blueswir1 | (unsigned int)(RAM_size / (1024 * 1024)), |
629 | 6ef05b95 | blueswir1 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
630 | ee76f82e | blueswir1 | exit(1);
|
631 | ee76f82e | blueswir1 | } |
632 | ee76f82e | blueswir1 | cpu_register_physical_memory(0, RAM_size, 0); |
633 | ee76f82e | blueswir1 | |
634 | ee76f82e | blueswir1 | /* load boot prom */
|
635 | ee76f82e | blueswir1 | prom_offset = RAM_size + hwdef->vram_size; |
636 | ee76f82e | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
637 | ee76f82e | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
638 | ee76f82e | blueswir1 | TARGET_PAGE_MASK, |
639 | ee76f82e | blueswir1 | prom_offset | IO_MEM_ROM); |
640 | ee76f82e | blueswir1 | |
641 | ee76f82e | blueswir1 | if (bios_name == NULL) |
642 | ee76f82e | blueswir1 | bios_name = PROM_FILENAME; |
643 | ee76f82e | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
644 | ee76f82e | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
645 | ee76f82e | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
646 | e01f4a1c | blueswir1 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
647 | ee76f82e | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
648 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
649 | ee76f82e | blueswir1 | buf); |
650 | ee76f82e | blueswir1 | exit(1);
|
651 | ee76f82e | blueswir1 | } |
652 | ee76f82e | blueswir1 | prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
653 | ee76f82e | blueswir1 | |
654 | ee76f82e | blueswir1 | /* set up devices */
|
655 | ee76f82e | blueswir1 | slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base, |
656 | ee76f82e | blueswir1 | &slavio_irq, cpu_irqs); |
657 | ee76f82e | blueswir1 | |
658 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
659 | ff403da6 | blueswir1 | slavio_irq[hwdef->me_irq]); |
660 | ee76f82e | blueswir1 | |
661 | ee76f82e | blueswir1 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
662 | ee76f82e | blueswir1 | iommu, &espdma_irq, &esp_reset); |
663 | ee76f82e | blueswir1 | |
664 | ee76f82e | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
665 | ee76f82e | blueswir1 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
666 | ee76f82e | blueswir1 | &le_reset); |
667 | ee76f82e | blueswir1 | |
668 | ee76f82e | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
669 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
670 | ee76f82e | blueswir1 | exit (1);
|
671 | ee76f82e | blueswir1 | } |
672 | ee76f82e | blueswir1 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
673 | ee76f82e | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
674 | ee76f82e | blueswir1 | |
675 | ee76f82e | blueswir1 | if (nd_table[0].model == NULL |
676 | ee76f82e | blueswir1 | || strcmp(nd_table[0].model, "lance") == 0) { |
677 | ee76f82e | blueswir1 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
678 | ee76f82e | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
679 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: Supported NICs: lance\n");
|
680 | ee76f82e | blueswir1 | exit (1);
|
681 | ee76f82e | blueswir1 | } else {
|
682 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
683 | ee76f82e | blueswir1 | exit (1);
|
684 | ee76f82e | blueswir1 | } |
685 | ee76f82e | blueswir1 | |
686 | ee76f82e | blueswir1 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
687 | 4aed2c33 | blueswir1 | hwdef->nvram_size, 2);
|
688 | ee76f82e | blueswir1 | |
689 | ee76f82e | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
690 | ee76f82e | blueswir1 | nographic); |
691 | ee76f82e | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
692 | ee76f82e | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
693 | ee76f82e | blueswir1 | slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
694 | ee76f82e | blueswir1 | serial_hds[1], serial_hds[0]); |
695 | ee76f82e | blueswir1 | |
696 | 2be17ebd | blueswir1 | slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
|
697 | 2be17ebd | blueswir1 | hwdef->aux1_base, hwdef->aux2_base, |
698 | 2be17ebd | blueswir1 | slavio_irq[hwdef->me_irq], env, &fdc_tc); |
699 | 2be17ebd | blueswir1 | |
700 | ee76f82e | blueswir1 | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
701 | ee76f82e | blueswir1 | /* there is zero or one floppy drive */
|
702 | ee76f82e | blueswir1 | fd[1] = fd[0] = NULL; |
703 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
704 | 22548760 | blueswir1 | if (drive_index != -1) |
705 | 22548760 | blueswir1 | fd[0] = drives_table[drive_index].bdrv;
|
706 | ee76f82e | blueswir1 | |
707 | 2be17ebd | blueswir1 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
708 | 2be17ebd | blueswir1 | fdc_tc); |
709 | ee76f82e | blueswir1 | } |
710 | ee76f82e | blueswir1 | |
711 | ee76f82e | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
712 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
713 | ee76f82e | blueswir1 | exit(1);
|
714 | ee76f82e | blueswir1 | } |
715 | ee76f82e | blueswir1 | |
716 | 5d20fa6b | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
717 | 8b17de88 | blueswir1 | espdma_memory_read, espdma_memory_write, |
718 | 8b17de88 | blueswir1 | espdma, *espdma_irq, esp_reset); |
719 | ee76f82e | blueswir1 | |
720 | ee76f82e | blueswir1 | for (i = 0; i < ESP_MAX_DEVS; i++) { |
721 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_SCSI, 0, i);
|
722 | 22548760 | blueswir1 | if (drive_index == -1) |
723 | ee76f82e | blueswir1 | continue;
|
724 | 22548760 | blueswir1 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
725 | ee76f82e | blueswir1 | } |
726 | ee76f82e | blueswir1 | |
727 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
728 | 293f78bc | blueswir1 | RAM_size); |
729 | ee76f82e | blueswir1 | |
730 | ee76f82e | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
731 | ee76f82e | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
732 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
733 | 905fdcb5 | blueswir1 | "Sun4c");
|
734 | 3cce6243 | blueswir1 | |
735 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
736 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
737 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
738 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
739 | ee76f82e | blueswir1 | } |
740 | ee76f82e | blueswir1 | |
741 | 905fdcb5 | blueswir1 | enum {
|
742 | 905fdcb5 | blueswir1 | ss2_id = 0,
|
743 | 905fdcb5 | blueswir1 | ss5_id = 32,
|
744 | 905fdcb5 | blueswir1 | vger_id, |
745 | 905fdcb5 | blueswir1 | lx_id, |
746 | 905fdcb5 | blueswir1 | ss4_id, |
747 | 905fdcb5 | blueswir1 | scls_id, |
748 | 905fdcb5 | blueswir1 | sbook_id, |
749 | 905fdcb5 | blueswir1 | ss10_id = 64,
|
750 | 905fdcb5 | blueswir1 | ss20_id, |
751 | 905fdcb5 | blueswir1 | ss600mp_id, |
752 | 905fdcb5 | blueswir1 | ss1000_id = 96,
|
753 | 905fdcb5 | blueswir1 | ss2000_id, |
754 | 905fdcb5 | blueswir1 | }; |
755 | 905fdcb5 | blueswir1 | |
756 | 36cd9210 | blueswir1 | static const struct hwdef hwdefs[] = { |
757 | 36cd9210 | blueswir1 | /* SS-5 */
|
758 | 36cd9210 | blueswir1 | { |
759 | 36cd9210 | blueswir1 | .iommu_base = 0x10000000,
|
760 | 36cd9210 | blueswir1 | .tcx_base = 0x50000000,
|
761 | 36cd9210 | blueswir1 | .cs_base = 0x6c000000,
|
762 | 384ccb5d | blueswir1 | .slavio_base = 0x70000000,
|
763 | 36cd9210 | blueswir1 | .ms_kb_base = 0x71000000,
|
764 | 36cd9210 | blueswir1 | .serial_base = 0x71100000,
|
765 | 36cd9210 | blueswir1 | .nvram_base = 0x71200000,
|
766 | 36cd9210 | blueswir1 | .fd_base = 0x71400000,
|
767 | 36cd9210 | blueswir1 | .counter_base = 0x71d00000,
|
768 | 36cd9210 | blueswir1 | .intctl_base = 0x71e00000,
|
769 | 4c2485de | blueswir1 | .idreg_base = 0x78000000,
|
770 | 36cd9210 | blueswir1 | .dma_base = 0x78400000,
|
771 | 36cd9210 | blueswir1 | .esp_base = 0x78800000,
|
772 | 36cd9210 | blueswir1 | .le_base = 0x78c00000,
|
773 | 127fc407 | blueswir1 | .apc_base = 0x6a000000,
|
774 | 0019ad53 | blueswir1 | .aux1_base = 0x71900000,
|
775 | 0019ad53 | blueswir1 | .aux2_base = 0x71910000,
|
776 | 7eb0c8e8 | blueswir1 | .ecc_base = -1,
|
777 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
778 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
779 | 36cd9210 | blueswir1 | .vram_size = 0x00100000,
|
780 | 36cd9210 | blueswir1 | .nvram_size = 0x2000,
|
781 | 36cd9210 | blueswir1 | .esp_irq = 18,
|
782 | 36cd9210 | blueswir1 | .le_irq = 16,
|
783 | e3a79bca | blueswir1 | .clock_irq = 7,
|
784 | 36cd9210 | blueswir1 | .clock1_irq = 19,
|
785 | 36cd9210 | blueswir1 | .ms_kb_irq = 14,
|
786 | 36cd9210 | blueswir1 | .ser_irq = 15,
|
787 | 36cd9210 | blueswir1 | .fd_irq = 22,
|
788 | 36cd9210 | blueswir1 | .me_irq = 30,
|
789 | 36cd9210 | blueswir1 | .cs_irq = 5,
|
790 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
791 | 905fdcb5 | blueswir1 | .machine_id = ss5_id, |
792 | cf3102ac | blueswir1 | .iommu_version = 0x05000000,
|
793 | e0353fe2 | blueswir1 | .intbit_to_level = { |
794 | f930d07e | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
795 | f930d07e | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
796 | e0353fe2 | blueswir1 | }, |
797 | 3ebf5aaf | blueswir1 | .max_mem = 0x10000000,
|
798 | 3ebf5aaf | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
799 | e0353fe2 | blueswir1 | }, |
800 | e0353fe2 | blueswir1 | /* SS-10 */
|
801 | e0353fe2 | blueswir1 | { |
802 | 5dcb6b91 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
803 | 5dcb6b91 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
804 | 803b3c7b | blueswir1 | .cs_base = -1,
|
805 | 5dcb6b91 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
806 | 5dcb6b91 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
807 | 5dcb6b91 | blueswir1 | .serial_base = 0xff1100000ULL,
|
808 | 5dcb6b91 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
809 | 5dcb6b91 | blueswir1 | .fd_base = 0xff1700000ULL,
|
810 | 5dcb6b91 | blueswir1 | .counter_base = 0xff1300000ULL,
|
811 | 5dcb6b91 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
812 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
813 | 5dcb6b91 | blueswir1 | .dma_base = 0xef0400000ULL,
|
814 | 5dcb6b91 | blueswir1 | .esp_base = 0xef0800000ULL,
|
815 | 5dcb6b91 | blueswir1 | .le_base = 0xef0c00000ULL,
|
816 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
817 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
818 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
819 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
820 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x10000000, // version 0, implementation 1 |
821 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
822 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
823 | e0353fe2 | blueswir1 | .vram_size = 0x00100000,
|
824 | e0353fe2 | blueswir1 | .nvram_size = 0x2000,
|
825 | e0353fe2 | blueswir1 | .esp_irq = 18,
|
826 | e0353fe2 | blueswir1 | .le_irq = 16,
|
827 | e3a79bca | blueswir1 | .clock_irq = 7,
|
828 | e0353fe2 | blueswir1 | .clock1_irq = 19,
|
829 | e0353fe2 | blueswir1 | .ms_kb_irq = 14,
|
830 | e0353fe2 | blueswir1 | .ser_irq = 15,
|
831 | e0353fe2 | blueswir1 | .fd_irq = 22,
|
832 | e0353fe2 | blueswir1 | .me_irq = 30,
|
833 | 803b3c7b | blueswir1 | .cs_irq = -1,
|
834 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
835 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
836 | 905fdcb5 | blueswir1 | .machine_id = ss10_id, |
837 | 7fbfb139 | blueswir1 | .iommu_version = 0x03000000,
|
838 | e0353fe2 | blueswir1 | .intbit_to_level = { |
839 | f930d07e | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
840 | f930d07e | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
841 | e0353fe2 | blueswir1 | }, |
842 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
843 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
844 | 36cd9210 | blueswir1 | }, |
845 | 6a3b9cc9 | blueswir1 | /* SS-600MP */
|
846 | 6a3b9cc9 | blueswir1 | { |
847 | 6a3b9cc9 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
848 | 6a3b9cc9 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
849 | 6a3b9cc9 | blueswir1 | .cs_base = -1,
|
850 | 6a3b9cc9 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
851 | 6a3b9cc9 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
852 | 6a3b9cc9 | blueswir1 | .serial_base = 0xff1100000ULL,
|
853 | 6a3b9cc9 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
854 | 6a3b9cc9 | blueswir1 | .fd_base = -1,
|
855 | 6a3b9cc9 | blueswir1 | .counter_base = 0xff1300000ULL,
|
856 | 6a3b9cc9 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
857 | 4c2485de | blueswir1 | .idreg_base = -1,
|
858 | 6a3b9cc9 | blueswir1 | .dma_base = 0xef0081000ULL,
|
859 | 6a3b9cc9 | blueswir1 | .esp_base = 0xef0080000ULL,
|
860 | 6a3b9cc9 | blueswir1 | .le_base = 0xef0060000ULL,
|
861 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
862 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
863 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL, // XXX should not exist |
864 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
865 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x00000000, // version 0, implementation 0 |
866 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
867 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
868 | 6a3b9cc9 | blueswir1 | .vram_size = 0x00100000,
|
869 | 6a3b9cc9 | blueswir1 | .nvram_size = 0x2000,
|
870 | 6a3b9cc9 | blueswir1 | .esp_irq = 18,
|
871 | 6a3b9cc9 | blueswir1 | .le_irq = 16,
|
872 | e3a79bca | blueswir1 | .clock_irq = 7,
|
873 | 6a3b9cc9 | blueswir1 | .clock1_irq = 19,
|
874 | 6a3b9cc9 | blueswir1 | .ms_kb_irq = 14,
|
875 | 6a3b9cc9 | blueswir1 | .ser_irq = 15,
|
876 | 6a3b9cc9 | blueswir1 | .fd_irq = 22,
|
877 | 6a3b9cc9 | blueswir1 | .me_irq = 30,
|
878 | 6a3b9cc9 | blueswir1 | .cs_irq = -1,
|
879 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
880 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x71,
|
881 | 905fdcb5 | blueswir1 | .machine_id = ss600mp_id, |
882 | 7fbfb139 | blueswir1 | .iommu_version = 0x01000000,
|
883 | 6a3b9cc9 | blueswir1 | .intbit_to_level = { |
884 | 6a3b9cc9 | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
885 | 6a3b9cc9 | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
886 | 6a3b9cc9 | blueswir1 | }, |
887 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
888 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
889 | 6a3b9cc9 | blueswir1 | }, |
890 | ae40972f | blueswir1 | /* SS-20 */
|
891 | ae40972f | blueswir1 | { |
892 | ae40972f | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
893 | ae40972f | blueswir1 | .tcx_base = 0xe20000000ULL,
|
894 | ae40972f | blueswir1 | .cs_base = -1,
|
895 | ae40972f | blueswir1 | .slavio_base = 0xff0000000ULL,
|
896 | ae40972f | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
897 | ae40972f | blueswir1 | .serial_base = 0xff1100000ULL,
|
898 | ae40972f | blueswir1 | .nvram_base = 0xff1200000ULL,
|
899 | ae40972f | blueswir1 | .fd_base = 0xff1700000ULL,
|
900 | ae40972f | blueswir1 | .counter_base = 0xff1300000ULL,
|
901 | ae40972f | blueswir1 | .intctl_base = 0xff1400000ULL,
|
902 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
903 | ae40972f | blueswir1 | .dma_base = 0xef0400000ULL,
|
904 | ae40972f | blueswir1 | .esp_base = 0xef0800000ULL,
|
905 | ae40972f | blueswir1 | .le_base = 0xef0c00000ULL,
|
906 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
907 | 577d8dd4 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
908 | 577d8dd4 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
909 | ae40972f | blueswir1 | .ecc_base = 0xf00000000ULL,
|
910 | ae40972f | blueswir1 | .ecc_version = 0x20000000, // version 0, implementation 2 |
911 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
912 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
913 | ae40972f | blueswir1 | .vram_size = 0x00100000,
|
914 | ae40972f | blueswir1 | .nvram_size = 0x2000,
|
915 | ae40972f | blueswir1 | .esp_irq = 18,
|
916 | ae40972f | blueswir1 | .le_irq = 16,
|
917 | e3a79bca | blueswir1 | .clock_irq = 7,
|
918 | ae40972f | blueswir1 | .clock1_irq = 19,
|
919 | ae40972f | blueswir1 | .ms_kb_irq = 14,
|
920 | ae40972f | blueswir1 | .ser_irq = 15,
|
921 | ae40972f | blueswir1 | .fd_irq = 22,
|
922 | ae40972f | blueswir1 | .me_irq = 30,
|
923 | ae40972f | blueswir1 | .cs_irq = -1,
|
924 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
925 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
926 | 905fdcb5 | blueswir1 | .machine_id = ss20_id, |
927 | ae40972f | blueswir1 | .iommu_version = 0x13000000,
|
928 | ae40972f | blueswir1 | .intbit_to_level = { |
929 | ae40972f | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
930 | ae40972f | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
931 | ae40972f | blueswir1 | }, |
932 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
933 | ae40972f | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
934 | ae40972f | blueswir1 | }, |
935 | ee76f82e | blueswir1 | /* SS-2 */
|
936 | ee76f82e | blueswir1 | { |
937 | ee76f82e | blueswir1 | .iommu_base = 0xf8000000,
|
938 | ee76f82e | blueswir1 | .tcx_base = 0xfe000000,
|
939 | ee76f82e | blueswir1 | .cs_base = -1,
|
940 | ee76f82e | blueswir1 | .slavio_base = 0xf6000000,
|
941 | ee76f82e | blueswir1 | .ms_kb_base = 0xf0000000,
|
942 | ee76f82e | blueswir1 | .serial_base = 0xf1000000,
|
943 | ee76f82e | blueswir1 | .nvram_base = 0xf2000000,
|
944 | ee76f82e | blueswir1 | .fd_base = 0xf7200000,
|
945 | ee76f82e | blueswir1 | .counter_base = -1,
|
946 | ee76f82e | blueswir1 | .intctl_base = -1,
|
947 | ee76f82e | blueswir1 | .dma_base = 0xf8400000,
|
948 | ee76f82e | blueswir1 | .esp_base = 0xf8800000,
|
949 | ee76f82e | blueswir1 | .le_base = 0xf8c00000,
|
950 | 0019ad53 | blueswir1 | .apc_base = -1,
|
951 | 0019ad53 | blueswir1 | .aux1_base = 0xf7400003,
|
952 | 0019ad53 | blueswir1 | .aux2_base = -1,
|
953 | ee76f82e | blueswir1 | .sun4c_intctl_base = 0xf5000000,
|
954 | ee76f82e | blueswir1 | .sun4c_counter_base = 0xf3000000,
|
955 | ee76f82e | blueswir1 | .vram_size = 0x00100000,
|
956 | 4aed2c33 | blueswir1 | .nvram_size = 0x800,
|
957 | ee76f82e | blueswir1 | .esp_irq = 2,
|
958 | ee76f82e | blueswir1 | .le_irq = 3,
|
959 | ee76f82e | blueswir1 | .clock_irq = 5,
|
960 | ee76f82e | blueswir1 | .clock1_irq = 7,
|
961 | ee76f82e | blueswir1 | .ms_kb_irq = 1,
|
962 | ee76f82e | blueswir1 | .ser_irq = 1,
|
963 | ee76f82e | blueswir1 | .fd_irq = 1,
|
964 | ee76f82e | blueswir1 | .me_irq = 1,
|
965 | ee76f82e | blueswir1 | .cs_irq = -1,
|
966 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x55,
|
967 | 905fdcb5 | blueswir1 | .machine_id = ss2_id, |
968 | ee76f82e | blueswir1 | .max_mem = 0x10000000,
|
969 | ee76f82e | blueswir1 | .default_cpu_model = "Cypress CY7C601",
|
970 | ee76f82e | blueswir1 | }, |
971 | a526a31c | blueswir1 | /* Voyager */
|
972 | a526a31c | blueswir1 | { |
973 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
974 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
975 | a526a31c | blueswir1 | .cs_base = -1,
|
976 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
977 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
978 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
979 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
980 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
981 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
982 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
983 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
984 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
985 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
986 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
987 | a526a31c | blueswir1 | .apc_base = 0x71300000, // pmc |
988 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
989 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
990 | a526a31c | blueswir1 | .ecc_base = -1,
|
991 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
992 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
993 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
994 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
995 | a526a31c | blueswir1 | .esp_irq = 18,
|
996 | a526a31c | blueswir1 | .le_irq = 16,
|
997 | a526a31c | blueswir1 | .clock_irq = 7,
|
998 | a526a31c | blueswir1 | .clock1_irq = 19,
|
999 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
1000 | a526a31c | blueswir1 | .ser_irq = 15,
|
1001 | a526a31c | blueswir1 | .fd_irq = 22,
|
1002 | a526a31c | blueswir1 | .me_irq = 30,
|
1003 | a526a31c | blueswir1 | .cs_irq = -1,
|
1004 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1005 | 905fdcb5 | blueswir1 | .machine_id = vger_id, |
1006 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1007 | a526a31c | blueswir1 | .intbit_to_level = { |
1008 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1009 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1010 | a526a31c | blueswir1 | }, |
1011 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1012 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1013 | a526a31c | blueswir1 | }, |
1014 | a526a31c | blueswir1 | /* LX */
|
1015 | a526a31c | blueswir1 | { |
1016 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1017 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1018 | a526a31c | blueswir1 | .cs_base = -1,
|
1019 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1020 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1021 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1022 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1023 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1024 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1025 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1026 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1027 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1028 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1029 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1030 | a526a31c | blueswir1 | .apc_base = -1,
|
1031 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1032 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1033 | a526a31c | blueswir1 | .ecc_base = -1,
|
1034 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
1035 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
1036 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
1037 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
1038 | a526a31c | blueswir1 | .esp_irq = 18,
|
1039 | a526a31c | blueswir1 | .le_irq = 16,
|
1040 | a526a31c | blueswir1 | .clock_irq = 7,
|
1041 | a526a31c | blueswir1 | .clock1_irq = 19,
|
1042 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
1043 | a526a31c | blueswir1 | .ser_irq = 15,
|
1044 | a526a31c | blueswir1 | .fd_irq = 22,
|
1045 | a526a31c | blueswir1 | .me_irq = 30,
|
1046 | a526a31c | blueswir1 | .cs_irq = -1,
|
1047 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1048 | 905fdcb5 | blueswir1 | .machine_id = lx_id, |
1049 | a526a31c | blueswir1 | .iommu_version = 0x04000000,
|
1050 | a526a31c | blueswir1 | .intbit_to_level = { |
1051 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1052 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1053 | a526a31c | blueswir1 | }, |
1054 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1055 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1056 | a526a31c | blueswir1 | }, |
1057 | a526a31c | blueswir1 | /* SS-4 */
|
1058 | a526a31c | blueswir1 | { |
1059 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1060 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1061 | a526a31c | blueswir1 | .cs_base = 0x6c000000,
|
1062 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1063 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1064 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1065 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1066 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1067 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1068 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1069 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1070 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1071 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1072 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1073 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1074 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1075 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1076 | a526a31c | blueswir1 | .ecc_base = -1,
|
1077 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
1078 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
1079 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
1080 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
1081 | a526a31c | blueswir1 | .esp_irq = 18,
|
1082 | a526a31c | blueswir1 | .le_irq = 16,
|
1083 | a526a31c | blueswir1 | .clock_irq = 7,
|
1084 | a526a31c | blueswir1 | .clock1_irq = 19,
|
1085 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
1086 | a526a31c | blueswir1 | .ser_irq = 15,
|
1087 | a526a31c | blueswir1 | .fd_irq = 22,
|
1088 | a526a31c | blueswir1 | .me_irq = 30,
|
1089 | a526a31c | blueswir1 | .cs_irq = 5,
|
1090 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1091 | 905fdcb5 | blueswir1 | .machine_id = ss4_id, |
1092 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1093 | a526a31c | blueswir1 | .intbit_to_level = { |
1094 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1095 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1096 | a526a31c | blueswir1 | }, |
1097 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1098 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1099 | a526a31c | blueswir1 | }, |
1100 | a526a31c | blueswir1 | /* SPARCClassic */
|
1101 | a526a31c | blueswir1 | { |
1102 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1103 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1104 | a526a31c | blueswir1 | .cs_base = -1,
|
1105 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1106 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1107 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1108 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1109 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1110 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1111 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1112 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1113 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1114 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1115 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1116 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1117 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1118 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1119 | a526a31c | blueswir1 | .ecc_base = -1,
|
1120 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
1121 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
1122 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
1123 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
1124 | a526a31c | blueswir1 | .esp_irq = 18,
|
1125 | a526a31c | blueswir1 | .le_irq = 16,
|
1126 | a526a31c | blueswir1 | .clock_irq = 7,
|
1127 | a526a31c | blueswir1 | .clock1_irq = 19,
|
1128 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
1129 | a526a31c | blueswir1 | .ser_irq = 15,
|
1130 | a526a31c | blueswir1 | .fd_irq = 22,
|
1131 | a526a31c | blueswir1 | .me_irq = 30,
|
1132 | a526a31c | blueswir1 | .cs_irq = -1,
|
1133 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1134 | 905fdcb5 | blueswir1 | .machine_id = scls_id, |
1135 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1136 | a526a31c | blueswir1 | .intbit_to_level = { |
1137 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1138 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1139 | a526a31c | blueswir1 | }, |
1140 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1141 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1142 | a526a31c | blueswir1 | }, |
1143 | a526a31c | blueswir1 | /* SPARCbook */
|
1144 | a526a31c | blueswir1 | { |
1145 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1146 | a526a31c | blueswir1 | .tcx_base = 0x50000000, // XXX |
1147 | a526a31c | blueswir1 | .cs_base = -1,
|
1148 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1149 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1150 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1151 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1152 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1153 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1154 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1155 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1156 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1157 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1158 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1159 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1160 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1161 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1162 | a526a31c | blueswir1 | .ecc_base = -1,
|
1163 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
1164 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
1165 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
1166 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
1167 | a526a31c | blueswir1 | .esp_irq = 18,
|
1168 | a526a31c | blueswir1 | .le_irq = 16,
|
1169 | a526a31c | blueswir1 | .clock_irq = 7,
|
1170 | a526a31c | blueswir1 | .clock1_irq = 19,
|
1171 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
1172 | a526a31c | blueswir1 | .ser_irq = 15,
|
1173 | a526a31c | blueswir1 | .fd_irq = 22,
|
1174 | a526a31c | blueswir1 | .me_irq = 30,
|
1175 | a526a31c | blueswir1 | .cs_irq = -1,
|
1176 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1177 | 905fdcb5 | blueswir1 | .machine_id = sbook_id, |
1178 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1179 | a526a31c | blueswir1 | .intbit_to_level = { |
1180 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1181 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1182 | a526a31c | blueswir1 | }, |
1183 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1184 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1185 | a526a31c | blueswir1 | }, |
1186 | 36cd9210 | blueswir1 | }; |
1187 | 36cd9210 | blueswir1 | |
1188 | 36cd9210 | blueswir1 | /* SPARCstation 5 hardware initialisation */
|
1189 | 00f82b8a | aurel32 | static void ss5_init(ram_addr_t RAM_size, int vga_ram_size, |
1190 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1191 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1192 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1193 | 36cd9210 | blueswir1 | { |
1194 | 3ebf5aaf | blueswir1 | sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
1195 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1196 | 420557e8 | bellard | } |
1197 | c0e564d5 | bellard | |
1198 | e0353fe2 | blueswir1 | /* SPARCstation 10 hardware initialisation */
|
1199 | 00f82b8a | aurel32 | static void ss10_init(ram_addr_t RAM_size, int vga_ram_size, |
1200 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1201 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1202 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1203 | e0353fe2 | blueswir1 | { |
1204 | 3ebf5aaf | blueswir1 | sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
1205 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1206 | e0353fe2 | blueswir1 | } |
1207 | e0353fe2 | blueswir1 | |
1208 | 6a3b9cc9 | blueswir1 | /* SPARCserver 600MP hardware initialisation */
|
1209 | 00f82b8a | aurel32 | static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size, |
1210 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1211 | 77f193da | blueswir1 | const char *kernel_filename, |
1212 | 77f193da | blueswir1 | const char *kernel_cmdline, |
1213 | 6a3b9cc9 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1214 | 6a3b9cc9 | blueswir1 | { |
1215 | 3ebf5aaf | blueswir1 | sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
|
1216 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1217 | 6a3b9cc9 | blueswir1 | } |
1218 | 6a3b9cc9 | blueswir1 | |
1219 | ae40972f | blueswir1 | /* SPARCstation 20 hardware initialisation */
|
1220 | 00f82b8a | aurel32 | static void ss20_init(ram_addr_t RAM_size, int vga_ram_size, |
1221 | ae40972f | blueswir1 | const char *boot_device, DisplayState *ds, |
1222 | ae40972f | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1223 | ae40972f | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1224 | ae40972f | blueswir1 | { |
1225 | ae40972f | blueswir1 | sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
|
1226 | ae40972f | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1227 | ae40972f | blueswir1 | } |
1228 | ae40972f | blueswir1 | |
1229 | ee76f82e | blueswir1 | /* SPARCstation 2 hardware initialisation */
|
1230 | 00f82b8a | aurel32 | static void ss2_init(ram_addr_t RAM_size, int vga_ram_size, |
1231 | ee76f82e | blueswir1 | const char *boot_device, DisplayState *ds, |
1232 | ee76f82e | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1233 | ee76f82e | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1234 | ee76f82e | blueswir1 | { |
1235 | ee76f82e | blueswir1 | sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
|
1236 | ee76f82e | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1237 | ee76f82e | blueswir1 | } |
1238 | ee76f82e | blueswir1 | |
1239 | a526a31c | blueswir1 | /* SPARCstation Voyager hardware initialisation */
|
1240 | 6ef05b95 | blueswir1 | static void vger_init(ram_addr_t RAM_size, int vga_ram_size, |
1241 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1242 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1243 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1244 | a526a31c | blueswir1 | { |
1245 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
|
1246 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1247 | a526a31c | blueswir1 | } |
1248 | a526a31c | blueswir1 | |
1249 | a526a31c | blueswir1 | /* SPARCstation LX hardware initialisation */
|
1250 | 6ef05b95 | blueswir1 | static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size, |
1251 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1252 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1253 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1254 | a526a31c | blueswir1 | { |
1255 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
|
1256 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1257 | a526a31c | blueswir1 | } |
1258 | a526a31c | blueswir1 | |
1259 | a526a31c | blueswir1 | /* SPARCstation 4 hardware initialisation */
|
1260 | 6ef05b95 | blueswir1 | static void ss4_init(ram_addr_t RAM_size, int vga_ram_size, |
1261 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1262 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1263 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1264 | a526a31c | blueswir1 | { |
1265 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
|
1266 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1267 | a526a31c | blueswir1 | } |
1268 | a526a31c | blueswir1 | |
1269 | a526a31c | blueswir1 | /* SPARCClassic hardware initialisation */
|
1270 | 6ef05b95 | blueswir1 | static void scls_init(ram_addr_t RAM_size, int vga_ram_size, |
1271 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1272 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1273 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1274 | a526a31c | blueswir1 | { |
1275 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
|
1276 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1277 | a526a31c | blueswir1 | } |
1278 | a526a31c | blueswir1 | |
1279 | a526a31c | blueswir1 | /* SPARCbook hardware initialisation */
|
1280 | 6ef05b95 | blueswir1 | static void sbook_init(ram_addr_t RAM_size, int vga_ram_size, |
1281 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1282 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1283 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1284 | a526a31c | blueswir1 | { |
1285 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
|
1286 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1287 | a526a31c | blueswir1 | } |
1288 | a526a31c | blueswir1 | |
1289 | 36cd9210 | blueswir1 | QEMUMachine ss5_machine = { |
1290 | 66de733b | blueswir1 | .name = "SS-5",
|
1291 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 5",
|
1292 | 66de733b | blueswir1 | .init = ss5_init, |
1293 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1294 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1295 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1296 | c0e564d5 | bellard | }; |
1297 | e0353fe2 | blueswir1 | |
1298 | e0353fe2 | blueswir1 | QEMUMachine ss10_machine = { |
1299 | 66de733b | blueswir1 | .name = "SS-10",
|
1300 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 10",
|
1301 | 66de733b | blueswir1 | .init = ss10_init, |
1302 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1303 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1304 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1305 | e0353fe2 | blueswir1 | }; |
1306 | 6a3b9cc9 | blueswir1 | |
1307 | 6a3b9cc9 | blueswir1 | QEMUMachine ss600mp_machine = { |
1308 | 66de733b | blueswir1 | .name = "SS-600MP",
|
1309 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCserver 600MP",
|
1310 | 66de733b | blueswir1 | .init = ss600mp_init, |
1311 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1312 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1313 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1314 | 6a3b9cc9 | blueswir1 | }; |
1315 | ae40972f | blueswir1 | |
1316 | ae40972f | blueswir1 | QEMUMachine ss20_machine = { |
1317 | 66de733b | blueswir1 | .name = "SS-20",
|
1318 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 20",
|
1319 | 66de733b | blueswir1 | .init = ss20_init, |
1320 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1321 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1322 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1323 | ae40972f | blueswir1 | }; |
1324 | ae40972f | blueswir1 | |
1325 | ee76f82e | blueswir1 | QEMUMachine ss2_machine = { |
1326 | 66de733b | blueswir1 | .name = "SS-2",
|
1327 | 66de733b | blueswir1 | .desc = "Sun4c platform, SPARCstation 2",
|
1328 | 66de733b | blueswir1 | .init = ss2_init, |
1329 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1330 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1331 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1332 | ee76f82e | blueswir1 | }; |
1333 | 7d85892b | blueswir1 | |
1334 | a526a31c | blueswir1 | QEMUMachine voyager_machine = { |
1335 | 66de733b | blueswir1 | .name = "Voyager",
|
1336 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation Voyager",
|
1337 | 66de733b | blueswir1 | .init = vger_init, |
1338 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1339 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1340 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1341 | a526a31c | blueswir1 | }; |
1342 | a526a31c | blueswir1 | |
1343 | a526a31c | blueswir1 | QEMUMachine ss_lx_machine = { |
1344 | 66de733b | blueswir1 | .name = "LX",
|
1345 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation LX",
|
1346 | 66de733b | blueswir1 | .init = ss_lx_init, |
1347 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1348 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1349 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1350 | a526a31c | blueswir1 | }; |
1351 | a526a31c | blueswir1 | |
1352 | a526a31c | blueswir1 | QEMUMachine ss4_machine = { |
1353 | 66de733b | blueswir1 | .name = "SS-4",
|
1354 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 4",
|
1355 | 66de733b | blueswir1 | .init = ss4_init, |
1356 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1357 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1358 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1359 | a526a31c | blueswir1 | }; |
1360 | a526a31c | blueswir1 | |
1361 | a526a31c | blueswir1 | QEMUMachine scls_machine = { |
1362 | 66de733b | blueswir1 | .name = "SPARCClassic",
|
1363 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCClassic",
|
1364 | 66de733b | blueswir1 | .init = scls_init, |
1365 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1366 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1367 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1368 | a526a31c | blueswir1 | }; |
1369 | a526a31c | blueswir1 | |
1370 | a526a31c | blueswir1 | QEMUMachine sbook_machine = { |
1371 | 66de733b | blueswir1 | .name = "SPARCbook",
|
1372 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCbook",
|
1373 | 66de733b | blueswir1 | .init = sbook_init, |
1374 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1375 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1376 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1377 | a526a31c | blueswir1 | }; |
1378 | a526a31c | blueswir1 | |
1379 | 7d85892b | blueswir1 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1380 | 7d85892b | blueswir1 | /* SS-1000 */
|
1381 | 7d85892b | blueswir1 | { |
1382 | 7d85892b | blueswir1 | .iounit_bases = { |
1383 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1384 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1385 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1386 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1387 | 7d85892b | blueswir1 | -1,
|
1388 | 7d85892b | blueswir1 | }, |
1389 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1390 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1391 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1392 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1393 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1394 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1395 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1396 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1397 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1398 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1399 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1400 | c1d00dc0 | blueswir1 | .vram_size = 0x00100000,
|
1401 | 7d85892b | blueswir1 | .nvram_size = 0x2000,
|
1402 | 7d85892b | blueswir1 | .esp_irq = 3,
|
1403 | 7d85892b | blueswir1 | .le_irq = 4,
|
1404 | 7d85892b | blueswir1 | .clock_irq = 14,
|
1405 | 7d85892b | blueswir1 | .clock1_irq = 10,
|
1406 | 7d85892b | blueswir1 | .ms_kb_irq = 12,
|
1407 | 7d85892b | blueswir1 | .ser_irq = 12,
|
1408 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1409 | 905fdcb5 | blueswir1 | .machine_id = ss1000_id, |
1410 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1411 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1412 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1413 | 7d85892b | blueswir1 | }, |
1414 | 7d85892b | blueswir1 | /* SS-2000 */
|
1415 | 7d85892b | blueswir1 | { |
1416 | 7d85892b | blueswir1 | .iounit_bases = { |
1417 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1418 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1419 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1420 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1421 | 7d85892b | blueswir1 | 0xfe4200000ULL,
|
1422 | 7d85892b | blueswir1 | }, |
1423 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1424 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1425 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1426 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1427 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1428 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1429 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1430 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1431 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1432 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1433 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1434 | c1d00dc0 | blueswir1 | .vram_size = 0x00100000,
|
1435 | 7d85892b | blueswir1 | .nvram_size = 0x2000,
|
1436 | 7d85892b | blueswir1 | .esp_irq = 3,
|
1437 | 7d85892b | blueswir1 | .le_irq = 4,
|
1438 | 7d85892b | blueswir1 | .clock_irq = 14,
|
1439 | 7d85892b | blueswir1 | .clock1_irq = 10,
|
1440 | 7d85892b | blueswir1 | .ms_kb_irq = 12,
|
1441 | 7d85892b | blueswir1 | .ser_irq = 12,
|
1442 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1443 | 905fdcb5 | blueswir1 | .machine_id = ss2000_id, |
1444 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1445 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1446 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1447 | 7d85892b | blueswir1 | }, |
1448 | 7d85892b | blueswir1 | }; |
1449 | 7d85892b | blueswir1 | |
1450 | 6ef05b95 | blueswir1 | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1451 | 7d85892b | blueswir1 | const char *boot_device, |
1452 | 7d85892b | blueswir1 | DisplayState *ds, const char *kernel_filename, |
1453 | 7d85892b | blueswir1 | const char *kernel_cmdline, |
1454 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1455 | 7d85892b | blueswir1 | { |
1456 | 7d85892b | blueswir1 | CPUState *env, *envs[MAX_CPUS]; |
1457 | 7d85892b | blueswir1 | unsigned int i; |
1458 | 7d85892b | blueswir1 | void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
|
1459 | 7d85892b | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, |
1460 | 7d85892b | blueswir1 | *espdma_irq, *ledma_irq; |
1461 | 7d85892b | blueswir1 | qemu_irq *esp_reset, *le_reset; |
1462 | 7d85892b | blueswir1 | unsigned long prom_offset, kernel_size; |
1463 | 7d85892b | blueswir1 | int ret;
|
1464 | 7d85892b | blueswir1 | char buf[1024]; |
1465 | 22548760 | blueswir1 | int drive_index;
|
1466 | 3cce6243 | blueswir1 | void *fw_cfg;
|
1467 | 7d85892b | blueswir1 | |
1468 | 7d85892b | blueswir1 | /* init CPUs */
|
1469 | 7d85892b | blueswir1 | if (!cpu_model)
|
1470 | 7d85892b | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1471 | 7d85892b | blueswir1 | |
1472 | 7d85892b | blueswir1 | for (i = 0; i < smp_cpus; i++) { |
1473 | 7d85892b | blueswir1 | env = cpu_init(cpu_model); |
1474 | 7d85892b | blueswir1 | if (!env) {
|
1475 | 8e82c6a8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
1476 | 7d85892b | blueswir1 | exit(1);
|
1477 | 7d85892b | blueswir1 | } |
1478 | 7d85892b | blueswir1 | cpu_sparc_set_id(env, i); |
1479 | 7d85892b | blueswir1 | envs[i] = env; |
1480 | 7d85892b | blueswir1 | if (i == 0) { |
1481 | 7d85892b | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
1482 | 7d85892b | blueswir1 | } else {
|
1483 | 7d85892b | blueswir1 | qemu_register_reset(secondary_cpu_reset, env); |
1484 | 7d85892b | blueswir1 | env->halted = 1;
|
1485 | 7d85892b | blueswir1 | } |
1486 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
1487 | 7d85892b | blueswir1 | env->prom_addr = hwdef->slavio_base; |
1488 | 7d85892b | blueswir1 | } |
1489 | 7d85892b | blueswir1 | |
1490 | 7d85892b | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
1491 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1492 | 7d85892b | blueswir1 | |
1493 | 7d85892b | blueswir1 | /* allocate RAM */
|
1494 | 7d85892b | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
1495 | 77f193da | blueswir1 | fprintf(stderr, |
1496 | 77f193da | blueswir1 | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
1497 | 6ef05b95 | blueswir1 | (unsigned int)(RAM_size / (1024 * 1024)), |
1498 | 7d85892b | blueswir1 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
1499 | 7d85892b | blueswir1 | exit(1);
|
1500 | 7d85892b | blueswir1 | } |
1501 | 7d85892b | blueswir1 | cpu_register_physical_memory(0, RAM_size, 0); |
1502 | 7d85892b | blueswir1 | |
1503 | 7d85892b | blueswir1 | /* load boot prom */
|
1504 | 7d85892b | blueswir1 | prom_offset = RAM_size + hwdef->vram_size; |
1505 | 7d85892b | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
1506 | 7d85892b | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
1507 | 7d85892b | blueswir1 | TARGET_PAGE_MASK, |
1508 | 7d85892b | blueswir1 | prom_offset | IO_MEM_ROM); |
1509 | 7d85892b | blueswir1 | |
1510 | 7d85892b | blueswir1 | if (bios_name == NULL) |
1511 | 7d85892b | blueswir1 | bios_name = PROM_FILENAME; |
1512 | 7d85892b | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
1513 | 7d85892b | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
1514 | 7d85892b | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
1515 | e01f4a1c | blueswir1 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
1516 | 7d85892b | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
1517 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
1518 | 7d85892b | blueswir1 | buf); |
1519 | 7d85892b | blueswir1 | exit(1);
|
1520 | 7d85892b | blueswir1 | } |
1521 | 7d85892b | blueswir1 | |
1522 | 7d85892b | blueswir1 | /* set up devices */
|
1523 | 7d85892b | blueswir1 | sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs); |
1524 | 7d85892b | blueswir1 | |
1525 | 7d85892b | blueswir1 | for (i = 0; i < MAX_IOUNITS; i++) |
1526 | 7d85892b | blueswir1 | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1527 | ff403da6 | blueswir1 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1528 | ff403da6 | blueswir1 | hwdef->iounit_version, |
1529 | ff403da6 | blueswir1 | sbi_irq[hwdef->me_irq]); |
1530 | 7d85892b | blueswir1 | |
1531 | 7d85892b | blueswir1 | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq], |
1532 | 7d85892b | blueswir1 | iounits[0], &espdma_irq, &esp_reset);
|
1533 | 7d85892b | blueswir1 | |
1534 | 7d85892b | blueswir1 | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq], |
1535 | 7d85892b | blueswir1 | iounits[0], &ledma_irq, &le_reset);
|
1536 | 7d85892b | blueswir1 | |
1537 | 7d85892b | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1538 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1539 | 7d85892b | blueswir1 | exit (1);
|
1540 | 7d85892b | blueswir1 | } |
1541 | 7d85892b | blueswir1 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
1542 | 7d85892b | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
1543 | 7d85892b | blueswir1 | |
1544 | 7d85892b | blueswir1 | if (nd_table[0].model == NULL |
1545 | 7d85892b | blueswir1 | || strcmp(nd_table[0].model, "lance") == 0) { |
1546 | 7d85892b | blueswir1 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
1547 | 7d85892b | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
1548 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Supported NICs: lance\n");
|
1549 | 7d85892b | blueswir1 | exit (1);
|
1550 | 7d85892b | blueswir1 | } else {
|
1551 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
1552 | 7d85892b | blueswir1 | exit (1);
|
1553 | 7d85892b | blueswir1 | } |
1554 | 7d85892b | blueswir1 | |
1555 | 7d85892b | blueswir1 | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, |
1556 | 7d85892b | blueswir1 | hwdef->nvram_size, 8);
|
1557 | 7d85892b | blueswir1 | |
1558 | 7d85892b | blueswir1 | slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq], |
1559 | 7d85892b | blueswir1 | sbi_cpu_irq, smp_cpus); |
1560 | 7d85892b | blueswir1 | |
1561 | 7d85892b | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq], |
1562 | 7d85892b | blueswir1 | nographic); |
1563 | 7d85892b | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1564 | 7d85892b | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1565 | 7d85892b | blueswir1 | slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], |
1566 | 7d85892b | blueswir1 | serial_hds[1], serial_hds[0]); |
1567 | 7d85892b | blueswir1 | |
1568 | 7d85892b | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1569 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1570 | 7d85892b | blueswir1 | exit(1);
|
1571 | 7d85892b | blueswir1 | } |
1572 | 7d85892b | blueswir1 | |
1573 | 5d20fa6b | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
1574 | 8b17de88 | blueswir1 | espdma_memory_read, espdma_memory_write, |
1575 | 8b17de88 | blueswir1 | espdma, *espdma_irq, esp_reset); |
1576 | 7d85892b | blueswir1 | |
1577 | 7d85892b | blueswir1 | for (i = 0; i < ESP_MAX_DEVS; i++) { |
1578 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_SCSI, 0, i);
|
1579 | 22548760 | blueswir1 | if (drive_index == -1) |
1580 | 7d85892b | blueswir1 | continue;
|
1581 | 22548760 | blueswir1 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
1582 | 7d85892b | blueswir1 | } |
1583 | 7d85892b | blueswir1 | |
1584 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1585 | 293f78bc | blueswir1 | RAM_size); |
1586 | 7d85892b | blueswir1 | |
1587 | 7d85892b | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1588 | 7d85892b | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1589 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1590 | 905fdcb5 | blueswir1 | "Sun4d");
|
1591 | 3cce6243 | blueswir1 | |
1592 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1593 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1594 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1595 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1596 | 7d85892b | blueswir1 | } |
1597 | 7d85892b | blueswir1 | |
1598 | 7d85892b | blueswir1 | /* SPARCserver 1000 hardware initialisation */
|
1599 | 00f82b8a | aurel32 | static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size, |
1600 | 7d85892b | blueswir1 | const char *boot_device, DisplayState *ds, |
1601 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1602 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1603 | 7d85892b | blueswir1 | { |
1604 | 7d85892b | blueswir1 | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
1605 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1606 | 7d85892b | blueswir1 | } |
1607 | 7d85892b | blueswir1 | |
1608 | 7d85892b | blueswir1 | /* SPARCcenter 2000 hardware initialisation */
|
1609 | 00f82b8a | aurel32 | static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size, |
1610 | 7d85892b | blueswir1 | const char *boot_device, DisplayState *ds, |
1611 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1612 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1613 | 7d85892b | blueswir1 | { |
1614 | 7d85892b | blueswir1 | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
1615 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1616 | 7d85892b | blueswir1 | } |
1617 | 7d85892b | blueswir1 | |
1618 | 7d85892b | blueswir1 | QEMUMachine ss1000_machine = { |
1619 | 66de733b | blueswir1 | .name = "SS-1000",
|
1620 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCserver 1000",
|
1621 | 66de733b | blueswir1 | .init = ss1000_init, |
1622 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1623 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1624 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1625 | 7d85892b | blueswir1 | }; |
1626 | 7d85892b | blueswir1 | |
1627 | 7d85892b | blueswir1 | QEMUMachine ss2000_machine = { |
1628 | 66de733b | blueswir1 | .name = "SS-2000",
|
1629 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCcenter 2000",
|
1630 | 66de733b | blueswir1 | .init = ss2000_init, |
1631 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1632 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1633 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1634 | 7d85892b | blueswir1 | }; |