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/*
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* Nokia N-series internet tablets.
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*
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* Copyright (C) 2007 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "qemu-common.h" |
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#include "sysemu.h" |
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#include "omap.h" |
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#include "arm-misc.h" |
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#include "irq.h" |
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#include "console.h" |
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#include "boards.h" |
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#include "i2c.h" |
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#include "devices.h" |
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#include "flash.h" |
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#include "hw.h" |
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#include "bt.h" |
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/* Nokia N8x0 support */
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struct n800_s {
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struct omap_mpu_state_s *cpu;
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struct rfbi_chip_s blizzard;
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struct {
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void *opaque;
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uint32_t (*txrx)(void *opaque, uint32_t value, int len); |
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struct uwire_slave_s *chip;
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} ts; |
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i2c_bus *i2c; |
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int keymap[0x80]; |
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i2c_slave *kbd; |
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struct tusb_s *usb;
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void *retu;
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void *tahvo;
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void *nand;
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}; |
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/* GPIO pins */
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#define N8X0_TUSB_ENABLE_GPIO 0 |
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#define N800_MMC2_WP_GPIO 8 |
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#define N800_UNKNOWN_GPIO0 9 /* out */ |
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#define N810_MMC2_VIOSD_GPIO 9 |
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#define N810_HEADSET_AMP_GPIO 10 |
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#define N800_CAM_TURN_GPIO 12 |
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#define N810_GPS_RESET_GPIO 12 |
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#define N800_BLIZZARD_POWERDOWN_GPIO 15 |
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#define N800_MMC1_WP_GPIO 23 |
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#define N810_MMC2_VSD_GPIO 23 |
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#define N8X0_ONENAND_GPIO 26 |
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#define N810_BLIZZARD_RESET_GPIO 30 |
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#define N800_UNKNOWN_GPIO2 53 /* out */ |
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#define N8X0_TUSB_INT_GPIO 58 |
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#define N8X0_BT_WKUP_GPIO 61 |
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#define N8X0_STI_GPIO 62 |
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#define N8X0_CBUS_SEL_GPIO 64 |
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#define N8X0_CBUS_DAT_GPIO 65 |
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#define N8X0_CBUS_CLK_GPIO 66 |
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#define N8X0_WLAN_IRQ_GPIO 87 |
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#define N8X0_BT_RESET_GPIO 92 |
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#define N8X0_TEA5761_CS_GPIO 93 |
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#define N800_UNKNOWN_GPIO 94 |
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#define N810_TSC_RESET_GPIO 94 |
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#define N800_CAM_ACT_GPIO 95 |
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#define N810_GPS_WAKEUP_GPIO 95 |
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#define N8X0_MMC_CS_GPIO 96 |
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#define N8X0_WLAN_PWR_GPIO 97 |
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#define N8X0_BT_HOST_WKUP_GPIO 98 |
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#define N810_SPEAKER_AMP_GPIO 101 |
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#define N810_KB_LOCK_GPIO 102 |
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#define N800_TSC_TS_GPIO 103 |
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#define N810_TSC_TS_GPIO 106 |
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#define N8X0_HEADPHONE_GPIO 107 |
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#define N8X0_RETU_GPIO 108 |
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#define N800_TSC_KP_IRQ_GPIO 109 |
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#define N810_KEYBOARD_GPIO 109 |
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#define N800_BAT_COVER_GPIO 110 |
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#define N810_SLIDE_GPIO 110 |
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#define N8X0_TAHVO_GPIO 111 |
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#define N800_UNKNOWN_GPIO4 112 /* out */ |
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#define N810_SLEEPX_LED_GPIO 112 |
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#define N800_TSC_RESET_GPIO 118 /* ? */ |
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#define N810_AIC33_RESET_GPIO 118 |
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#define N800_TSC_UNKNOWN_GPIO 119 /* out */ |
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#define N8X0_TMP105_GPIO 125 |
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|
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/* Config */
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#define BT_UART 0 |
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#define XLDR_LL_UART 1 |
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/* Addresses on the I2C bus 0 */
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#define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */ |
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#define N8X0_TCM825x_ADDR 0x29 /* Camera */ |
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#define N810_LP5521_ADDR 0x32 /* LEDs */ |
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#define N810_TSL2563_ADDR 0x3d /* Light sensor */ |
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#define N810_LM8323_ADDR 0x45 /* Keyboard */ |
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/* Addresses on the I2C bus 1 */
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#define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */ |
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#define N8X0_MENELAUS_ADDR 0x72 /* Power management */ |
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/* Chipselects on GPMC NOR interface */
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#define N8X0_ONENAND_CS 0 |
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#define N8X0_USB_ASYNC_CS 1 |
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#define N8X0_USB_SYNC_CS 4 |
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#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81 |
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static void n800_mmc_cs_cb(void *opaque, int line, int level) |
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{ |
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/* TODO: this seems to actually be connected to the menelaus, to
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* which also both MMC slots connect. */
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omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
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printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1); |
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} |
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static void n8x0_gpio_setup(struct n800_s *s) |
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{ |
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qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
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omap2_gpio_out_set(s->cpu->gpif, N8X0_MMC_CS_GPIO, mmc_cs[0]);
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qemu_irq_lower(omap2_gpio_in_get(s->cpu->gpif, N800_BAT_COVER_GPIO)[0]);
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} |
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#define MAEMO_CAL_HEADER(...) \
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'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \ |
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__VA_ARGS__, \ |
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
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static const uint8_t n8x0_cal_wlan_mac[] = { |
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MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c') |
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0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3, |
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0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00, |
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0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, |
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0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00, |
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0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, |
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}; |
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static const uint8_t n8x0_cal_bt_id[] = { |
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MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0) |
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0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96, |
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0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00, |
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N8X0_BD_ADDR, |
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}; |
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static void n8x0_nand_setup(struct n800_s *s) |
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{ |
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char *otp_region;
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/* Either ec40xx or ec48xx are OK for the ID */
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omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
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onenand_base_unmap, |
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(s->nand = onenand_init(0xec4800, 1, |
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omap2_gpio_in_get(s->cpu->gpif, |
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N8X0_ONENAND_GPIO)[0])));
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otp_region = onenand_raw_otp(s->nand); |
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memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac)); |
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memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id)); |
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/* XXX: in theory should also update the OOB for both pages */
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} |
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static void n8x0_i2c_setup(struct n800_s *s) |
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{ |
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qemu_irq tmp_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TMP105_GPIO)[0];
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/* Attach the CPU on one end of our I2C bus. */
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s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
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/* Attach a menelaus PM chip */
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i2c_set_slave_address( |
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twl92230_init(s->i2c, |
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s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]),
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N8X0_MENELAUS_ADDR); |
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/* Attach a TMP105 PM chip (A0 wired to ground) */
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i2c_set_slave_address(tmp105_init(s->i2c, tmp_irq), N8X0_TMP105_ADDR); |
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} |
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/* Touchscreen and keypad controller */
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static struct mouse_transform_info_s n800_pointercal = { |
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.x = 800,
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.y = 480,
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.a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 }, |
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}; |
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static struct mouse_transform_info_s n810_pointercal = { |
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.x = 800,
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.y = 480,
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.a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 }, |
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}; |
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#define RETU_KEYCODE 61 /* F3 */ |
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static void n800_key_event(void *opaque, int keycode) |
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{ |
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struct n800_s *s = (struct n800_s *) opaque; |
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int code = s->keymap[keycode & 0x7f]; |
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if (code == -1) { |
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if ((keycode & 0x7f) == RETU_KEYCODE) |
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retu_key_event(s->retu, !(keycode & 0x80));
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return;
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} |
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tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
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} |
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static const int n800_keys[16] = { |
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-1,
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72, /* Up */ |
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63, /* Home (F5) */ |
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-1,
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75, /* Left */ |
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28, /* Enter */ |
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77, /* Right */ |
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-1,
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1, /* Cycle (ESC) */ |
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80, /* Down */ |
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62, /* Menu (F4) */ |
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-1,
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66, /* Zoom- (F8) */ |
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64, /* FullScreen (F6) */ |
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65, /* Zoom+ (F7) */ |
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-1,
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}; |
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static void n800_tsc_kbd_setup(struct n800_s *s) |
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{ |
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int i;
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/* XXX: are the three pins inverted inside the chip between the
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* tsc and the cpu (N4111)? */
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qemu_irq penirq = 0; /* NC */ |
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qemu_irq kbirq = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_KP_IRQ_GPIO)[0];
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qemu_irq dav = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_TS_GPIO)[0];
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s->ts.chip = tsc2301_init(penirq, kbirq, dav, 0);
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s->ts.opaque = s->ts.chip->opaque; |
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s->ts.txrx = tsc210x_txrx; |
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for (i = 0; i < 0x80; i ++) |
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s->keymap[i] = -1;
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for (i = 0; i < 0x10; i ++) |
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if (n800_keys[i] >= 0) |
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s->keymap[n800_keys[i]] = i; |
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qemu_add_kbd_event_handler(n800_key_event, s); |
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tsc210x_set_transform(s->ts.chip, &n800_pointercal); |
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} |
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static void n810_tsc_setup(struct n800_s *s) |
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{ |
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qemu_irq pintdav = omap2_gpio_in_get(s->cpu->gpif, N810_TSC_TS_GPIO)[0];
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s->ts.opaque = tsc2005_init(pintdav); |
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s->ts.txrx = tsc2005_txrx; |
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tsc2005_set_transform(s->ts.opaque, &n810_pointercal); |
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} |
280 |
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/* N810 Keyboard controller */
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static void n810_key_event(void *opaque, int keycode) |
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{ |
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struct n800_s *s = (struct n800_s *) opaque; |
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int code = s->keymap[keycode & 0x7f]; |
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if (code == -1) { |
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if ((keycode & 0x7f) == RETU_KEYCODE) |
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retu_key_event(s->retu, !(keycode & 0x80));
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return;
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} |
292 |
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lm832x_key_event(s->kbd, code, !(keycode & 0x80));
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} |
295 |
|
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#define M 0 |
297 |
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static int n810_keys[0x80] = { |
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[0x01] = 16, /* Q */ |
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[0x02] = 37, /* K */ |
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[0x03] = 24, /* O */ |
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[0x04] = 25, /* P */ |
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[0x05] = 14, /* Backspace */ |
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[0x06] = 30, /* A */ |
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[0x07] = 31, /* S */ |
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[0x08] = 32, /* D */ |
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[0x09] = 33, /* F */ |
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[0x0a] = 34, /* G */ |
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[0x0b] = 35, /* H */ |
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[0x0c] = 36, /* J */ |
311 |
|
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[0x11] = 17, /* W */ |
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[0x12] = 62, /* Menu (F4) */ |
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[0x13] = 38, /* L */ |
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[0x14] = 40, /* ' (Apostrophe) */ |
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[0x16] = 44, /* Z */ |
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[0x17] = 45, /* X */ |
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[0x18] = 46, /* C */ |
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[0x19] = 47, /* V */ |
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[0x1a] = 48, /* B */ |
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[0x1b] = 49, /* N */ |
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[0x1c] = 42, /* Shift (Left shift) */ |
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[0x1f] = 65, /* Zoom+ (F7) */ |
324 |
|
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[0x21] = 18, /* E */ |
326 |
[0x22] = 39, /* ; (Semicolon) */ |
327 |
[0x23] = 12, /* - (Minus) */ |
328 |
[0x24] = 13, /* = (Equal) */ |
329 |
[0x2b] = 56, /* Fn (Left Alt) */ |
330 |
[0x2c] = 50, /* M */ |
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[0x2f] = 66, /* Zoom- (F8) */ |
332 |
|
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[0x31] = 19, /* R */ |
334 |
[0x32] = 29 | M, /* Right Ctrl */ |
335 |
[0x34] = 57, /* Space */ |
336 |
[0x35] = 51, /* , (Comma) */ |
337 |
[0x37] = 72 | M, /* Up */ |
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[0x3c] = 82 | M, /* Compose (Insert) */ |
339 |
[0x3f] = 64, /* FullScreen (F6) */ |
340 |
|
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[0x41] = 20, /* T */ |
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[0x44] = 52, /* . (Dot) */ |
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[0x46] = 77 | M, /* Right */ |
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[0x4f] = 63, /* Home (F5) */ |
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[0x51] = 21, /* Y */ |
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[0x53] = 80 | M, /* Down */ |
347 |
[0x55] = 28, /* Enter */ |
348 |
[0x5f] = 1, /* Cycle (ESC) */ |
349 |
|
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[0x61] = 22, /* U */ |
351 |
[0x64] = 75 | M, /* Left */ |
352 |
|
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[0x71] = 23, /* I */ |
354 |
#if 0
|
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[0x75] = 28 | M, /* KP Enter (KP Enter) */
|
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#else
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[0x75] = 15, /* KP Enter (Tab) */ |
358 |
#endif
|
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}; |
360 |
|
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#undef M
|
362 |
|
363 |
static void n810_kbd_setup(struct n800_s *s) |
364 |
{ |
365 |
qemu_irq kbd_irq = omap2_gpio_in_get(s->cpu->gpif, N810_KEYBOARD_GPIO)[0];
|
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int i;
|
367 |
|
368 |
for (i = 0; i < 0x80; i ++) |
369 |
s->keymap[i] = -1;
|
370 |
for (i = 0; i < 0x80; i ++) |
371 |
if (n810_keys[i] > 0) |
372 |
s->keymap[n810_keys[i]] = i; |
373 |
|
374 |
qemu_add_kbd_event_handler(n810_key_event, s); |
375 |
|
376 |
/* Attach the LM8322 keyboard to the I2C bus,
|
377 |
* should happen in n8x0_i2c_setup and s->kbd be initialised here. */
|
378 |
s->kbd = lm8323_init(s->i2c, kbd_irq); |
379 |
i2c_set_slave_address(s->kbd, N810_LM8323_ADDR); |
380 |
} |
381 |
|
382 |
/* LCD MIPI DBI-C controller (URAL) */
|
383 |
struct mipid_s {
|
384 |
int resp[4]; |
385 |
int param[4]; |
386 |
int p;
|
387 |
int pm;
|
388 |
int cmd;
|
389 |
|
390 |
int sleep;
|
391 |
int booster;
|
392 |
int te;
|
393 |
int selfcheck;
|
394 |
int partial;
|
395 |
int normal;
|
396 |
int vscr;
|
397 |
int invert;
|
398 |
int onoff;
|
399 |
int gamma;
|
400 |
uint32_t id; |
401 |
}; |
402 |
|
403 |
static void mipid_reset(struct mipid_s *s) |
404 |
{ |
405 |
if (!s->sleep)
|
406 |
fprintf(stderr, "%s: Display off\n", __FUNCTION__);
|
407 |
|
408 |
s->pm = 0;
|
409 |
s->cmd = 0;
|
410 |
|
411 |
s->sleep = 1;
|
412 |
s->booster = 0;
|
413 |
s->selfcheck = |
414 |
(1 << 7) | /* Register loading OK. */ |
415 |
(1 << 5) | /* The chip is attached. */ |
416 |
(1 << 4); /* Display glass still in one piece. */ |
417 |
s->te = 0;
|
418 |
s->partial = 0;
|
419 |
s->normal = 1;
|
420 |
s->vscr = 0;
|
421 |
s->invert = 0;
|
422 |
s->onoff = 1;
|
423 |
s->gamma = 0;
|
424 |
} |
425 |
|
426 |
static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len) |
427 |
{ |
428 |
struct mipid_s *s = (struct mipid_s *) opaque; |
429 |
uint8_t ret; |
430 |
|
431 |
if (len > 9) |
432 |
cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
|
433 |
__FUNCTION__, len); |
434 |
|
435 |
if (s->p >= sizeof(s->resp) / sizeof(*s->resp)) |
436 |
ret = 0;
|
437 |
else
|
438 |
ret = s->resp[s->p ++]; |
439 |
if (s->pm --> 0) |
440 |
s->param[s->pm] = cmd; |
441 |
else
|
442 |
s->cmd = cmd; |
443 |
|
444 |
switch (s->cmd) {
|
445 |
case 0x00: /* NOP */ |
446 |
break;
|
447 |
|
448 |
case 0x01: /* SWRESET */ |
449 |
mipid_reset(s); |
450 |
break;
|
451 |
|
452 |
case 0x02: /* BSTROFF */ |
453 |
s->booster = 0;
|
454 |
break;
|
455 |
case 0x03: /* BSTRON */ |
456 |
s->booster = 1;
|
457 |
break;
|
458 |
|
459 |
case 0x04: /* RDDID */ |
460 |
s->p = 0;
|
461 |
s->resp[0] = (s->id >> 16) & 0xff; |
462 |
s->resp[1] = (s->id >> 8) & 0xff; |
463 |
s->resp[2] = (s->id >> 0) & 0xff; |
464 |
break;
|
465 |
|
466 |
case 0x06: /* RD_RED */ |
467 |
case 0x07: /* RD_GREEN */ |
468 |
/* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
|
469 |
* for the bootloader one needs to change this. */
|
470 |
case 0x08: /* RD_BLUE */ |
471 |
s->p = 0;
|
472 |
/* TODO: return first pixel components */
|
473 |
s->resp[0] = 0x01; |
474 |
break;
|
475 |
|
476 |
case 0x09: /* RDDST */ |
477 |
s->p = 0;
|
478 |
s->resp[0] = s->booster << 7; |
479 |
s->resp[1] = (5 << 4) | (s->partial << 2) | |
480 |
(s->sleep << 1) | s->normal;
|
481 |
s->resp[2] = (s->vscr << 7) | (s->invert << 5) | |
482 |
(s->onoff << 2) | (s->te << 1) | (s->gamma >> 2); |
483 |
s->resp[3] = s->gamma << 6; |
484 |
break;
|
485 |
|
486 |
case 0x0a: /* RDDPM */ |
487 |
s->p = 0;
|
488 |
s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) | |
489 |
(s->partial << 5) | (s->sleep << 6) | (s->booster << 7); |
490 |
break;
|
491 |
case 0x0b: /* RDDMADCTR */ |
492 |
s->p = 0;
|
493 |
s->resp[0] = 0; |
494 |
break;
|
495 |
case 0x0c: /* RDDCOLMOD */ |
496 |
s->p = 0;
|
497 |
s->resp[0] = 5; /* 65K colours */ |
498 |
break;
|
499 |
case 0x0d: /* RDDIM */ |
500 |
s->p = 0;
|
501 |
s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma; |
502 |
break;
|
503 |
case 0x0e: /* RDDSM */ |
504 |
s->p = 0;
|
505 |
s->resp[0] = s->te << 7; |
506 |
break;
|
507 |
case 0x0f: /* RDDSDR */ |
508 |
s->p = 0;
|
509 |
s->resp[0] = s->selfcheck;
|
510 |
break;
|
511 |
|
512 |
case 0x10: /* SLPIN */ |
513 |
s->sleep = 1;
|
514 |
break;
|
515 |
case 0x11: /* SLPOUT */ |
516 |
s->sleep = 0;
|
517 |
s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */ |
518 |
break;
|
519 |
|
520 |
case 0x12: /* PTLON */ |
521 |
s->partial = 1;
|
522 |
s->normal = 0;
|
523 |
s->vscr = 0;
|
524 |
break;
|
525 |
case 0x13: /* NORON */ |
526 |
s->partial = 0;
|
527 |
s->normal = 1;
|
528 |
s->vscr = 0;
|
529 |
break;
|
530 |
|
531 |
case 0x20: /* INVOFF */ |
532 |
s->invert = 0;
|
533 |
break;
|
534 |
case 0x21: /* INVON */ |
535 |
s->invert = 1;
|
536 |
break;
|
537 |
|
538 |
case 0x22: /* APOFF */ |
539 |
case 0x23: /* APON */ |
540 |
goto bad_cmd;
|
541 |
|
542 |
case 0x25: /* WRCNTR */ |
543 |
if (s->pm < 0) |
544 |
s->pm = 1;
|
545 |
goto bad_cmd;
|
546 |
|
547 |
case 0x26: /* GAMSET */ |
548 |
if (!s->pm)
|
549 |
s->gamma = ffs(s->param[0] & 0xf) - 1; |
550 |
else if (s->pm < 0) |
551 |
s->pm = 1;
|
552 |
break;
|
553 |
|
554 |
case 0x28: /* DISPOFF */ |
555 |
s->onoff = 0;
|
556 |
fprintf(stderr, "%s: Display off\n", __FUNCTION__);
|
557 |
break;
|
558 |
case 0x29: /* DISPON */ |
559 |
s->onoff = 1;
|
560 |
fprintf(stderr, "%s: Display on\n", __FUNCTION__);
|
561 |
break;
|
562 |
|
563 |
case 0x2a: /* CASET */ |
564 |
case 0x2b: /* RASET */ |
565 |
case 0x2c: /* RAMWR */ |
566 |
case 0x2d: /* RGBSET */ |
567 |
case 0x2e: /* RAMRD */ |
568 |
case 0x30: /* PTLAR */ |
569 |
case 0x33: /* SCRLAR */ |
570 |
goto bad_cmd;
|
571 |
|
572 |
case 0x34: /* TEOFF */ |
573 |
s->te = 0;
|
574 |
break;
|
575 |
case 0x35: /* TEON */ |
576 |
if (!s->pm)
|
577 |
s->te = 1;
|
578 |
else if (s->pm < 0) |
579 |
s->pm = 1;
|
580 |
break;
|
581 |
|
582 |
case 0x36: /* MADCTR */ |
583 |
goto bad_cmd;
|
584 |
|
585 |
case 0x37: /* VSCSAD */ |
586 |
s->partial = 0;
|
587 |
s->normal = 0;
|
588 |
s->vscr = 1;
|
589 |
break;
|
590 |
|
591 |
case 0x38: /* IDMOFF */ |
592 |
case 0x39: /* IDMON */ |
593 |
case 0x3a: /* COLMOD */ |
594 |
goto bad_cmd;
|
595 |
|
596 |
case 0xb0: /* CLKINT / DISCTL */ |
597 |
case 0xb1: /* CLKEXT */ |
598 |
if (s->pm < 0) |
599 |
s->pm = 2;
|
600 |
break;
|
601 |
|
602 |
case 0xb4: /* FRMSEL */ |
603 |
break;
|
604 |
|
605 |
case 0xb5: /* FRM8SEL */ |
606 |
case 0xb6: /* TMPRNG / INIESC */ |
607 |
case 0xb7: /* TMPHIS / NOP2 */ |
608 |
case 0xb8: /* TMPREAD / MADCTL */ |
609 |
case 0xba: /* DISTCTR */ |
610 |
case 0xbb: /* EPVOL */ |
611 |
goto bad_cmd;
|
612 |
|
613 |
case 0xbd: /* Unknown */ |
614 |
s->p = 0;
|
615 |
s->resp[0] = 0; |
616 |
s->resp[1] = 1; |
617 |
break;
|
618 |
|
619 |
case 0xc2: /* IFMOD */ |
620 |
if (s->pm < 0) |
621 |
s->pm = 2;
|
622 |
break;
|
623 |
|
624 |
case 0xc6: /* PWRCTL */ |
625 |
case 0xc7: /* PPWRCTL */ |
626 |
case 0xd0: /* EPWROUT */ |
627 |
case 0xd1: /* EPWRIN */ |
628 |
case 0xd4: /* RDEV */ |
629 |
case 0xd5: /* RDRR */ |
630 |
goto bad_cmd;
|
631 |
|
632 |
case 0xda: /* RDID1 */ |
633 |
s->p = 0;
|
634 |
s->resp[0] = (s->id >> 16) & 0xff; |
635 |
break;
|
636 |
case 0xdb: /* RDID2 */ |
637 |
s->p = 0;
|
638 |
s->resp[0] = (s->id >> 8) & 0xff; |
639 |
break;
|
640 |
case 0xdc: /* RDID3 */ |
641 |
s->p = 0;
|
642 |
s->resp[0] = (s->id >> 0) & 0xff; |
643 |
break;
|
644 |
|
645 |
default:
|
646 |
bad_cmd:
|
647 |
fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
|
648 |
break;
|
649 |
} |
650 |
|
651 |
return ret;
|
652 |
} |
653 |
|
654 |
static void *mipid_init(void) |
655 |
{ |
656 |
struct mipid_s *s = (struct mipid_s *) qemu_mallocz(sizeof(*s)); |
657 |
|
658 |
s->id = 0x838f03;
|
659 |
mipid_reset(s); |
660 |
|
661 |
return s;
|
662 |
} |
663 |
|
664 |
static void n8x0_spi_setup(struct n800_s *s) |
665 |
{ |
666 |
void *tsc = s->ts.opaque;
|
667 |
void *mipid = mipid_init();
|
668 |
|
669 |
omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0); |
670 |
omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1); |
671 |
} |
672 |
|
673 |
/* This task is normally performed by the bootloader. If we're loading
|
674 |
* a kernel directly, we need to enable the Blizzard ourselves. */
|
675 |
static void n800_dss_init(struct rfbi_chip_s *chip) |
676 |
{ |
677 |
uint8_t *fb_blank; |
678 |
|
679 |
chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */ |
680 |
chip->write(chip->opaque, 1, 0x64); |
681 |
chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */ |
682 |
chip->write(chip->opaque, 1, 0x1e); |
683 |
chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */ |
684 |
chip->write(chip->opaque, 1, 0xe0); |
685 |
chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */ |
686 |
chip->write(chip->opaque, 1, 0x01); |
687 |
chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */ |
688 |
chip->write(chip->opaque, 1, 0x06); |
689 |
chip->write(chip->opaque, 0, 0x68); /* Display Mode register */ |
690 |
chip->write(chip->opaque, 1, 1); /* Enable bit */ |
691 |
|
692 |
chip->write(chip->opaque, 0, 0x6c); |
693 |
chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ |
694 |
chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ |
695 |
chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ |
696 |
chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ |
697 |
chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */ |
698 |
chip->write(chip->opaque, 1, 0x03); /* Input X End Position */ |
699 |
chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */ |
700 |
chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */ |
701 |
chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ |
702 |
chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ |
703 |
chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ |
704 |
chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ |
705 |
chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */ |
706 |
chip->write(chip->opaque, 1, 0x03); /* Output X End Position */ |
707 |
chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */ |
708 |
chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */ |
709 |
chip->write(chip->opaque, 1, 0x01); /* Input Data Format */ |
710 |
chip->write(chip->opaque, 1, 0x01); /* Data Source Select */ |
711 |
|
712 |
fb_blank = memset(qemu_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2); |
713 |
/* Display Memory Data Port */
|
714 |
chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800); |
715 |
free(fb_blank); |
716 |
} |
717 |
|
718 |
static void n8x0_dss_setup(struct n800_s *s, DisplayState *ds) |
719 |
{ |
720 |
s->blizzard.opaque = s1d13745_init(0, ds);
|
721 |
s->blizzard.block = s1d13745_write_block; |
722 |
s->blizzard.write = s1d13745_write; |
723 |
s->blizzard.read = s1d13745_read; |
724 |
|
725 |
omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
|
726 |
} |
727 |
|
728 |
static void n8x0_cbus_setup(struct n800_s *s) |
729 |
{ |
730 |
qemu_irq dat_out = omap2_gpio_in_get(s->cpu->gpif, N8X0_CBUS_DAT_GPIO)[0];
|
731 |
qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0];
|
732 |
qemu_irq tahvo_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TAHVO_GPIO)[0];
|
733 |
|
734 |
struct cbus_s *cbus = cbus_init(dat_out);
|
735 |
|
736 |
omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_CLK_GPIO, cbus->clk); |
737 |
omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_DAT_GPIO, cbus->dat); |
738 |
omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_SEL_GPIO, cbus->sel); |
739 |
|
740 |
cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
|
741 |
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
|
742 |
} |
743 |
|
744 |
static void n8x0_usb_power_cb(void *opaque, int line, int level) |
745 |
{ |
746 |
struct n800_s *s = opaque;
|
747 |
|
748 |
tusb6010_power(s->usb, level); |
749 |
} |
750 |
|
751 |
static void n8x0_usb_setup(struct n800_s *s) |
752 |
{ |
753 |
qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0];
|
754 |
qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0]; |
755 |
struct tusb_s *tusb = tusb6010_init(tusb_irq);
|
756 |
|
757 |
/* Using the NOR interface */
|
758 |
omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS, |
759 |
tusb6010_async_io(tusb), 0, 0, tusb); |
760 |
omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS, |
761 |
tusb6010_sync_io(tusb), 0, 0, tusb); |
762 |
|
763 |
s->usb = tusb; |
764 |
omap2_gpio_out_set(s->cpu->gpif, N8X0_TUSB_ENABLE_GPIO, tusb_pwr); |
765 |
} |
766 |
|
767 |
/* Setup done before the main bootloader starts by some early setup code
|
768 |
* - used when we want to run the main bootloader in emulation. This
|
769 |
* isn't documented. */
|
770 |
static uint32_t n800_pinout[104] = { |
771 |
0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0, |
772 |
0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808, |
773 |
0x08080808, 0x180800c4, 0x00b80000, 0x08080808, |
774 |
0x080800bc, 0x00cc0808, 0x08081818, 0x18180128, |
775 |
0x01241800, 0x18181818, 0x000000f0, 0x01300000, |
776 |
0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b, |
777 |
0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080, |
778 |
0x007c0000, 0x00000000, 0x00000088, 0x00840000, |
779 |
0x00000000, 0x00000094, 0x00980300, 0x0f180003, |
780 |
0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c, |
781 |
0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008, |
782 |
0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f, |
783 |
0x181800f4, 0x00f81818, 0x00000018, 0x000000fc, |
784 |
0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008, |
785 |
0x00000000, 0x00000038, 0x00340000, 0x00000000, |
786 |
0x1a080070, 0x00641a1a, 0x08080808, 0x08080060, |
787 |
0x005c0808, 0x08080808, 0x08080058, 0x00540808, |
788 |
0x08080808, 0x0808006c, 0x00680808, 0x08080808, |
789 |
0x000000a8, 0x00b00000, 0x08080808, 0x000000a0, |
790 |
0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808, |
791 |
0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff, |
792 |
0x000000ac, 0x01040800, 0x08080b0f, 0x18180100, |
793 |
0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a, |
794 |
0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00, |
795 |
0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118, |
796 |
0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b, |
797 |
}; |
798 |
|
799 |
static void n800_setup_nolo_tags(void *sram_base) |
800 |
{ |
801 |
int i;
|
802 |
uint32_t *p = sram_base + 0x8000;
|
803 |
uint32_t *v = sram_base + 0xa000;
|
804 |
|
805 |
memset(p, 0, 0x3000); |
806 |
|
807 |
strcpy((void *) (p + 0), "QEMU N800"); |
808 |
|
809 |
strcpy((void *) (p + 8), "F5"); |
810 |
|
811 |
stl_raw(p + 10, 0x04f70000); |
812 |
strcpy((void *) (p + 9), "RX-34"); |
813 |
|
814 |
/* RAM size in MB? */
|
815 |
stl_raw(p + 12, 0x80); |
816 |
|
817 |
/* Pointer to the list of tags */
|
818 |
stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000); |
819 |
|
820 |
/* The NOLO tags start here */
|
821 |
p = sram_base + 0x9000;
|
822 |
#define ADD_TAG(tag, len) \
|
823 |
stw_raw((uint16_t *) p + 0, tag); \
|
824 |
stw_raw((uint16_t *) p + 1, len); p ++; \
|
825 |
stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff)); |
826 |
|
827 |
/* OMAP STI console? Pin out settings? */
|
828 |
ADD_TAG(0x6e01, 414); |
829 |
for (i = 0; i < sizeof(n800_pinout) / 4; i ++) |
830 |
stl_raw(v ++, n800_pinout[i]); |
831 |
|
832 |
/* Kernel memsize? */
|
833 |
ADD_TAG(0x6e05, 1); |
834 |
stl_raw(v ++, 2);
|
835 |
|
836 |
/* NOLO serial console */
|
837 |
ADD_TAG(0x6e02, 4); |
838 |
stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
|
839 |
|
840 |
#if 0
|
841 |
/* CBUS settings (Retu/AVilma) */
|
842 |
ADD_TAG(0x6e03, 6);
|
843 |
stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
|
844 |
stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
|
845 |
stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
|
846 |
v += 2;
|
847 |
#endif
|
848 |
|
849 |
/* Nokia ASIC BB5 (Retu/Tahvo) */
|
850 |
ADD_TAG(0x6e0a, 4); |
851 |
stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */ |
852 |
stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */ |
853 |
v ++; |
854 |
|
855 |
/* LCD console? */
|
856 |
ADD_TAG(0x6e04, 4); |
857 |
stw_raw((uint16_t *) v + 0, 30); /* ??? */ |
858 |
stw_raw((uint16_t *) v + 1, 24); /* ??? */ |
859 |
v ++; |
860 |
|
861 |
#if 0
|
862 |
/* LCD settings */
|
863 |
ADD_TAG(0x6e06, 2);
|
864 |
stw_raw((uint16_t *) (v ++), 15); /* ??? */
|
865 |
#endif
|
866 |
|
867 |
/* I^2C (Menelaus) */
|
868 |
ADD_TAG(0x6e07, 4); |
869 |
stl_raw(v ++, 0x00720000); /* ??? */ |
870 |
|
871 |
/* Unknown */
|
872 |
ADD_TAG(0x6e0b, 6); |
873 |
stw_raw((uint16_t *) v + 0, 94); /* ??? */ |
874 |
stw_raw((uint16_t *) v + 1, 23); /* ??? */ |
875 |
stw_raw((uint16_t *) v + 2, 0); /* ??? */ |
876 |
v += 2;
|
877 |
|
878 |
/* OMAP gpio switch info */
|
879 |
ADD_TAG(0x6e0c, 80); |
880 |
strcpy((void *) v, "bat_cover"); v += 3; |
881 |
stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */ |
882 |
stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */ |
883 |
v += 2;
|
884 |
strcpy((void *) v, "cam_act"); v += 3; |
885 |
stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */ |
886 |
stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */ |
887 |
v += 2;
|
888 |
strcpy((void *) v, "cam_turn"); v += 3; |
889 |
stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */ |
890 |
stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */ |
891 |
v += 2;
|
892 |
strcpy((void *) v, "headphone"); v += 3; |
893 |
stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */ |
894 |
stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */ |
895 |
v += 2;
|
896 |
|
897 |
/* Bluetooth */
|
898 |
ADD_TAG(0x6e0e, 12); |
899 |
stl_raw(v ++, 0x5c623d01); /* ??? */ |
900 |
stl_raw(v ++, 0x00000201); /* ??? */ |
901 |
stl_raw(v ++, 0x00000000); /* ??? */ |
902 |
|
903 |
/* CX3110x WLAN settings */
|
904 |
ADD_TAG(0x6e0f, 8); |
905 |
stl_raw(v ++, 0x00610025); /* ??? */ |
906 |
stl_raw(v ++, 0xffff0057); /* ??? */ |
907 |
|
908 |
/* MMC host settings */
|
909 |
ADD_TAG(0x6e10, 12); |
910 |
stl_raw(v ++, 0xffff000f); /* ??? */ |
911 |
stl_raw(v ++, 0xffffffff); /* ??? */ |
912 |
stl_raw(v ++, 0x00000060); /* ??? */ |
913 |
|
914 |
/* OneNAND chip select */
|
915 |
ADD_TAG(0x6e11, 10); |
916 |
stl_raw(v ++, 0x00000401); /* ??? */ |
917 |
stl_raw(v ++, 0x0002003a); /* ??? */ |
918 |
stl_raw(v ++, 0x00000002); /* ??? */ |
919 |
|
920 |
/* TEA5761 sensor settings */
|
921 |
ADD_TAG(0x6e12, 2); |
922 |
stl_raw(v ++, 93); /* GPIO num ??? */ |
923 |
|
924 |
#if 0
|
925 |
/* Unknown tag */
|
926 |
ADD_TAG(6e09, 0);
|
927 |
|
928 |
/* Kernel UART / console */
|
929 |
ADD_TAG(6e12, 0);
|
930 |
#endif
|
931 |
|
932 |
/* End of the list */
|
933 |
stl_raw(p ++, 0x00000000);
|
934 |
stl_raw(p ++, 0x00000000);
|
935 |
} |
936 |
|
937 |
/* This task is normally performed by the bootloader. If we're loading
|
938 |
* a kernel directly, we need to set up GPMC mappings ourselves. */
|
939 |
static void n800_gpmc_init(struct n800_s *s) |
940 |
{ |
941 |
uint32_t config7 = |
942 |
(0xf << 8) | /* MASKADDRESS */ |
943 |
(1 << 6) | /* CSVALID */ |
944 |
(4 << 0); /* BASEADDRESS */ |
945 |
|
946 |
cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */ |
947 |
(void *) &config7, sizeof(config7)); |
948 |
} |
949 |
|
950 |
/* Setup sequence done by the bootloader */
|
951 |
static void n8x0_boot_init(void *opaque) |
952 |
{ |
953 |
struct n800_s *s = (struct n800_s *) opaque; |
954 |
uint32_t buf; |
955 |
|
956 |
/* PRCM setup */
|
957 |
#define omap_writel(addr, val) \
|
958 |
buf = (val); \ |
959 |
cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf)) |
960 |
|
961 |
omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */ |
962 |
omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */ |
963 |
omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */ |
964 |
omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */ |
965 |
omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */ |
966 |
omap_writel(0x48008098, 0); /* PRCM_POLCTRL */ |
967 |
omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */ |
968 |
omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */ |
969 |
omap_writel(0x48008158, 1); /* RM_RSTST_MPU */ |
970 |
omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */ |
971 |
omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */ |
972 |
omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */ |
973 |
omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */ |
974 |
omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */ |
975 |
omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */ |
976 |
omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */ |
977 |
omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */ |
978 |
omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */ |
979 |
omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */ |
980 |
omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */ |
981 |
omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */ |
982 |
omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */ |
983 |
omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */ |
984 |
omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */ |
985 |
omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */ |
986 |
omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */ |
987 |
omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */ |
988 |
omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */ |
989 |
omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */ |
990 |
omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */ |
991 |
omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */ |
992 |
omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */ |
993 |
omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */ |
994 |
omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */ |
995 |
omap_writel(0x48008540, /* CM_CLKSEL1_PLL */ |
996 |
(0x78 << 12) | (6 << 8)); |
997 |
omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */ |
998 |
|
999 |
/* GPMC setup */
|
1000 |
n800_gpmc_init(s); |
1001 |
|
1002 |
/* Video setup */
|
1003 |
n800_dss_init(&s->blizzard); |
1004 |
|
1005 |
/* CPU setup */
|
1006 |
s->cpu->env->regs[15] = s->cpu->env->boot_info->loader_start;
|
1007 |
s->cpu->env->GE = 0x5;
|
1008 |
|
1009 |
/* If the machine has a slided keyboard, open it */
|
1010 |
if (s->kbd)
|
1011 |
qemu_irq_raise(omap2_gpio_in_get(s->cpu->gpif, N810_SLIDE_GPIO)[0]);
|
1012 |
} |
1013 |
|
1014 |
#define OMAP_TAG_NOKIA_BT 0x4e01 |
1015 |
#define OMAP_TAG_WLAN_CX3110X 0x4e02 |
1016 |
#define OMAP_TAG_CBUS 0x4e03 |
1017 |
#define OMAP_TAG_EM_ASIC_BB5 0x4e04 |
1018 |
|
1019 |
static struct omap_gpiosw_info_s { |
1020 |
const char *name; |
1021 |
int line;
|
1022 |
int type;
|
1023 |
} n800_gpiosw_info[] = { |
1024 |
{ |
1025 |
"bat_cover", N800_BAT_COVER_GPIO,
|
1026 |
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
1027 |
}, { |
1028 |
"cam_act", N800_CAM_ACT_GPIO,
|
1029 |
OMAP_GPIOSW_TYPE_ACTIVITY, |
1030 |
}, { |
1031 |
"cam_turn", N800_CAM_TURN_GPIO,
|
1032 |
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED, |
1033 |
}, { |
1034 |
"headphone", N8X0_HEADPHONE_GPIO,
|
1035 |
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, |
1036 |
}, |
1037 |
{ 0 }
|
1038 |
}, n810_gpiosw_info[] = { |
1039 |
{ |
1040 |
"gps_reset", N810_GPS_RESET_GPIO,
|
1041 |
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, |
1042 |
}, { |
1043 |
"gps_wakeup", N810_GPS_WAKEUP_GPIO,
|
1044 |
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, |
1045 |
}, { |
1046 |
"headphone", N8X0_HEADPHONE_GPIO,
|
1047 |
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, |
1048 |
}, { |
1049 |
"kb_lock", N810_KB_LOCK_GPIO,
|
1050 |
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
1051 |
}, { |
1052 |
"sleepx_led", N810_SLEEPX_LED_GPIO,
|
1053 |
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT, |
1054 |
}, { |
1055 |
"slide", N810_SLIDE_GPIO,
|
1056 |
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
1057 |
}, |
1058 |
{ 0 }
|
1059 |
}; |
1060 |
|
1061 |
static struct omap_partition_info_s { |
1062 |
uint32_t offset; |
1063 |
uint32_t size; |
1064 |
int mask;
|
1065 |
const char *name; |
1066 |
} n800_part_info[] = { |
1067 |
{ 0x00000000, 0x00020000, 0x3, "bootloader" }, |
1068 |
{ 0x00020000, 0x00060000, 0x0, "config" }, |
1069 |
{ 0x00080000, 0x00200000, 0x0, "kernel" }, |
1070 |
{ 0x00280000, 0x00200000, 0x3, "initfs" }, |
1071 |
{ 0x00480000, 0x0fb80000, 0x3, "rootfs" }, |
1072 |
|
1073 |
{ 0, 0, 0, 0 } |
1074 |
}, n810_part_info[] = { |
1075 |
{ 0x00000000, 0x00020000, 0x3, "bootloader" }, |
1076 |
{ 0x00020000, 0x00060000, 0x0, "config" }, |
1077 |
{ 0x00080000, 0x00220000, 0x0, "kernel" }, |
1078 |
{ 0x002a0000, 0x00400000, 0x0, "initfs" }, |
1079 |
{ 0x006a0000, 0x0f960000, 0x0, "rootfs" }, |
1080 |
|
1081 |
{ 0, 0, 0, 0 } |
1082 |
}; |
1083 |
|
1084 |
static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
|
1085 |
|
1086 |
static int n8x0_atag_setup(void *p, int model) |
1087 |
{ |
1088 |
uint8_t *b; |
1089 |
uint16_t *w; |
1090 |
uint32_t *l; |
1091 |
struct omap_gpiosw_info_s *gpiosw;
|
1092 |
struct omap_partition_info_s *partition;
|
1093 |
const char *tag; |
1094 |
|
1095 |
w = p; |
1096 |
|
1097 |
stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
|
1098 |
stw_raw(w ++, 4); /* u16 len */ |
1099 |
stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */ |
1100 |
w ++; |
1101 |
|
1102 |
#if 0
|
1103 |
stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
|
1104 |
stw_raw(w ++, 4); /* u16 len */
|
1105 |
stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
|
1106 |
stw_raw(w ++, 115200); /* u32 console_speed */
|
1107 |
#endif
|
1108 |
|
1109 |
stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
|
1110 |
stw_raw(w ++, 36); /* u16 len */ |
1111 |
strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */ |
1112 |
w += 8;
|
1113 |
strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */ |
1114 |
w += 8;
|
1115 |
stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
|
1116 |
stw_raw(w ++, 24); /* u8 data_lines */ |
1117 |
|
1118 |
stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
|
1119 |
stw_raw(w ++, 8); /* u16 len */ |
1120 |
stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
|
1121 |
stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
|
1122 |
stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
|
1123 |
w ++; |
1124 |
|
1125 |
stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
|
1126 |
stw_raw(w ++, 4); /* u16 len */ |
1127 |
stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
|
1128 |
stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
|
1129 |
|
1130 |
gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
|
1131 |
for (; gpiosw->name; gpiosw ++) {
|
1132 |
stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
|
1133 |
stw_raw(w ++, 20); /* u16 len */ |
1134 |
strcpy((void *) w, gpiosw->name); /* char name[12] */ |
1135 |
w += 6;
|
1136 |
stw_raw(w ++, gpiosw->line); /* u16 gpio */
|
1137 |
stw_raw(w ++, gpiosw->type); |
1138 |
stw_raw(w ++, 0);
|
1139 |
stw_raw(w ++, 0);
|
1140 |
} |
1141 |
|
1142 |
stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
|
1143 |
stw_raw(w ++, 12); /* u16 len */ |
1144 |
b = (void *) w;
|
1145 |
stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */ |
1146 |
stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
|
1147 |
stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
|
1148 |
stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
|
1149 |
stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */ |
1150 |
memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */ |
1151 |
b += 6;
|
1152 |
stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */ |
1153 |
w = (void *) b;
|
1154 |
|
1155 |
stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
|
1156 |
stw_raw(w ++, 8); /* u16 len */ |
1157 |
stw_raw(w ++, 0x25); /* u8 chip_type */ |
1158 |
stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
|
1159 |
stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
|
1160 |
stw_raw(w ++, -1); /* s16 spi_cs_gpio */ |
1161 |
|
1162 |
stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
|
1163 |
stw_raw(w ++, 16); /* u16 len */ |
1164 |
if (model == 810) { |
1165 |
stw_raw(w ++, 0x23f); /* unsigned flags */ |
1166 |
stw_raw(w ++, -1); /* s16 power_pin */ |
1167 |
stw_raw(w ++, -1); /* s16 switch_pin */ |
1168 |
stw_raw(w ++, -1); /* s16 wp_pin */ |
1169 |
stw_raw(w ++, 0x240); /* unsigned flags */ |
1170 |
stw_raw(w ++, 0xc000); /* s16 power_pin */ |
1171 |
stw_raw(w ++, 0x0248); /* s16 switch_pin */ |
1172 |
stw_raw(w ++, 0xc000); /* s16 wp_pin */ |
1173 |
} else {
|
1174 |
stw_raw(w ++, 0xf); /* unsigned flags */ |
1175 |
stw_raw(w ++, -1); /* s16 power_pin */ |
1176 |
stw_raw(w ++, -1); /* s16 switch_pin */ |
1177 |
stw_raw(w ++, -1); /* s16 wp_pin */ |
1178 |
stw_raw(w ++, 0); /* unsigned flags */ |
1179 |
stw_raw(w ++, 0); /* s16 power_pin */ |
1180 |
stw_raw(w ++, 0); /* s16 switch_pin */ |
1181 |
stw_raw(w ++, 0); /* s16 wp_pin */ |
1182 |
} |
1183 |
|
1184 |
stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
|
1185 |
stw_raw(w ++, 4); /* u16 len */ |
1186 |
stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
|
1187 |
w ++; |
1188 |
|
1189 |
partition = (model == 810) ? n810_part_info : n800_part_info;
|
1190 |
for (; partition->name; partition ++) {
|
1191 |
stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
|
1192 |
stw_raw(w ++, 28); /* u16 len */ |
1193 |
strcpy((void *) w, partition->name); /* char name[16] */ |
1194 |
l = (void *) (w + 8); |
1195 |
stl_raw(l ++, partition->size); /* unsigned int size */
|
1196 |
stl_raw(l ++, partition->offset); /* unsigned int offset */
|
1197 |
stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
|
1198 |
w = (void *) l;
|
1199 |
} |
1200 |
|
1201 |
stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
|
1202 |
stw_raw(w ++, 12); /* u16 len */ |
1203 |
#if 0
|
1204 |
strcpy((void *) w, "por"); /* char reason_str[12] */
|
1205 |
strcpy((void *) w, "charger"); /* char reason_str[12] */
|
1206 |
strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
|
1207 |
strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
|
1208 |
strcpy((void *) w, "mbus"); /* char reason_str[12] */
|
1209 |
strcpy((void *) w, "unknown"); /* char reason_str[12] */
|
1210 |
strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
|
1211 |
strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
|
1212 |
strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
|
1213 |
strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
|
1214 |
#else
|
1215 |
strcpy((void *) w, "pwr_key"); /* char reason_str[12] */ |
1216 |
#endif
|
1217 |
w += 6;
|
1218 |
|
1219 |
tag = (model == 810) ? "RX-44" : "RX-34"; |
1220 |
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
|
1221 |
stw_raw(w ++, 24); /* u16 len */ |
1222 |
strcpy((void *) w, "product"); /* char component[12] */ |
1223 |
w += 6;
|
1224 |
strcpy((void *) w, tag); /* char version[12] */ |
1225 |
w += 6;
|
1226 |
|
1227 |
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
|
1228 |
stw_raw(w ++, 24); /* u16 len */ |
1229 |
strcpy((void *) w, "hw-build"); /* char component[12] */ |
1230 |
w += 6;
|
1231 |
strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */ |
1232 |
w += 6;
|
1233 |
|
1234 |
tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu"; |
1235 |
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
|
1236 |
stw_raw(w ++, 24); /* u16 len */ |
1237 |
strcpy((void *) w, "nolo"); /* char component[12] */ |
1238 |
w += 6;
|
1239 |
strcpy((void *) w, tag); /* char version[12] */ |
1240 |
w += 6;
|
1241 |
|
1242 |
return (void *) w - p; |
1243 |
} |
1244 |
|
1245 |
static int n800_atag_setup(struct arm_boot_info *info, void *p) |
1246 |
{ |
1247 |
return n8x0_atag_setup(p, 800); |
1248 |
} |
1249 |
|
1250 |
static int n810_atag_setup(struct arm_boot_info *info, void *p) |
1251 |
{ |
1252 |
return n8x0_atag_setup(p, 810); |
1253 |
} |
1254 |
|
1255 |
static void n8x0_init(ram_addr_t ram_size, const char *boot_device, |
1256 |
DisplayState *ds, const char *kernel_filename, |
1257 |
const char *kernel_cmdline, const char *initrd_filename, |
1258 |
const char *cpu_model, struct arm_boot_info *binfo, int model) |
1259 |
{ |
1260 |
struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s)); |
1261 |
int sdram_size = binfo->ram_size;
|
1262 |
int onenandram_size = 0x00010000; |
1263 |
|
1264 |
if (ram_size < sdram_size + onenandram_size + OMAP242X_SRAM_SIZE) {
|
1265 |
fprintf(stderr, "This architecture uses %i bytes of memory\n",
|
1266 |
sdram_size + onenandram_size + OMAP242X_SRAM_SIZE); |
1267 |
exit(1);
|
1268 |
} |
1269 |
|
1270 |
s->cpu = omap2420_mpu_init(sdram_size, NULL, cpu_model);
|
1271 |
|
1272 |
/* Setup peripherals
|
1273 |
*
|
1274 |
* Believed external peripherals layout in the N810:
|
1275 |
* (spi bus 1)
|
1276 |
* tsc2005
|
1277 |
* lcd_mipid
|
1278 |
* (spi bus 2)
|
1279 |
* Conexant cx3110x (WLAN)
|
1280 |
* optional: pc2400m (WiMAX)
|
1281 |
* (i2c bus 0)
|
1282 |
* TLV320AIC33 (audio codec)
|
1283 |
* TCM825x (camera by Toshiba)
|
1284 |
* lp5521 (clever LEDs)
|
1285 |
* tsl2563 (light sensor, hwmon, model 7, rev. 0)
|
1286 |
* lm8323 (keypad, manf 00, rev 04)
|
1287 |
* (i2c bus 1)
|
1288 |
* tmp105 (temperature sensor, hwmon)
|
1289 |
* menelaus (pm)
|
1290 |
* (somewhere on i2c - maybe N800-only)
|
1291 |
* tea5761 (FM tuner)
|
1292 |
* (serial 0)
|
1293 |
* GPS
|
1294 |
* (some serial port)
|
1295 |
* csr41814 (Bluetooth)
|
1296 |
*/
|
1297 |
n8x0_gpio_setup(s); |
1298 |
n8x0_nand_setup(s); |
1299 |
n8x0_i2c_setup(s); |
1300 |
if (model == 800) |
1301 |
n800_tsc_kbd_setup(s); |
1302 |
else if (model == 810) { |
1303 |
n810_tsc_setup(s); |
1304 |
n810_kbd_setup(s); |
1305 |
} |
1306 |
n8x0_spi_setup(s); |
1307 |
n8x0_dss_setup(s, ds); |
1308 |
n8x0_cbus_setup(s); |
1309 |
if (usb_enabled)
|
1310 |
n8x0_usb_setup(s); |
1311 |
|
1312 |
/* Setup initial (reset) machine state */
|
1313 |
|
1314 |
/* Start at the OneNAND bootloader. */
|
1315 |
s->cpu->env->regs[15] = 0; |
1316 |
|
1317 |
if (kernel_filename) {
|
1318 |
/* Or at the linux loader. */
|
1319 |
binfo->kernel_filename = kernel_filename; |
1320 |
binfo->kernel_cmdline = kernel_cmdline; |
1321 |
binfo->initrd_filename = initrd_filename; |
1322 |
arm_load_kernel(s->cpu->env, binfo); |
1323 |
|
1324 |
qemu_register_reset(n8x0_boot_init, s); |
1325 |
n8x0_boot_init(s); |
1326 |
} |
1327 |
|
1328 |
if (option_rom[0] && (boot_device[0] == 'n' || !kernel_filename)) { |
1329 |
/* No, wait, better start at the ROM. */
|
1330 |
s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000; |
1331 |
|
1332 |
/* This is intended for loading the `secondary.bin' program from
|
1333 |
* Nokia images (the NOLO bootloader). The entry point seems
|
1334 |
* to be at OMAP2_Q2_BASE + 0x400000.
|
1335 |
*
|
1336 |
* The `2nd.bin' files contain some kind of earlier boot code and
|
1337 |
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
|
1338 |
*
|
1339 |
* The code above is for loading the `zImage' file from Nokia
|
1340 |
* images. */
|
1341 |
printf("%i bytes of image loaded\n", load_image(option_rom[0], |
1342 |
phys_ram_base + 0x400000));
|
1343 |
|
1344 |
n800_setup_nolo_tags(phys_ram_base + sdram_size); |
1345 |
} |
1346 |
/* FIXME: We shouldn't really be doing this here. The LCD controller
|
1347 |
will set the size once configured, so this just sets an initial
|
1348 |
size until the guest activates the display. */
|
1349 |
dpy_resize(ds, 800, 480); |
1350 |
} |
1351 |
|
1352 |
static struct arm_boot_info n800_binfo = { |
1353 |
.loader_start = OMAP2_Q2_BASE, |
1354 |
/* Actually two chips of 0x4000000 bytes each */
|
1355 |
.ram_size = 0x08000000,
|
1356 |
.board_id = 0x4f7,
|
1357 |
.atag_board = n800_atag_setup, |
1358 |
}; |
1359 |
|
1360 |
static struct arm_boot_info n810_binfo = { |
1361 |
.loader_start = OMAP2_Q2_BASE, |
1362 |
/* Actually two chips of 0x4000000 bytes each */
|
1363 |
.ram_size = 0x08000000,
|
1364 |
/* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
|
1365 |
* used by some older versions of the bootloader and 5555 is used
|
1366 |
* instead (including versions that shipped with many devices). */
|
1367 |
.board_id = 0x60c,
|
1368 |
.atag_board = n810_atag_setup, |
1369 |
}; |
1370 |
|
1371 |
static void n800_init(ram_addr_t ram_size, int vga_ram_size, |
1372 |
const char *boot_device, DisplayState *ds, |
1373 |
const char *kernel_filename, const char *kernel_cmdline, |
1374 |
const char *initrd_filename, const char *cpu_model) |
1375 |
{ |
1376 |
return n8x0_init(ram_size, boot_device, ds,
|
1377 |
kernel_filename, kernel_cmdline, initrd_filename, |
1378 |
cpu_model, &n800_binfo, 800);
|
1379 |
} |
1380 |
|
1381 |
static void n810_init(ram_addr_t ram_size, int vga_ram_size, |
1382 |
const char *boot_device, DisplayState *ds, |
1383 |
const char *kernel_filename, const char *kernel_cmdline, |
1384 |
const char *initrd_filename, const char *cpu_model) |
1385 |
{ |
1386 |
return n8x0_init(ram_size, boot_device, ds,
|
1387 |
kernel_filename, kernel_cmdline, initrd_filename, |
1388 |
cpu_model, &n810_binfo, 810);
|
1389 |
} |
1390 |
|
1391 |
QEMUMachine n800_machine = { |
1392 |
"n800",
|
1393 |
"Nokia N800 tablet aka. RX-34 (OMAP2420)",
|
1394 |
n800_init, |
1395 |
(0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | RAMSIZE_FIXED, |
1396 |
}; |
1397 |
|
1398 |
QEMUMachine n810_machine = { |
1399 |
"n810",
|
1400 |
"Nokia N810 tablet aka. RX-44 (OMAP2420)",
|
1401 |
n810_init, |
1402 |
(0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | RAMSIZE_FIXED, |
1403 |
}; |