root / target-arm / op_mem.h @ 1b2b0af5
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1 | b5ff1b31 | bellard | /* ARM memory operations. */
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2 | b5ff1b31 | bellard | |
3 | b5ff1b31 | bellard | /* Load from address T1 into T0. */
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4 | b5ff1b31 | bellard | #define MEM_LD_OP(name) \
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5 | b5ff1b31 | bellard | void OPPROTO glue(op_ld##name,MEMSUFFIX)(void) \ |
6 | b5ff1b31 | bellard | { \ |
7 | b5ff1b31 | bellard | T0 = glue(ld##name,MEMSUFFIX)(T1); \ |
8 | b5ff1b31 | bellard | FORCE_RET(); \ |
9 | b5ff1b31 | bellard | } |
10 | b5ff1b31 | bellard | |
11 | b5ff1b31 | bellard | MEM_LD_OP(ub) |
12 | b5ff1b31 | bellard | MEM_LD_OP(sb) |
13 | b5ff1b31 | bellard | MEM_LD_OP(uw) |
14 | b5ff1b31 | bellard | MEM_LD_OP(sw) |
15 | b5ff1b31 | bellard | MEM_LD_OP(l) |
16 | b5ff1b31 | bellard | |
17 | b5ff1b31 | bellard | #undef MEM_LD_OP
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18 | b5ff1b31 | bellard | |
19 | b5ff1b31 | bellard | /* Store T0 to address T1. */
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20 | b5ff1b31 | bellard | #define MEM_ST_OP(name) \
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21 | b5ff1b31 | bellard | void OPPROTO glue(op_st##name,MEMSUFFIX)(void) \ |
22 | b5ff1b31 | bellard | { \ |
23 | b5ff1b31 | bellard | glue(st##name,MEMSUFFIX)(T1, T0); \ |
24 | b5ff1b31 | bellard | FORCE_RET(); \ |
25 | b5ff1b31 | bellard | } |
26 | b5ff1b31 | bellard | |
27 | b5ff1b31 | bellard | MEM_ST_OP(b) |
28 | b5ff1b31 | bellard | MEM_ST_OP(w) |
29 | b5ff1b31 | bellard | MEM_ST_OP(l) |
30 | b5ff1b31 | bellard | |
31 | b5ff1b31 | bellard | #undef MEM_ST_OP
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32 | b5ff1b31 | bellard | |
33 | b5ff1b31 | bellard | /* Swap T0 with memory at address T1. */
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34 | b5ff1b31 | bellard | /* ??? Is this exception safe? */
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35 | b5ff1b31 | bellard | #define MEM_SWP_OP(name, lname) \
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36 | b5ff1b31 | bellard | void OPPROTO glue(op_swp##name,MEMSUFFIX)(void) \ |
37 | b5ff1b31 | bellard | { \ |
38 | b5ff1b31 | bellard | uint32_t tmp; \ |
39 | b5ff1b31 | bellard | cpu_lock(); \ |
40 | b5ff1b31 | bellard | tmp = glue(ld##lname,MEMSUFFIX)(T1); \ |
41 | b5ff1b31 | bellard | glue(st##name,MEMSUFFIX)(T1, T0); \ |
42 | b5ff1b31 | bellard | T0 = tmp; \ |
43 | b5ff1b31 | bellard | cpu_unlock(); \ |
44 | b5ff1b31 | bellard | FORCE_RET(); \ |
45 | b5ff1b31 | bellard | } |
46 | b5ff1b31 | bellard | |
47 | b5ff1b31 | bellard | MEM_SWP_OP(b, ub) |
48 | b5ff1b31 | bellard | MEM_SWP_OP(l, l) |
49 | b5ff1b31 | bellard | |
50 | b5ff1b31 | bellard | #undef MEM_SWP_OP
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51 | b5ff1b31 | bellard | |
52 | b5ff1b31 | bellard | /* Floating point load/store. Address is in T1 */
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53 | b5ff1b31 | bellard | #define VFP_MEM_OP(p, w) \
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54 | b5ff1b31 | bellard | void OPPROTO glue(op_vfp_ld##p,MEMSUFFIX)(void) \ |
55 | b5ff1b31 | bellard | { \ |
56 | b5ff1b31 | bellard | FT0##p = glue(ldf##w,MEMSUFFIX)(T1); \ |
57 | b5ff1b31 | bellard | FORCE_RET(); \ |
58 | b5ff1b31 | bellard | } \ |
59 | b5ff1b31 | bellard | void OPPROTO glue(op_vfp_st##p,MEMSUFFIX)(void) \ |
60 | b5ff1b31 | bellard | { \ |
61 | b5ff1b31 | bellard | glue(stf##w,MEMSUFFIX)(T1, FT0##p); \ |
62 | b5ff1b31 | bellard | FORCE_RET(); \ |
63 | b5ff1b31 | bellard | } |
64 | b5ff1b31 | bellard | |
65 | b5ff1b31 | bellard | VFP_MEM_OP(s,l) |
66 | b5ff1b31 | bellard | VFP_MEM_OP(d,q) |
67 | b5ff1b31 | bellard | |
68 | b5ff1b31 | bellard | #undef VFP_MEM_OP
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69 | b5ff1b31 | bellard | |
70 | b5ff1b31 | bellard | #undef MEMSUFFIX |