root / hw / unin_pci.c @ 1b9d9ebb
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1 | 502a5395 | pbrook | /*
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2 | 502a5395 | pbrook | * QEMU Uninorth PCI host (for all Mac99 and newer machines)
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3 | 502a5395 | pbrook | *
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4 | 502a5395 | pbrook | * Copyright (c) 2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
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12 | 502a5395 | pbrook | *
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13 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
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15 | 502a5395 | pbrook | *
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16 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 502a5395 | pbrook | * THE SOFTWARE.
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23 | 502a5395 | pbrook | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc_mac.h" |
26 | 87ecb68b | pbrook | #include "pci.h" |
27 | 87ecb68b | pbrook | |
28 | 502a5395 | pbrook | typedef target_phys_addr_t pci_addr_t;
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29 | 502a5395 | pbrook | #include "pci_host.h" |
30 | 502a5395 | pbrook | |
31 | 502a5395 | pbrook | typedef PCIHostState UNINState;
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32 | 502a5395 | pbrook | |
33 | 502a5395 | pbrook | static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
34 | 502a5395 | pbrook | uint32_t val) |
35 | 502a5395 | pbrook | { |
36 | 502a5395 | pbrook | UNINState *s = opaque; |
37 | 502a5395 | pbrook | int i;
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38 | 502a5395 | pbrook | |
39 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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40 | 502a5395 | pbrook | val = bswap32(val); |
41 | 502a5395 | pbrook | #endif
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42 | 502a5395 | pbrook | |
43 | 502a5395 | pbrook | for (i = 11; i < 32; i++) { |
44 | 502a5395 | pbrook | if ((val & (1 << i)) != 0) |
45 | 502a5395 | pbrook | break;
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46 | 502a5395 | pbrook | } |
47 | 502a5395 | pbrook | #if 0
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48 | 502a5395 | pbrook | s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
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49 | 502a5395 | pbrook | #else
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50 | 502a5395 | pbrook | s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11); |
51 | 502a5395 | pbrook | #endif
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52 | 502a5395 | pbrook | } |
53 | 502a5395 | pbrook | |
54 | 502a5395 | pbrook | static uint32_t pci_unin_main_config_readl (void *opaque, |
55 | 502a5395 | pbrook | target_phys_addr_t addr) |
56 | 502a5395 | pbrook | { |
57 | 502a5395 | pbrook | UNINState *s = opaque; |
58 | 502a5395 | pbrook | uint32_t val; |
59 | 502a5395 | pbrook | int devfn;
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60 | 502a5395 | pbrook | |
61 | 502a5395 | pbrook | devfn = (s->config_reg >> 8) & 0xFF; |
62 | 502a5395 | pbrook | val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC); |
63 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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64 | 502a5395 | pbrook | val = bswap32(val); |
65 | 502a5395 | pbrook | #endif
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66 | 502a5395 | pbrook | |
67 | 502a5395 | pbrook | return val;
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68 | 502a5395 | pbrook | } |
69 | 502a5395 | pbrook | |
70 | 502a5395 | pbrook | static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
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71 | 502a5395 | pbrook | &pci_unin_main_config_writel, |
72 | 502a5395 | pbrook | &pci_unin_main_config_writel, |
73 | 502a5395 | pbrook | &pci_unin_main_config_writel, |
74 | 502a5395 | pbrook | }; |
75 | 502a5395 | pbrook | |
76 | 502a5395 | pbrook | static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
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77 | 502a5395 | pbrook | &pci_unin_main_config_readl, |
78 | 502a5395 | pbrook | &pci_unin_main_config_readl, |
79 | 502a5395 | pbrook | &pci_unin_main_config_readl, |
80 | 502a5395 | pbrook | }; |
81 | 502a5395 | pbrook | |
82 | 502a5395 | pbrook | static CPUWriteMemoryFunc *pci_unin_main_write[] = {
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83 | 502a5395 | pbrook | &pci_host_data_writeb, |
84 | 502a5395 | pbrook | &pci_host_data_writew, |
85 | 502a5395 | pbrook | &pci_host_data_writel, |
86 | 502a5395 | pbrook | }; |
87 | 502a5395 | pbrook | |
88 | 502a5395 | pbrook | static CPUReadMemoryFunc *pci_unin_main_read[] = {
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89 | 502a5395 | pbrook | &pci_host_data_readb, |
90 | 502a5395 | pbrook | &pci_host_data_readw, |
91 | 502a5395 | pbrook | &pci_host_data_readl, |
92 | 502a5395 | pbrook | }; |
93 | 502a5395 | pbrook | |
94 | 502a5395 | pbrook | #if 0
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95 | 502a5395 | pbrook | |
96 | 502a5395 | pbrook | static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
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97 | 502a5395 | pbrook | uint32_t val)
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98 | 502a5395 | pbrook | {
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99 | 502a5395 | pbrook | UNINState *s = opaque;
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100 | 502a5395 | pbrook | |
101 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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102 | 502a5395 | pbrook | val = bswap32(val);
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103 | 502a5395 | pbrook | #endif
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104 | 502a5395 | pbrook | s->config_reg = 0x80000000 | (val & ~0x00000001); |
105 | 502a5395 | pbrook | } |
106 | 502a5395 | pbrook | |
107 | 502a5395 | pbrook | static uint32_t pci_unin_config_readl (void *opaque, |
108 | 502a5395 | pbrook | target_phys_addr_t addr) |
109 | 502a5395 | pbrook | { |
110 | 502a5395 | pbrook | UNINState *s = opaque; |
111 | 502a5395 | pbrook | uint32_t val; |
112 | 502a5395 | pbrook | |
113 | 502a5395 | pbrook | val = (s->config_reg | 0x00000001) & ~0x80000000; |
114 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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115 | 502a5395 | pbrook | val = bswap32(val); |
116 | 502a5395 | pbrook | #endif
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117 | 502a5395 | pbrook | |
118 | 502a5395 | pbrook | return val;
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119 | 502a5395 | pbrook | } |
120 | 502a5395 | pbrook | |
121 | 502a5395 | pbrook | static CPUWriteMemoryFunc *pci_unin_config_write[] = {
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122 | 502a5395 | pbrook | &pci_unin_config_writel, |
123 | 502a5395 | pbrook | &pci_unin_config_writel, |
124 | 502a5395 | pbrook | &pci_unin_config_writel, |
125 | 502a5395 | pbrook | }; |
126 | 502a5395 | pbrook | |
127 | 502a5395 | pbrook | static CPUReadMemoryFunc *pci_unin_config_read[] = {
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128 | 502a5395 | pbrook | &pci_unin_config_readl, |
129 | 502a5395 | pbrook | &pci_unin_config_readl, |
130 | 502a5395 | pbrook | &pci_unin_config_readl, |
131 | 502a5395 | pbrook | }; |
132 | 502a5395 | pbrook | |
133 | 502a5395 | pbrook | static CPUWriteMemoryFunc *pci_unin_write[] = {
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134 | 502a5395 | pbrook | &pci_host_pci_writeb, |
135 | 502a5395 | pbrook | &pci_host_pci_writew, |
136 | 502a5395 | pbrook | &pci_host_pci_writel, |
137 | 502a5395 | pbrook | }; |
138 | 502a5395 | pbrook | |
139 | 502a5395 | pbrook | static CPUReadMemoryFunc *pci_unin_read[] = {
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140 | 502a5395 | pbrook | &pci_host_pci_readb, |
141 | 502a5395 | pbrook | &pci_host_pci_readw, |
142 | 502a5395 | pbrook | &pci_host_pci_readl, |
143 | 502a5395 | pbrook | }; |
144 | 502a5395 | pbrook | #endif
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145 | 502a5395 | pbrook | |
146 | d2b59317 | pbrook | /* Don't know if this matches real hardware, but it agrees with OHW. */
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147 | d2b59317 | pbrook | static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) |
148 | 502a5395 | pbrook | { |
149 | d2b59317 | pbrook | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
150 | d2b59317 | pbrook | } |
151 | d2b59317 | pbrook | |
152 | d537cf6c | pbrook | static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level) |
153 | d2b59317 | pbrook | { |
154 | d537cf6c | pbrook | qemu_set_irq(pic[irq_num + 8], level);
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155 | 502a5395 | pbrook | } |
156 | 502a5395 | pbrook | |
157 | d537cf6c | pbrook | PCIBus *pci_pmac_init(qemu_irq *pic) |
158 | 502a5395 | pbrook | { |
159 | 502a5395 | pbrook | UNINState *s; |
160 | 502a5395 | pbrook | PCIDevice *d; |
161 | 502a5395 | pbrook | int pci_mem_config, pci_mem_data;
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162 | 502a5395 | pbrook | |
163 | 502a5395 | pbrook | /* Use values found on a real PowerMac */
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164 | 502a5395 | pbrook | /* Uninorth main bus */
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165 | 502a5395 | pbrook | s = qemu_mallocz(sizeof(UNINState));
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166 | d2b59317 | pbrook | s->bus = pci_register_bus(pci_unin_set_irq, pci_unin_map_irq, |
167 | 80b3ada7 | pbrook | pic, 11 << 3, 4); |
168 | 502a5395 | pbrook | |
169 | 5fafdf24 | ths | pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
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170 | 502a5395 | pbrook | pci_unin_main_config_write, s); |
171 | 502a5395 | pbrook | pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
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172 | 502a5395 | pbrook | pci_unin_main_write, s); |
173 | 502a5395 | pbrook | cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config); |
174 | 502a5395 | pbrook | cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data); |
175 | 5fafdf24 | ths | d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice), |
176 | 502a5395 | pbrook | 11 << 3, NULL, NULL); |
177 | 502a5395 | pbrook | d->config[0x00] = 0x6b; // vendor_id : Apple |
178 | 502a5395 | pbrook | d->config[0x01] = 0x10; |
179 | 502a5395 | pbrook | d->config[0x02] = 0x1F; // device_id |
180 | 502a5395 | pbrook | d->config[0x03] = 0x00; |
181 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision |
182 | 502a5395 | pbrook | d->config[0x0A] = 0x00; // class_sub = pci host |
183 | 502a5395 | pbrook | d->config[0x0B] = 0x06; // class_base = PCI_bridge |
184 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size |
185 | 502a5395 | pbrook | d->config[0x0D] = 0x10; // latency_timer |
186 | 502a5395 | pbrook | d->config[0x0E] = 0x00; // header_type |
187 | 502a5395 | pbrook | d->config[0x34] = 0x00; // capabilities_pointer |
188 | 502a5395 | pbrook | |
189 | 9f083493 | ths | #if 0 // XXX: not activated as PPC BIOS doesn't handle multiple buses properly
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190 | 502a5395 | pbrook | /* pci-to-pci bridge */
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191 | 502a5395 | pbrook | d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
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192 | 502a5395 | pbrook | NULL, NULL);
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193 | 502a5395 | pbrook | d->config[0x00] = 0x11; // vendor_id : TI
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194 | 502a5395 | pbrook | d->config[0x01] = 0x10;
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195 | 502a5395 | pbrook | d->config[0x02] = 0x26; // device_id
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196 | 502a5395 | pbrook | d->config[0x03] = 0x00;
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197 | 502a5395 | pbrook | d->config[0x08] = 0x05; // revision
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198 | 502a5395 | pbrook | d->config[0x0A] = 0x04; // class_sub = pci2pci
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199 | 502a5395 | pbrook | d->config[0x0B] = 0x06; // class_base = PCI_bridge
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200 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size
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201 | 502a5395 | pbrook | d->config[0x0D] = 0x20; // latency_timer
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202 | 502a5395 | pbrook | d->config[0x0E] = 0x01; // header_type
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203 | 502a5395 | pbrook | |
204 | 502a5395 | pbrook | d->config[0x18] = 0x01; // primary_bus
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205 | 502a5395 | pbrook | d->config[0x19] = 0x02; // secondary_bus
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206 | 502a5395 | pbrook | d->config[0x1A] = 0x02; // subordinate_bus
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207 | 502a5395 | pbrook | d->config[0x1B] = 0x20; // secondary_latency_timer
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208 | 502a5395 | pbrook | d->config[0x1C] = 0x11; // io_base
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209 | 502a5395 | pbrook | d->config[0x1D] = 0x01; // io_limit
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210 | 502a5395 | pbrook | d->config[0x20] = 0x00; // memory_base
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211 | 502a5395 | pbrook | d->config[0x21] = 0x80;
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212 | 502a5395 | pbrook | d->config[0x22] = 0x00; // memory_limit
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213 | 502a5395 | pbrook | d->config[0x23] = 0x80;
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214 | 502a5395 | pbrook | d->config[0x24] = 0x01; // prefetchable_memory_base
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215 | 502a5395 | pbrook | d->config[0x25] = 0x80;
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216 | 502a5395 | pbrook | d->config[0x26] = 0xF1; // prefectchable_memory_limit
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217 | 502a5395 | pbrook | d->config[0x27] = 0x7F;
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218 | 502a5395 | pbrook | // d->config[0x34] = 0xdc // capabilities_pointer
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219 | 502a5395 | pbrook | #endif
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220 | 502a5395 | pbrook | #if 0 // XXX: not needed for now
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221 | 502a5395 | pbrook | /* Uninorth AGP bus */
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222 | 502a5395 | pbrook | s = &pci_bridge[1];
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223 | 5fafdf24 | ths | pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
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224 | 502a5395 | pbrook | pci_unin_config_write, s);
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225 | 502a5395 | pbrook | pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
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226 | 502a5395 | pbrook | pci_unin_write, s);
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227 | 502a5395 | pbrook | cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
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228 | 502a5395 | pbrook | cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
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229 | 502a5395 | pbrook | |
230 | 502a5395 | pbrook | d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
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231 | 502a5395 | pbrook | NULL, NULL);
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232 | 502a5395 | pbrook | d->config[0x00] = 0x6b; // vendor_id : Apple
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233 | 502a5395 | pbrook | d->config[0x01] = 0x10;
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234 | 502a5395 | pbrook | d->config[0x02] = 0x20; // device_id
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235 | 502a5395 | pbrook | d->config[0x03] = 0x00;
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236 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision
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237 | 502a5395 | pbrook | d->config[0x0A] = 0x00; // class_sub = pci host
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238 | 502a5395 | pbrook | d->config[0x0B] = 0x06; // class_base = PCI_bridge
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239 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size
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240 | 502a5395 | pbrook | d->config[0x0D] = 0x10; // latency_timer
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241 | 502a5395 | pbrook | d->config[0x0E] = 0x00; // header_type
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242 | 502a5395 | pbrook | // d->config[0x34] = 0x80; // capabilities_pointer
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243 | 502a5395 | pbrook | #endif
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244 | 502a5395 | pbrook | |
245 | 502a5395 | pbrook | #if 0 // XXX: not needed for now
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246 | 502a5395 | pbrook | /* Uninorth internal bus */
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247 | 502a5395 | pbrook | s = &pci_bridge[2];
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248 | 5fafdf24 | ths | pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
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249 | 502a5395 | pbrook | pci_unin_config_write, s);
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250 | 502a5395 | pbrook | pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
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251 | 502a5395 | pbrook | pci_unin_write, s);
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252 | 502a5395 | pbrook | cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
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253 | 502a5395 | pbrook | cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
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254 | 502a5395 | pbrook | |
255 | 502a5395 | pbrook | d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
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256 | 502a5395 | pbrook | 3, 11 << 3, NULL, NULL);
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257 | 502a5395 | pbrook | d->config[0x00] = 0x6b; // vendor_id : Apple
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258 | 502a5395 | pbrook | d->config[0x01] = 0x10;
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259 | 502a5395 | pbrook | d->config[0x02] = 0x1E; // device_id
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260 | 502a5395 | pbrook | d->config[0x03] = 0x00;
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261 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision
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262 | 502a5395 | pbrook | d->config[0x0A] = 0x00; // class_sub = pci host
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263 | 502a5395 | pbrook | d->config[0x0B] = 0x06; // class_base = PCI_bridge
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264 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size
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265 | 502a5395 | pbrook | d->config[0x0D] = 0x10; // latency_timer
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266 | 502a5395 | pbrook | d->config[0x0E] = 0x00; // header_type
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267 | 502a5395 | pbrook | d->config[0x34] = 0x00; // capabilities_pointer
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268 | 502a5395 | pbrook | #endif
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269 | 502a5395 | pbrook | return s->bus;
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270 | 502a5395 | pbrook | } |