root / hw / ppc4xx_devs.c @ 1b9d9ebb
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/*
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* QEMU PowerPC 4xx embedded processors shared devices emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "ppc.h" |
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#include "ppc4xx.h" |
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#include "sysemu.h" |
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extern int loglevel; |
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extern FILE *logfile;
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//#define DEBUG_MMIO
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//#define DEBUG_UNASSIGNED
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#define DEBUG_UIC
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/*****************************************************************************/
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/* Generic PowerPC 4xx processor instanciation */
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CPUState *ppc4xx_init (const unsigned char *cpu_model, |
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clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
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uint32_t sysclk) |
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{ |
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CPUState *env; |
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/* init CPUs */
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env = cpu_init(cpu_model); |
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if (!env) {
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fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
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cpu_model); |
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exit(1);
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} |
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cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ |
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cpu_clk->opaque = env; |
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/* Set time-base frequency to sysclk */
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tb_clk->cb = ppc_emb_timers_init(env, sysclk); |
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tb_clk->opaque = env; |
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ppc_dcr_init(env, NULL, NULL); |
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/* Register qemu callbacks */
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qemu_register_reset(&cpu_ppc_reset, env); |
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
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return env;
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} |
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/*****************************************************************************/
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/* Fake device used to map multiple devices in a single memory page */
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#define MMIO_AREA_BITS 8 |
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#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS) |
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#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS)) |
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#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1)) |
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struct ppc4xx_mmio_t {
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target_phys_addr_t base; |
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CPUReadMemoryFunc **mem_read[MMIO_AREA_NB]; |
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CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB]; |
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void *opaque[MMIO_AREA_NB];
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}; |
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static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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#ifdef DEBUG_UNASSIGNED
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ppc4xx_mmio_t *mmio; |
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mmio = opaque; |
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printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n", |
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addr, mmio->base); |
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#endif
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return 0; |
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} |
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static void unassigned_mmio_writeb (void *opaque, |
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target_phys_addr_t addr, uint32_t val) |
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{ |
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#ifdef DEBUG_UNASSIGNED
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ppc4xx_mmio_t *mmio; |
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mmio = opaque; |
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printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n", |
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addr, val, mmio->base); |
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#endif
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} |
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static CPUReadMemoryFunc *unassigned_mmio_read[3] = { |
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unassigned_mmio_readb, |
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unassigned_mmio_readb, |
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unassigned_mmio_readb, |
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}; |
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static CPUWriteMemoryFunc *unassigned_mmio_write[3] = { |
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unassigned_mmio_writeb, |
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unassigned_mmio_writeb, |
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unassigned_mmio_writeb, |
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}; |
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static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
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target_phys_addr_t addr, int len)
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{ |
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CPUReadMemoryFunc **mem_read; |
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uint32_t ret; |
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int idx;
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idx = MMIO_IDX(addr - mmio->base); |
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#if defined(DEBUG_MMIO)
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printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__, |
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mmio, len, addr, idx); |
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#endif
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mem_read = mmio->mem_read[idx]; |
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ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base); |
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return ret;
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} |
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static void mmio_writelen (ppc4xx_mmio_t *mmio, |
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target_phys_addr_t addr, uint32_t value, int len)
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{ |
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CPUWriteMemoryFunc **mem_write; |
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int idx;
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idx = MMIO_IDX(addr - mmio->base); |
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#if defined(DEBUG_MMIO)
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printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n", |
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__func__, mmio, len, addr, idx, value); |
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#endif
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mem_write = mmio->mem_write[idx]; |
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(*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value); |
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} |
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static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr); |
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#endif
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return mmio_readlen(opaque, addr, 0); |
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} |
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static void mmio_writeb (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
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#endif
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mmio_writelen(opaque, addr, value, 0);
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} |
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static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr); |
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#endif
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return mmio_readlen(opaque, addr, 1); |
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} |
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static void mmio_writew (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
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#endif
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mmio_writelen(opaque, addr, value, 1);
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} |
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static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX "\n", __func__, addr); |
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#endif
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return mmio_readlen(opaque, addr, 2); |
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} |
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static void mmio_writel (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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#if defined(DEBUG_MMIO)
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
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#endif
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mmio_writelen(opaque, addr, value, 2);
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} |
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static CPUReadMemoryFunc *mmio_read[] = {
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&mmio_readb, |
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&mmio_readw, |
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&mmio_readl, |
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}; |
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static CPUWriteMemoryFunc *mmio_write[] = {
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&mmio_writeb, |
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&mmio_writew, |
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&mmio_writel, |
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}; |
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int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
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target_phys_addr_t offset, uint32_t len, |
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CPUReadMemoryFunc **mem_read, |
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CPUWriteMemoryFunc **mem_write, void *opaque)
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{ |
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target_phys_addr_t end; |
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int idx, eidx;
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if ((offset + len) > TARGET_PAGE_SIZE)
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return -1; |
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idx = MMIO_IDX(offset); |
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end = offset + len - 1;
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eidx = MMIO_IDX(end); |
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#if defined(DEBUG_MMIO)
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printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n", |
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__func__, offset, len, end, idx, eidx); |
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#endif
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for (; idx <= eidx; idx++) {
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mmio->mem_read[idx] = mem_read; |
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mmio->mem_write[idx] = mem_write; |
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mmio->opaque[idx] = opaque; |
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} |
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return 0; |
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} |
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ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base) |
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{ |
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ppc4xx_mmio_t *mmio; |
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int mmio_memory;
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mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
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if (mmio != NULL) { |
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mmio->base = base; |
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mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
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#if defined(DEBUG_MMIO)
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printf("%s: base " PADDRX " len %08x %d\n", __func__, |
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base, TARGET_PAGE_SIZE, mmio_memory); |
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#endif
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cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory); |
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ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
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unassigned_mmio_read, unassigned_mmio_write, |
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mmio); |
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} |
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return mmio;
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} |
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/*****************************************************************************/
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/* "Universal" Interrupt controller */
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enum {
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DCR_UICSR = 0x000,
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DCR_UICSRS = 0x001,
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DCR_UICER = 0x002,
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DCR_UICCR = 0x003,
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DCR_UICPR = 0x004,
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DCR_UICTR = 0x005,
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DCR_UICMSR = 0x006,
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DCR_UICVR = 0x007,
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DCR_UICVCR = 0x008,
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DCR_UICMAX = 0x009,
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}; |
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#define UIC_MAX_IRQ 32 |
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typedef struct ppcuic_t ppcuic_t; |
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struct ppcuic_t {
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uint32_t dcr_base; |
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int use_vectors;
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uint32_t level; /* Remembers the state of level-triggered interrupts. */
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uint32_t uicsr; /* Status register */
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uint32_t uicer; /* Enable register */
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uint32_t uiccr; /* Critical register */
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uint32_t uicpr; /* Polarity register */
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uint32_t uictr; /* Triggering register */
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uint32_t uicvcr; /* Vector configuration register */
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uint32_t uicvr; |
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qemu_irq *irqs; |
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}; |
291 |
|
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static void ppcuic_trigger_irq (ppcuic_t *uic) |
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{ |
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uint32_t ir, cr; |
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int start, end, inc, i;
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/* Trigger interrupt if any is pending */
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ir = uic->uicsr & uic->uicer & (~uic->uiccr); |
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cr = uic->uicsr & uic->uicer & uic->uiccr; |
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#ifdef DEBUG_UIC
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32 |
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" uiccr %08" PRIx32 "\n" |
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" %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", |
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__func__, uic->uicsr, uic->uicer, uic->uiccr, |
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uic->uicsr & uic->uicer, ir, cr); |
307 |
} |
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#endif
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if (ir != 0x0000000) { |
310 |
#ifdef DEBUG_UIC
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "Raise UIC interrupt\n");
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} |
314 |
#endif
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qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); |
316 |
} else {
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317 |
#ifdef DEBUG_UIC
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "Lower UIC interrupt\n");
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320 |
} |
321 |
#endif
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322 |
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); |
323 |
} |
324 |
/* Trigger critical interrupt if any is pending and update vector */
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325 |
if (cr != 0x0000000) { |
326 |
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); |
327 |
if (uic->use_vectors) {
|
328 |
/* Compute critical IRQ vector */
|
329 |
if (uic->uicvcr & 1) { |
330 |
start = 31;
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331 |
end = 0;
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332 |
inc = -1;
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333 |
} else {
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334 |
start = 0;
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335 |
end = 31;
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336 |
inc = 1;
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337 |
} |
338 |
uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
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339 |
for (i = start; i <= end; i += inc) {
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340 |
if (cr & (1 << i)) { |
341 |
uic->uicvr += (i - start) * 512 * inc;
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342 |
break;
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343 |
} |
344 |
} |
345 |
} |
346 |
#ifdef DEBUG_UIC
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347 |
if (loglevel & CPU_LOG_INT) {
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348 |
fprintf(logfile, "Raise UIC critical interrupt - "
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349 |
"vector %08" PRIx32 "\n", uic->uicvr); |
350 |
} |
351 |
#endif
|
352 |
} else {
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353 |
#ifdef DEBUG_UIC
|
354 |
if (loglevel & CPU_LOG_INT) {
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355 |
fprintf(logfile, "Lower UIC critical interrupt\n");
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356 |
} |
357 |
#endif
|
358 |
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); |
359 |
uic->uicvr = 0x00000000;
|
360 |
} |
361 |
} |
362 |
|
363 |
static void ppcuic_set_irq (void *opaque, int irq_num, int level) |
364 |
{ |
365 |
ppcuic_t *uic; |
366 |
uint32_t mask, sr; |
367 |
|
368 |
uic = opaque; |
369 |
mask = 1 << (31-irq_num); |
370 |
#ifdef DEBUG_UIC
|
371 |
if (loglevel & CPU_LOG_INT) {
|
372 |
fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
|
373 |
" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", |
374 |
__func__, irq_num, level, |
375 |
uic->uicsr, mask, uic->uicsr & mask, level << irq_num); |
376 |
} |
377 |
#endif
|
378 |
if (irq_num < 0 || irq_num > 31) |
379 |
return;
|
380 |
sr = uic->uicsr; |
381 |
|
382 |
/* Update status register */
|
383 |
if (uic->uictr & mask) {
|
384 |
/* Edge sensitive interrupt */
|
385 |
if (level == 1) |
386 |
uic->uicsr |= mask; |
387 |
} else {
|
388 |
/* Level sensitive interrupt */
|
389 |
if (level == 1) { |
390 |
uic->uicsr |= mask; |
391 |
uic->level |= mask; |
392 |
} else {
|
393 |
uic->uicsr &= ~mask; |
394 |
uic->level &= ~mask; |
395 |
} |
396 |
} |
397 |
#ifdef DEBUG_UIC
|
398 |
if (loglevel & CPU_LOG_INT) {
|
399 |
fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => " |
400 |
"%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); |
401 |
} |
402 |
#endif
|
403 |
if (sr != uic->uicsr)
|
404 |
ppcuic_trigger_irq(uic); |
405 |
} |
406 |
|
407 |
static target_ulong dcr_read_uic (void *opaque, int dcrn) |
408 |
{ |
409 |
ppcuic_t *uic; |
410 |
target_ulong ret; |
411 |
|
412 |
uic = opaque; |
413 |
dcrn -= uic->dcr_base; |
414 |
switch (dcrn) {
|
415 |
case DCR_UICSR:
|
416 |
case DCR_UICSRS:
|
417 |
ret = uic->uicsr; |
418 |
break;
|
419 |
case DCR_UICER:
|
420 |
ret = uic->uicer; |
421 |
break;
|
422 |
case DCR_UICCR:
|
423 |
ret = uic->uiccr; |
424 |
break;
|
425 |
case DCR_UICPR:
|
426 |
ret = uic->uicpr; |
427 |
break;
|
428 |
case DCR_UICTR:
|
429 |
ret = uic->uictr; |
430 |
break;
|
431 |
case DCR_UICMSR:
|
432 |
ret = uic->uicsr & uic->uicer; |
433 |
break;
|
434 |
case DCR_UICVR:
|
435 |
if (!uic->use_vectors)
|
436 |
goto no_read;
|
437 |
ret = uic->uicvr; |
438 |
break;
|
439 |
case DCR_UICVCR:
|
440 |
if (!uic->use_vectors)
|
441 |
goto no_read;
|
442 |
ret = uic->uicvcr; |
443 |
break;
|
444 |
default:
|
445 |
no_read:
|
446 |
ret = 0x00000000;
|
447 |
break;
|
448 |
} |
449 |
|
450 |
return ret;
|
451 |
} |
452 |
|
453 |
static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) |
454 |
{ |
455 |
ppcuic_t *uic; |
456 |
|
457 |
uic = opaque; |
458 |
dcrn -= uic->dcr_base; |
459 |
#ifdef DEBUG_UIC
|
460 |
if (loglevel & CPU_LOG_INT) {
|
461 |
fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val); |
462 |
} |
463 |
#endif
|
464 |
switch (dcrn) {
|
465 |
case DCR_UICSR:
|
466 |
uic->uicsr &= ~val; |
467 |
uic->uicsr |= uic->level; |
468 |
ppcuic_trigger_irq(uic); |
469 |
break;
|
470 |
case DCR_UICSRS:
|
471 |
uic->uicsr |= val; |
472 |
ppcuic_trigger_irq(uic); |
473 |
break;
|
474 |
case DCR_UICER:
|
475 |
uic->uicer = val; |
476 |
ppcuic_trigger_irq(uic); |
477 |
break;
|
478 |
case DCR_UICCR:
|
479 |
uic->uiccr = val; |
480 |
ppcuic_trigger_irq(uic); |
481 |
break;
|
482 |
case DCR_UICPR:
|
483 |
uic->uicpr = val; |
484 |
break;
|
485 |
case DCR_UICTR:
|
486 |
uic->uictr = val; |
487 |
ppcuic_trigger_irq(uic); |
488 |
break;
|
489 |
case DCR_UICMSR:
|
490 |
break;
|
491 |
case DCR_UICVR:
|
492 |
break;
|
493 |
case DCR_UICVCR:
|
494 |
uic->uicvcr = val & 0xFFFFFFFD;
|
495 |
ppcuic_trigger_irq(uic); |
496 |
break;
|
497 |
} |
498 |
} |
499 |
|
500 |
static void ppcuic_reset (void *opaque) |
501 |
{ |
502 |
ppcuic_t *uic; |
503 |
|
504 |
uic = opaque; |
505 |
uic->uiccr = 0x00000000;
|
506 |
uic->uicer = 0x00000000;
|
507 |
uic->uicpr = 0x00000000;
|
508 |
uic->uicsr = 0x00000000;
|
509 |
uic->uictr = 0x00000000;
|
510 |
if (uic->use_vectors) {
|
511 |
uic->uicvcr = 0x00000000;
|
512 |
uic->uicvr = 0x0000000;
|
513 |
} |
514 |
} |
515 |
|
516 |
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
517 |
uint32_t dcr_base, int has_ssr, int has_vr) |
518 |
{ |
519 |
ppcuic_t *uic; |
520 |
int i;
|
521 |
|
522 |
uic = qemu_mallocz(sizeof(ppcuic_t));
|
523 |
if (uic != NULL) { |
524 |
uic->dcr_base = dcr_base; |
525 |
uic->irqs = irqs; |
526 |
if (has_vr)
|
527 |
uic->use_vectors = 1;
|
528 |
for (i = 0; i < DCR_UICMAX; i++) { |
529 |
ppc_dcr_register(env, dcr_base + i, uic, |
530 |
&dcr_read_uic, &dcr_write_uic); |
531 |
} |
532 |
qemu_register_reset(ppcuic_reset, uic); |
533 |
ppcuic_reset(uic); |
534 |
} |
535 |
|
536 |
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
|
537 |
} |