root / hw / mipsnet.c @ 1baffa46
History | View | Annotate | Download (7 kB)
1 | 87ecb68b | pbrook | #include "hw.h" |
---|---|---|---|
2 | 87ecb68b | pbrook | #include "mips.h" |
3 | 87ecb68b | pbrook | #include "net.h" |
4 | 87ecb68b | pbrook | #include "isa.h" |
5 | f0fc6f8f | ths | |
6 | 57ba97de | ths | //#define DEBUG_MIPSNET_SEND
|
7 | 57ba97de | ths | //#define DEBUG_MIPSNET_RECEIVE
|
8 | f0fc6f8f | ths | //#define DEBUG_MIPSNET_DATA
|
9 | 57ba97de | ths | //#define DEBUG_MIPSNET_IRQ
|
10 | f0fc6f8f | ths | |
11 | f0fc6f8f | ths | /* MIPSnet register offsets */
|
12 | f0fc6f8f | ths | |
13 | f0fc6f8f | ths | #define MIPSNET_DEV_ID 0x00 |
14 | f0fc6f8f | ths | #define MIPSNET_BUSY 0x08 |
15 | f0fc6f8f | ths | #define MIPSNET_RX_DATA_COUNT 0x0c |
16 | f0fc6f8f | ths | #define MIPSNET_TX_DATA_COUNT 0x10 |
17 | f0fc6f8f | ths | #define MIPSNET_INT_CTL 0x14 |
18 | f0fc6f8f | ths | # define MIPSNET_INTCTL_TXDONE 0x00000001 |
19 | f0fc6f8f | ths | # define MIPSNET_INTCTL_RXDONE 0x00000002 |
20 | f0fc6f8f | ths | # define MIPSNET_INTCTL_TESTBIT 0x80000000 |
21 | f0fc6f8f | ths | #define MIPSNET_INTERRUPT_INFO 0x18 |
22 | f0fc6f8f | ths | #define MIPSNET_RX_DATA_BUFFER 0x1c |
23 | f0fc6f8f | ths | #define MIPSNET_TX_DATA_BUFFER 0x20 |
24 | f0fc6f8f | ths | |
25 | f0fc6f8f | ths | #define MAX_ETH_FRAME_SIZE 1514 |
26 | f0fc6f8f | ths | |
27 | f0fc6f8f | ths | typedef struct MIPSnetState { |
28 | f0fc6f8f | ths | uint32_t busy; |
29 | f0fc6f8f | ths | uint32_t rx_count; |
30 | f0fc6f8f | ths | uint32_t rx_read; |
31 | f0fc6f8f | ths | uint32_t tx_count; |
32 | f0fc6f8f | ths | uint32_t tx_written; |
33 | f0fc6f8f | ths | uint32_t intctl; |
34 | f0fc6f8f | ths | uint8_t rx_buffer[MAX_ETH_FRAME_SIZE]; |
35 | f0fc6f8f | ths | uint8_t tx_buffer[MAX_ETH_FRAME_SIZE]; |
36 | b946a153 | aliguori | int io_base;
|
37 | f0fc6f8f | ths | qemu_irq irq; |
38 | f0fc6f8f | ths | VLANClientState *vc; |
39 | f0fc6f8f | ths | } MIPSnetState; |
40 | f0fc6f8f | ths | |
41 | f0fc6f8f | ths | static void mipsnet_reset(MIPSnetState *s) |
42 | f0fc6f8f | ths | { |
43 | f0fc6f8f | ths | s->busy = 1;
|
44 | f0fc6f8f | ths | s->rx_count = 0;
|
45 | f0fc6f8f | ths | s->rx_read = 0;
|
46 | f0fc6f8f | ths | s->tx_count = 0;
|
47 | f0fc6f8f | ths | s->tx_written = 0;
|
48 | f0fc6f8f | ths | s->intctl = 0;
|
49 | f0fc6f8f | ths | memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
|
50 | f0fc6f8f | ths | memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
|
51 | f0fc6f8f | ths | } |
52 | f0fc6f8f | ths | |
53 | f0fc6f8f | ths | static void mipsnet_update_irq(MIPSnetState *s) |
54 | f0fc6f8f | ths | { |
55 | f0fc6f8f | ths | int isr = !!s->intctl;
|
56 | f0fc6f8f | ths | #ifdef DEBUG_MIPSNET_IRQ
|
57 | f0fc6f8f | ths | printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
|
58 | f0fc6f8f | ths | #endif
|
59 | f0fc6f8f | ths | qemu_set_irq(s->irq, isr); |
60 | f0fc6f8f | ths | } |
61 | f0fc6f8f | ths | |
62 | f0fc6f8f | ths | static int mipsnet_buffer_full(MIPSnetState *s) |
63 | f0fc6f8f | ths | { |
64 | f0fc6f8f | ths | if (s->rx_count >= MAX_ETH_FRAME_SIZE)
|
65 | f0fc6f8f | ths | return 1; |
66 | f0fc6f8f | ths | return 0; |
67 | f0fc6f8f | ths | } |
68 | f0fc6f8f | ths | |
69 | e3f5ec2b | Mark McLoughlin | static int mipsnet_can_receive(VLANClientState *vc) |
70 | f0fc6f8f | ths | { |
71 | e3f5ec2b | Mark McLoughlin | MIPSnetState *s = vc->opaque; |
72 | f0fc6f8f | ths | |
73 | f0fc6f8f | ths | if (s->busy)
|
74 | f0fc6f8f | ths | return 0; |
75 | f0fc6f8f | ths | return !mipsnet_buffer_full(s);
|
76 | f0fc6f8f | ths | } |
77 | f0fc6f8f | ths | |
78 | 4f1c942b | Mark McLoughlin | static ssize_t mipsnet_receive(VLANClientState *vc, const uint8_t *buf, size_t size) |
79 | f0fc6f8f | ths | { |
80 | e3f5ec2b | Mark McLoughlin | MIPSnetState *s = vc->opaque; |
81 | f0fc6f8f | ths | |
82 | f0fc6f8f | ths | #ifdef DEBUG_MIPSNET_RECEIVE
|
83 | f0fc6f8f | ths | printf("mipsnet: receiving len=%d\n", size);
|
84 | f0fc6f8f | ths | #endif
|
85 | e3f5ec2b | Mark McLoughlin | if (!mipsnet_can_receive(vc))
|
86 | 4f1c942b | Mark McLoughlin | return -1; |
87 | f0fc6f8f | ths | |
88 | f0fc6f8f | ths | s->busy = 1;
|
89 | f0fc6f8f | ths | |
90 | f0fc6f8f | ths | /* Just accept everything. */
|
91 | f0fc6f8f | ths | |
92 | f0fc6f8f | ths | /* Write packet data. */
|
93 | f0fc6f8f | ths | memcpy(s->rx_buffer, buf, size); |
94 | f0fc6f8f | ths | |
95 | f0fc6f8f | ths | s->rx_count = size; |
96 | f0fc6f8f | ths | s->rx_read = 0;
|
97 | f0fc6f8f | ths | |
98 | f0fc6f8f | ths | /* Now we can signal we have received something. */
|
99 | f0fc6f8f | ths | s->intctl |= MIPSNET_INTCTL_RXDONE; |
100 | f0fc6f8f | ths | mipsnet_update_irq(s); |
101 | 4f1c942b | Mark McLoughlin | |
102 | 4f1c942b | Mark McLoughlin | return size;
|
103 | f0fc6f8f | ths | } |
104 | f0fc6f8f | ths | |
105 | f0fc6f8f | ths | static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr) |
106 | f0fc6f8f | ths | { |
107 | f0fc6f8f | ths | MIPSnetState *s = opaque; |
108 | f0fc6f8f | ths | int ret = 0; |
109 | f0fc6f8f | ths | |
110 | f0fc6f8f | ths | addr &= 0x3f;
|
111 | f0fc6f8f | ths | switch (addr) {
|
112 | f0fc6f8f | ths | case MIPSNET_DEV_ID:
|
113 | 9b595395 | aurel32 | ret = be32_to_cpu(0x4d495053); /* MIPS */ |
114 | f0fc6f8f | ths | break;
|
115 | f0fc6f8f | ths | case MIPSNET_DEV_ID + 4: |
116 | 9b595395 | aurel32 | ret = be32_to_cpu(0x4e455430); /* NET0 */ |
117 | f0fc6f8f | ths | break;
|
118 | f0fc6f8f | ths | case MIPSNET_BUSY:
|
119 | f0fc6f8f | ths | ret = s->busy; |
120 | f0fc6f8f | ths | break;
|
121 | f0fc6f8f | ths | case MIPSNET_RX_DATA_COUNT:
|
122 | f0fc6f8f | ths | ret = s->rx_count; |
123 | f0fc6f8f | ths | break;
|
124 | f0fc6f8f | ths | case MIPSNET_TX_DATA_COUNT:
|
125 | f0fc6f8f | ths | ret = s->tx_count; |
126 | f0fc6f8f | ths | break;
|
127 | f0fc6f8f | ths | case MIPSNET_INT_CTL:
|
128 | f0fc6f8f | ths | ret = s->intctl; |
129 | f0fc6f8f | ths | s->intctl &= ~MIPSNET_INTCTL_TESTBIT; |
130 | f0fc6f8f | ths | break;
|
131 | f0fc6f8f | ths | case MIPSNET_INTERRUPT_INFO:
|
132 | f0fc6f8f | ths | /* XXX: This seems to be a per-VPE interrupt number. */
|
133 | f0fc6f8f | ths | ret = 0;
|
134 | f0fc6f8f | ths | break;
|
135 | f0fc6f8f | ths | case MIPSNET_RX_DATA_BUFFER:
|
136 | f0fc6f8f | ths | if (s->rx_count) {
|
137 | f0fc6f8f | ths | s->rx_count--; |
138 | f0fc6f8f | ths | ret = s->rx_buffer[s->rx_read++]; |
139 | f0fc6f8f | ths | } |
140 | f0fc6f8f | ths | break;
|
141 | f0fc6f8f | ths | /* Reads as zero. */
|
142 | f0fc6f8f | ths | case MIPSNET_TX_DATA_BUFFER:
|
143 | f0fc6f8f | ths | default:
|
144 | f0fc6f8f | ths | break;
|
145 | f0fc6f8f | ths | } |
146 | f0fc6f8f | ths | #ifdef DEBUG_MIPSNET_DATA
|
147 | f0fc6f8f | ths | printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
|
148 | f0fc6f8f | ths | #endif
|
149 | f0fc6f8f | ths | return ret;
|
150 | f0fc6f8f | ths | } |
151 | f0fc6f8f | ths | |
152 | f0fc6f8f | ths | static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
153 | f0fc6f8f | ths | { |
154 | f0fc6f8f | ths | MIPSnetState *s = opaque; |
155 | f0fc6f8f | ths | |
156 | f0fc6f8f | ths | addr &= 0x3f;
|
157 | f0fc6f8f | ths | #ifdef DEBUG_MIPSNET_DATA
|
158 | f0fc6f8f | ths | printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
|
159 | f0fc6f8f | ths | #endif
|
160 | f0fc6f8f | ths | switch (addr) {
|
161 | f0fc6f8f | ths | case MIPSNET_TX_DATA_COUNT:
|
162 | f0fc6f8f | ths | s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
|
163 | f0fc6f8f | ths | s->tx_written = 0;
|
164 | f0fc6f8f | ths | break;
|
165 | f0fc6f8f | ths | case MIPSNET_INT_CTL:
|
166 | f0fc6f8f | ths | if (val & MIPSNET_INTCTL_TXDONE) {
|
167 | f0fc6f8f | ths | s->intctl &= ~MIPSNET_INTCTL_TXDONE; |
168 | f0fc6f8f | ths | } else if (val & MIPSNET_INTCTL_RXDONE) { |
169 | f0fc6f8f | ths | s->intctl &= ~MIPSNET_INTCTL_RXDONE; |
170 | f0fc6f8f | ths | } else if (val & MIPSNET_INTCTL_TESTBIT) { |
171 | f0fc6f8f | ths | mipsnet_reset(s); |
172 | f0fc6f8f | ths | s->intctl |= MIPSNET_INTCTL_TESTBIT; |
173 | f0fc6f8f | ths | } else if (!val) { |
174 | f0fc6f8f | ths | /* ACK testbit interrupt, flag was cleared on read. */
|
175 | f0fc6f8f | ths | } |
176 | f0fc6f8f | ths | s->busy = !!s->intctl; |
177 | f0fc6f8f | ths | mipsnet_update_irq(s); |
178 | f0fc6f8f | ths | break;
|
179 | f0fc6f8f | ths | case MIPSNET_TX_DATA_BUFFER:
|
180 | f0fc6f8f | ths | s->tx_buffer[s->tx_written++] = val; |
181 | f0fc6f8f | ths | if (s->tx_written == s->tx_count) {
|
182 | f0fc6f8f | ths | /* Send buffer. */
|
183 | f0fc6f8f | ths | #ifdef DEBUG_MIPSNET_SEND
|
184 | f0fc6f8f | ths | printf("mipsnet: sending len=%d\n", s->tx_count);
|
185 | f0fc6f8f | ths | #endif
|
186 | f0fc6f8f | ths | qemu_send_packet(s->vc, s->tx_buffer, s->tx_count); |
187 | f0fc6f8f | ths | s->tx_count = s->tx_written = 0;
|
188 | f0fc6f8f | ths | s->intctl |= MIPSNET_INTCTL_TXDONE; |
189 | f0fc6f8f | ths | s->busy = 1;
|
190 | f0fc6f8f | ths | mipsnet_update_irq(s); |
191 | f0fc6f8f | ths | } |
192 | f0fc6f8f | ths | break;
|
193 | f0fc6f8f | ths | /* Read-only registers */
|
194 | f0fc6f8f | ths | case MIPSNET_DEV_ID:
|
195 | f0fc6f8f | ths | case MIPSNET_BUSY:
|
196 | f0fc6f8f | ths | case MIPSNET_RX_DATA_COUNT:
|
197 | f0fc6f8f | ths | case MIPSNET_INTERRUPT_INFO:
|
198 | f0fc6f8f | ths | case MIPSNET_RX_DATA_BUFFER:
|
199 | f0fc6f8f | ths | default:
|
200 | f0fc6f8f | ths | break;
|
201 | f0fc6f8f | ths | } |
202 | f0fc6f8f | ths | } |
203 | f0fc6f8f | ths | |
204 | f0fc6f8f | ths | static void mipsnet_save(QEMUFile *f, void *opaque) |
205 | f0fc6f8f | ths | { |
206 | f0fc6f8f | ths | MIPSnetState *s = opaque; |
207 | f0fc6f8f | ths | |
208 | f0fc6f8f | ths | qemu_put_be32s(f, &s->busy); |
209 | f0fc6f8f | ths | qemu_put_be32s(f, &s->rx_count); |
210 | f0fc6f8f | ths | qemu_put_be32s(f, &s->rx_read); |
211 | f0fc6f8f | ths | qemu_put_be32s(f, &s->tx_count); |
212 | f0fc6f8f | ths | qemu_put_be32s(f, &s->tx_written); |
213 | f0fc6f8f | ths | qemu_put_be32s(f, &s->intctl); |
214 | f0fc6f8f | ths | qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE); |
215 | f0fc6f8f | ths | qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE); |
216 | f0fc6f8f | ths | } |
217 | f0fc6f8f | ths | |
218 | f0fc6f8f | ths | static int mipsnet_load(QEMUFile *f, void *opaque, int version_id) |
219 | f0fc6f8f | ths | { |
220 | f0fc6f8f | ths | MIPSnetState *s = opaque; |
221 | f0fc6f8f | ths | |
222 | f0fc6f8f | ths | if (version_id > 0) |
223 | f0fc6f8f | ths | return -EINVAL;
|
224 | f0fc6f8f | ths | |
225 | f0fc6f8f | ths | qemu_get_be32s(f, &s->busy); |
226 | f0fc6f8f | ths | qemu_get_be32s(f, &s->rx_count); |
227 | f0fc6f8f | ths | qemu_get_be32s(f, &s->rx_read); |
228 | f0fc6f8f | ths | qemu_get_be32s(f, &s->tx_count); |
229 | f0fc6f8f | ths | qemu_get_be32s(f, &s->tx_written); |
230 | f0fc6f8f | ths | qemu_get_be32s(f, &s->intctl); |
231 | f0fc6f8f | ths | qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE); |
232 | f0fc6f8f | ths | qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE); |
233 | f0fc6f8f | ths | |
234 | f0fc6f8f | ths | return 0; |
235 | f0fc6f8f | ths | } |
236 | f0fc6f8f | ths | |
237 | b946a153 | aliguori | static void mipsnet_cleanup(VLANClientState *vc) |
238 | b946a153 | aliguori | { |
239 | b946a153 | aliguori | MIPSnetState *s = vc->opaque; |
240 | b946a153 | aliguori | |
241 | b946a153 | aliguori | unregister_savevm("mipsnet", s);
|
242 | b946a153 | aliguori | |
243 | b946a153 | aliguori | isa_unassign_ioport(s->io_base, 36);
|
244 | b946a153 | aliguori | |
245 | b946a153 | aliguori | qemu_free(s); |
246 | b946a153 | aliguori | } |
247 | b946a153 | aliguori | |
248 | f0fc6f8f | ths | void mipsnet_init (int base, qemu_irq irq, NICInfo *nd) |
249 | f0fc6f8f | ths | { |
250 | f0fc6f8f | ths | MIPSnetState *s; |
251 | f0fc6f8f | ths | |
252 | 0ae18cee | aliguori | qemu_check_nic_model(nd, "mipsnet");
|
253 | 0ae18cee | aliguori | |
254 | f0fc6f8f | ths | s = qemu_mallocz(sizeof(MIPSnetState));
|
255 | f0fc6f8f | ths | |
256 | f0fc6f8f | ths | register_ioport_write(base, 36, 1, mipsnet_ioport_write, s); |
257 | f0fc6f8f | ths | register_ioport_read(base, 36, 1, mipsnet_ioport_read, s); |
258 | f0fc6f8f | ths | register_ioport_write(base, 36, 2, mipsnet_ioport_write, s); |
259 | f0fc6f8f | ths | register_ioport_read(base, 36, 2, mipsnet_ioport_read, s); |
260 | f0fc6f8f | ths | register_ioport_write(base, 36, 4, mipsnet_ioport_write, s); |
261 | f0fc6f8f | ths | register_ioport_read(base, 36, 4, mipsnet_ioport_read, s); |
262 | f0fc6f8f | ths | |
263 | b946a153 | aliguori | s->io_base = base; |
264 | f0fc6f8f | ths | s->irq = irq; |
265 | f0fc6f8f | ths | if (nd && nd->vlan) {
|
266 | ae50b274 | Mark McLoughlin | s->vc = nd->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name, |
267 | ae50b274 | Mark McLoughlin | mipsnet_can_receive, mipsnet_receive, |
268 | ae50b274 | Mark McLoughlin | NULL, mipsnet_cleanup, s);
|
269 | f0fc6f8f | ths | } else {
|
270 | f0fc6f8f | ths | s->vc = NULL;
|
271 | f0fc6f8f | ths | } |
272 | f0fc6f8f | ths | |
273 | ad067148 | aliguori | qemu_format_nic_info_str(s->vc, nd->macaddr); |
274 | f0fc6f8f | ths | |
275 | f0fc6f8f | ths | mipsnet_reset(s); |
276 | f0fc6f8f | ths | register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s); |
277 | f0fc6f8f | ths | } |