root / target-mips / exec.h @ 1c02e2a1
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| 1 | 6af0bf9c | bellard | #if !defined(__QEMU_MIPS_EXEC_H__)
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| 2 | 6af0bf9c | bellard | #define __QEMU_MIPS_EXEC_H__
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| 3 | 6af0bf9c | bellard | |
| 4 | 01dbbdf1 | bellard | //#define DEBUG_OP
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| 5 | 6af0bf9c | bellard | |
| 6 | c570fd16 | ths | #include "config.h" |
| 7 | 6af0bf9c | bellard | #include "mips-defs.h" |
| 8 | 6af0bf9c | bellard | #include "dyngen-exec.h" |
| 9 | 01179c38 | ths | #include "cpu-defs.h" |
| 10 | 6af0bf9c | bellard | |
| 11 | 6af0bf9c | bellard | register struct CPUMIPSState *env asm(AREG0); |
| 12 | 6af0bf9c | bellard | |
| 13 | 6af0bf9c | bellard | #include "cpu.h" |
| 14 | 6af0bf9c | bellard | #include "exec-all.h" |
| 15 | 6af0bf9c | bellard | |
| 16 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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| 17 | a9049a07 | bellard | #include "softmmu_exec.h" |
| 18 | 6af0bf9c | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
| 19 | 6af0bf9c | bellard | |
| 20 | 6a4955a8 | aliguori | static inline int cpu_has_work(CPUState *env) |
| 21 | 6a4955a8 | aliguori | {
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| 22 | 6a4955a8 | aliguori | return (env->interrupt_request &
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| 23 | 6a4955a8 | aliguori | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)); |
| 24 | 6a4955a8 | aliguori | } |
| 25 | 6a4955a8 | aliguori | |
| 26 | 6a4955a8 | aliguori | |
| 27 | c904ef0e | ths | static inline int cpu_halted(CPUState *env) |
| 28 | 08fa4bab | ths | {
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| 29 | bfed01fc | ths | if (!env->halted)
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| 30 | bfed01fc | ths | return 0; |
| 31 | 6a4955a8 | aliguori | if (cpu_has_work(env)) {
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| 32 | bfed01fc | ths | env->halted = 0;
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| 33 | bfed01fc | ths | return 0; |
| 34 | bfed01fc | ths | } |
| 35 | bfed01fc | ths | return EXCP_HALTED;
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| 36 | bfed01fc | ths | } |
| 37 | bfed01fc | ths | |
| 38 | c904ef0e | ths | static inline void compute_hflags(CPUState *env) |
| 39 | 08fa4bab | ths | {
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| 40 | b8aa4598 | ths | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
| 41 | 2623c1ec | aurel32 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
| 42 | 2623c1ec | aurel32 | MIPS_HFLAG_UX); |
| 43 | 08fa4bab | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
| 44 | 08fa4bab | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
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| 45 | 671880e6 | ths | !(env->hflags & MIPS_HFLAG_DM)) {
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| 46 | 623a930e | ths | env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
| 47 | 671880e6 | ths | } |
| 48 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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| 49 | 623a930e | ths | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
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| 50 | 08fa4bab | ths | (env->CP0_Status & (1 << CP0St_PX)) ||
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| 51 | 08fa4bab | ths | (env->CP0_Status & (1 << CP0St_UX)))
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| 52 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_64; |
| 53 | 2623c1ec | aurel32 | if (env->CP0_Status & (1 << CP0St_UX)) |
| 54 | 2623c1ec | aurel32 | env->hflags |= MIPS_HFLAG_UX; |
| 55 | 08fa4bab | ths | #endif
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| 56 | 671880e6 | ths | if ((env->CP0_Status & (1 << CP0St_CU0)) || |
| 57 | 623a930e | ths | !(env->hflags & MIPS_HFLAG_KSU)) |
| 58 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_CP0; |
| 59 | 08fa4bab | ths | if (env->CP0_Status & (1 << CP0St_CU1)) |
| 60 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_FPU; |
| 61 | 08fa4bab | ths | if (env->CP0_Status & (1 << CP0St_FR)) |
| 62 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_F64; |
| 63 | b8aa4598 | ths | if (env->insn_flags & ISA_MIPS32R2) {
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| 64 | f01be154 | ths | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
| 65 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
| 66 | b8aa4598 | ths | } else if (env->insn_flags & ISA_MIPS32) { |
| 67 | b8aa4598 | ths | if (env->hflags & MIPS_HFLAG_64)
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| 68 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
| 69 | b8aa4598 | ths | } else if (env->insn_flags & ISA_MIPS4) { |
| 70 | b8aa4598 | ths | /* All supported MIPS IV CPUs use the XX (CU3) to enable
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| 71 | b8aa4598 | ths | and disable the MIPS IV extensions to the MIPS III ISA.
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| 72 | b8aa4598 | ths | Some other MIPS IV CPUs ignore the bit, so the check here
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| 73 | b8aa4598 | ths | would be too restrictive for them. */
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| 74 | b8aa4598 | ths | if (env->CP0_Status & (1 << CP0St_CU3)) |
| 75 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
| 76 | b8aa4598 | ths | } |
| 77 | 08fa4bab | ths | } |
| 78 | 08fa4bab | ths | |
| 79 | 10eb0cc0 | Paolo Bonzini | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
| 80 | 10eb0cc0 | Paolo Bonzini | {
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| 81 | 10eb0cc0 | Paolo Bonzini | env->active_tc.PC = tb->pc; |
| 82 | 10eb0cc0 | Paolo Bonzini | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 83 | 10eb0cc0 | Paolo Bonzini | env->hflags |= tb->flags & MIPS_HFLAG_BMASK; |
| 84 | 10eb0cc0 | Paolo Bonzini | } |
| 85 | 10eb0cc0 | Paolo Bonzini | |
| 86 | 6af0bf9c | bellard | #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |