root / target-mips / cpu.h @ 1c12e1f5
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1 | 6af0bf9c | bellard | #if !defined (__MIPS_CPU_H__)
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2 | 6af0bf9c | bellard | #define __MIPS_CPU_H__
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3 | 6af0bf9c | bellard | |
4 | 3e457172 | Blue Swirl | //#define DEBUG_OP
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5 | 3e457172 | Blue Swirl | |
6 | 4ad40f36 | bellard | #define TARGET_HAS_ICE 1 |
7 | 4ad40f36 | bellard | |
8 | 9042c0e2 | ths | #define ELF_MACHINE EM_MIPS
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9 | 9042c0e2 | ths | |
10 | 9349b4f9 | Andreas Färber | #define CPUArchState struct CPUMIPSState |
11 | c2764719 | pbrook | |
12 | c5d6edc3 | bellard | #include "config.h" |
13 | 9a78eead | Stefan Weil | #include "qemu-common.h" |
14 | 6af0bf9c | bellard | #include "mips-defs.h" |
15 | 6af0bf9c | bellard | #include "cpu-defs.h" |
16 | 6af0bf9c | bellard | #include "softfloat.h" |
17 | 6af0bf9c | bellard | |
18 | ead9360e | ths | struct CPUMIPSState;
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19 | 6af0bf9c | bellard | |
20 | c227f099 | Anthony Liguori | typedef struct r4k_tlb_t r4k_tlb_t; |
21 | c227f099 | Anthony Liguori | struct r4k_tlb_t {
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22 | 6af0bf9c | bellard | target_ulong VPN; |
23 | 9c2149c8 | ths | uint32_t PageMask; |
24 | 98c1b82b | pbrook | uint_fast8_t ASID; |
25 | 98c1b82b | pbrook | uint_fast16_t G:1;
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26 | 98c1b82b | pbrook | uint_fast16_t C0:3;
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27 | 98c1b82b | pbrook | uint_fast16_t C1:3;
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28 | 98c1b82b | pbrook | uint_fast16_t V0:1;
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29 | 98c1b82b | pbrook | uint_fast16_t V1:1;
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30 | 98c1b82b | pbrook | uint_fast16_t D0:1;
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31 | 98c1b82b | pbrook | uint_fast16_t D1:1;
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32 | 6af0bf9c | bellard | target_ulong PFN[2];
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33 | 6af0bf9c | bellard | }; |
34 | 6af0bf9c | bellard | |
35 | 3c7b48b7 | Paul Brook | #if !defined(CONFIG_USER_ONLY)
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36 | ead9360e | ths | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
37 | ead9360e | ths | struct CPUMIPSTLBContext {
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38 | ead9360e | ths | uint32_t nb_tlb; |
39 | ead9360e | ths | uint32_t tlb_in_use; |
40 | a8170e5e | Avi Kivity | int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type); |
41 | 895c2d04 | Blue Swirl | void (*helper_tlbwi)(struct CPUMIPSState *env); |
42 | 895c2d04 | Blue Swirl | void (*helper_tlbwr)(struct CPUMIPSState *env); |
43 | 895c2d04 | Blue Swirl | void (*helper_tlbp)(struct CPUMIPSState *env); |
44 | 895c2d04 | Blue Swirl | void (*helper_tlbr)(struct CPUMIPSState *env); |
45 | ead9360e | ths | union {
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46 | ead9360e | ths | struct {
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47 | c227f099 | Anthony Liguori | r4k_tlb_t tlb[MIPS_TLB_MAX]; |
48 | ead9360e | ths | } r4k; |
49 | ead9360e | ths | } mmu; |
50 | ead9360e | ths | }; |
51 | 3c7b48b7 | Paul Brook | #endif
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52 | 51b2772f | ths | |
53 | c227f099 | Anthony Liguori | typedef union fpr_t fpr_t; |
54 | c227f099 | Anthony Liguori | union fpr_t {
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55 | ead9360e | ths | float64 fd; /* ieee double precision */
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56 | ead9360e | ths | float32 fs[2];/* ieee single precision */ |
57 | ead9360e | ths | uint64_t d; /* binary double fixed-point */
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58 | ead9360e | ths | uint32_t w[2]; /* binary single fixed-point */ |
59 | ead9360e | ths | }; |
60 | ead9360e | ths | /* define FP_ENDIAN_IDX to access the same location
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61 | 4ff9786c | Stefan Weil | * in the fpr_t union regardless of the host endianness
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62 | ead9360e | ths | */
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63 | e2542fe2 | Juan Quintela | #if defined(HOST_WORDS_BIGENDIAN)
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64 | ead9360e | ths | # define FP_ENDIAN_IDX 1 |
65 | ead9360e | ths | #else
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66 | ead9360e | ths | # define FP_ENDIAN_IDX 0 |
67 | c570fd16 | ths | #endif
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68 | ead9360e | ths | |
69 | ead9360e | ths | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; |
70 | ead9360e | ths | struct CPUMIPSFPUContext {
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71 | 6af0bf9c | bellard | /* Floating point registers */
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72 | c227f099 | Anthony Liguori | fpr_t fpr[32];
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73 | 6ea83fed | bellard | float_status fp_status; |
74 | 5a5012ec | ths | /* fpu implementation/revision register (fir) */
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75 | 6af0bf9c | bellard | uint32_t fcr0; |
76 | 5a5012ec | ths | #define FCR0_F64 22 |
77 | 5a5012ec | ths | #define FCR0_L 21 |
78 | 5a5012ec | ths | #define FCR0_W 20 |
79 | 5a5012ec | ths | #define FCR0_3D 19 |
80 | 5a5012ec | ths | #define FCR0_PS 18 |
81 | 5a5012ec | ths | #define FCR0_D 17 |
82 | 5a5012ec | ths | #define FCR0_S 16 |
83 | 5a5012ec | ths | #define FCR0_PRID 8 |
84 | 5a5012ec | ths | #define FCR0_REV 0 |
85 | 6ea83fed | bellard | /* fcsr */
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86 | 6ea83fed | bellard | uint32_t fcr31; |
87 | f01be154 | ths | #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
88 | f01be154 | ths | #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
89 | f01be154 | ths | #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) |
90 | 5a5012ec | ths | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
91 | 5a5012ec | ths | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
92 | 5a5012ec | ths | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) |
93 | 5a5012ec | ths | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) |
94 | 5a5012ec | ths | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) |
95 | 5a5012ec | ths | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) |
96 | 5a5012ec | ths | #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) |
97 | 6ea83fed | bellard | #define FP_INEXACT 1 |
98 | 6ea83fed | bellard | #define FP_UNDERFLOW 2 |
99 | 6ea83fed | bellard | #define FP_OVERFLOW 4 |
100 | 6ea83fed | bellard | #define FP_DIV0 8 |
101 | 6ea83fed | bellard | #define FP_INVALID 16 |
102 | 6ea83fed | bellard | #define FP_UNIMPLEMENTED 32 |
103 | ead9360e | ths | }; |
104 | ead9360e | ths | |
105 | 623a930e | ths | #define NB_MMU_MODES 3 |
106 | 6ebbf390 | j_mayer | |
107 | ead9360e | ths | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
108 | ead9360e | ths | struct CPUMIPSMVPContext {
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109 | ead9360e | ths | int32_t CP0_MVPControl; |
110 | ead9360e | ths | #define CP0MVPCo_CPA 3 |
111 | ead9360e | ths | #define CP0MVPCo_STLB 2 |
112 | ead9360e | ths | #define CP0MVPCo_VPC 1 |
113 | ead9360e | ths | #define CP0MVPCo_EVP 0 |
114 | ead9360e | ths | int32_t CP0_MVPConf0; |
115 | ead9360e | ths | #define CP0MVPC0_M 31 |
116 | ead9360e | ths | #define CP0MVPC0_TLBS 29 |
117 | ead9360e | ths | #define CP0MVPC0_GS 28 |
118 | ead9360e | ths | #define CP0MVPC0_PCP 27 |
119 | ead9360e | ths | #define CP0MVPC0_PTLBE 16 |
120 | ead9360e | ths | #define CP0MVPC0_TCA 15 |
121 | ead9360e | ths | #define CP0MVPC0_PVPE 10 |
122 | ead9360e | ths | #define CP0MVPC0_PTC 0 |
123 | ead9360e | ths | int32_t CP0_MVPConf1; |
124 | ead9360e | ths | #define CP0MVPC1_CIM 31 |
125 | ead9360e | ths | #define CP0MVPC1_CIF 30 |
126 | ead9360e | ths | #define CP0MVPC1_PCX 20 |
127 | ead9360e | ths | #define CP0MVPC1_PCP2 10 |
128 | ead9360e | ths | #define CP0MVPC1_PCP1 0 |
129 | ead9360e | ths | }; |
130 | ead9360e | ths | |
131 | c227f099 | Anthony Liguori | typedef struct mips_def_t mips_def_t; |
132 | ead9360e | ths | |
133 | ead9360e | ths | #define MIPS_SHADOW_SET_MAX 16 |
134 | ead9360e | ths | #define MIPS_TC_MAX 5 |
135 | f01be154 | ths | #define MIPS_FPU_MAX 1 |
136 | ead9360e | ths | #define MIPS_DSP_ACC 4 |
137 | ead9360e | ths | |
138 | b5dc7732 | ths | typedef struct TCState TCState; |
139 | b5dc7732 | ths | struct TCState {
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140 | b5dc7732 | ths | target_ulong gpr[32];
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141 | b5dc7732 | ths | target_ulong PC; |
142 | b5dc7732 | ths | target_ulong HI[MIPS_DSP_ACC]; |
143 | b5dc7732 | ths | target_ulong LO[MIPS_DSP_ACC]; |
144 | b5dc7732 | ths | target_ulong ACX[MIPS_DSP_ACC]; |
145 | b5dc7732 | ths | target_ulong DSPControl; |
146 | b5dc7732 | ths | int32_t CP0_TCStatus; |
147 | b5dc7732 | ths | #define CP0TCSt_TCU3 31 |
148 | b5dc7732 | ths | #define CP0TCSt_TCU2 30 |
149 | b5dc7732 | ths | #define CP0TCSt_TCU1 29 |
150 | b5dc7732 | ths | #define CP0TCSt_TCU0 28 |
151 | b5dc7732 | ths | #define CP0TCSt_TMX 27 |
152 | b5dc7732 | ths | #define CP0TCSt_RNST 23 |
153 | b5dc7732 | ths | #define CP0TCSt_TDS 21 |
154 | b5dc7732 | ths | #define CP0TCSt_DT 20 |
155 | b5dc7732 | ths | #define CP0TCSt_DA 15 |
156 | b5dc7732 | ths | #define CP0TCSt_A 13 |
157 | b5dc7732 | ths | #define CP0TCSt_TKSU 11 |
158 | b5dc7732 | ths | #define CP0TCSt_IXMT 10 |
159 | b5dc7732 | ths | #define CP0TCSt_TASID 0 |
160 | b5dc7732 | ths | int32_t CP0_TCBind; |
161 | b5dc7732 | ths | #define CP0TCBd_CurTC 21 |
162 | b5dc7732 | ths | #define CP0TCBd_TBE 17 |
163 | b5dc7732 | ths | #define CP0TCBd_CurVPE 0 |
164 | b5dc7732 | ths | target_ulong CP0_TCHalt; |
165 | b5dc7732 | ths | target_ulong CP0_TCContext; |
166 | b5dc7732 | ths | target_ulong CP0_TCSchedule; |
167 | b5dc7732 | ths | target_ulong CP0_TCScheFBack; |
168 | b5dc7732 | ths | int32_t CP0_Debug_tcstatus; |
169 | b5dc7732 | ths | }; |
170 | b5dc7732 | ths | |
171 | ead9360e | ths | typedef struct CPUMIPSState CPUMIPSState; |
172 | ead9360e | ths | struct CPUMIPSState {
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173 | b5dc7732 | ths | TCState active_tc; |
174 | f01be154 | ths | CPUMIPSFPUContext active_fpu; |
175 | b5dc7732 | ths | |
176 | ead9360e | ths | uint32_t current_tc; |
177 | f01be154 | ths | uint32_t current_fpu; |
178 | 36d23958 | ths | |
179 | e034e2c3 | ths | uint32_t SEGBITS; |
180 | 6d35524c | ths | uint32_t PABITS; |
181 | b6d96bed | ths | target_ulong SEGMask; |
182 | 6d35524c | ths | target_ulong PAMask; |
183 | 29929e34 | ths | |
184 | 9c2149c8 | ths | int32_t CP0_Index; |
185 | ead9360e | ths | /* CP0_MVP* are per MVP registers. */
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186 | 9c2149c8 | ths | int32_t CP0_Random; |
187 | ead9360e | ths | int32_t CP0_VPEControl; |
188 | ead9360e | ths | #define CP0VPECo_YSI 21 |
189 | ead9360e | ths | #define CP0VPECo_GSI 20 |
190 | ead9360e | ths | #define CP0VPECo_EXCPT 16 |
191 | ead9360e | ths | #define CP0VPECo_TE 15 |
192 | ead9360e | ths | #define CP0VPECo_TargTC 0 |
193 | ead9360e | ths | int32_t CP0_VPEConf0; |
194 | ead9360e | ths | #define CP0VPEC0_M 31 |
195 | ead9360e | ths | #define CP0VPEC0_XTC 21 |
196 | ead9360e | ths | #define CP0VPEC0_TCS 19 |
197 | ead9360e | ths | #define CP0VPEC0_SCS 18 |
198 | ead9360e | ths | #define CP0VPEC0_DSC 17 |
199 | ead9360e | ths | #define CP0VPEC0_ICS 16 |
200 | ead9360e | ths | #define CP0VPEC0_MVP 1 |
201 | ead9360e | ths | #define CP0VPEC0_VPA 0 |
202 | ead9360e | ths | int32_t CP0_VPEConf1; |
203 | ead9360e | ths | #define CP0VPEC1_NCX 20 |
204 | ead9360e | ths | #define CP0VPEC1_NCP2 10 |
205 | ead9360e | ths | #define CP0VPEC1_NCP1 0 |
206 | ead9360e | ths | target_ulong CP0_YQMask; |
207 | ead9360e | ths | target_ulong CP0_VPESchedule; |
208 | ead9360e | ths | target_ulong CP0_VPEScheFBack; |
209 | ead9360e | ths | int32_t CP0_VPEOpt; |
210 | ead9360e | ths | #define CP0VPEOpt_IWX7 15 |
211 | ead9360e | ths | #define CP0VPEOpt_IWX6 14 |
212 | ead9360e | ths | #define CP0VPEOpt_IWX5 13 |
213 | ead9360e | ths | #define CP0VPEOpt_IWX4 12 |
214 | ead9360e | ths | #define CP0VPEOpt_IWX3 11 |
215 | ead9360e | ths | #define CP0VPEOpt_IWX2 10 |
216 | ead9360e | ths | #define CP0VPEOpt_IWX1 9 |
217 | ead9360e | ths | #define CP0VPEOpt_IWX0 8 |
218 | ead9360e | ths | #define CP0VPEOpt_DWX7 7 |
219 | ead9360e | ths | #define CP0VPEOpt_DWX6 6 |
220 | ead9360e | ths | #define CP0VPEOpt_DWX5 5 |
221 | ead9360e | ths | #define CP0VPEOpt_DWX4 4 |
222 | ead9360e | ths | #define CP0VPEOpt_DWX3 3 |
223 | ead9360e | ths | #define CP0VPEOpt_DWX2 2 |
224 | ead9360e | ths | #define CP0VPEOpt_DWX1 1 |
225 | ead9360e | ths | #define CP0VPEOpt_DWX0 0 |
226 | 9c2149c8 | ths | target_ulong CP0_EntryLo0; |
227 | 9c2149c8 | ths | target_ulong CP0_EntryLo1; |
228 | 9c2149c8 | ths | target_ulong CP0_Context; |
229 | 9c2149c8 | ths | int32_t CP0_PageMask; |
230 | 9c2149c8 | ths | int32_t CP0_PageGrain; |
231 | 9c2149c8 | ths | int32_t CP0_Wired; |
232 | ead9360e | ths | int32_t CP0_SRSConf0_rw_bitmask; |
233 | ead9360e | ths | int32_t CP0_SRSConf0; |
234 | ead9360e | ths | #define CP0SRSC0_M 31 |
235 | ead9360e | ths | #define CP0SRSC0_SRS3 20 |
236 | ead9360e | ths | #define CP0SRSC0_SRS2 10 |
237 | ead9360e | ths | #define CP0SRSC0_SRS1 0 |
238 | ead9360e | ths | int32_t CP0_SRSConf1_rw_bitmask; |
239 | ead9360e | ths | int32_t CP0_SRSConf1; |
240 | ead9360e | ths | #define CP0SRSC1_M 31 |
241 | ead9360e | ths | #define CP0SRSC1_SRS6 20 |
242 | ead9360e | ths | #define CP0SRSC1_SRS5 10 |
243 | ead9360e | ths | #define CP0SRSC1_SRS4 0 |
244 | ead9360e | ths | int32_t CP0_SRSConf2_rw_bitmask; |
245 | ead9360e | ths | int32_t CP0_SRSConf2; |
246 | ead9360e | ths | #define CP0SRSC2_M 31 |
247 | ead9360e | ths | #define CP0SRSC2_SRS9 20 |
248 | ead9360e | ths | #define CP0SRSC2_SRS8 10 |
249 | ead9360e | ths | #define CP0SRSC2_SRS7 0 |
250 | ead9360e | ths | int32_t CP0_SRSConf3_rw_bitmask; |
251 | ead9360e | ths | int32_t CP0_SRSConf3; |
252 | ead9360e | ths | #define CP0SRSC3_M 31 |
253 | ead9360e | ths | #define CP0SRSC3_SRS12 20 |
254 | ead9360e | ths | #define CP0SRSC3_SRS11 10 |
255 | ead9360e | ths | #define CP0SRSC3_SRS10 0 |
256 | ead9360e | ths | int32_t CP0_SRSConf4_rw_bitmask; |
257 | ead9360e | ths | int32_t CP0_SRSConf4; |
258 | ead9360e | ths | #define CP0SRSC4_SRS15 20 |
259 | ead9360e | ths | #define CP0SRSC4_SRS14 10 |
260 | ead9360e | ths | #define CP0SRSC4_SRS13 0 |
261 | 9c2149c8 | ths | int32_t CP0_HWREna; |
262 | c570fd16 | ths | target_ulong CP0_BadVAddr; |
263 | 9c2149c8 | ths | int32_t CP0_Count; |
264 | 9c2149c8 | ths | target_ulong CP0_EntryHi; |
265 | 9c2149c8 | ths | int32_t CP0_Compare; |
266 | 9c2149c8 | ths | int32_t CP0_Status; |
267 | 6af0bf9c | bellard | #define CP0St_CU3 31 |
268 | 6af0bf9c | bellard | #define CP0St_CU2 30 |
269 | 6af0bf9c | bellard | #define CP0St_CU1 29 |
270 | 6af0bf9c | bellard | #define CP0St_CU0 28 |
271 | 6af0bf9c | bellard | #define CP0St_RP 27 |
272 | 6ea83fed | bellard | #define CP0St_FR 26 |
273 | 6af0bf9c | bellard | #define CP0St_RE 25 |
274 | 7a387fff | ths | #define CP0St_MX 24 |
275 | 7a387fff | ths | #define CP0St_PX 23 |
276 | 6af0bf9c | bellard | #define CP0St_BEV 22 |
277 | 6af0bf9c | bellard | #define CP0St_TS 21 |
278 | 6af0bf9c | bellard | #define CP0St_SR 20 |
279 | 6af0bf9c | bellard | #define CP0St_NMI 19 |
280 | 6af0bf9c | bellard | #define CP0St_IM 8 |
281 | 7a387fff | ths | #define CP0St_KX 7 |
282 | 7a387fff | ths | #define CP0St_SX 6 |
283 | 7a387fff | ths | #define CP0St_UX 5 |
284 | 623a930e | ths | #define CP0St_KSU 3 |
285 | 6af0bf9c | bellard | #define CP0St_ERL 2 |
286 | 6af0bf9c | bellard | #define CP0St_EXL 1 |
287 | 6af0bf9c | bellard | #define CP0St_IE 0 |
288 | 9c2149c8 | ths | int32_t CP0_IntCtl; |
289 | ead9360e | ths | #define CP0IntCtl_IPTI 29 |
290 | ead9360e | ths | #define CP0IntCtl_IPPC1 26 |
291 | ead9360e | ths | #define CP0IntCtl_VS 5 |
292 | 9c2149c8 | ths | int32_t CP0_SRSCtl; |
293 | ead9360e | ths | #define CP0SRSCtl_HSS 26 |
294 | ead9360e | ths | #define CP0SRSCtl_EICSS 18 |
295 | ead9360e | ths | #define CP0SRSCtl_ESS 12 |
296 | ead9360e | ths | #define CP0SRSCtl_PSS 6 |
297 | ead9360e | ths | #define CP0SRSCtl_CSS 0 |
298 | 9c2149c8 | ths | int32_t CP0_SRSMap; |
299 | ead9360e | ths | #define CP0SRSMap_SSV7 28 |
300 | ead9360e | ths | #define CP0SRSMap_SSV6 24 |
301 | ead9360e | ths | #define CP0SRSMap_SSV5 20 |
302 | ead9360e | ths | #define CP0SRSMap_SSV4 16 |
303 | ead9360e | ths | #define CP0SRSMap_SSV3 12 |
304 | ead9360e | ths | #define CP0SRSMap_SSV2 8 |
305 | ead9360e | ths | #define CP0SRSMap_SSV1 4 |
306 | ead9360e | ths | #define CP0SRSMap_SSV0 0 |
307 | 9c2149c8 | ths | int32_t CP0_Cause; |
308 | 7a387fff | ths | #define CP0Ca_BD 31 |
309 | 7a387fff | ths | #define CP0Ca_TI 30 |
310 | 7a387fff | ths | #define CP0Ca_CE 28 |
311 | 7a387fff | ths | #define CP0Ca_DC 27 |
312 | 7a387fff | ths | #define CP0Ca_PCI 26 |
313 | 6af0bf9c | bellard | #define CP0Ca_IV 23 |
314 | 7a387fff | ths | #define CP0Ca_WP 22 |
315 | 7a387fff | ths | #define CP0Ca_IP 8 |
316 | 4de9b249 | ths | #define CP0Ca_IP_mask 0x0000FF00 |
317 | 7a387fff | ths | #define CP0Ca_EC 2 |
318 | c570fd16 | ths | target_ulong CP0_EPC; |
319 | 9c2149c8 | ths | int32_t CP0_PRid; |
320 | b29a0341 | ths | int32_t CP0_EBase; |
321 | 9c2149c8 | ths | int32_t CP0_Config0; |
322 | 6af0bf9c | bellard | #define CP0C0_M 31 |
323 | 6af0bf9c | bellard | #define CP0C0_K23 28 |
324 | 6af0bf9c | bellard | #define CP0C0_KU 25 |
325 | 6af0bf9c | bellard | #define CP0C0_MDU 20 |
326 | 6af0bf9c | bellard | #define CP0C0_MM 17 |
327 | 6af0bf9c | bellard | #define CP0C0_BM 16 |
328 | 6af0bf9c | bellard | #define CP0C0_BE 15 |
329 | 6af0bf9c | bellard | #define CP0C0_AT 13 |
330 | 6af0bf9c | bellard | #define CP0C0_AR 10 |
331 | 6af0bf9c | bellard | #define CP0C0_MT 7 |
332 | 7a387fff | ths | #define CP0C0_VI 3 |
333 | 6af0bf9c | bellard | #define CP0C0_K0 0 |
334 | 9c2149c8 | ths | int32_t CP0_Config1; |
335 | 7a387fff | ths | #define CP0C1_M 31 |
336 | 6af0bf9c | bellard | #define CP0C1_MMU 25 |
337 | 6af0bf9c | bellard | #define CP0C1_IS 22 |
338 | 6af0bf9c | bellard | #define CP0C1_IL 19 |
339 | 6af0bf9c | bellard | #define CP0C1_IA 16 |
340 | 6af0bf9c | bellard | #define CP0C1_DS 13 |
341 | 6af0bf9c | bellard | #define CP0C1_DL 10 |
342 | 6af0bf9c | bellard | #define CP0C1_DA 7 |
343 | 7a387fff | ths | #define CP0C1_C2 6 |
344 | 7a387fff | ths | #define CP0C1_MD 5 |
345 | 6af0bf9c | bellard | #define CP0C1_PC 4 |
346 | 6af0bf9c | bellard | #define CP0C1_WR 3 |
347 | 6af0bf9c | bellard | #define CP0C1_CA 2 |
348 | 6af0bf9c | bellard | #define CP0C1_EP 1 |
349 | 6af0bf9c | bellard | #define CP0C1_FP 0 |
350 | 9c2149c8 | ths | int32_t CP0_Config2; |
351 | 7a387fff | ths | #define CP0C2_M 31 |
352 | 7a387fff | ths | #define CP0C2_TU 28 |
353 | 7a387fff | ths | #define CP0C2_TS 24 |
354 | 7a387fff | ths | #define CP0C2_TL 20 |
355 | 7a387fff | ths | #define CP0C2_TA 16 |
356 | 7a387fff | ths | #define CP0C2_SU 12 |
357 | 7a387fff | ths | #define CP0C2_SS 8 |
358 | 7a387fff | ths | #define CP0C2_SL 4 |
359 | 7a387fff | ths | #define CP0C2_SA 0 |
360 | 9c2149c8 | ths | int32_t CP0_Config3; |
361 | 7a387fff | ths | #define CP0C3_M 31 |
362 | bbfa8f72 | Nathan Froyd | #define CP0C3_ISA_ON_EXC 16 |
363 | 7a387fff | ths | #define CP0C3_DSPP 10 |
364 | 7a387fff | ths | #define CP0C3_LPA 7 |
365 | 7a387fff | ths | #define CP0C3_VEIC 6 |
366 | 7a387fff | ths | #define CP0C3_VInt 5 |
367 | 7a387fff | ths | #define CP0C3_SP 4 |
368 | 7a387fff | ths | #define CP0C3_MT 2 |
369 | 7a387fff | ths | #define CP0C3_SM 1 |
370 | 7a387fff | ths | #define CP0C3_TL 0 |
371 | e397ee33 | ths | int32_t CP0_Config6; |
372 | e397ee33 | ths | int32_t CP0_Config7; |
373 | ead9360e | ths | /* XXX: Maybe make LLAddr per-TC? */
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374 | 5499b6ff | Aurelien Jarno | target_ulong lladdr; |
375 | 590bc601 | Paul Brook | target_ulong llval; |
376 | 590bc601 | Paul Brook | target_ulong llnewval; |
377 | 590bc601 | Paul Brook | target_ulong llreg; |
378 | 2a6e32dd | Aurelien Jarno | target_ulong CP0_LLAddr_rw_bitmask; |
379 | 2a6e32dd | Aurelien Jarno | int CP0_LLAddr_shift;
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380 | fd88b6ab | ths | target_ulong CP0_WatchLo[8];
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381 | fd88b6ab | ths | int32_t CP0_WatchHi[8];
|
382 | 9c2149c8 | ths | target_ulong CP0_XContext; |
383 | 9c2149c8 | ths | int32_t CP0_Framemask; |
384 | 9c2149c8 | ths | int32_t CP0_Debug; |
385 | ead9360e | ths | #define CP0DB_DBD 31 |
386 | 6af0bf9c | bellard | #define CP0DB_DM 30 |
387 | 6af0bf9c | bellard | #define CP0DB_LSNM 28 |
388 | 6af0bf9c | bellard | #define CP0DB_Doze 27 |
389 | 6af0bf9c | bellard | #define CP0DB_Halt 26 |
390 | 6af0bf9c | bellard | #define CP0DB_CNT 25 |
391 | 6af0bf9c | bellard | #define CP0DB_IBEP 24 |
392 | 6af0bf9c | bellard | #define CP0DB_DBEP 21 |
393 | 6af0bf9c | bellard | #define CP0DB_IEXI 20 |
394 | 6af0bf9c | bellard | #define CP0DB_VER 15 |
395 | 6af0bf9c | bellard | #define CP0DB_DEC 10 |
396 | 6af0bf9c | bellard | #define CP0DB_SSt 8 |
397 | 6af0bf9c | bellard | #define CP0DB_DINT 5 |
398 | 6af0bf9c | bellard | #define CP0DB_DIB 4 |
399 | 6af0bf9c | bellard | #define CP0DB_DDBS 3 |
400 | 6af0bf9c | bellard | #define CP0DB_DDBL 2 |
401 | 6af0bf9c | bellard | #define CP0DB_DBp 1 |
402 | 6af0bf9c | bellard | #define CP0DB_DSS 0 |
403 | c570fd16 | ths | target_ulong CP0_DEPC; |
404 | 9c2149c8 | ths | int32_t CP0_Performance0; |
405 | 9c2149c8 | ths | int32_t CP0_TagLo; |
406 | 9c2149c8 | ths | int32_t CP0_DataLo; |
407 | 9c2149c8 | ths | int32_t CP0_TagHi; |
408 | 9c2149c8 | ths | int32_t CP0_DataHi; |
409 | c570fd16 | ths | target_ulong CP0_ErrorEPC; |
410 | 9c2149c8 | ths | int32_t CP0_DESAVE; |
411 | b5dc7732 | ths | /* We waste some space so we can handle shadow registers like TCs. */
|
412 | b5dc7732 | ths | TCState tcs[MIPS_SHADOW_SET_MAX]; |
413 | f01be154 | ths | CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
414 | 5cbdb3a3 | Stefan Weil | /* QEMU */
|
415 | 6af0bf9c | bellard | int error_code;
|
416 | 6af0bf9c | bellard | uint32_t hflags; /* CPU State */
|
417 | 6af0bf9c | bellard | /* TMASK defines different execution modes */
|
418 | 853c3240 | Jia Liu | #define MIPS_HFLAG_TMASK 0xC07FF |
419 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ |
420 | 623a930e | ths | /* The KSU flags must be the lowest bits in hflags. The flag order
|
421 | 623a930e | ths | must be the same as defined for CP0 Status. This allows to use
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422 | 623a930e | ths | the bits as the value of mmu_idx. */
|
423 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ |
424 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ |
425 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ |
426 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ |
427 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ |
428 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ |
429 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ |
430 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ |
431 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ |
432 | b8aa4598 | ths | /* True if the MIPS IV COP1X instructions can be used. This also
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433 | b8aa4598 | ths | controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
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434 | b8aa4598 | ths | and RSQRT.D. */
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435 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ |
436 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ |
437 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */ |
438 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ |
439 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_M16_SHIFT 10 |
440 | 4ad40f36 | bellard | /* If translation is interrupted between the branch instruction and
|
441 | 4ad40f36 | bellard | * the delay slot, record what type of branch it is so that we can
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442 | 4ad40f36 | bellard | * resume translation properly. It might be possible to reduce
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443 | 4ad40f36 | bellard | * this from three bits to two. */
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444 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_BMASK_BASE 0x03800 |
445 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ |
446 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ |
447 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ |
448 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ |
449 | 79ef2c4c | Nathan Froyd | /* Extra flags about the current pending branch. */
|
450 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_BMASK_EXT 0x3C000 |
451 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ |
452 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ |
453 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ |
454 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */ |
455 | 79ef2c4c | Nathan Froyd | #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
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456 | 853c3240 | Jia Liu | /* MIPS DSP resources access. */
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457 | 853c3240 | Jia Liu | #define MIPS_HFLAG_DSP 0x40000 /* Enable access to MIPS DSP resources. */ |
458 | 853c3240 | Jia Liu | #define MIPS_HFLAG_DSPR2 0x80000 /* Enable access to MIPS DSPR2 resources. */ |
459 | 6af0bf9c | bellard | target_ulong btarget; /* Jump / branch target */
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460 | 1ba74fb8 | aurel32 | target_ulong bcond; /* Branch condition (if needed) */
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461 | a316d335 | bellard | |
462 | 7a387fff | ths | int SYNCI_Step; /* Address step size for SYNCI */ |
463 | 7a387fff | ths | int CCRes; /* Cycle count resolution/divisor */ |
464 | ead9360e | ths | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
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465 | ead9360e | ths | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
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466 | e189e748 | ths | int insn_flags; /* Supported instruction set */ |
467 | 7a387fff | ths | |
468 | 0eaef5aa | ths | target_ulong tls_value; /* For usermode emulation */
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469 | 6f5b89a0 | ths | |
470 | a316d335 | bellard | CPU_COMMON |
471 | 6ae81775 | ths | |
472 | 51cc2e78 | Blue Swirl | CPUMIPSMVPContext *mvp; |
473 | 3c7b48b7 | Paul Brook | #if !defined(CONFIG_USER_ONLY)
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474 | 51cc2e78 | Blue Swirl | CPUMIPSTLBContext *tlb; |
475 | 3c7b48b7 | Paul Brook | #endif
|
476 | 51cc2e78 | Blue Swirl | |
477 | c227f099 | Anthony Liguori | const mips_def_t *cpu_model;
|
478 | 33ac7f16 | ths | void *irq[8]; |
479 | 6ae81775 | ths | struct QEMUTimer *timer; /* Internal timer */ |
480 | 6af0bf9c | bellard | }; |
481 | 6af0bf9c | bellard | |
482 | 0f71a709 | Andreas Färber | #include "cpu-qom.h" |
483 | 0f71a709 | Andreas Färber | |
484 | 3c7b48b7 | Paul Brook | #if !defined(CONFIG_USER_ONLY)
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485 | a8170e5e | Avi Kivity | int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
486 | 29929e34 | ths | target_ulong address, int rw, int access_type); |
487 | a8170e5e | Avi Kivity | int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
488 | 29929e34 | ths | target_ulong address, int rw, int access_type); |
489 | a8170e5e | Avi Kivity | int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
490 | 29929e34 | ths | target_ulong address, int rw, int access_type); |
491 | 895c2d04 | Blue Swirl | void r4k_helper_tlbwi(CPUMIPSState *env);
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492 | 895c2d04 | Blue Swirl | void r4k_helper_tlbwr(CPUMIPSState *env);
|
493 | 895c2d04 | Blue Swirl | void r4k_helper_tlbp(CPUMIPSState *env);
|
494 | 895c2d04 | Blue Swirl | void r4k_helper_tlbr(CPUMIPSState *env);
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495 | 33d68b5f | ths | |
496 | a8170e5e | Avi Kivity | void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
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497 | b14ef7c9 | Blue Swirl | int is_write, int is_exec, int unused, int size); |
498 | 3c7b48b7 | Paul Brook | #endif
|
499 | 3c7b48b7 | Paul Brook | |
500 | 9a78eead | Stefan Weil | void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
|
501 | 647de6ca | ths | |
502 | 9467d44c | ths | #define cpu_exec cpu_mips_exec
|
503 | 9467d44c | ths | #define cpu_gen_code cpu_mips_gen_code
|
504 | 9467d44c | ths | #define cpu_signal_handler cpu_mips_signal_handler
|
505 | c732abe2 | j_mayer | #define cpu_list mips_cpu_list
|
506 | 9467d44c | ths | |
507 | b3c7724c | pbrook | #define CPU_SAVE_VERSION 3 |
508 | b3c7724c | pbrook | |
509 | 623a930e | ths | /* MMU modes definitions. We carefully match the indices with our
|
510 | 623a930e | ths | hflags layout. */
|
511 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
|
512 | 623a930e | ths | #define MMU_MODE1_SUFFIX _super
|
513 | 623a930e | ths | #define MMU_MODE2_SUFFIX _user
|
514 | 623a930e | ths | #define MMU_USER_IDX 2 |
515 | 7db13fae | Andreas Färber | static inline int cpu_mmu_index (CPUMIPSState *env) |
516 | 6ebbf390 | j_mayer | { |
517 | 623a930e | ths | return env->hflags & MIPS_HFLAG_KSU;
|
518 | 6ebbf390 | j_mayer | } |
519 | 6ebbf390 | j_mayer | |
520 | 7db13fae | Andreas Färber | static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp) |
521 | 6e68e076 | pbrook | { |
522 | f8ed7070 | pbrook | if (newsp)
|
523 | b5dc7732 | ths | env->active_tc.gpr[29] = newsp;
|
524 | b5dc7732 | ths | env->active_tc.gpr[7] = 0; |
525 | b5dc7732 | ths | env->active_tc.gpr[2] = 0; |
526 | 6e68e076 | pbrook | } |
527 | 6e68e076 | pbrook | |
528 | 7db13fae | Andreas Färber | static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) |
529 | 138afb02 | Edgar E. Iglesias | { |
530 | 138afb02 | Edgar E. Iglesias | int32_t pending; |
531 | 138afb02 | Edgar E. Iglesias | int32_t status; |
532 | 138afb02 | Edgar E. Iglesias | int r;
|
533 | 138afb02 | Edgar E. Iglesias | |
534 | 4cdc1cd1 | Aurelien Jarno | if (!(env->CP0_Status & (1 << CP0St_IE)) || |
535 | 4cdc1cd1 | Aurelien Jarno | (env->CP0_Status & (1 << CP0St_EXL)) ||
|
536 | 4cdc1cd1 | Aurelien Jarno | (env->CP0_Status & (1 << CP0St_ERL)) ||
|
537 | 344eecf6 | Edgar E. Iglesias | /* Note that the TCStatus IXMT field is initialized to zero,
|
538 | 344eecf6 | Edgar E. Iglesias | and only MT capable cores can set it to one. So we don't
|
539 | 344eecf6 | Edgar E. Iglesias | need to check for MT capabilities here. */
|
540 | 344eecf6 | Edgar E. Iglesias | (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
|
541 | 4cdc1cd1 | Aurelien Jarno | (env->hflags & MIPS_HFLAG_DM)) { |
542 | 4cdc1cd1 | Aurelien Jarno | /* Interrupts are disabled */
|
543 | 4cdc1cd1 | Aurelien Jarno | return 0; |
544 | 4cdc1cd1 | Aurelien Jarno | } |
545 | 4cdc1cd1 | Aurelien Jarno | |
546 | 138afb02 | Edgar E. Iglesias | pending = env->CP0_Cause & CP0Ca_IP_mask; |
547 | 138afb02 | Edgar E. Iglesias | status = env->CP0_Status & CP0Ca_IP_mask; |
548 | 138afb02 | Edgar E. Iglesias | |
549 | 138afb02 | Edgar E. Iglesias | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { |
550 | 138afb02 | Edgar E. Iglesias | /* A MIPS configured with a vectorizing external interrupt controller
|
551 | 138afb02 | Edgar E. Iglesias | will feed a vector into the Cause pending lines. The core treats
|
552 | 138afb02 | Edgar E. Iglesias | the status lines as a vector level, not as indiviual masks. */
|
553 | 138afb02 | Edgar E. Iglesias | r = pending > status; |
554 | 138afb02 | Edgar E. Iglesias | } else {
|
555 | 138afb02 | Edgar E. Iglesias | /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
|
556 | 138afb02 | Edgar E. Iglesias | treats the pending lines as individual interrupt lines, the status
|
557 | 138afb02 | Edgar E. Iglesias | lines are individual masks. */
|
558 | 138afb02 | Edgar E. Iglesias | r = pending & status; |
559 | 138afb02 | Edgar E. Iglesias | } |
560 | 138afb02 | Edgar E. Iglesias | return r;
|
561 | 138afb02 | Edgar E. Iglesias | } |
562 | 138afb02 | Edgar E. Iglesias | |
563 | 6af0bf9c | bellard | #include "cpu-all.h" |
564 | 6af0bf9c | bellard | |
565 | 6af0bf9c | bellard | /* Memory access type :
|
566 | 6af0bf9c | bellard | * may be needed for precise access rights control and precise exceptions.
|
567 | 6af0bf9c | bellard | */
|
568 | 6af0bf9c | bellard | enum {
|
569 | 6af0bf9c | bellard | /* 1 bit to define user level / supervisor access */
|
570 | 6af0bf9c | bellard | ACCESS_USER = 0x00,
|
571 | 6af0bf9c | bellard | ACCESS_SUPER = 0x01,
|
572 | 6af0bf9c | bellard | /* 1 bit to indicate direction */
|
573 | 6af0bf9c | bellard | ACCESS_STORE = 0x02,
|
574 | 6af0bf9c | bellard | /* Type of instruction that generated the access */
|
575 | 6af0bf9c | bellard | ACCESS_CODE = 0x10, /* Code fetch access */ |
576 | 6af0bf9c | bellard | ACCESS_INT = 0x20, /* Integer load/store access */ |
577 | 6af0bf9c | bellard | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
578 | 6af0bf9c | bellard | }; |
579 | 6af0bf9c | bellard | |
580 | 6af0bf9c | bellard | /* Exceptions */
|
581 | 6af0bf9c | bellard | enum {
|
582 | 6af0bf9c | bellard | EXCP_NONE = -1,
|
583 | 6af0bf9c | bellard | EXCP_RESET = 0,
|
584 | 6af0bf9c | bellard | EXCP_SRESET, |
585 | 6af0bf9c | bellard | EXCP_DSS, |
586 | 6af0bf9c | bellard | EXCP_DINT, |
587 | 14e51cc7 | ths | EXCP_DDBL, |
588 | 14e51cc7 | ths | EXCP_DDBS, |
589 | 6af0bf9c | bellard | EXCP_NMI, |
590 | 6af0bf9c | bellard | EXCP_MCHECK, |
591 | 14e51cc7 | ths | EXCP_EXT_INTERRUPT, /* 8 */
|
592 | 6af0bf9c | bellard | EXCP_DFWATCH, |
593 | 14e51cc7 | ths | EXCP_DIB, |
594 | 6af0bf9c | bellard | EXCP_IWATCH, |
595 | 6af0bf9c | bellard | EXCP_AdEL, |
596 | 6af0bf9c | bellard | EXCP_AdES, |
597 | 6af0bf9c | bellard | EXCP_TLBF, |
598 | 6af0bf9c | bellard | EXCP_IBE, |
599 | 14e51cc7 | ths | EXCP_DBp, /* 16 */
|
600 | 6af0bf9c | bellard | EXCP_SYSCALL, |
601 | 14e51cc7 | ths | EXCP_BREAK, |
602 | 4ad40f36 | bellard | EXCP_CpU, |
603 | 6af0bf9c | bellard | EXCP_RI, |
604 | 6af0bf9c | bellard | EXCP_OVERFLOW, |
605 | 6af0bf9c | bellard | EXCP_TRAP, |
606 | 5a5012ec | ths | EXCP_FPE, |
607 | 14e51cc7 | ths | EXCP_DWATCH, /* 24 */
|
608 | 6af0bf9c | bellard | EXCP_LTLBL, |
609 | 6af0bf9c | bellard | EXCP_TLBL, |
610 | 6af0bf9c | bellard | EXCP_TLBS, |
611 | 6af0bf9c | bellard | EXCP_DBE, |
612 | ead9360e | ths | EXCP_THREAD, |
613 | 14e51cc7 | ths | EXCP_MDMX, |
614 | 14e51cc7 | ths | EXCP_C2E, |
615 | 14e51cc7 | ths | EXCP_CACHE, /* 32 */
|
616 | 853c3240 | Jia Liu | EXCP_DSPDIS, |
617 | 14e51cc7 | ths | |
618 | 853c3240 | Jia Liu | EXCP_LAST = EXCP_DSPDIS, |
619 | 6af0bf9c | bellard | }; |
620 | 590bc601 | Paul Brook | /* Dummy exception for conditional stores. */
|
621 | 590bc601 | Paul Brook | #define EXCP_SC 0x100 |
622 | 6af0bf9c | bellard | |
623 | f249412c | Edgar E. Iglesias | /*
|
624 | f249412c | Edgar E. Iglesias | * This is an interrnally generated WAKE request line.
|
625 | f249412c | Edgar E. Iglesias | * It is driven by the CPU itself. Raised when the MT
|
626 | f249412c | Edgar E. Iglesias | * block wants to wake a VPE from an inactive state and
|
627 | f249412c | Edgar E. Iglesias | * cleared when VPE goes from active to inactive.
|
628 | f249412c | Edgar E. Iglesias | */
|
629 | f249412c | Edgar E. Iglesias | #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
|
630 | f249412c | Edgar E. Iglesias | |
631 | 6af0bf9c | bellard | int cpu_mips_exec(CPUMIPSState *s);
|
632 | 30bf942d | Andreas Färber | MIPSCPU *cpu_mips_init(const char *cpu_model); |
633 | 388bb21a | ths | int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
634 | 6af0bf9c | bellard | |
635 | 30bf942d | Andreas Färber | static inline CPUMIPSState *cpu_init(const char *cpu_model) |
636 | 30bf942d | Andreas Färber | { |
637 | 30bf942d | Andreas Färber | MIPSCPU *cpu = cpu_mips_init(cpu_model); |
638 | 30bf942d | Andreas Färber | if (cpu == NULL) { |
639 | 30bf942d | Andreas Färber | return NULL; |
640 | 30bf942d | Andreas Färber | } |
641 | 30bf942d | Andreas Färber | return &cpu->env;
|
642 | 30bf942d | Andreas Färber | } |
643 | 30bf942d | Andreas Färber | |
644 | b7e516ce | Andreas Färber | /* TODO QOM'ify CPU reset and remove */
|
645 | b7e516ce | Andreas Färber | void cpu_state_reset(CPUMIPSState *s);
|
646 | b7e516ce | Andreas Färber | |
647 | f9480ffc | ths | /* mips_timer.c */
|
648 | 7db13fae | Andreas Färber | uint32_t cpu_mips_get_random (CPUMIPSState *env); |
649 | 7db13fae | Andreas Färber | uint32_t cpu_mips_get_count (CPUMIPSState *env); |
650 | 7db13fae | Andreas Färber | void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
|
651 | 7db13fae | Andreas Färber | void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
|
652 | 7db13fae | Andreas Färber | void cpu_mips_start_count(CPUMIPSState *env);
|
653 | 7db13fae | Andreas Färber | void cpu_mips_stop_count(CPUMIPSState *env);
|
654 | f9480ffc | ths | |
655 | 5dc5d9f0 | Aurelien Jarno | /* mips_int.c */
|
656 | 7db13fae | Andreas Färber | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); |
657 | 5dc5d9f0 | Aurelien Jarno | |
658 | f9480ffc | ths | /* helper.c */
|
659 | 7db13fae | Andreas Färber | int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, |
660 | 97b348e7 | Blue Swirl | int mmu_idx);
|
661 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
|
662 | 7db13fae | Andreas Färber | void do_interrupt (CPUMIPSState *env);
|
663 | 3c7b48b7 | Paul Brook | #if !defined(CONFIG_USER_ONLY)
|
664 | 7db13fae | Andreas Färber | void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); |
665 | a8170e5e | Avi Kivity | hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, |
666 | c36bbb28 | Aurelien Jarno | int rw);
|
667 | 3c7b48b7 | Paul Brook | #endif
|
668 | f9480ffc | ths | |
669 | 7db13fae | Andreas Färber | static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, |
670 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
|
671 | 6b917547 | aliguori | { |
672 | 6b917547 | aliguori | *pc = env->active_tc.PC; |
673 | 6b917547 | aliguori | *cs_base = 0;
|
674 | 6b917547 | aliguori | *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
675 | 6b917547 | aliguori | } |
676 | 6b917547 | aliguori | |
677 | 7db13fae | Andreas Färber | static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls) |
678 | ff867ddc | Paul Brook | { |
679 | ff867ddc | Paul Brook | env->tls_value = newtls; |
680 | ff867ddc | Paul Brook | } |
681 | ff867ddc | Paul Brook | |
682 | 7db13fae | Andreas Färber | static inline int mips_vpe_active(CPUMIPSState *env) |
683 | f249412c | Edgar E. Iglesias | { |
684 | f249412c | Edgar E. Iglesias | int active = 1; |
685 | f249412c | Edgar E. Iglesias | |
686 | f249412c | Edgar E. Iglesias | /* Check that the VPE is enabled. */
|
687 | f249412c | Edgar E. Iglesias | if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { |
688 | f249412c | Edgar E. Iglesias | active = 0;
|
689 | f249412c | Edgar E. Iglesias | } |
690 | 4abf79a4 | Dong Xu Wang | /* Check that the VPE is activated. */
|
691 | f249412c | Edgar E. Iglesias | if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { |
692 | f249412c | Edgar E. Iglesias | active = 0;
|
693 | f249412c | Edgar E. Iglesias | } |
694 | f249412c | Edgar E. Iglesias | |
695 | f249412c | Edgar E. Iglesias | /* Now verify that there are active thread contexts in the VPE.
|
696 | f249412c | Edgar E. Iglesias | |
697 | f249412c | Edgar E. Iglesias | This assumes the CPU model will internally reschedule threads
|
698 | f249412c | Edgar E. Iglesias | if the active one goes to sleep. If there are no threads available
|
699 | f249412c | Edgar E. Iglesias | the active one will be in a sleeping state, and we can turn off
|
700 | f249412c | Edgar E. Iglesias | the entire VPE. */
|
701 | f249412c | Edgar E. Iglesias | if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { |
702 | f249412c | Edgar E. Iglesias | /* TC is not activated. */
|
703 | f249412c | Edgar E. Iglesias | active = 0;
|
704 | f249412c | Edgar E. Iglesias | } |
705 | f249412c | Edgar E. Iglesias | if (env->active_tc.CP0_TCHalt & 1) { |
706 | f249412c | Edgar E. Iglesias | /* TC is in halt state. */
|
707 | f249412c | Edgar E. Iglesias | active = 0;
|
708 | f249412c | Edgar E. Iglesias | } |
709 | f249412c | Edgar E. Iglesias | |
710 | f249412c | Edgar E. Iglesias | return active;
|
711 | f249412c | Edgar E. Iglesias | } |
712 | f249412c | Edgar E. Iglesias | |
713 | 3993c6bd | Andreas Färber | static inline bool cpu_has_work(CPUState *cpu) |
714 | f081c76c | Blue Swirl | { |
715 | 3993c6bd | Andreas Färber | CPUMIPSState *env = &MIPS_CPU(cpu)->env; |
716 | 3993c6bd | Andreas Färber | bool has_work = false; |
717 | f081c76c | Blue Swirl | |
718 | f081c76c | Blue Swirl | /* It is implementation dependent if non-enabled interrupts
|
719 | f081c76c | Blue Swirl | wake-up the CPU, however most of the implementations only
|
720 | f081c76c | Blue Swirl | check for interrupts that can be taken. */
|
721 | f081c76c | Blue Swirl | if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
|
722 | f081c76c | Blue Swirl | cpu_mips_hw_interrupts_pending(env)) { |
723 | 3993c6bd | Andreas Färber | has_work = true;
|
724 | f081c76c | Blue Swirl | } |
725 | f081c76c | Blue Swirl | |
726 | f249412c | Edgar E. Iglesias | /* MIPS-MT has the ability to halt the CPU. */
|
727 | f249412c | Edgar E. Iglesias | if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
728 | f249412c | Edgar E. Iglesias | /* The QEMU model will issue an _WAKE request whenever the CPUs
|
729 | f249412c | Edgar E. Iglesias | should be woken up. */
|
730 | f249412c | Edgar E. Iglesias | if (env->interrupt_request & CPU_INTERRUPT_WAKE) {
|
731 | 3993c6bd | Andreas Färber | has_work = true;
|
732 | f249412c | Edgar E. Iglesias | } |
733 | f249412c | Edgar E. Iglesias | |
734 | f249412c | Edgar E. Iglesias | if (!mips_vpe_active(env)) {
|
735 | 3993c6bd | Andreas Färber | has_work = false;
|
736 | f249412c | Edgar E. Iglesias | } |
737 | f249412c | Edgar E. Iglesias | } |
738 | f081c76c | Blue Swirl | return has_work;
|
739 | f081c76c | Blue Swirl | } |
740 | f081c76c | Blue Swirl | |
741 | f081c76c | Blue Swirl | #include "exec-all.h" |
742 | f081c76c | Blue Swirl | |
743 | 7db13fae | Andreas Färber | static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb) |
744 | f081c76c | Blue Swirl | { |
745 | f081c76c | Blue Swirl | env->active_tc.PC = tb->pc; |
746 | f081c76c | Blue Swirl | env->hflags &= ~MIPS_HFLAG_BMASK; |
747 | f081c76c | Blue Swirl | env->hflags |= tb->flags & MIPS_HFLAG_BMASK; |
748 | f081c76c | Blue Swirl | } |
749 | f081c76c | Blue Swirl | |
750 | 03e6e501 | Maciej W. Rozycki | static inline void compute_hflags(CPUMIPSState *env) |
751 | 03e6e501 | Maciej W. Rozycki | { |
752 | 03e6e501 | Maciej W. Rozycki | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
753 | 03e6e501 | Maciej W. Rozycki | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
754 | 03e6e501 | Maciej W. Rozycki | MIPS_HFLAG_UX); |
755 | 03e6e501 | Maciej W. Rozycki | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
756 | 03e6e501 | Maciej W. Rozycki | !(env->CP0_Status & (1 << CP0St_ERL)) &&
|
757 | 03e6e501 | Maciej W. Rozycki | !(env->hflags & MIPS_HFLAG_DM)) { |
758 | 03e6e501 | Maciej W. Rozycki | env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
759 | 03e6e501 | Maciej W. Rozycki | } |
760 | 03e6e501 | Maciej W. Rozycki | #if defined(TARGET_MIPS64)
|
761 | 03e6e501 | Maciej W. Rozycki | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
|
762 | 03e6e501 | Maciej W. Rozycki | (env->CP0_Status & (1 << CP0St_PX)) ||
|
763 | 03e6e501 | Maciej W. Rozycki | (env->CP0_Status & (1 << CP0St_UX))) {
|
764 | 03e6e501 | Maciej W. Rozycki | env->hflags |= MIPS_HFLAG_64; |
765 | 03e6e501 | Maciej W. Rozycki | } |
766 | 03e6e501 | Maciej W. Rozycki | if (env->CP0_Status & (1 << CP0St_UX)) { |
767 | 03e6e501 | Maciej W. Rozycki | env->hflags |= MIPS_HFLAG_UX; |
768 | 03e6e501 | Maciej W. Rozycki | } |
769 | 03e6e501 | Maciej W. Rozycki | #endif
|
770 | 03e6e501 | Maciej W. Rozycki | if ((env->CP0_Status & (1 << CP0St_CU0)) || |
771 | 03e6e501 | Maciej W. Rozycki | !(env->hflags & MIPS_HFLAG_KSU)) { |
772 | 03e6e501 | Maciej W. Rozycki | env->hflags |= MIPS_HFLAG_CP0; |
773 | 03e6e501 | Maciej W. Rozycki | } |
774 | 03e6e501 | Maciej W. Rozycki | if (env->CP0_Status & (1 << CP0St_CU1)) { |
775 | 03e6e501 | Maciej W. Rozycki | env->hflags |= MIPS_HFLAG_FPU; |
776 | 03e6e501 | Maciej W. Rozycki | } |
777 | 03e6e501 | Maciej W. Rozycki | if (env->CP0_Status & (1 << CP0St_FR)) { |
778 | 03e6e501 | Maciej W. Rozycki | env->hflags |= MIPS_HFLAG_F64; |
779 | 03e6e501 | Maciej W. Rozycki | } |
780 | 853c3240 | Jia Liu | if (env->insn_flags & ASE_DSPR2) {
|
781 | 853c3240 | Jia Liu | /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
|
782 | 853c3240 | Jia Liu | so enable to access DSPR2 resources. */
|
783 | 853c3240 | Jia Liu | if (env->CP0_Status & (1 << CP0St_MX)) { |
784 | 853c3240 | Jia Liu | env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; |
785 | 853c3240 | Jia Liu | } |
786 | 853c3240 | Jia Liu | |
787 | 853c3240 | Jia Liu | } else if (env->insn_flags & ASE_DSP) { |
788 | 853c3240 | Jia Liu | /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
|
789 | 853c3240 | Jia Liu | so enable to access DSP resources. */
|
790 | 853c3240 | Jia Liu | if (env->CP0_Status & (1 << CP0St_MX)) { |
791 | 853c3240 | Jia Liu | env->hflags |= MIPS_HFLAG_DSP; |
792 | 853c3240 | Jia Liu | } |
793 | 853c3240 | Jia Liu | |
794 | 853c3240 | Jia Liu | } |
795 | 03e6e501 | Maciej W. Rozycki | if (env->insn_flags & ISA_MIPS32R2) {
|
796 | 03e6e501 | Maciej W. Rozycki | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { |
797 | 03e6e501 | Maciej W. Rozycki | env->hflags |= MIPS_HFLAG_COP1X; |
798 | 03e6e501 | Maciej W. Rozycki | } |
799 | 03e6e501 | Maciej W. Rozycki | } else if (env->insn_flags & ISA_MIPS32) { |
800 | 03e6e501 | Maciej W. Rozycki | if (env->hflags & MIPS_HFLAG_64) {
|
801 | 03e6e501 | Maciej W. Rozycki | env->hflags |= MIPS_HFLAG_COP1X; |
802 | 03e6e501 | Maciej W. Rozycki | } |
803 | 03e6e501 | Maciej W. Rozycki | } else if (env->insn_flags & ISA_MIPS4) { |
804 | 03e6e501 | Maciej W. Rozycki | /* All supported MIPS IV CPUs use the XX (CU3) to enable
|
805 | 03e6e501 | Maciej W. Rozycki | and disable the MIPS IV extensions to the MIPS III ISA.
|
806 | 03e6e501 | Maciej W. Rozycki | Some other MIPS IV CPUs ignore the bit, so the check here
|
807 | 03e6e501 | Maciej W. Rozycki | would be too restrictive for them. */
|
808 | 03e6e501 | Maciej W. Rozycki | if (env->CP0_Status & (1 << CP0St_CU3)) { |
809 | 03e6e501 | Maciej W. Rozycki | env->hflags |= MIPS_HFLAG_COP1X; |
810 | 03e6e501 | Maciej W. Rozycki | } |
811 | 03e6e501 | Maciej W. Rozycki | } |
812 | 03e6e501 | Maciej W. Rozycki | } |
813 | 03e6e501 | Maciej W. Rozycki | |
814 | 6af0bf9c | bellard | #endif /* !defined (__MIPS_CPU_H__) */ |