Revision 1cdb9c3d target-ppc/op_helper.c
b/target-ppc/op_helper.c | ||
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922 | 922 |
} |
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#endif |
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925 |
#ifdef CONFIG_SOFTFLOAT
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#if USE_PRECISE_EMULATION
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void do_fadd (void) |
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{ |
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if (unlikely(float64_is_signaling_nan(FT0) || |
... | ... | |
989 | 989 |
FT0 = float64_div(FT0, FT1, &env->fp_status); |
990 | 990 |
} |
991 | 991 |
} |
992 |
#endif /* CONFIG_SOFTFLOAT */
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#endif /* USE_PRECISE_EMULATION */
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994 | 994 |
void do_fctiw (void) |
995 | 995 |
{ |
... | ... | |
1003 | 1003 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
1004 | 1004 |
} else { |
1005 | 1005 |
p.ll = float64_to_int32(FT0, &env->fp_status); |
1006 |
#ifdef CONFIG_SOFTFLOAT
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1006 |
#if USE_PRECISE_EMULATION
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1007 | 1007 |
/* XXX: higher bits are not supposed to be significant. |
1008 | 1008 |
* to make tests easier, return the same as a real PowerPC 750 |
1009 | 1009 |
*/ |
... | ... | |
1025 | 1025 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
1026 | 1026 |
} else { |
1027 | 1027 |
p.ll = float64_to_int32_round_to_zero(FT0, &env->fp_status); |
1028 |
#ifdef CONFIG_SOFTFLOAT
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1028 |
#if USE_PRECISE_EMULATION
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1029 | 1029 |
/* XXX: higher bits are not supposed to be significant. |
1030 | 1030 |
* to make tests easier, return the same as a real PowerPC 750 |
1031 | 1031 |
*/ |
... | ... | |
1114 | 1114 |
do_fri(float_round_down); |
1115 | 1115 |
} |
1116 | 1116 |
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#ifdef CONFIG_SOFTFLOAT
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1117 |
#if USE_PRECISE_EMULATION
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1118 | 1118 |
void do_fmadd (void) |
1119 | 1119 |
{ |
1120 | 1120 |
if (unlikely(float64_is_signaling_nan(FT0) || |
... | ... | |
1164 | 1164 |
#endif |
1165 | 1165 |
} |
1166 | 1166 |
} |
1167 |
#endif /* CONFIG_SOFTFLOAT */
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1167 |
#endif /* USE_PRECISE_EMULATION */
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1168 | 1168 |
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void do_fnmadd (void) |
1170 | 1170 |
{ |
... | ... | |
1174 | 1174 |
/* sNaN operation */ |
1175 | 1175 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1176 | 1176 |
} else { |
1177 |
#ifdef CONFIG_SOFTFLOAT
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1177 |
#if USE_PRECISE_EMULATION
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1178 | 1178 |
#ifdef FLOAT128 |
1179 | 1179 |
/* This is the way the PowerPC specification defines it */ |
1180 | 1180 |
float128 ft0_128, ft1_128; |
... | ... | |
1206 | 1206 |
/* sNaN operation */ |
1207 | 1207 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1208 | 1208 |
} else { |
1209 |
#ifdef CONFIG_SOFTFLOAT
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1209 |
#if USE_PRECISE_EMULATION
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1210 | 1210 |
#ifdef FLOAT128 |
1211 | 1211 |
/* This is the way the PowerPC specification defines it */ |
1212 | 1212 |
float128 ft0_128, ft1_128; |
... | ... | |
1230 | 1230 |
} |
1231 | 1231 |
} |
1232 | 1232 |
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1233 |
#ifdef CONFIG_SOFTFLOAT
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1233 |
#if USE_PRECISE_EMULATION
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1234 | 1234 |
void do_frsp (void) |
1235 | 1235 |
{ |
1236 | 1236 |
if (unlikely(float64_is_signaling_nan(FT0))) { |
... | ... | |
1240 | 1240 |
FT0 = float64_to_float32(FT0, &env->fp_status); |
1241 | 1241 |
} |
1242 | 1242 |
} |
1243 |
#endif /* CONFIG_SOFTFLOAT */
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1243 |
#endif /* USE_PRECISE_EMULATION */
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1244 | 1244 |
|
1245 | 1245 |
void do_fsqrt (void) |
1246 | 1246 |
{ |
... | ... | |
1295 | 1295 |
/* Zero reciprocal */ |
1296 | 1296 |
float_zero_divide_excp(); |
1297 | 1297 |
} else if (likely(isnormal(FT0))) { |
1298 |
#ifdef CONFIG_SOFTFLOAT
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1298 |
#if USE_PRECISE_EMULATION
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1299 | 1299 |
FT0 = float64_div(1.0, FT0, &env->fp_status); |
1300 | 1300 |
FT0 = float64_to_float32(FT0, &env->fp_status); |
1301 | 1301 |
#else |
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