Revision 1d01299d target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 3836 | 3836 |
break; |
| 3837 | 3837 |
case 0x051: /* VIS I fpadd16s */ |
| 3838 | 3838 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3839 |
gen_op_load_fpr_FT0(rs1); |
|
| 3840 |
gen_op_load_fpr_FT1(rs2); |
|
| 3841 |
tcg_gen_helper_0_0(helper_fpadd16s); |
|
| 3842 |
gen_op_store_FT0_fpr(rd); |
|
| 3839 |
tcg_gen_helper_1_2(helper_fpadd16s, cpu_fpr[rd], |
|
| 3840 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 3843 | 3841 |
break; |
| 3844 | 3842 |
case 0x052: /* VIS I fpadd32 */ |
| 3845 | 3843 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3850 | 3848 |
break; |
| 3851 | 3849 |
case 0x053: /* VIS I fpadd32s */ |
| 3852 | 3850 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3853 |
gen_op_load_fpr_FT0(rs1); |
|
| 3854 |
gen_op_load_fpr_FT1(rs2); |
|
| 3855 |
tcg_gen_helper_0_0(helper_fpadd32s); |
|
| 3856 |
gen_op_store_FT0_fpr(rd); |
|
| 3851 |
tcg_gen_helper_1_2(helper_fpadd32s, cpu_fpr[rd], |
|
| 3852 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 3857 | 3853 |
break; |
| 3858 | 3854 |
case 0x054: /* VIS I fpsub16 */ |
| 3859 | 3855 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3864 | 3860 |
break; |
| 3865 | 3861 |
case 0x055: /* VIS I fpsub16s */ |
| 3866 | 3862 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3867 |
gen_op_load_fpr_FT0(rs1); |
|
| 3868 |
gen_op_load_fpr_FT1(rs2); |
|
| 3869 |
tcg_gen_helper_0_0(helper_fpsub16s); |
|
| 3870 |
gen_op_store_FT0_fpr(rd); |
|
| 3863 |
tcg_gen_helper_1_2(helper_fpsub16s, cpu_fpr[rd], |
|
| 3864 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 3871 | 3865 |
break; |
| 3872 | 3866 |
case 0x056: /* VIS I fpsub32 */ |
| 3873 | 3867 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3878 | 3872 |
break; |
| 3879 | 3873 |
case 0x057: /* VIS I fpsub32s */ |
| 3880 | 3874 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3881 |
gen_op_load_fpr_FT0(rs1); |
|
| 3882 |
gen_op_load_fpr_FT1(rs2); |
|
| 3883 |
tcg_gen_helper_0_0(helper_fpsub32s); |
|
| 3884 |
gen_op_store_FT0_fpr(rd); |
|
| 3875 |
tcg_gen_helper_1_2(helper_fpsub32s, cpu_fpr[rd], |
|
| 3876 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 3885 | 3877 |
break; |
| 3886 | 3878 |
case 0x060: /* VIS I fzero */ |
| 3887 | 3879 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3888 |
tcg_gen_helper_0_0(helper_movl_DT0_0);
|
|
| 3889 |
gen_op_store_DT0_fpr(DFPREG(rd));
|
|
| 3880 |
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
|
|
| 3881 |
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0);
|
|
| 3890 | 3882 |
break; |
| 3891 | 3883 |
case 0x061: /* VIS I fzeros */ |
| 3892 | 3884 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3893 |
tcg_gen_helper_0_0(helper_movl_FT0_0); |
|
| 3894 |
gen_op_store_FT0_fpr(rd); |
|
| 3885 |
tcg_gen_movi_i32(cpu_fpr[rd], 0); |
|
| 3895 | 3886 |
break; |
| 3896 | 3887 |
case 0x062: /* VIS I fnor */ |
| 3897 | 3888 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3902 | 3893 |
break; |
| 3903 | 3894 |
case 0x063: /* VIS I fnors */ |
| 3904 | 3895 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3905 |
gen_op_load_fpr_FT0(rs1); |
|
| 3906 |
gen_op_load_fpr_FT1(rs2); |
|
| 3907 |
tcg_gen_helper_0_0(helper_fnors); |
|
| 3908 |
gen_op_store_FT0_fpr(rd); |
|
| 3896 |
tcg_gen_or_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 3897 |
tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1); |
|
| 3909 | 3898 |
break; |
| 3910 | 3899 |
case 0x064: /* VIS I fandnot2 */ |
| 3911 | 3900 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3916 | 3905 |
break; |
| 3917 | 3906 |
case 0x065: /* VIS I fandnot2s */ |
| 3918 | 3907 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3919 |
gen_op_load_fpr_FT1(rs1); |
|
| 3920 |
gen_op_load_fpr_FT0(rs2); |
|
| 3921 |
tcg_gen_helper_0_0(helper_fandnots); |
|
| 3922 |
gen_op_store_FT0_fpr(rd); |
|
| 3908 |
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1); |
|
| 3909 |
tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]); |
|
| 3923 | 3910 |
break; |
| 3924 | 3911 |
case 0x066: /* VIS I fnot2 */ |
| 3925 | 3912 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3929 | 3916 |
break; |
| 3930 | 3917 |
case 0x067: /* VIS I fnot2s */ |
| 3931 | 3918 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3932 |
gen_op_load_fpr_FT1(rs2); |
|
| 3933 |
tcg_gen_helper_0_0(helper_fnot); |
|
| 3934 |
gen_op_store_FT0_fpr(rd); |
|
| 3919 |
tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs2], -1); |
|
| 3935 | 3920 |
break; |
| 3936 | 3921 |
case 0x068: /* VIS I fandnot1 */ |
| 3937 | 3922 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3942 | 3927 |
break; |
| 3943 | 3928 |
case 0x069: /* VIS I fandnot1s */ |
| 3944 | 3929 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3945 |
gen_op_load_fpr_FT0(rs1); |
|
| 3946 |
gen_op_load_fpr_FT1(rs2); |
|
| 3947 |
tcg_gen_helper_0_0(helper_fandnots); |
|
| 3948 |
gen_op_store_FT0_fpr(rd); |
|
| 3930 |
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); |
|
| 3931 |
tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
|
| 3949 | 3932 |
break; |
| 3950 | 3933 |
case 0x06a: /* VIS I fnot1 */ |
| 3951 | 3934 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3955 | 3938 |
break; |
| 3956 | 3939 |
case 0x06b: /* VIS I fnot1s */ |
| 3957 | 3940 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3958 |
gen_op_load_fpr_FT1(rs1); |
|
| 3959 |
tcg_gen_helper_0_0(helper_fnot); |
|
| 3960 |
gen_op_store_FT0_fpr(rd); |
|
| 3941 |
tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs1], -1); |
|
| 3961 | 3942 |
break; |
| 3962 | 3943 |
case 0x06c: /* VIS I fxor */ |
| 3963 | 3944 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3968 | 3949 |
break; |
| 3969 | 3950 |
case 0x06d: /* VIS I fxors */ |
| 3970 | 3951 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3971 |
gen_op_load_fpr_FT0(rs1); |
|
| 3972 |
gen_op_load_fpr_FT1(rs2); |
|
| 3973 |
tcg_gen_helper_0_0(helper_fxors); |
|
| 3974 |
gen_op_store_FT0_fpr(rd); |
|
| 3952 |
tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 3975 | 3953 |
break; |
| 3976 | 3954 |
case 0x06e: /* VIS I fnand */ |
| 3977 | 3955 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3982 | 3960 |
break; |
| 3983 | 3961 |
case 0x06f: /* VIS I fnands */ |
| 3984 | 3962 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3985 |
gen_op_load_fpr_FT0(rs1); |
|
| 3986 |
gen_op_load_fpr_FT1(rs2); |
|
| 3987 |
tcg_gen_helper_0_0(helper_fnands); |
|
| 3988 |
gen_op_store_FT0_fpr(rd); |
|
| 3963 |
tcg_gen_and_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 3964 |
tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1); |
|
| 3989 | 3965 |
break; |
| 3990 | 3966 |
case 0x070: /* VIS I fand */ |
| 3991 | 3967 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3996 | 3972 |
break; |
| 3997 | 3973 |
case 0x071: /* VIS I fands */ |
| 3998 | 3974 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3999 |
gen_op_load_fpr_FT0(rs1); |
|
| 4000 |
gen_op_load_fpr_FT1(rs2); |
|
| 4001 |
tcg_gen_helper_0_0(helper_fands); |
|
| 4002 |
gen_op_store_FT0_fpr(rd); |
|
| 3975 |
tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 4003 | 3976 |
break; |
| 4004 | 3977 |
case 0x072: /* VIS I fxnor */ |
| 4005 | 3978 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4010 | 3983 |
break; |
| 4011 | 3984 |
case 0x073: /* VIS I fxnors */ |
| 4012 | 3985 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4013 |
gen_op_load_fpr_FT0(rs1); |
|
| 4014 |
gen_op_load_fpr_FT1(rs2); |
|
| 4015 |
tcg_gen_helper_0_0(helper_fxnors); |
|
| 4016 |
gen_op_store_FT0_fpr(rd); |
|
| 3986 |
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); |
|
| 3987 |
tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
|
| 4017 | 3988 |
break; |
| 4018 | 3989 |
case 0x074: /* VIS I fsrc1 */ |
| 4019 | 3990 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4020 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
|
| 4021 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
|
| 3991 |
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
|
| 3992 |
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], |
|
| 3993 |
cpu_fpr[DFPREG(rs1) + 1]); |
|
| 4022 | 3994 |
break; |
| 4023 | 3995 |
case 0x075: /* VIS I fsrc1s */ |
| 4024 | 3996 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4025 |
gen_op_load_fpr_FT0(rs1); |
|
| 4026 |
gen_op_store_FT0_fpr(rd); |
|
| 3997 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
|
| 4027 | 3998 |
break; |
| 4028 | 3999 |
case 0x076: /* VIS I fornot2 */ |
| 4029 | 4000 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4034 | 4005 |
break; |
| 4035 | 4006 |
case 0x077: /* VIS I fornot2s */ |
| 4036 | 4007 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4037 |
gen_op_load_fpr_FT1(rs1); |
|
| 4038 |
gen_op_load_fpr_FT0(rs2); |
|
| 4039 |
tcg_gen_helper_0_0(helper_fornots); |
|
| 4040 |
gen_op_store_FT0_fpr(rd); |
|
| 4008 |
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1); |
|
| 4009 |
tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]); |
|
| 4041 | 4010 |
break; |
| 4042 | 4011 |
case 0x078: /* VIS I fsrc2 */ |
| 4043 | 4012 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4046 | 4015 |
break; |
| 4047 | 4016 |
case 0x079: /* VIS I fsrc2s */ |
| 4048 | 4017 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4049 |
gen_op_load_fpr_FT0(rs2); |
|
| 4050 |
gen_op_store_FT0_fpr(rd); |
|
| 4018 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
|
| 4051 | 4019 |
break; |
| 4052 | 4020 |
case 0x07a: /* VIS I fornot1 */ |
| 4053 | 4021 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4058 | 4026 |
break; |
| 4059 | 4027 |
case 0x07b: /* VIS I fornot1s */ |
| 4060 | 4028 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4061 |
gen_op_load_fpr_FT0(rs1); |
|
| 4062 |
gen_op_load_fpr_FT1(rs2); |
|
| 4063 |
tcg_gen_helper_0_0(helper_fornots); |
|
| 4064 |
gen_op_store_FT0_fpr(rd); |
|
| 4029 |
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); |
|
| 4030 |
tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
|
| 4065 | 4031 |
break; |
| 4066 | 4032 |
case 0x07c: /* VIS I for */ |
| 4067 | 4033 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4072 | 4038 |
break; |
| 4073 | 4039 |
case 0x07d: /* VIS I fors */ |
| 4074 | 4040 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4075 |
gen_op_load_fpr_FT0(rs1); |
|
| 4076 |
gen_op_load_fpr_FT1(rs2); |
|
| 4077 |
tcg_gen_helper_0_0(helper_fors); |
|
| 4078 |
gen_op_store_FT0_fpr(rd); |
|
| 4041 |
tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
|
| 4079 | 4042 |
break; |
| 4080 | 4043 |
case 0x07e: /* VIS I fone */ |
| 4081 | 4044 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4082 |
tcg_gen_helper_0_0(helper_movl_DT0_1);
|
|
| 4083 |
gen_op_store_DT0_fpr(DFPREG(rd));
|
|
| 4045 |
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
|
|
| 4046 |
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1);
|
|
| 4084 | 4047 |
break; |
| 4085 | 4048 |
case 0x07f: /* VIS I fones */ |
| 4086 | 4049 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4087 |
tcg_gen_helper_0_0(helper_movl_FT0_1); |
|
| 4088 |
gen_op_store_FT0_fpr(rd); |
|
| 4050 |
tcg_gen_movi_i32(cpu_fpr[rd], -1); |
|
| 4089 | 4051 |
break; |
| 4090 | 4052 |
case 0x080: /* VIS I shutdown */ |
| 4091 | 4053 |
case 0x081: /* VIS II siam */ |
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