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1 | aa0aa4fa | bellard | /* Print SPARC instructions.
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2 | aa0aa4fa | bellard | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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3 | aa0aa4fa | bellard | 2000, 2002 Free Software Foundation, Inc.
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4 | aa0aa4fa | bellard | |
5 | aa0aa4fa | bellard | This program is free software; you can redistribute it and/or modify
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6 | aa0aa4fa | bellard | it under the terms of the GNU General Public License as published by
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7 | aa0aa4fa | bellard | the Free Software Foundation; either version 2 of the License, or
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8 | aa0aa4fa | bellard | (at your option) any later version.
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9 | aa0aa4fa | bellard | |
10 | aa0aa4fa | bellard | This program is distributed in the hope that it will be useful,
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11 | aa0aa4fa | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 | aa0aa4fa | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 | aa0aa4fa | bellard | GNU General Public License for more details.
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14 | aa0aa4fa | bellard | |
15 | aa0aa4fa | bellard | You should have received a copy of the GNU General Public License
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16 | aa0aa4fa | bellard | along with this program; if not, write to the Free Software
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17 | aa0aa4fa | bellard | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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18 | aa0aa4fa | bellard | #include <stdlib.h> |
19 | aa0aa4fa | bellard | #include "dis-asm.h" |
20 | aa0aa4fa | bellard | |
21 | aa0aa4fa | bellard | /* The SPARC opcode table (and other related data) is defined in
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22 | aa0aa4fa | bellard | the opcodes library in sparc-opc.c. If you change anything here, make
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23 | aa0aa4fa | bellard | sure you fix up that file, and vice versa. */
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24 | aa0aa4fa | bellard | |
25 | aa0aa4fa | bellard | /* FIXME-someday: perhaps the ,a's and such should be embedded in the
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26 | aa0aa4fa | bellard | instruction's name rather than the args. This would make gas faster, pinsn
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27 | aa0aa4fa | bellard | slower, but would mess up some macros a bit. xoxorich. */
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28 | aa0aa4fa | bellard | |
29 | aa0aa4fa | bellard | /* List of instruction sets variations.
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30 | aa0aa4fa | bellard | These values are such that each element is either a superset of a
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31 | aa0aa4fa | bellard | preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
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32 | aa0aa4fa | bellard | returns non-zero.
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33 | aa0aa4fa | bellard | The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
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34 | aa0aa4fa | bellard | Don't change this without updating sparc-opc.c. */
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35 | aa0aa4fa | bellard | |
36 | aa0aa4fa | bellard | enum sparc_opcode_arch_val {
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37 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_V6 = 0,
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38 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_V7, |
39 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_V8, |
40 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_SPARCLET, |
41 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_SPARCLITE, |
42 | aa0aa4fa | bellard | /* v9 variants must appear last */
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43 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_V9, |
44 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
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45 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
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46 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
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47 | aa0aa4fa | bellard | }; |
48 | aa0aa4fa | bellard | |
49 | aa0aa4fa | bellard | /* The highest architecture in the table. */
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50 | aa0aa4fa | bellard | #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) |
51 | aa0aa4fa | bellard | |
52 | aa0aa4fa | bellard | /* Given an enum sparc_opcode_arch_val, return the bitmask to use in
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53 | aa0aa4fa | bellard | insn encoding/decoding. */
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54 | aa0aa4fa | bellard | #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) |
55 | aa0aa4fa | bellard | |
56 | aa0aa4fa | bellard | /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
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57 | aa0aa4fa | bellard | #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
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58 | aa0aa4fa | bellard | |
59 | aa0aa4fa | bellard | /* Table of cpu variants. */
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60 | aa0aa4fa | bellard | |
61 | aa0aa4fa | bellard | struct sparc_opcode_arch {
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62 | aa0aa4fa | bellard | const char *name; |
63 | aa0aa4fa | bellard | /* Mask of sparc_opcode_arch_val's supported.
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64 | aa0aa4fa | bellard | EG: For v7 this would be
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65 | aa0aa4fa | bellard | (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
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66 | aa0aa4fa | bellard | These are short's because sparc_opcode.architecture is. */
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67 | aa0aa4fa | bellard | short supported;
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68 | aa0aa4fa | bellard | }; |
69 | aa0aa4fa | bellard | |
70 | aa0aa4fa | bellard | extern const struct sparc_opcode_arch sparc_opcode_archs[]; |
71 | aa0aa4fa | bellard | |
72 | aa0aa4fa | bellard | /* Given architecture name, look up it's sparc_opcode_arch_val value. */
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73 | aa0aa4fa | bellard | extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch |
74 | aa0aa4fa | bellard | PARAMS ((const char *)); |
75 | aa0aa4fa | bellard | |
76 | aa0aa4fa | bellard | /* Return the bitmask of supported architectures for ARCH. */
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77 | aa0aa4fa | bellard | #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
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78 | aa0aa4fa | bellard | |
79 | aa0aa4fa | bellard | /* Non-zero if ARCH1 conflicts with ARCH2.
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80 | aa0aa4fa | bellard | IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
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81 | aa0aa4fa | bellard | #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
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82 | aa0aa4fa | bellard | (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ |
83 | aa0aa4fa | bellard | != SPARC_OPCODE_SUPPORTED (ARCH1)) \ |
84 | aa0aa4fa | bellard | && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ |
85 | aa0aa4fa | bellard | != SPARC_OPCODE_SUPPORTED (ARCH2))) |
86 | aa0aa4fa | bellard | |
87 | aa0aa4fa | bellard | /* Structure of an opcode table entry. */
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88 | aa0aa4fa | bellard | |
89 | aa0aa4fa | bellard | struct sparc_opcode {
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90 | aa0aa4fa | bellard | const char *name; |
91 | aa0aa4fa | bellard | unsigned long match; /* Bits that must be set. */ |
92 | aa0aa4fa | bellard | unsigned long lose; /* Bits that must not be set. */ |
93 | aa0aa4fa | bellard | const char *args; |
94 | aa0aa4fa | bellard | /* This was called "delayed" in versions before the flags. */
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95 | aa0aa4fa | bellard | char flags;
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96 | aa0aa4fa | bellard | short architecture; /* Bitmask of sparc_opcode_arch_val's. */ |
97 | aa0aa4fa | bellard | }; |
98 | aa0aa4fa | bellard | |
99 | aa0aa4fa | bellard | #define F_DELAYED 1 /* Delayed branch */ |
100 | aa0aa4fa | bellard | #define F_ALIAS 2 /* Alias for a "real" instruction */ |
101 | aa0aa4fa | bellard | #define F_UNBR 4 /* Unconditional branch */ |
102 | aa0aa4fa | bellard | #define F_CONDBR 8 /* Conditional branch */ |
103 | aa0aa4fa | bellard | #define F_JSR 16 /* Subroutine call */ |
104 | aa0aa4fa | bellard | #define F_FLOAT 32 /* Floating point instruction (not a branch) */ |
105 | aa0aa4fa | bellard | #define F_FBR 64 /* Floating point branch */ |
106 | aa0aa4fa | bellard | /* FIXME: Add F_ANACHRONISTIC flag for v9. */
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107 | aa0aa4fa | bellard | |
108 | aa0aa4fa | bellard | /*
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109 | aa0aa4fa | bellard | |
110 | aa0aa4fa | bellard | All sparc opcodes are 32 bits, except for the `set' instruction (really a
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111 | aa0aa4fa | bellard | macro), which is 64 bits. It is handled as a special case.
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112 | aa0aa4fa | bellard | |
113 | aa0aa4fa | bellard | The match component is a mask saying which bits must match a particular
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114 | aa0aa4fa | bellard | opcode in order for an instruction to be an instance of that opcode.
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115 | aa0aa4fa | bellard | |
116 | aa0aa4fa | bellard | The args component is a string containing one character for each operand of the
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117 | aa0aa4fa | bellard | instruction.
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118 | aa0aa4fa | bellard | |
119 | aa0aa4fa | bellard | Kinds of operands:
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120 | aa0aa4fa | bellard | # Number used by optimizer. It is ignored.
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121 | aa0aa4fa | bellard | 1 rs1 register.
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122 | aa0aa4fa | bellard | 2 rs2 register.
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123 | aa0aa4fa | bellard | d rd register.
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124 | aa0aa4fa | bellard | e frs1 floating point register.
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125 | aa0aa4fa | bellard | v frs1 floating point register (double/even).
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126 | aa0aa4fa | bellard | V frs1 floating point register (quad/multiple of 4).
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127 | aa0aa4fa | bellard | f frs2 floating point register.
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128 | aa0aa4fa | bellard | B frs2 floating point register (double/even).
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129 | aa0aa4fa | bellard | R frs2 floating point register (quad/multiple of 4).
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130 | aa0aa4fa | bellard | g frsd floating point register.
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131 | aa0aa4fa | bellard | H frsd floating point register (double/even).
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132 | aa0aa4fa | bellard | J frsd floating point register (quad/multiple of 4).
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133 | aa0aa4fa | bellard | b crs1 coprocessor register
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134 | aa0aa4fa | bellard | c crs2 coprocessor register
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135 | aa0aa4fa | bellard | D crsd coprocessor register
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136 | aa0aa4fa | bellard | m alternate space register (asr) in rd
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137 | aa0aa4fa | bellard | M alternate space register (asr) in rs1
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138 | aa0aa4fa | bellard | h 22 high bits.
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139 | aa0aa4fa | bellard | X 5 bit unsigned immediate
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140 | aa0aa4fa | bellard | Y 6 bit unsigned immediate
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141 | aa0aa4fa | bellard | 3 SIAM mode (3 bits). (v9b)
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142 | aa0aa4fa | bellard | K MEMBAR mask (7 bits). (v9)
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143 | aa0aa4fa | bellard | j 10 bit Immediate. (v9)
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144 | aa0aa4fa | bellard | I 11 bit Immediate. (v9)
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145 | aa0aa4fa | bellard | i 13 bit Immediate.
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146 | aa0aa4fa | bellard | n 22 bit immediate.
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147 | aa0aa4fa | bellard | k 2+14 bit PC relative immediate. (v9)
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148 | aa0aa4fa | bellard | G 19 bit PC relative immediate. (v9)
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149 | aa0aa4fa | bellard | l 22 bit PC relative immediate.
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150 | aa0aa4fa | bellard | L 30 bit PC relative immediate.
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151 | aa0aa4fa | bellard | a Annul. The annul bit is set.
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152 | aa0aa4fa | bellard | A Alternate address space. Stored as 8 bits.
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153 | aa0aa4fa | bellard | C Coprocessor state register.
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154 | aa0aa4fa | bellard | F floating point state register.
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155 | aa0aa4fa | bellard | p Processor state register.
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156 | aa0aa4fa | bellard | N Branch predict clear ",pn" (v9)
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157 | aa0aa4fa | bellard | T Branch predict set ",pt" (v9)
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158 | aa0aa4fa | bellard | z %icc. (v9)
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159 | aa0aa4fa | bellard | Z %xcc. (v9)
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160 | aa0aa4fa | bellard | q Floating point queue.
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161 | aa0aa4fa | bellard | r Single register that is both rs1 and rd.
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162 | aa0aa4fa | bellard | O Single register that is both rs2 and rd.
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163 | aa0aa4fa | bellard | Q Coprocessor queue.
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164 | aa0aa4fa | bellard | S Special case.
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165 | aa0aa4fa | bellard | t Trap base register.
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166 | aa0aa4fa | bellard | w Window invalid mask register.
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167 | aa0aa4fa | bellard | y Y register.
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168 | aa0aa4fa | bellard | u sparclet coprocessor registers in rd position
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169 | aa0aa4fa | bellard | U sparclet coprocessor registers in rs1 position
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170 | aa0aa4fa | bellard | E %ccr. (v9)
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171 | aa0aa4fa | bellard | s %fprs. (v9)
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172 | aa0aa4fa | bellard | P %pc. (v9)
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173 | aa0aa4fa | bellard | W %tick. (v9)
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174 | aa0aa4fa | bellard | o %asi. (v9)
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175 | aa0aa4fa | bellard | 6 %fcc0. (v9)
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176 | aa0aa4fa | bellard | 7 %fcc1. (v9)
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177 | aa0aa4fa | bellard | 8 %fcc2. (v9)
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178 | aa0aa4fa | bellard | 9 %fcc3. (v9)
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179 | aa0aa4fa | bellard | ! Privileged Register in rd (v9)
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180 | aa0aa4fa | bellard | ? Privileged Register in rs1 (v9)
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181 | aa0aa4fa | bellard | * Prefetch function constant. (v9)
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182 | aa0aa4fa | bellard | x OPF field (v9 impdep).
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183 | aa0aa4fa | bellard | 0 32/64 bit immediate for set or setx (v9) insns
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184 | aa0aa4fa | bellard | _ Ancillary state register in rd (v9a)
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185 | aa0aa4fa | bellard | / Ancillary state register in rs1 (v9a)
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186 | aa0aa4fa | bellard | |
187 | aa0aa4fa | bellard | The following chars are unused: (note: ,[] are used as punctuation)
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188 | aa0aa4fa | bellard | [45]
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189 | aa0aa4fa | bellard | |
190 | aa0aa4fa | bellard | */
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191 | aa0aa4fa | bellard | |
192 | aa0aa4fa | bellard | #define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ |
193 | aa0aa4fa | bellard | #define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ |
194 | aa0aa4fa | bellard | #define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ |
195 | aa0aa4fa | bellard | #define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ |
196 | aa0aa4fa | bellard | #define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ |
197 | aa0aa4fa | bellard | #define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ |
198 | aa0aa4fa | bellard | #define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ |
199 | aa0aa4fa | bellard | #define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ |
200 | aa0aa4fa | bellard | #define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ |
201 | aa0aa4fa | bellard | #define F1(x) (OP(x))
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202 | aa0aa4fa | bellard | #define DISP30(x) ((x)&0x3fffffff) |
203 | aa0aa4fa | bellard | #define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ |
204 | aa0aa4fa | bellard | #define RS2(x) ((x)&0x1f) /* rs2 field */ |
205 | aa0aa4fa | bellard | #define SIMM13(x) ((x)&0x1fff) /* simm13 field */ |
206 | aa0aa4fa | bellard | #define RD(x) (((x)&0x1f) << 25) /* destination register field */ |
207 | aa0aa4fa | bellard | #define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ |
208 | aa0aa4fa | bellard | #define ASI_RS2(x) (SIMM13(x))
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209 | aa0aa4fa | bellard | #define MEMBAR(x) ((x)&0x7f) |
210 | aa0aa4fa | bellard | #define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */ |
211 | aa0aa4fa | bellard | |
212 | aa0aa4fa | bellard | #define ANNUL (1<<29) |
213 | aa0aa4fa | bellard | #define BPRED (1<<19) /* v9 */ |
214 | aa0aa4fa | bellard | #define IMMED F3I(1) |
215 | aa0aa4fa | bellard | #define RD_G0 RD(~0) |
216 | aa0aa4fa | bellard | #define RS1_G0 RS1(~0) |
217 | aa0aa4fa | bellard | #define RS2_G0 RS2(~0) |
218 | aa0aa4fa | bellard | |
219 | aa0aa4fa | bellard | extern const struct sparc_opcode sparc_opcodes[]; |
220 | aa0aa4fa | bellard | extern const int sparc_num_opcodes; |
221 | aa0aa4fa | bellard | |
222 | aa0aa4fa | bellard | extern int sparc_encode_asi PARAMS ((const char *)); |
223 | aa0aa4fa | bellard | extern const char *sparc_decode_asi PARAMS ((int)); |
224 | aa0aa4fa | bellard | extern int sparc_encode_membar PARAMS ((const char *)); |
225 | aa0aa4fa | bellard | extern const char *sparc_decode_membar PARAMS ((int)); |
226 | aa0aa4fa | bellard | extern int sparc_encode_prefetch PARAMS ((const char *)); |
227 | aa0aa4fa | bellard | extern const char *sparc_decode_prefetch PARAMS ((int)); |
228 | aa0aa4fa | bellard | extern int sparc_encode_sparclet_cpreg PARAMS ((const char *)); |
229 | aa0aa4fa | bellard | extern const char *sparc_decode_sparclet_cpreg PARAMS ((int)); |
230 | aa0aa4fa | bellard | |
231 | aa0aa4fa | bellard | /* Some defines to make life easy. */
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232 | aa0aa4fa | bellard | #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
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233 | aa0aa4fa | bellard | #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
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234 | aa0aa4fa | bellard | #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
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235 | aa0aa4fa | bellard | #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
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236 | aa0aa4fa | bellard | #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
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237 | aa0aa4fa | bellard | #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
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238 | aa0aa4fa | bellard | #define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
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239 | aa0aa4fa | bellard | #define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
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240 | aa0aa4fa | bellard | |
241 | aa0aa4fa | bellard | /* Bit masks of architectures supporting the insn. */
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242 | aa0aa4fa | bellard | |
243 | aa0aa4fa | bellard | #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
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244 | aa0aa4fa | bellard | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
245 | aa0aa4fa | bellard | /* v6 insns not supported on the sparclet */
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246 | aa0aa4fa | bellard | #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
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247 | aa0aa4fa | bellard | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
248 | aa0aa4fa | bellard | #define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
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249 | aa0aa4fa | bellard | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
250 | aa0aa4fa | bellard | /* Although not all insns are implemented in hardware, sparclite is defined
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251 | aa0aa4fa | bellard | to be a superset of v8. Unimplemented insns trap and are then theoretically
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252 | aa0aa4fa | bellard | implemented in software.
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253 | aa0aa4fa | bellard | It's not clear that the same is true for sparclet, although the docs
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254 | aa0aa4fa | bellard | suggest it is. Rather than complicating things, the sparclet assembler
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255 | aa0aa4fa | bellard | recognizes all v8 insns. */
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256 | aa0aa4fa | bellard | #define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
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257 | aa0aa4fa | bellard | | MASK_V9 | MASK_V9A | MASK_V9B) |
258 | aa0aa4fa | bellard | #define sparclet (MASK_SPARCLET)
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259 | aa0aa4fa | bellard | #define sparclite (MASK_SPARCLITE)
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260 | aa0aa4fa | bellard | #define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
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261 | aa0aa4fa | bellard | #define v9a (MASK_V9A | MASK_V9B)
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262 | aa0aa4fa | bellard | #define v9b (MASK_V9B)
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263 | aa0aa4fa | bellard | /* v6 insns not supported by v9 */
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264 | aa0aa4fa | bellard | #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
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265 | aa0aa4fa | bellard | | MASK_SPARCLET | MASK_SPARCLITE) |
266 | aa0aa4fa | bellard | /* v9a instructions which would appear to be aliases to v9's impdep's
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267 | aa0aa4fa | bellard | otherwise */
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268 | aa0aa4fa | bellard | #define v9notv9a (MASK_V9)
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269 | aa0aa4fa | bellard | |
270 | aa0aa4fa | bellard | /* Table of opcode architectures.
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271 | aa0aa4fa | bellard | The order is defined in opcode/sparc.h. */
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272 | aa0aa4fa | bellard | |
273 | aa0aa4fa | bellard | const struct sparc_opcode_arch sparc_opcode_archs[] = { |
274 | aa0aa4fa | bellard | { "v6", MASK_V6 },
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275 | aa0aa4fa | bellard | { "v7", MASK_V6 | MASK_V7 },
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276 | aa0aa4fa | bellard | { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
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277 | aa0aa4fa | bellard | { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
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278 | aa0aa4fa | bellard | { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
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279 | aa0aa4fa | bellard | /* ??? Don't some v8 priviledged insns conflict with v9? */
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280 | aa0aa4fa | bellard | { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
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281 | aa0aa4fa | bellard | /* v9 with ultrasparc additions */
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282 | aa0aa4fa | bellard | { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
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283 | aa0aa4fa | bellard | /* v9 with cheetah additions */
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284 | aa0aa4fa | bellard | { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
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285 | aa0aa4fa | bellard | { NULL, 0 } |
286 | aa0aa4fa | bellard | }; |
287 | aa0aa4fa | bellard | |
288 | aa0aa4fa | bellard | /* Given NAME, return it's architecture entry. */
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289 | aa0aa4fa | bellard | |
290 | aa0aa4fa | bellard | enum sparc_opcode_arch_val
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291 | aa0aa4fa | bellard | sparc_opcode_lookup_arch (name) |
292 | aa0aa4fa | bellard | const char *name; |
293 | aa0aa4fa | bellard | { |
294 | aa0aa4fa | bellard | const struct sparc_opcode_arch *p; |
295 | aa0aa4fa | bellard | |
296 | aa0aa4fa | bellard | for (p = &sparc_opcode_archs[0]; p->name; ++p) |
297 | aa0aa4fa | bellard | { |
298 | aa0aa4fa | bellard | if (strcmp (name, p->name) == 0) |
299 | aa0aa4fa | bellard | return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); |
300 | aa0aa4fa | bellard | } |
301 | aa0aa4fa | bellard | |
302 | aa0aa4fa | bellard | return SPARC_OPCODE_ARCH_BAD;
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303 | aa0aa4fa | bellard | } |
304 | aa0aa4fa | bellard | |
305 | aa0aa4fa | bellard | /* Branch condition field. */
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306 | aa0aa4fa | bellard | #define COND(x) (((x)&0xf)<<25) |
307 | aa0aa4fa | bellard | |
308 | aa0aa4fa | bellard | /* v9: Move (MOVcc and FMOVcc) condition field. */
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309 | aa0aa4fa | bellard | #define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */ |
310 | aa0aa4fa | bellard | |
311 | aa0aa4fa | bellard | /* v9: Move register (MOVRcc and FMOVRcc) condition field. */
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312 | aa0aa4fa | bellard | #define RCOND(x) (((x)&0x7)<<10) /* v9 */ |
313 | aa0aa4fa | bellard | |
314 | aa0aa4fa | bellard | #define CONDA (COND(0x8)) |
315 | aa0aa4fa | bellard | #define CONDCC (COND(0xd)) |
316 | aa0aa4fa | bellard | #define CONDCS (COND(0x5)) |
317 | aa0aa4fa | bellard | #define CONDE (COND(0x1)) |
318 | aa0aa4fa | bellard | #define CONDG (COND(0xa)) |
319 | aa0aa4fa | bellard | #define CONDGE (COND(0xb)) |
320 | aa0aa4fa | bellard | #define CONDGU (COND(0xc)) |
321 | aa0aa4fa | bellard | #define CONDL (COND(0x3)) |
322 | aa0aa4fa | bellard | #define CONDLE (COND(0x2)) |
323 | aa0aa4fa | bellard | #define CONDLEU (COND(0x4)) |
324 | aa0aa4fa | bellard | #define CONDN (COND(0x0)) |
325 | aa0aa4fa | bellard | #define CONDNE (COND(0x9)) |
326 | aa0aa4fa | bellard | #define CONDNEG (COND(0x6)) |
327 | aa0aa4fa | bellard | #define CONDPOS (COND(0xe)) |
328 | aa0aa4fa | bellard | #define CONDVC (COND(0xf)) |
329 | aa0aa4fa | bellard | #define CONDVS (COND(0x7)) |
330 | aa0aa4fa | bellard | |
331 | aa0aa4fa | bellard | #define CONDNZ CONDNE
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332 | aa0aa4fa | bellard | #define CONDZ CONDE
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333 | aa0aa4fa | bellard | #define CONDGEU CONDCC
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334 | aa0aa4fa | bellard | #define CONDLU CONDCS
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335 | aa0aa4fa | bellard | |
336 | aa0aa4fa | bellard | #define FCONDA (COND(0x8)) |
337 | aa0aa4fa | bellard | #define FCONDE (COND(0x9)) |
338 | aa0aa4fa | bellard | #define FCONDG (COND(0x6)) |
339 | aa0aa4fa | bellard | #define FCONDGE (COND(0xb)) |
340 | aa0aa4fa | bellard | #define FCONDL (COND(0x4)) |
341 | aa0aa4fa | bellard | #define FCONDLE (COND(0xd)) |
342 | aa0aa4fa | bellard | #define FCONDLG (COND(0x2)) |
343 | aa0aa4fa | bellard | #define FCONDN (COND(0x0)) |
344 | aa0aa4fa | bellard | #define FCONDNE (COND(0x1)) |
345 | aa0aa4fa | bellard | #define FCONDO (COND(0xf)) |
346 | aa0aa4fa | bellard | #define FCONDU (COND(0x7)) |
347 | aa0aa4fa | bellard | #define FCONDUE (COND(0xa)) |
348 | aa0aa4fa | bellard | #define FCONDUG (COND(0x5)) |
349 | aa0aa4fa | bellard | #define FCONDUGE (COND(0xc)) |
350 | aa0aa4fa | bellard | #define FCONDUL (COND(0x3)) |
351 | aa0aa4fa | bellard | #define FCONDULE (COND(0xe)) |
352 | aa0aa4fa | bellard | |
353 | aa0aa4fa | bellard | #define FCONDNZ FCONDNE
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354 | aa0aa4fa | bellard | #define FCONDZ FCONDE
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355 | aa0aa4fa | bellard | |
356 | aa0aa4fa | bellard | #define ICC (0) /* v9 */ |
357 | aa0aa4fa | bellard | #define XCC (1<<12) /* v9 */ |
358 | aa0aa4fa | bellard | #define FCC(x) (((x)&0x3)<<11) /* v9 */ |
359 | aa0aa4fa | bellard | #define FBFCC(x) (((x)&0x3)<<20) /* v9 */ |
360 | aa0aa4fa | bellard | |
361 | aa0aa4fa | bellard | /* The order of the opcodes in the table is significant:
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362 | aa0aa4fa | bellard |
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363 | aa0aa4fa | bellard | * The assembler requires that all instances of the same mnemonic must
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364 | aa0aa4fa | bellard | be consecutive. If they aren't, the assembler will bomb at runtime.
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365 | aa0aa4fa | bellard | |
366 | aa0aa4fa | bellard | * The disassembler should not care about the order of the opcodes.
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367 | aa0aa4fa | bellard | |
368 | aa0aa4fa | bellard | */
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369 | aa0aa4fa | bellard | |
370 | aa0aa4fa | bellard | /* Entries for commutative arithmetic operations. */
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371 | aa0aa4fa | bellard | /* ??? More entries can make use of this. */
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372 | aa0aa4fa | bellard | #define COMMUTEOP(opcode, op3, arch_mask) \
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373 | aa0aa4fa | bellard | { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \ |
374 | aa0aa4fa | bellard | { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ |
375 | aa0aa4fa | bellard | { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } |
376 | aa0aa4fa | bellard | |
377 | aa0aa4fa | bellard | const struct sparc_opcode sparc_opcodes[] = { |
378 | aa0aa4fa | bellard | |
379 | aa0aa4fa | bellard | { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, |
380 | aa0aa4fa | bellard | { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ |
381 | aa0aa4fa | bellard | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 }, |
382 | aa0aa4fa | bellard | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 }, |
383 | aa0aa4fa | bellard | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 }, |
384 | aa0aa4fa | bellard | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ |
385 | aa0aa4fa | bellard | { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 }, |
386 | aa0aa4fa | bellard | { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */ |
387 | aa0aa4fa | bellard | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 }, |
388 | aa0aa4fa | bellard | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 }, |
389 | aa0aa4fa | bellard | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 }, |
390 | aa0aa4fa | bellard | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */ |
391 | aa0aa4fa | bellard | |
392 | aa0aa4fa | bellard | { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 }, |
393 | aa0aa4fa | bellard | { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */ |
394 | aa0aa4fa | bellard | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 }, |
395 | aa0aa4fa | bellard | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 }, |
396 | aa0aa4fa | bellard | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 }, |
397 | aa0aa4fa | bellard | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */ |
398 | aa0aa4fa | bellard | |
399 | aa0aa4fa | bellard | { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 }, |
400 | aa0aa4fa | bellard | { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */ |
401 | aa0aa4fa | bellard | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 }, |
402 | aa0aa4fa | bellard | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 }, |
403 | aa0aa4fa | bellard | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, |
404 | aa0aa4fa | bellard | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */ |
405 | aa0aa4fa | bellard | { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 }, |
406 | aa0aa4fa | bellard | { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */ |
407 | aa0aa4fa | bellard | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 }, |
408 | aa0aa4fa | bellard | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 }, |
409 | aa0aa4fa | bellard | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 }, |
410 | aa0aa4fa | bellard | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */ |
411 | aa0aa4fa | bellard | |
412 | aa0aa4fa | bellard | /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
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413 | aa0aa4fa | bellard | 'ld' pseudo-op in v9. */
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414 | aa0aa4fa | bellard | { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, |
415 | aa0aa4fa | bellard | { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ |
416 | aa0aa4fa | bellard | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, |
417 | aa0aa4fa | bellard | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, |
418 | aa0aa4fa | bellard | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, |
419 | aa0aa4fa | bellard | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ |
420 | aa0aa4fa | bellard | |
421 | aa0aa4fa | bellard | { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
422 | aa0aa4fa | bellard | { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */ |
423 | aa0aa4fa | bellard | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 }, |
424 | aa0aa4fa | bellard | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 }, |
425 | aa0aa4fa | bellard | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 }, |
426 | aa0aa4fa | bellard | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */ |
427 | aa0aa4fa | bellard | { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 }, |
428 | aa0aa4fa | bellard | { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */ |
429 | aa0aa4fa | bellard | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 }, |
430 | aa0aa4fa | bellard | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 }, |
431 | aa0aa4fa | bellard | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 }, |
432 | aa0aa4fa | bellard | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */ |
433 | aa0aa4fa | bellard | |
434 | aa0aa4fa | bellard | { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 }, |
435 | aa0aa4fa | bellard | { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */ |
436 | aa0aa4fa | bellard | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 }, |
437 | aa0aa4fa | bellard | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 }, |
438 | aa0aa4fa | bellard | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, |
439 | aa0aa4fa | bellard | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */ |
440 | aa0aa4fa | bellard | |
441 | aa0aa4fa | bellard | { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 }, |
442 | aa0aa4fa | bellard | { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */ |
443 | aa0aa4fa | bellard | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 }, |
444 | aa0aa4fa | bellard | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 }, |
445 | aa0aa4fa | bellard | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 }, |
446 | aa0aa4fa | bellard | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */ |
447 | aa0aa4fa | bellard | |
448 | aa0aa4fa | bellard | { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
449 | aa0aa4fa | bellard | { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */ |
450 | aa0aa4fa | bellard | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 }, |
451 | aa0aa4fa | bellard | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 }, |
452 | aa0aa4fa | bellard | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 }, |
453 | aa0aa4fa | bellard | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */ |
454 | aa0aa4fa | bellard | |
455 | aa0aa4fa | bellard | { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */ |
456 | aa0aa4fa | bellard | { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
457 | aa0aa4fa | bellard | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 }, |
458 | aa0aa4fa | bellard | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 }, |
459 | aa0aa4fa | bellard | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 }, |
460 | aa0aa4fa | bellard | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */ |
461 | aa0aa4fa | bellard | |
462 | aa0aa4fa | bellard | { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
463 | aa0aa4fa | bellard | { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */ |
464 | aa0aa4fa | bellard | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 }, |
465 | aa0aa4fa | bellard | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 }, |
466 | aa0aa4fa | bellard | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 }, |
467 | aa0aa4fa | bellard | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */ |
468 | aa0aa4fa | bellard | |
469 | aa0aa4fa | bellard | { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 }, |
470 | aa0aa4fa | bellard | { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */ |
471 | aa0aa4fa | bellard | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 }, |
472 | aa0aa4fa | bellard | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 }, |
473 | aa0aa4fa | bellard | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 }, |
474 | aa0aa4fa | bellard | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */ |
475 | aa0aa4fa | bellard | |
476 | aa0aa4fa | bellard | { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
477 | aa0aa4fa | bellard | { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */ |
478 | aa0aa4fa | bellard | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 }, |
479 | aa0aa4fa | bellard | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 }, |
480 | aa0aa4fa | bellard | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 }, |
481 | aa0aa4fa | bellard | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */ |
482 | aa0aa4fa | bellard | |
483 | aa0aa4fa | bellard | { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
484 | aa0aa4fa | bellard | { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */ |
485 | aa0aa4fa | bellard | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 }, |
486 | aa0aa4fa | bellard | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 }, |
487 | aa0aa4fa | bellard | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 }, |
488 | aa0aa4fa | bellard | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */ |
489 | aa0aa4fa | bellard | |
490 | aa0aa4fa | bellard | { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 }, |
491 | aa0aa4fa | bellard | { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */ |
492 | aa0aa4fa | bellard | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 }, |
493 | aa0aa4fa | bellard | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 }, |
494 | aa0aa4fa | bellard | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 }, |
495 | aa0aa4fa | bellard | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */ |
496 | aa0aa4fa | bellard | |
497 | aa0aa4fa | bellard | { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 }, |
498 | aa0aa4fa | bellard | { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */ |
499 | aa0aa4fa | bellard | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 }, |
500 | aa0aa4fa | bellard | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 }, |
501 | aa0aa4fa | bellard | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 }, |
502 | aa0aa4fa | bellard | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */ |
503 | aa0aa4fa | bellard | |
504 | aa0aa4fa | bellard | { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, |
505 | aa0aa4fa | bellard | { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ |
506 | aa0aa4fa | bellard | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 }, |
507 | aa0aa4fa | bellard | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 }, |
508 | aa0aa4fa | bellard | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
509 | aa0aa4fa | bellard | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
510 | aa0aa4fa | bellard | { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 }, |
511 | aa0aa4fa | bellard | { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */ |
512 | aa0aa4fa | bellard | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 }, |
513 | aa0aa4fa | bellard | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 }, |
514 | aa0aa4fa | bellard | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 }, |
515 | aa0aa4fa | bellard | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */ |
516 | aa0aa4fa | bellard | |
517 | aa0aa4fa | bellard | { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 }, |
518 | aa0aa4fa | bellard | { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */ |
519 | aa0aa4fa | bellard | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 }, |
520 | aa0aa4fa | bellard | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 }, |
521 | aa0aa4fa | bellard | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
522 | aa0aa4fa | bellard | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
523 | aa0aa4fa | bellard | |
524 | aa0aa4fa | bellard | { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 }, |
525 | aa0aa4fa | bellard | { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */ |
526 | aa0aa4fa | bellard | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 }, |
527 | aa0aa4fa | bellard | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 }, |
528 | aa0aa4fa | bellard | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 }, |
529 | aa0aa4fa | bellard | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */ |
530 | aa0aa4fa | bellard | |
531 | aa0aa4fa | bellard | { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 }, |
532 | aa0aa4fa | bellard | { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */ |
533 | aa0aa4fa | bellard | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 }, |
534 | aa0aa4fa | bellard | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 }, |
535 | aa0aa4fa | bellard | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 }, |
536 | aa0aa4fa | bellard | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */ |
537 | aa0aa4fa | bellard | |
538 | aa0aa4fa | bellard | { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 }, |
539 | aa0aa4fa | bellard | { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */ |
540 | aa0aa4fa | bellard | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 }, |
541 | aa0aa4fa | bellard | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 }, |
542 | aa0aa4fa | bellard | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
543 | aa0aa4fa | bellard | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
544 | aa0aa4fa | bellard | |
545 | aa0aa4fa | bellard | { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 }, |
546 | aa0aa4fa | bellard | { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */ |
547 | aa0aa4fa | bellard | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 }, |
548 | aa0aa4fa | bellard | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 }, |
549 | aa0aa4fa | bellard | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
550 | aa0aa4fa | bellard | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
551 | aa0aa4fa | bellard | |
552 | aa0aa4fa | bellard | { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 }, |
553 | aa0aa4fa | bellard | { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */ |
554 | aa0aa4fa | bellard | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 }, |
555 | aa0aa4fa | bellard | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 }, |
556 | aa0aa4fa | bellard | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
557 | aa0aa4fa | bellard | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
558 | aa0aa4fa | bellard | |
559 | aa0aa4fa | bellard | { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 }, |
560 | aa0aa4fa | bellard | { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ |
561 | aa0aa4fa | bellard | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 }, |
562 | aa0aa4fa | bellard | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 }, |
563 | aa0aa4fa | bellard | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
564 | aa0aa4fa | bellard | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
565 | aa0aa4fa | bellard | |
566 | aa0aa4fa | bellard | { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 }, |
567 | aa0aa4fa | bellard | { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */ |
568 | aa0aa4fa | bellard | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 }, |
569 | aa0aa4fa | bellard | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 }, |
570 | aa0aa4fa | bellard | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
571 | aa0aa4fa | bellard | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
572 | aa0aa4fa | bellard | |
573 | aa0aa4fa | bellard | { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 }, |
574 | aa0aa4fa | bellard | { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */ |
575 | aa0aa4fa | bellard | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 }, |
576 | aa0aa4fa | bellard | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 }, |
577 | aa0aa4fa | bellard | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
578 | aa0aa4fa | bellard | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
579 | aa0aa4fa | bellard | |
580 | aa0aa4fa | bellard | { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */ |
581 | aa0aa4fa | bellard | { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */ |
582 | aa0aa4fa | bellard | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 }, |
583 | aa0aa4fa | bellard | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 }, |
584 | aa0aa4fa | bellard | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 }, |
585 | aa0aa4fa | bellard | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */ |
586 | aa0aa4fa | bellard | |
587 | aa0aa4fa | bellard | { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 }, |
588 | aa0aa4fa | bellard | { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ |
589 | aa0aa4fa | bellard | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 }, |
590 | aa0aa4fa | bellard | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 }, |
591 | aa0aa4fa | bellard | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
592 | aa0aa4fa | bellard | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
593 | aa0aa4fa | bellard | |
594 | aa0aa4fa | bellard | { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
595 | aa0aa4fa | bellard | { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */ |
596 | aa0aa4fa | bellard | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 }, |
597 | aa0aa4fa | bellard | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 }, |
598 | aa0aa4fa | bellard | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
599 | aa0aa4fa | bellard | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */ |
600 | aa0aa4fa | bellard | { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, |
601 | aa0aa4fa | bellard | { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */ |
602 | aa0aa4fa | bellard | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 }, |
603 | aa0aa4fa | bellard | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 }, |
604 | aa0aa4fa | bellard | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 }, |
605 | aa0aa4fa | bellard | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */ |
606 | aa0aa4fa | bellard | |
607 | aa0aa4fa | bellard | { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, |
608 | aa0aa4fa | bellard | { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ |
609 | aa0aa4fa | bellard | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 }, |
610 | aa0aa4fa | bellard | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 }, |
611 | aa0aa4fa | bellard | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, |
612 | aa0aa4fa | bellard | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ |
613 | aa0aa4fa | bellard | { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 }, |
614 | aa0aa4fa | bellard | { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ |
615 | aa0aa4fa | bellard | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 }, |
616 | aa0aa4fa | bellard | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 }, |
617 | aa0aa4fa | bellard | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 }, |
618 | aa0aa4fa | bellard | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ |
619 | aa0aa4fa | bellard | |
620 | aa0aa4fa | bellard | { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 }, |
621 | aa0aa4fa | bellard | { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */ |
622 | aa0aa4fa | bellard | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 }, |
623 | aa0aa4fa | bellard | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 }, |
624 | aa0aa4fa | bellard | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 }, |
625 | aa0aa4fa | bellard | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */ |
626 | aa0aa4fa | bellard | |
627 | aa0aa4fa | bellard | { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, |
628 | aa0aa4fa | bellard | { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
629 | aa0aa4fa | bellard | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, |
630 | aa0aa4fa | bellard | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, |
631 | aa0aa4fa | bellard | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, |
632 | aa0aa4fa | bellard | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
633 | aa0aa4fa | bellard | { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, |
634 | aa0aa4fa | bellard | { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
635 | aa0aa4fa | bellard | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, |
636 | aa0aa4fa | bellard | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, |
637 | aa0aa4fa | bellard | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, |
638 | aa0aa4fa | bellard | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
639 | aa0aa4fa | bellard | { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, |
640 | aa0aa4fa | bellard | { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
641 | aa0aa4fa | bellard | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, |
642 | aa0aa4fa | bellard | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, |
643 | aa0aa4fa | bellard | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, |
644 | aa0aa4fa | bellard | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
645 | aa0aa4fa | bellard | |
646 | aa0aa4fa | bellard | { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
647 | aa0aa4fa | bellard | { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */ |
648 | aa0aa4fa | bellard | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 }, |
649 | aa0aa4fa | bellard | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 }, |
650 | aa0aa4fa | bellard | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
651 | aa0aa4fa | bellard | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */ |
652 | aa0aa4fa | bellard | |
653 | aa0aa4fa | bellard | { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 }, |
654 | aa0aa4fa | bellard | { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */ |
655 | aa0aa4fa | bellard | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 }, |
656 | aa0aa4fa | bellard | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 }, |
657 | aa0aa4fa | bellard | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
658 | aa0aa4fa | bellard | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */ |
659 | aa0aa4fa | bellard | |
660 | aa0aa4fa | bellard | { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 }, |
661 | aa0aa4fa | bellard | { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */ |
662 | aa0aa4fa | bellard | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 }, |
663 | aa0aa4fa | bellard | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 }, |
664 | aa0aa4fa | bellard | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 }, |
665 | aa0aa4fa | bellard | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */ |
666 | aa0aa4fa | bellard | |
667 | aa0aa4fa | bellard | { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, |
668 | aa0aa4fa | bellard | { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
669 | aa0aa4fa | bellard | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
670 | aa0aa4fa | bellard | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
671 | aa0aa4fa | bellard | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
672 | aa0aa4fa | bellard | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
673 | aa0aa4fa | bellard | { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, |
674 | aa0aa4fa | bellard | { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
675 | aa0aa4fa | bellard | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
676 | aa0aa4fa | bellard | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
677 | aa0aa4fa | bellard | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
678 | aa0aa4fa | bellard | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
679 | aa0aa4fa | bellard | { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, |
680 | aa0aa4fa | bellard | { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
681 | aa0aa4fa | bellard | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
682 | aa0aa4fa | bellard | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
683 | aa0aa4fa | bellard | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
684 | aa0aa4fa | bellard | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
685 | aa0aa4fa | bellard | |
686 | aa0aa4fa | bellard | { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
687 | aa0aa4fa | bellard | { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */ |
688 | aa0aa4fa | bellard | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 }, |
689 | aa0aa4fa | bellard | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 }, |
690 | aa0aa4fa | bellard | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
691 | aa0aa4fa | bellard | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */ |
692 | aa0aa4fa | bellard | |
693 | aa0aa4fa | bellard | { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
694 | aa0aa4fa | bellard | { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ |
695 | aa0aa4fa | bellard | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, |
696 | aa0aa4fa | bellard | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, |
697 | aa0aa4fa | bellard | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
698 | aa0aa4fa | bellard | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ |
699 | aa0aa4fa | bellard | { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
700 | aa0aa4fa | bellard | { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ |
701 | aa0aa4fa | bellard | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, |
702 | aa0aa4fa | bellard | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, |
703 | aa0aa4fa | bellard | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
704 | aa0aa4fa | bellard | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ |
705 | aa0aa4fa | bellard | |
706 | aa0aa4fa | bellard | { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 }, |
707 | aa0aa4fa | bellard | { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */ |
708 | aa0aa4fa | bellard | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 }, |
709 | aa0aa4fa | bellard | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 }, |
710 | aa0aa4fa | bellard | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
711 | aa0aa4fa | bellard | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */ |
712 | aa0aa4fa | bellard | |
713 | aa0aa4fa | bellard | { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
714 | aa0aa4fa | bellard | { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ |
715 | aa0aa4fa | bellard | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
716 | aa0aa4fa | bellard | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
717 | aa0aa4fa | bellard | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
718 | aa0aa4fa | bellard | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ |
719 | aa0aa4fa | bellard | { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
720 | aa0aa4fa | bellard | { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ |
721 | aa0aa4fa | bellard | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
722 | aa0aa4fa | bellard | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
723 | aa0aa4fa | bellard | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
724 | aa0aa4fa | bellard | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ |
725 | aa0aa4fa | bellard | |
726 | aa0aa4fa | bellard | { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
727 | aa0aa4fa | bellard | { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */ |
728 | aa0aa4fa | bellard | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 }, |
729 | aa0aa4fa | bellard | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 }, |
730 | aa0aa4fa | bellard | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
731 | aa0aa4fa | bellard | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */ |
732 | aa0aa4fa | bellard | |
733 | aa0aa4fa | bellard | { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 }, |
734 | aa0aa4fa | bellard | { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ |
735 | aa0aa4fa | bellard | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 }, |
736 | aa0aa4fa | bellard | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 }, |
737 | aa0aa4fa | bellard | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 }, |
738 | aa0aa4fa | bellard | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ |
739 | aa0aa4fa | bellard | { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 }, |
740 | aa0aa4fa | bellard | { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */ |
741 | aa0aa4fa | bellard | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 }, |
742 | aa0aa4fa | bellard | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 }, |
743 | aa0aa4fa | bellard | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 }, |
744 | aa0aa4fa | bellard | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */ |
745 | aa0aa4fa | bellard | |
746 | aa0aa4fa | bellard | { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 }, |
747 | aa0aa4fa | bellard | { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ |
748 | aa0aa4fa | bellard | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 }, |
749 | aa0aa4fa | bellard | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 }, |
750 | aa0aa4fa | bellard | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 }, |
751 | aa0aa4fa | bellard | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ |
752 | aa0aa4fa | bellard | { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, |
753 | aa0aa4fa | bellard | { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ |
754 | aa0aa4fa | bellard | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 }, |
755 | aa0aa4fa | bellard | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 }, |
756 | aa0aa4fa | bellard | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, |
757 | aa0aa4fa | bellard | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ |
758 | aa0aa4fa | bellard | |
759 | aa0aa4fa | bellard | { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
760 | aa0aa4fa | bellard | { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */ |
761 | aa0aa4fa | bellard | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 }, |
762 | aa0aa4fa | bellard | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 }, |
763 | aa0aa4fa | bellard | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
764 | aa0aa4fa | bellard | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */ |
765 | aa0aa4fa | bellard | |
766 | aa0aa4fa | bellard | { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 }, |
767 | aa0aa4fa | bellard | { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */ |
768 | aa0aa4fa | bellard | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 }, |
769 | aa0aa4fa | bellard | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 }, |
770 | aa0aa4fa | bellard | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
771 | aa0aa4fa | bellard | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */ |
772 | aa0aa4fa | bellard | { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 }, |
773 | aa0aa4fa | bellard | { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */ |
774 | aa0aa4fa | bellard | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 }, |
775 | aa0aa4fa | bellard | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 }, |
776 | aa0aa4fa | bellard | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 }, |
777 | aa0aa4fa | bellard | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */ |
778 | aa0aa4fa | bellard | |
779 | aa0aa4fa | bellard | { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
780 | aa0aa4fa | bellard | { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */ |
781 | aa0aa4fa | bellard | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 }, |
782 | aa0aa4fa | bellard | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 }, |
783 | aa0aa4fa | bellard | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
784 | aa0aa4fa | bellard | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */ |
785 | aa0aa4fa | bellard | |
786 | aa0aa4fa | bellard | { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
787 | aa0aa4fa | bellard | { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ |
788 | aa0aa4fa | bellard | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, |
789 | aa0aa4fa | bellard | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, |
790 | aa0aa4fa | bellard | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
791 | aa0aa4fa | bellard | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ |
792 | aa0aa4fa | bellard | { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
793 | aa0aa4fa | bellard | { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ |
794 | aa0aa4fa | bellard | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, |
795 | aa0aa4fa | bellard | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, |
796 | aa0aa4fa | bellard | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
797 | aa0aa4fa | bellard | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ |
798 | aa0aa4fa | bellard | |
799 | aa0aa4fa | bellard | { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 }, |
800 | aa0aa4fa | bellard | { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */ |
801 | aa0aa4fa | bellard | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 }, |
802 | aa0aa4fa | bellard | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 }, |
803 | aa0aa4fa | bellard | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
804 | aa0aa4fa | bellard | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */ |
805 | aa0aa4fa | bellard | |
806 | aa0aa4fa | bellard | { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
807 | aa0aa4fa | bellard | { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ |
808 | aa0aa4fa | bellard | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
809 | aa0aa4fa | bellard | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
810 | aa0aa4fa | bellard | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
811 | aa0aa4fa | bellard | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ |
812 | aa0aa4fa | bellard | { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
813 | aa0aa4fa | bellard | { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ |
814 | aa0aa4fa | bellard | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
815 | aa0aa4fa | bellard | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
816 | aa0aa4fa | bellard | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
817 | aa0aa4fa | bellard | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ |
818 | aa0aa4fa | bellard | |
819 | aa0aa4fa | bellard | { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 }, |
820 | aa0aa4fa | bellard | { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ |
821 | aa0aa4fa | bellard | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 }, |
822 | aa0aa4fa | bellard | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 }, |
823 | aa0aa4fa | bellard | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 }, |
824 | aa0aa4fa | bellard | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */ |
825 | aa0aa4fa | bellard | |
826 | aa0aa4fa | bellard | { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 }, |
827 | aa0aa4fa | bellard | { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ |
828 | aa0aa4fa | bellard | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 }, |
829 | aa0aa4fa | bellard | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 }, |
830 | aa0aa4fa | bellard | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 }, |
831 | aa0aa4fa | bellard | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */ |
832 | aa0aa4fa | bellard | |
833 | aa0aa4fa | bellard | { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 }, |
834 | aa0aa4fa | bellard | { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */ |
835 | aa0aa4fa | bellard | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 }, |
836 | aa0aa4fa | bellard | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 }, |
837 | aa0aa4fa | bellard | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
838 | aa0aa4fa | bellard | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */ |
839 | aa0aa4fa | bellard | |
840 | aa0aa4fa | bellard | { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 }, |
841 | aa0aa4fa | bellard | { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */ |
842 | aa0aa4fa | bellard | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 }, |
843 | aa0aa4fa | bellard | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 }, |
844 | aa0aa4fa | bellard | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 }, |
845 | aa0aa4fa | bellard | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */ |
846 | aa0aa4fa | bellard | |
847 | aa0aa4fa | bellard | { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 }, |
848 | aa0aa4fa | bellard | { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */ |
849 | aa0aa4fa | bellard | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 }, |
850 | aa0aa4fa | bellard | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 }, |
851 | aa0aa4fa | bellard | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 }, |
852 | aa0aa4fa | bellard | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */ |
853 | aa0aa4fa | bellard | |
854 | aa0aa4fa | bellard | { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 }, |
855 | aa0aa4fa | bellard | { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */ |
856 | aa0aa4fa | bellard | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 }, |
857 | aa0aa4fa | bellard | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 }, |
858 | aa0aa4fa | bellard | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 }, |
859 | aa0aa4fa | bellard | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */ |
860 | aa0aa4fa | bellard | |
861 | aa0aa4fa | bellard | { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 }, |
862 | aa0aa4fa | bellard | { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */ |
863 | aa0aa4fa | bellard | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 }, |
864 | aa0aa4fa | bellard | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 }, |
865 | aa0aa4fa | bellard | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
866 | aa0aa4fa | bellard | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */ |
867 | aa0aa4fa | bellard | |
868 | aa0aa4fa | bellard | { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
869 | aa0aa4fa | bellard | { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */ |
870 | aa0aa4fa | bellard | { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 }, |
871 | aa0aa4fa | bellard | { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */ |
872 | aa0aa4fa | bellard | |
873 | aa0aa4fa | bellard | { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */ |
874 | aa0aa4fa | bellard | { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */ |
875 | aa0aa4fa | bellard | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */ |
876 | aa0aa4fa | bellard | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ |
877 | aa0aa4fa | bellard | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ |
878 | aa0aa4fa | bellard | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */ |
879 | aa0aa4fa | bellard | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */ |
880 | aa0aa4fa | bellard | |
881 | aa0aa4fa | bellard | { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
882 | aa0aa4fa | bellard | { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 }, |
883 | aa0aa4fa | bellard | { "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 }, |
884 | aa0aa4fa | bellard | |
885 | aa0aa4fa | bellard | { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ |
886 | aa0aa4fa | bellard | { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */ |
887 | aa0aa4fa | bellard | |
888 | aa0aa4fa | bellard | { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 }, |
889 | aa0aa4fa | bellard | { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ |
890 | aa0aa4fa | bellard | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */ |
891 | aa0aa4fa | bellard | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */ |
892 | aa0aa4fa | bellard | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 }, |
893 | aa0aa4fa | bellard | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 }, |
894 | aa0aa4fa | bellard | |
895 | aa0aa4fa | bellard | { "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
896 | aa0aa4fa | bellard | { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
897 | aa0aa4fa | bellard | { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
898 | aa0aa4fa | bellard | { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
899 | aa0aa4fa | bellard | { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 }, |
900 | aa0aa4fa | bellard | |
901 | aa0aa4fa | bellard | { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 }, |
902 | aa0aa4fa | bellard | { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */ |
903 | aa0aa4fa | bellard | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */ |
904 | aa0aa4fa | bellard | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */ |
905 | aa0aa4fa | bellard | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 }, |
906 | aa0aa4fa | bellard | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 }, |
907 | aa0aa4fa | bellard | |
908 | aa0aa4fa | bellard | /* IFLUSH was renamed to FLUSH in v8. */
|
909 | aa0aa4fa | bellard | { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 }, |
910 | aa0aa4fa | bellard | { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */ |
911 | aa0aa4fa | bellard | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */ |
912 | aa0aa4fa | bellard | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 }, |
913 | aa0aa4fa | bellard | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 }, |
914 | aa0aa4fa | bellard | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 }, |
915 | aa0aa4fa | bellard | |
916 | aa0aa4fa | bellard | { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 }, |
917 | aa0aa4fa | bellard | { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */ |
918 | aa0aa4fa | bellard | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */ |
919 | aa0aa4fa | bellard | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */ |
920 | aa0aa4fa | bellard | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 }, |
921 | aa0aa4fa | bellard | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 }, |
922 | aa0aa4fa | bellard | |
923 | aa0aa4fa | bellard | { "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 }, |
924 | aa0aa4fa | bellard | |
925 | aa0aa4fa | bellard | { "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 }, |
926 | aa0aa4fa | bellard | { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 }, |
927 | aa0aa4fa | bellard | |
928 | aa0aa4fa | bellard | { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 }, |
929 | aa0aa4fa | bellard | { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ |
930 | aa0aa4fa | bellard | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 }, |
931 | aa0aa4fa | bellard | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 }, |
932 | aa0aa4fa | bellard | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 }, |
933 | aa0aa4fa | bellard | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ |
934 | aa0aa4fa | bellard | { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 }, |
935 | aa0aa4fa | bellard | { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ |
936 | aa0aa4fa | bellard | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 }, |
937 | aa0aa4fa | bellard | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 }, |
938 | aa0aa4fa | bellard | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 }, |
939 | aa0aa4fa | bellard | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */ |
940 | aa0aa4fa | bellard | |
941 | aa0aa4fa | bellard | { "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, |
942 | aa0aa4fa | bellard | { "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, |
943 | aa0aa4fa | bellard | { "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, |
944 | aa0aa4fa | bellard | { "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, |
945 | aa0aa4fa | bellard | { "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, |
946 | aa0aa4fa | bellard | { "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, |
947 | aa0aa4fa | bellard | |
948 | aa0aa4fa | bellard | { "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, |
949 | aa0aa4fa | bellard | { "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, |
950 | aa0aa4fa | bellard | { "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, |
951 | aa0aa4fa | bellard | { "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, |
952 | aa0aa4fa | bellard | { "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, |
953 | aa0aa4fa | bellard | { "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, |
954 | aa0aa4fa | bellard | |
955 | aa0aa4fa | bellard | { "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
956 | aa0aa4fa | bellard | { "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 }, |
957 | aa0aa4fa | bellard | |
958 | aa0aa4fa | bellard | { "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite }, |
959 | aa0aa4fa | bellard | { "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite }, |
960 | aa0aa4fa | bellard | |
961 | aa0aa4fa | bellard | { "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite }, |
962 | aa0aa4fa | bellard | { "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite }, |
963 | aa0aa4fa | bellard | |
964 | aa0aa4fa | bellard | { "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 }, |
965 | aa0aa4fa | bellard | { "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 }, |
966 | aa0aa4fa | bellard | |
967 | aa0aa4fa | bellard | { "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */ |
968 | aa0aa4fa | bellard | { "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */ |
969 | aa0aa4fa | bellard | { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, |
970 | aa0aa4fa | bellard | { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ |
971 | aa0aa4fa | bellard | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, |
972 | aa0aa4fa | bellard | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, |
973 | aa0aa4fa | bellard | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, |
974 | aa0aa4fa | bellard | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */ |
975 | aa0aa4fa | bellard | |
976 | aa0aa4fa | bellard | { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, |
977 | aa0aa4fa | bellard | { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ |
978 | aa0aa4fa | bellard | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, |
979 | aa0aa4fa | bellard | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, |
980 | aa0aa4fa | bellard | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, |
981 | aa0aa4fa | bellard | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */ |
982 | aa0aa4fa | bellard | |
983 | aa0aa4fa | bellard | { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, |
984 | aa0aa4fa | bellard | { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ |
985 | aa0aa4fa | bellard | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, |
986 | aa0aa4fa | bellard | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, |
987 | aa0aa4fa | bellard | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, |
988 | aa0aa4fa | bellard | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */ |
989 | aa0aa4fa | bellard | |
990 | aa0aa4fa | bellard | { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 }, |
991 | aa0aa4fa | bellard | { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */ |
992 | aa0aa4fa | bellard | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 }, |
993 | aa0aa4fa | bellard | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 }, |
994 | aa0aa4fa | bellard | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 }, |
995 | aa0aa4fa | bellard | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */ |
996 | aa0aa4fa | bellard | |
997 | aa0aa4fa | bellard | { "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
998 | aa0aa4fa | bellard | { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 }, |
999 | aa0aa4fa | bellard | { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 }, |
1000 | aa0aa4fa | bellard | |
1001 | aa0aa4fa | bellard | /* This is not a commutative instruction. */
|
1002 | aa0aa4fa | bellard | { "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1003 | aa0aa4fa | bellard | { "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 }, |
1004 | aa0aa4fa | bellard | |
1005 | aa0aa4fa | bellard | /* This is not a commutative instruction. */
|
1006 | aa0aa4fa | bellard | { "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1007 | aa0aa4fa | bellard | { "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 }, |
1008 | aa0aa4fa | bellard | |
1009 | aa0aa4fa | bellard | { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */ |
1010 | aa0aa4fa | bellard | { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */ |
1011 | aa0aa4fa | bellard | { "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */ |
1012 | aa0aa4fa | bellard | |
1013 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ |
1014 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ |
1015 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ |
1016 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ |
1017 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ |
1018 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ |
1019 | aa0aa4fa | bellard | { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */ |
1020 | aa0aa4fa | bellard | { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */ |
1021 | aa0aa4fa | bellard | { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ |
1022 | aa0aa4fa | bellard | { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */ |
1023 | aa0aa4fa | bellard | { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */ |
1024 | aa0aa4fa | bellard | { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ |
1025 | aa0aa4fa | bellard | { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */ |
1026 | aa0aa4fa | bellard | { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */ |
1027 | aa0aa4fa | bellard | { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ |
1028 | aa0aa4fa | bellard | |
1029 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */ |
1030 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */ |
1031 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */ |
1032 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */ |
1033 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */ |
1034 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */ |
1035 | aa0aa4fa | bellard | |
1036 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */ |
1037 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */ |
1038 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */ |
1039 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */ |
1040 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */ |
1041 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */ |
1042 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */ |
1043 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */ |
1044 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */ |
1045 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */ |
1046 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */ |
1047 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */ |
1048 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */ |
1049 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */ |
1050 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */ |
1051 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */ |
1052 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */ |
1053 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */ |
1054 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */ |
1055 | aa0aa4fa | bellard | { "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */ |
1056 | aa0aa4fa | bellard | |
1057 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */ |
1058 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ |
1059 | aa0aa4fa | bellard | { "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */ |
1060 | aa0aa4fa | bellard | { "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */ |
1061 | aa0aa4fa | bellard | { "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */ |
1062 | aa0aa4fa | bellard | |
1063 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */ |
1064 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */ |
1065 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */ |
1066 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */ |
1067 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */ |
1068 | aa0aa4fa | bellard | |
1069 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */ |
1070 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */ |
1071 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */ |
1072 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */ |
1073 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */ |
1074 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */ |
1075 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */ |
1076 | aa0aa4fa | bellard | { "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */ |
1077 | aa0aa4fa | bellard | |
1078 | aa0aa4fa | bellard | { "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */ |
1079 | aa0aa4fa | bellard | { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */ |
1080 | aa0aa4fa | bellard | { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */ |
1081 | aa0aa4fa | bellard | { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */ |
1082 | aa0aa4fa | bellard | { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */ |
1083 | aa0aa4fa | bellard | { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */ |
1084 | aa0aa4fa | bellard | |
1085 | aa0aa4fa | bellard | /* ??? This group seems wrong. A three operand move? */
|
1086 | aa0aa4fa | bellard | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ |
1087 | aa0aa4fa | bellard | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ |
1088 | aa0aa4fa | bellard | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */ |
1089 | aa0aa4fa | bellard | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */ |
1090 | aa0aa4fa | bellard | { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */ |
1091 | aa0aa4fa | bellard | { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */ |
1092 | aa0aa4fa | bellard | { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */ |
1093 | aa0aa4fa | bellard | { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */ |
1094 | aa0aa4fa | bellard | { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */ |
1095 | aa0aa4fa | bellard | { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */ |
1096 | aa0aa4fa | bellard | |
1097 | aa0aa4fa | bellard | { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */ |
1098 | aa0aa4fa | bellard | { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */ |
1099 | aa0aa4fa | bellard | { "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */ |
1100 | aa0aa4fa | bellard | { "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */ |
1101 | aa0aa4fa | bellard | { "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */ |
1102 | aa0aa4fa | bellard | |
1103 | aa0aa4fa | bellard | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ |
1104 | aa0aa4fa | bellard | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */ |
1105 | aa0aa4fa | bellard | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */ |
1106 | aa0aa4fa | bellard | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ |
1107 | aa0aa4fa | bellard | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */ |
1108 | aa0aa4fa | bellard | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */ |
1109 | aa0aa4fa | bellard | { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ |
1110 | aa0aa4fa | bellard | { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */ |
1111 | aa0aa4fa | bellard | { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */ |
1112 | aa0aa4fa | bellard | { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ |
1113 | aa0aa4fa | bellard | { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */ |
1114 | aa0aa4fa | bellard | { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */ |
1115 | aa0aa4fa | bellard | { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ |
1116 | aa0aa4fa | bellard | { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */ |
1117 | aa0aa4fa | bellard | { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */ |
1118 | aa0aa4fa | bellard | |
1119 | aa0aa4fa | bellard | { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */ |
1120 | aa0aa4fa | bellard | { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */ |
1121 | aa0aa4fa | bellard | { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */ |
1122 | aa0aa4fa | bellard | { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */ |
1123 | aa0aa4fa | bellard | |
1124 | aa0aa4fa | bellard | { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1125 | aa0aa4fa | bellard | { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 }, |
1126 | aa0aa4fa | bellard | { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 }, |
1127 | aa0aa4fa | bellard | |
1128 | aa0aa4fa | bellard | { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */ |
1129 | aa0aa4fa | bellard | { "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */ |
1130 | aa0aa4fa | bellard | |
1131 | aa0aa4fa | bellard | /* This is not a commutative instruction. */
|
1132 | aa0aa4fa | bellard | { "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1133 | aa0aa4fa | bellard | { "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 }, |
1134 | aa0aa4fa | bellard | |
1135 | aa0aa4fa | bellard | /* This is not a commutative instruction. */
|
1136 | aa0aa4fa | bellard | { "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1137 | aa0aa4fa | bellard | { "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 }, |
1138 | aa0aa4fa | bellard | |
1139 | aa0aa4fa | bellard | { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */ |
1140 | aa0aa4fa | bellard | { "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */ |
1141 | aa0aa4fa | bellard | |
1142 | aa0aa4fa | bellard | { "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */ |
1143 | aa0aa4fa | bellard | { "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */ |
1144 | aa0aa4fa | bellard | |
1145 | aa0aa4fa | bellard | { "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1146 | aa0aa4fa | bellard | { "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 }, |
1147 | aa0aa4fa | bellard | |
1148 | aa0aa4fa | bellard | { "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1149 | aa0aa4fa | bellard | { "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 }, |
1150 | aa0aa4fa | bellard | |
1151 | aa0aa4fa | bellard | { "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
1152 | aa0aa4fa | bellard | { "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 }, |
1153 | aa0aa4fa | bellard | { "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1154 | aa0aa4fa | bellard | { "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 }, |
1155 | aa0aa4fa | bellard | |
1156 | aa0aa4fa | bellard | { "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
1157 | aa0aa4fa | bellard | { "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 }, |
1158 | aa0aa4fa | bellard | { "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1159 | aa0aa4fa | bellard | { "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 }, |
1160 | aa0aa4fa | bellard | |
1161 | aa0aa4fa | bellard | { "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1162 | aa0aa4fa | bellard | { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 }, |
1163 | aa0aa4fa | bellard | { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 }, |
1164 | aa0aa4fa | bellard | |
1165 | aa0aa4fa | bellard | { "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1166 | aa0aa4fa | bellard | { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 }, |
1167 | aa0aa4fa | bellard | { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 }, |
1168 | aa0aa4fa | bellard | |
1169 | aa0aa4fa | bellard | { "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */ |
1170 | aa0aa4fa | bellard | { "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */ |
1171 | aa0aa4fa | bellard | { "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */ |
1172 | aa0aa4fa | bellard | { "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */ |
1173 | aa0aa4fa | bellard | { "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */ |
1174 | aa0aa4fa | bellard | { "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */ |
1175 | aa0aa4fa | bellard | { "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */ |
1176 | aa0aa4fa | bellard | { "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */ |
1177 | aa0aa4fa | bellard | |
1178 | aa0aa4fa | bellard | { "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ |
1179 | aa0aa4fa | bellard | { "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ |
1180 | aa0aa4fa | bellard | |
1181 | aa0aa4fa | bellard | { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */ |
1182 | aa0aa4fa | bellard | { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */ |
1183 | aa0aa4fa | bellard | |
1184 | aa0aa4fa | bellard | { "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1185 | aa0aa4fa | bellard | { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 }, |
1186 | aa0aa4fa | bellard | { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 }, |
1187 | aa0aa4fa | bellard | { "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1188 | aa0aa4fa | bellard | { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 }, |
1189 | aa0aa4fa | bellard | { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 }, |
1190 | aa0aa4fa | bellard | |
1191 | aa0aa4fa | bellard | { "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
1192 | aa0aa4fa | bellard | { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 }, |
1193 | aa0aa4fa | bellard | { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 }, |
1194 | aa0aa4fa | bellard | { "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1195 | aa0aa4fa | bellard | { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 }, |
1196 | aa0aa4fa | bellard | { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 }, |
1197 | aa0aa4fa | bellard | |
1198 | aa0aa4fa | bellard | { "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
1199 | aa0aa4fa | bellard | { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 }, |
1200 | aa0aa4fa | bellard | { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 }, |
1201 | aa0aa4fa | bellard | { "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1202 | aa0aa4fa | bellard | { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 }, |
1203 | aa0aa4fa | bellard | { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 }, |
1204 | aa0aa4fa | bellard | |
1205 | aa0aa4fa | bellard | { "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1206 | aa0aa4fa | bellard | { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 }, |
1207 | aa0aa4fa | bellard | { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 }, |
1208 | aa0aa4fa | bellard | { "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1209 | aa0aa4fa | bellard | { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 }, |
1210 | aa0aa4fa | bellard | { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 }, |
1211 | aa0aa4fa | bellard | { "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1212 | aa0aa4fa | bellard | { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 }, |
1213 | aa0aa4fa | bellard | { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 }, |
1214 | aa0aa4fa | bellard | { "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1215 | aa0aa4fa | bellard | { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 }, |
1216 | aa0aa4fa | bellard | { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 }, |
1217 | aa0aa4fa | bellard | { "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1218 | aa0aa4fa | bellard | { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 }, |
1219 | aa0aa4fa | bellard | { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 }, |
1220 | aa0aa4fa | bellard | { "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1221 | aa0aa4fa | bellard | { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 }, |
1222 | aa0aa4fa | bellard | { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 }, |
1223 | aa0aa4fa | bellard | { "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1224 | aa0aa4fa | bellard | { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 }, |
1225 | aa0aa4fa | bellard | { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 }, |
1226 | aa0aa4fa | bellard | { "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1227 | aa0aa4fa | bellard | { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 }, |
1228 | aa0aa4fa | bellard | { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 }, |
1229 | aa0aa4fa | bellard | |
1230 | aa0aa4fa | bellard | { "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1231 | aa0aa4fa | bellard | { "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 }, |
1232 | aa0aa4fa | bellard | { "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1233 | aa0aa4fa | bellard | { "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 }, |
1234 | aa0aa4fa | bellard | { "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1235 | aa0aa4fa | bellard | { "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 }, |
1236 | aa0aa4fa | bellard | |
1237 | aa0aa4fa | bellard | { "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 }, |
1238 | aa0aa4fa | bellard | { "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 }, |
1239 | aa0aa4fa | bellard | |
1240 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */ |
1241 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 }, |
1242 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */ |
1243 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 }, |
1244 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */ |
1245 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 }, |
1246 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */ |
1247 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 }, |
1248 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */ |
1249 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 }, |
1250 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ |
1251 | aa0aa4fa | bellard | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 }, |
1252 | aa0aa4fa | bellard | |
1253 | aa0aa4fa | bellard | |
1254 | aa0aa4fa | bellard | /* Conditional instructions.
|
1255 | aa0aa4fa | bellard | |
1256 | aa0aa4fa | bellard | Because this part of the table was such a mess earlier, I have
|
1257 | aa0aa4fa | bellard | macrofied it so that all the branches and traps are generated from
|
1258 | aa0aa4fa | bellard | a single-line description of each condition value. John Gilmore. */
|
1259 | aa0aa4fa | bellard | |
1260 | aa0aa4fa | bellard | /* Define branches -- one annulled, one without, etc. */
|
1261 | aa0aa4fa | bellard | #define br(opcode, mask, lose, flags) \
|
1262 | aa0aa4fa | bellard | { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \
|
1263 | aa0aa4fa | bellard | { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 }
|
1264 | aa0aa4fa | bellard | |
1265 | aa0aa4fa | bellard | #define brx(opcode, mask, lose, flags) /* v9 */ \ |
1266 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \ |
1267 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \ |
1268 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \ |
1269 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \ |
1270 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \ |
1271 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \ |
1272 | aa0aa4fa | bellard | { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \ |
1273 | aa0aa4fa | bellard | { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \ |
1274 | aa0aa4fa | bellard | { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \ |
1275 | aa0aa4fa | bellard | { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \ |
1276 | aa0aa4fa | bellard | { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \ |
1277 | aa0aa4fa | bellard | { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 } |
1278 | aa0aa4fa | bellard | |
1279 | aa0aa4fa | bellard | /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
|
1280 | aa0aa4fa | bellard | #define tr(opcode, mask, lose, flags) \
|
1281 | aa0aa4fa | bellard | { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ |
1282 | aa0aa4fa | bellard | { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ |
1283 | aa0aa4fa | bellard | { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ |
1284 | aa0aa4fa | bellard | { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ |
1285 | aa0aa4fa | bellard | { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ |
1286 | aa0aa4fa | bellard | { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ |
1287 | aa0aa4fa | bellard | { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ |
1288 | aa0aa4fa | bellard | { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ |
1289 | aa0aa4fa | bellard | { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ |
1290 | aa0aa4fa | bellard | { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ |
1291 | aa0aa4fa | bellard | { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ |
1292 | aa0aa4fa | bellard | { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ |
1293 | aa0aa4fa | bellard | |
1294 | aa0aa4fa | bellard | /* v9: We must put `brx' before `br', to ensure that we never match something
|
1295 | aa0aa4fa | bellard | v9: against an expression unless it is an expression. Otherwise, we end
|
1296 | aa0aa4fa | bellard | v9: up with undefined symbol tables entries, because they get added, but
|
1297 | aa0aa4fa | bellard | v9: are not deleted if the pattern fails to match. */
|
1298 | aa0aa4fa | bellard | |
1299 | aa0aa4fa | bellard | /* Define both branches and traps based on condition mask */
|
1300 | aa0aa4fa | bellard | #define cond(bop, top, mask, flags) \
|
1301 | aa0aa4fa | bellard | brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ |
1302 | aa0aa4fa | bellard | br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ |
1303 | aa0aa4fa | bellard | tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) |
1304 | aa0aa4fa | bellard | |
1305 | aa0aa4fa | bellard | /* Define all the conditions, all the branches, all the traps. */
|
1306 | aa0aa4fa | bellard | |
1307 | aa0aa4fa | bellard | /* Standard branch, trap mnemonics */
|
1308 | aa0aa4fa | bellard | cond ("b", "ta", CONDA, F_UNBR), |
1309 | aa0aa4fa | bellard | /* Alternative form (just for assembly, not for disassembly) */
|
1310 | aa0aa4fa | bellard | cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), |
1311 | aa0aa4fa | bellard | |
1312 | aa0aa4fa | bellard | cond ("bcc", "tcc", CONDCC, F_CONDBR), |
1313 | aa0aa4fa | bellard | cond ("bcs", "tcs", CONDCS, F_CONDBR), |
1314 | aa0aa4fa | bellard | cond ("be", "te", CONDE, F_CONDBR), |
1315 | aa0aa4fa | bellard | cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), |
1316 | aa0aa4fa | bellard | cond ("bg", "tg", CONDG, F_CONDBR), |
1317 | aa0aa4fa | bellard | cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), |
1318 | aa0aa4fa | bellard | cond ("bge", "tge", CONDGE, F_CONDBR), |
1319 | aa0aa4fa | bellard | cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ |
1320 | aa0aa4fa | bellard | cond ("bgu", "tgu", CONDGU, F_CONDBR), |
1321 | aa0aa4fa | bellard | cond ("bl", "tl", CONDL, F_CONDBR), |
1322 | aa0aa4fa | bellard | cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), |
1323 | aa0aa4fa | bellard | cond ("ble", "tle", CONDLE, F_CONDBR), |
1324 | aa0aa4fa | bellard | cond ("bleu", "tleu", CONDLEU, F_CONDBR), |
1325 | aa0aa4fa | bellard | cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ |
1326 | aa0aa4fa | bellard | cond ("bn", "tn", CONDN, F_CONDBR), |
1327 | aa0aa4fa | bellard | cond ("bne", "tne", CONDNE, F_CONDBR), |
1328 | aa0aa4fa | bellard | cond ("bneg", "tneg", CONDNEG, F_CONDBR), |
1329 | aa0aa4fa | bellard | cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ |
1330 | aa0aa4fa | bellard | cond ("bpos", "tpos", CONDPOS, F_CONDBR), |
1331 | aa0aa4fa | bellard | cond ("bvc", "tvc", CONDVC, F_CONDBR), |
1332 | aa0aa4fa | bellard | cond ("bvs", "tvs", CONDVS, F_CONDBR), |
1333 | aa0aa4fa | bellard | cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ |
1334 | aa0aa4fa | bellard | |
1335 | aa0aa4fa | bellard | #undef cond
|
1336 | aa0aa4fa | bellard | #undef br
|
1337 | aa0aa4fa | bellard | #undef brr /* v9 */ |
1338 | aa0aa4fa | bellard | #undef tr
|
1339 | aa0aa4fa | bellard | |
1340 | aa0aa4fa | bellard | #define brr(opcode, mask, lose, flags) /* v9 */ \ |
1341 | aa0aa4fa | bellard | { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \
|
1342 | aa0aa4fa | bellard | { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \
|
1343 | aa0aa4fa | bellard | { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \
|
1344 | aa0aa4fa | bellard | { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
|
1345 | aa0aa4fa | bellard | { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \
|
1346 | aa0aa4fa | bellard | { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
|
1347 | aa0aa4fa | bellard | |
1348 | aa0aa4fa | bellard | #define condr(bop, mask, flags) /* v9 */ \ |
1349 | aa0aa4fa | bellard | brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ |
1350 | aa0aa4fa | bellard | |
1351 | aa0aa4fa | bellard | /* v9 */ condr("brnz", 0x5, F_CONDBR), |
1352 | aa0aa4fa | bellard | /* v9 */ condr("brz", 0x1, F_CONDBR), |
1353 | aa0aa4fa | bellard | /* v9 */ condr("brgez", 0x7, F_CONDBR), |
1354 | aa0aa4fa | bellard | /* v9 */ condr("brlz", 0x3, F_CONDBR), |
1355 | aa0aa4fa | bellard | /* v9 */ condr("brlez", 0x2, F_CONDBR), |
1356 | aa0aa4fa | bellard | /* v9 */ condr("brgz", 0x6, F_CONDBR), |
1357 | aa0aa4fa | bellard | |
1358 | aa0aa4fa | bellard | #undef condr /* v9 */ |
1359 | aa0aa4fa | bellard | #undef brr /* v9 */ |
1360 | aa0aa4fa | bellard | |
1361 | aa0aa4fa | bellard | #define movr(opcode, mask, flags) /* v9 */ \ |
1362 | aa0aa4fa | bellard | { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \ |
1363 | aa0aa4fa | bellard | { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 } |
1364 | aa0aa4fa | bellard | |
1365 | aa0aa4fa | bellard | #define fmrrs(opcode, mask, lose, flags) /* v9 */ \ |
1366 | aa0aa4fa | bellard | { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 }
|
1367 | aa0aa4fa | bellard | #define fmrrd(opcode, mask, lose, flags) /* v9 */ \ |
1368 | aa0aa4fa | bellard | { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 }
|
1369 | aa0aa4fa | bellard | #define fmrrq(opcode, mask, lose, flags) /* v9 */ \ |
1370 | aa0aa4fa | bellard | { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
|
1371 | aa0aa4fa | bellard | |
1372 | aa0aa4fa | bellard | #define fmovrs(mop, mask, flags) /* v9 */ \ |
1373 | aa0aa4fa | bellard | fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ |
1374 | aa0aa4fa | bellard | #define fmovrd(mop, mask, flags) /* v9 */ \ |
1375 | aa0aa4fa | bellard | fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ |
1376 | aa0aa4fa | bellard | #define fmovrq(mop, mask, flags) /* v9 */ \ |
1377 | aa0aa4fa | bellard | fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ |
1378 | aa0aa4fa | bellard | |
1379 | aa0aa4fa | bellard | /* v9 */ movr("movrne", 0x5, 0), |
1380 | aa0aa4fa | bellard | /* v9 */ movr("movre", 0x1, 0), |
1381 | aa0aa4fa | bellard | /* v9 */ movr("movrgez", 0x7, 0), |
1382 | aa0aa4fa | bellard | /* v9 */ movr("movrlz", 0x3, 0), |
1383 | aa0aa4fa | bellard | /* v9 */ movr("movrlez", 0x2, 0), |
1384 | aa0aa4fa | bellard | /* v9 */ movr("movrgz", 0x6, 0), |
1385 | aa0aa4fa | bellard | /* v9 */ movr("movrnz", 0x5, F_ALIAS), |
1386 | aa0aa4fa | bellard | /* v9 */ movr("movrz", 0x1, F_ALIAS), |
1387 | aa0aa4fa | bellard | |
1388 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrsne", 0x5, 0), |
1389 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrse", 0x1, 0), |
1390 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrsgez", 0x7, 0), |
1391 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrslz", 0x3, 0), |
1392 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrslez", 0x2, 0), |
1393 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrsgz", 0x6, 0), |
1394 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS), |
1395 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS), |
1396 | aa0aa4fa | bellard | |
1397 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdne", 0x5, 0), |
1398 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrde", 0x1, 0), |
1399 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdgez", 0x7, 0), |
1400 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdlz", 0x3, 0), |
1401 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdlez", 0x2, 0), |
1402 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdgz", 0x6, 0), |
1403 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS), |
1404 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS), |
1405 | aa0aa4fa | bellard | |
1406 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqne", 0x5, 0), |
1407 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqe", 0x1, 0), |
1408 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqgez", 0x7, 0), |
1409 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqlz", 0x3, 0), |
1410 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqlez", 0x2, 0), |
1411 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqgz", 0x6, 0), |
1412 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS), |
1413 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS), |
1414 | aa0aa4fa | bellard | |
1415 | aa0aa4fa | bellard | #undef movr /* v9 */ |
1416 | aa0aa4fa | bellard | #undef fmovr /* v9 */ |
1417 | aa0aa4fa | bellard | #undef fmrr /* v9 */ |
1418 | aa0aa4fa | bellard | |
1419 | aa0aa4fa | bellard | #define movicc(opcode, cond, flags) /* v9 */ \ |
1420 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \ |
1421 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \ |
1422 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \ |
1423 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 } |
1424 | aa0aa4fa | bellard | |
1425 | aa0aa4fa | bellard | #define movfcc(opcode, fcond, flags) /* v9 */ \ |
1426 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \ |
1427 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \ |
1428 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \ |
1429 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \ |
1430 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \ |
1431 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \ |
1432 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \ |
1433 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 } |
1434 | aa0aa4fa | bellard | |
1435 | aa0aa4fa | bellard | #define movcc(opcode, cond, fcond, flags) /* v9 */ \ |
1436 | aa0aa4fa | bellard | movfcc (opcode, fcond, flags), /* v9 */ \
|
1437 | aa0aa4fa | bellard | movicc (opcode, cond, flags) /* v9 */
|
1438 | aa0aa4fa | bellard | |
1439 | aa0aa4fa | bellard | /* v9 */ movcc ("mova", CONDA, FCONDA, 0), |
1440 | aa0aa4fa | bellard | /* v9 */ movicc ("movcc", CONDCC, 0), |
1441 | aa0aa4fa | bellard | /* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), |
1442 | aa0aa4fa | bellard | /* v9 */ movicc ("movcs", CONDCS, 0), |
1443 | aa0aa4fa | bellard | /* v9 */ movicc ("movlu", CONDLU, F_ALIAS), |
1444 | aa0aa4fa | bellard | /* v9 */ movcc ("move", CONDE, FCONDE, 0), |
1445 | aa0aa4fa | bellard | /* v9 */ movcc ("movg", CONDG, FCONDG, 0), |
1446 | aa0aa4fa | bellard | /* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), |
1447 | aa0aa4fa | bellard | /* v9 */ movicc ("movgu", CONDGU, 0), |
1448 | aa0aa4fa | bellard | /* v9 */ movcc ("movl", CONDL, FCONDL, 0), |
1449 | aa0aa4fa | bellard | /* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), |
1450 | aa0aa4fa | bellard | /* v9 */ movicc ("movleu", CONDLEU, 0), |
1451 | aa0aa4fa | bellard | /* v9 */ movfcc ("movlg", FCONDLG, 0), |
1452 | aa0aa4fa | bellard | /* v9 */ movcc ("movn", CONDN, FCONDN, 0), |
1453 | aa0aa4fa | bellard | /* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), |
1454 | aa0aa4fa | bellard | /* v9 */ movicc ("movneg", CONDNEG, 0), |
1455 | aa0aa4fa | bellard | /* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), |
1456 | aa0aa4fa | bellard | /* v9 */ movfcc ("movo", FCONDO, 0), |
1457 | aa0aa4fa | bellard | /* v9 */ movicc ("movpos", CONDPOS, 0), |
1458 | aa0aa4fa | bellard | /* v9 */ movfcc ("movu", FCONDU, 0), |
1459 | aa0aa4fa | bellard | /* v9 */ movfcc ("movue", FCONDUE, 0), |
1460 | aa0aa4fa | bellard | /* v9 */ movfcc ("movug", FCONDUG, 0), |
1461 | aa0aa4fa | bellard | /* v9 */ movfcc ("movuge", FCONDUGE, 0), |
1462 | aa0aa4fa | bellard | /* v9 */ movfcc ("movul", FCONDUL, 0), |
1463 | aa0aa4fa | bellard | /* v9 */ movfcc ("movule", FCONDULE, 0), |
1464 | aa0aa4fa | bellard | /* v9 */ movicc ("movvc", CONDVC, 0), |
1465 | aa0aa4fa | bellard | /* v9 */ movicc ("movvs", CONDVS, 0), |
1466 | aa0aa4fa | bellard | /* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), |
1467 | aa0aa4fa | bellard | |
1468 | aa0aa4fa | bellard | #undef movicc /* v9 */ |
1469 | aa0aa4fa | bellard | #undef movfcc /* v9 */ |
1470 | aa0aa4fa | bellard | #undef movcc /* v9 */ |
1471 | aa0aa4fa | bellard | |
1472 | aa0aa4fa | bellard | #define FM_SF 1 /* v9 - values for fpsize */ |
1473 | aa0aa4fa | bellard | #define FM_DF 2 /* v9 */ |
1474 | aa0aa4fa | bellard | #define FM_QF 3 /* v9 */ |
1475 | aa0aa4fa | bellard | |
1476 | aa0aa4fa | bellard | #define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \ |
1477 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \ |
1478 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags, v9 } |
1479 | aa0aa4fa | bellard | |
1480 | aa0aa4fa | bellard | #define fmovfcc(opcode, fpsize, fcond, flags) /* v9 */ \ |
1481 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \ |
1482 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \ |
1483 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \ |
1484 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 } |
1485 | aa0aa4fa | bellard | |
1486 | aa0aa4fa | bellard | /* FIXME: use fmovicc/fmovfcc? */ /* v9 */ |
1487 | aa0aa4fa | bellard | #define fmovcc(opcode, fpsize, cond, fcond, flags) /* v9 */ \ |
1488 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags | F_FLOAT, v9 }, \ |
1489 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags | F_FLOAT, v9 }, \ |
1490 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags | F_FLOAT, v9 }, \ |
1491 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags | F_FLOAT, v9 }, \ |
1492 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags | F_FLOAT, v9 }, \ |
1493 | aa0aa4fa | bellard | { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags | F_FLOAT, v9 } |
1494 | aa0aa4fa | bellard | |
1495 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovda", FM_DF, CONDA, FCONDA, 0), |
1496 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovqa", FM_QF, CONDA, FCONDA, 0), |
1497 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovsa", FM_SF, CONDA, FCONDA, 0), |
1498 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovdcc", FM_DF, CONDCC, 0), |
1499 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovqcc", FM_QF, CONDCC, 0), |
1500 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovscc", FM_SF, CONDCC, 0), |
1501 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovdcs", FM_DF, CONDCS, 0), |
1502 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovqcs", FM_QF, CONDCS, 0), |
1503 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovscs", FM_SF, CONDCS, 0), |
1504 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovde", FM_DF, CONDE, FCONDE, 0), |
1505 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovqe", FM_QF, CONDE, FCONDE, 0), |
1506 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovse", FM_SF, CONDE, FCONDE, 0), |
1507 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovdg", FM_DF, CONDG, FCONDG, 0), |
1508 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovqg", FM_QF, CONDG, FCONDG, 0), |
1509 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovsg", FM_SF, CONDG, FCONDG, 0), |
1510 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovdge", FM_DF, CONDGE, FCONDGE, 0), |
1511 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovqge", FM_QF, CONDGE, FCONDGE, 0), |
1512 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovsge", FM_SF, CONDGE, FCONDGE, 0), |
1513 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovdgeu", FM_DF, CONDGEU, F_ALIAS), |
1514 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovqgeu", FM_QF, CONDGEU, F_ALIAS), |
1515 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovsgeu", FM_SF, CONDGEU, F_ALIAS), |
1516 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovdgu", FM_DF, CONDGU, 0), |
1517 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovqgu", FM_QF, CONDGU, 0), |
1518 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovsgu", FM_SF, CONDGU, 0), |
1519 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovdl", FM_DF, CONDL, FCONDL, 0), |
1520 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovql", FM_QF, CONDL, FCONDL, 0), |
1521 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovsl", FM_SF, CONDL, FCONDL, 0), |
1522 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovdle", FM_DF, CONDLE, FCONDLE, 0), |
1523 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovqle", FM_QF, CONDLE, FCONDLE, 0), |
1524 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovsle", FM_SF, CONDLE, FCONDLE, 0), |
1525 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovdleu", FM_DF, CONDLEU, 0), |
1526 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovqleu", FM_QF, CONDLEU, 0), |
1527 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovsleu", FM_SF, CONDLEU, 0), |
1528 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovdlg", FM_DF, FCONDLG, 0), |
1529 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovqlg", FM_QF, FCONDLG, 0), |
1530 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovslg", FM_SF, FCONDLG, 0), |
1531 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovdlu", FM_DF, CONDLU, F_ALIAS), |
1532 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovqlu", FM_QF, CONDLU, F_ALIAS), |
1533 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovslu", FM_SF, CONDLU, F_ALIAS), |
1534 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovdn", FM_DF, CONDN, FCONDN, 0), |
1535 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovqn", FM_QF, CONDN, FCONDN, 0), |
1536 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovsn", FM_SF, CONDN, FCONDN, 0), |
1537 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovdne", FM_DF, CONDNE, FCONDNE, 0), |
1538 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovqne", FM_QF, CONDNE, FCONDNE, 0), |
1539 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovsne", FM_SF, CONDNE, FCONDNE, 0), |
1540 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovdneg", FM_DF, CONDNEG, 0), |
1541 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovqneg", FM_QF, CONDNEG, 0), |
1542 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovsneg", FM_SF, CONDNEG, 0), |
1543 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovdnz", FM_DF, CONDNZ, FCONDNZ, F_ALIAS), |
1544 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovqnz", FM_QF, CONDNZ, FCONDNZ, F_ALIAS), |
1545 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovsnz", FM_SF, CONDNZ, FCONDNZ, F_ALIAS), |
1546 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovdo", FM_DF, FCONDO, 0), |
1547 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovqo", FM_QF, FCONDO, 0), |
1548 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovso", FM_SF, FCONDO, 0), |
1549 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovdpos", FM_DF, CONDPOS, 0), |
1550 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovqpos", FM_QF, CONDPOS, 0), |
1551 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovspos", FM_SF, CONDPOS, 0), |
1552 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovdu", FM_DF, FCONDU, 0), |
1553 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovqu", FM_QF, FCONDU, 0), |
1554 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovsu", FM_SF, FCONDU, 0), |
1555 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovdue", FM_DF, FCONDUE, 0), |
1556 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovque", FM_QF, FCONDUE, 0), |
1557 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovsue", FM_SF, FCONDUE, 0), |
1558 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovdug", FM_DF, FCONDUG, 0), |
1559 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovqug", FM_QF, FCONDUG, 0), |
1560 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovsug", FM_SF, FCONDUG, 0), |
1561 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovduge", FM_DF, FCONDUGE, 0), |
1562 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovquge", FM_QF, FCONDUGE, 0), |
1563 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovsuge", FM_SF, FCONDUGE, 0), |
1564 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovdul", FM_DF, FCONDUL, 0), |
1565 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovqul", FM_QF, FCONDUL, 0), |
1566 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovsul", FM_SF, FCONDUL, 0), |
1567 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovdule", FM_DF, FCONDULE, 0), |
1568 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovqule", FM_QF, FCONDULE, 0), |
1569 | aa0aa4fa | bellard | /* v9 */ fmovfcc ("fmovsule", FM_SF, FCONDULE, 0), |
1570 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovdvc", FM_DF, CONDVC, 0), |
1571 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovqvc", FM_QF, CONDVC, 0), |
1572 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovsvc", FM_SF, CONDVC, 0), |
1573 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovdvs", FM_DF, CONDVS, 0), |
1574 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovqvs", FM_QF, CONDVS, 0), |
1575 | aa0aa4fa | bellard | /* v9 */ fmovicc ("fmovsvs", FM_SF, CONDVS, 0), |
1576 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovdz", FM_DF, CONDZ, FCONDZ, F_ALIAS), |
1577 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovqz", FM_QF, CONDZ, FCONDZ, F_ALIAS), |
1578 | aa0aa4fa | bellard | /* v9 */ fmovcc ("fmovsz", FM_SF, CONDZ, FCONDZ, F_ALIAS), |
1579 | aa0aa4fa | bellard | |
1580 | aa0aa4fa | bellard | #undef fmovicc /* v9 */ |
1581 | aa0aa4fa | bellard | #undef fmovfcc /* v9 */ |
1582 | aa0aa4fa | bellard | #undef fmovcc /* v9 */ |
1583 | aa0aa4fa | bellard | #undef FM_DF /* v9 */ |
1584 | aa0aa4fa | bellard | #undef FM_QF /* v9 */ |
1585 | aa0aa4fa | bellard | #undef FM_SF /* v9 */ |
1586 | aa0aa4fa | bellard | |
1587 | aa0aa4fa | bellard | /* Coprocessor branches. */
|
1588 | aa0aa4fa | bellard | #define CBR(opcode, mask, lose, flags, arch) \
|
1589 | aa0aa4fa | bellard | { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \
|
1590 | aa0aa4fa | bellard | { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch }
|
1591 | aa0aa4fa | bellard | |
1592 | aa0aa4fa | bellard | /* Floating point branches. */
|
1593 | aa0aa4fa | bellard | #define FBR(opcode, mask, lose, flags) \
|
1594 | aa0aa4fa | bellard | { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED|F_FBR, v6 }, \
|
1595 | aa0aa4fa | bellard | { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 }
|
1596 | aa0aa4fa | bellard | |
1597 | aa0aa4fa | bellard | /* V9 extended floating point branches. */
|
1598 | aa0aa4fa | bellard | #define FBRX(opcode, mask, lose, flags) /* v9 */ \ |
1599 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1600 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1601 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1602 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1603 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1604 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1605 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1606 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1607 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1608 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1609 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1610 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1611 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1612 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1613 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1614 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1615 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1616 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1617 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1618 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1619 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1620 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1621 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1622 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 } |
1623 | aa0aa4fa | bellard | |
1624 | aa0aa4fa | bellard | /* v9: We must put `FBRX' before `FBR', to ensure that we never match
|
1625 | aa0aa4fa | bellard | v9: something against an expression unless it is an expression. Otherwise,
|
1626 | aa0aa4fa | bellard | v9: we end up with undefined symbol tables entries, because they get added,
|
1627 | aa0aa4fa | bellard | v9: but are not deleted if the pattern fails to match. */
|
1628 | aa0aa4fa | bellard | |
1629 | aa0aa4fa | bellard | #define CONDFC(fop, cop, mask, flags) \
|
1630 | aa0aa4fa | bellard | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
1631 | aa0aa4fa | bellard | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ |
1632 | aa0aa4fa | bellard | CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) |
1633 | aa0aa4fa | bellard | |
1634 | aa0aa4fa | bellard | #define CONDFCL(fop, cop, mask, flags) \
|
1635 | aa0aa4fa | bellard | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
1636 | aa0aa4fa | bellard | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ |
1637 | aa0aa4fa | bellard | CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) |
1638 | aa0aa4fa | bellard | |
1639 | aa0aa4fa | bellard | #define CONDF(fop, mask, flags) \
|
1640 | aa0aa4fa | bellard | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
1641 | aa0aa4fa | bellard | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) |
1642 | aa0aa4fa | bellard | |
1643 | aa0aa4fa | bellard | CONDFC ("fb", "cb", 0x8, F_UNBR), |
1644 | aa0aa4fa | bellard | CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS), |
1645 | aa0aa4fa | bellard | CONDFC ("fbe", "cb0", 0x9, F_CONDBR), |
1646 | aa0aa4fa | bellard | CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS), |
1647 | aa0aa4fa | bellard | CONDFC ("fbg", "cb2", 0x6, F_CONDBR), |
1648 | aa0aa4fa | bellard | CONDFC ("fbge", "cb02", 0xb, F_CONDBR), |
1649 | aa0aa4fa | bellard | CONDFC ("fbl", "cb1", 0x4, F_CONDBR), |
1650 | aa0aa4fa | bellard | CONDFC ("fble", "cb01", 0xd, F_CONDBR), |
1651 | aa0aa4fa | bellard | CONDFC ("fblg", "cb12", 0x2, F_CONDBR), |
1652 | aa0aa4fa | bellard | CONDFCL ("fbn", "cbn", 0x0, F_UNBR), |
1653 | aa0aa4fa | bellard | CONDFC ("fbne", "cb123", 0x1, F_CONDBR), |
1654 | aa0aa4fa | bellard | CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS), |
1655 | aa0aa4fa | bellard | CONDFC ("fbo", "cb012", 0xf, F_CONDBR), |
1656 | aa0aa4fa | bellard | CONDFC ("fbu", "cb3", 0x7, F_CONDBR), |
1657 | aa0aa4fa | bellard | CONDFC ("fbue", "cb03", 0xa, F_CONDBR), |
1658 | aa0aa4fa | bellard | CONDFC ("fbug", "cb23", 0x5, F_CONDBR), |
1659 | aa0aa4fa | bellard | CONDFC ("fbuge", "cb023", 0xc, F_CONDBR), |
1660 | aa0aa4fa | bellard | CONDFC ("fbul", "cb13", 0x3, F_CONDBR), |
1661 | aa0aa4fa | bellard | CONDFC ("fbule", "cb013", 0xe, F_CONDBR), |
1662 | aa0aa4fa | bellard | |
1663 | aa0aa4fa | bellard | #undef CONDFC
|
1664 | aa0aa4fa | bellard | #undef CONDFCL
|
1665 | aa0aa4fa | bellard | #undef CONDF
|
1666 | aa0aa4fa | bellard | #undef CBR
|
1667 | aa0aa4fa | bellard | #undef FBR
|
1668 | aa0aa4fa | bellard | #undef FBRX /* v9 */ |
1669 | aa0aa4fa | bellard | |
1670 | aa0aa4fa | bellard | { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ |
1671 | aa0aa4fa | bellard | { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ |
1672 | aa0aa4fa | bellard | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ |
1673 | aa0aa4fa | bellard | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ |
1674 | aa0aa4fa | bellard | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ |
1675 | aa0aa4fa | bellard | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */ |
1676 | aa0aa4fa | bellard | |
1677 | aa0aa4fa | bellard | { "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ |
1678 | aa0aa4fa | bellard | |
1679 | aa0aa4fa | bellard | { "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 }, |
1680 | aa0aa4fa | bellard | { "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, |
1681 | aa0aa4fa | bellard | { "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, |
1682 | aa0aa4fa | bellard | { "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, |
1683 | aa0aa4fa | bellard | |
1684 | aa0aa4fa | bellard | { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, |
1685 | aa0aa4fa | bellard | |
1686 | aa0aa4fa | bellard | { "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1687 | aa0aa4fa | bellard | { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 }, |
1688 | aa0aa4fa | bellard | { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 }, |
1689 | aa0aa4fa | bellard | { "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1690 | aa0aa4fa | bellard | { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 }, |
1691 | aa0aa4fa | bellard | { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 }, |
1692 | aa0aa4fa | bellard | |
1693 | aa0aa4fa | bellard | { "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1694 | aa0aa4fa | bellard | { "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 }, |
1695 | aa0aa4fa | bellard | { "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1696 | aa0aa4fa | bellard | { "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 }, |
1697 | aa0aa4fa | bellard | |
1698 | aa0aa4fa | bellard | { "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 }, |
1699 | aa0aa4fa | bellard | { "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 }, |
1700 | aa0aa4fa | bellard | |
1701 | aa0aa4fa | bellard | /* This *is* a commutative instruction. */
|
1702 | aa0aa4fa | bellard | { "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1703 | aa0aa4fa | bellard | { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 }, |
1704 | aa0aa4fa | bellard | { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 }, |
1705 | aa0aa4fa | bellard | /* This *is* a commutative instruction. */
|
1706 | aa0aa4fa | bellard | { "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1707 | aa0aa4fa | bellard | { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 }, |
1708 | aa0aa4fa | bellard | { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 }, |
1709 | aa0aa4fa | bellard | { "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1710 | aa0aa4fa | bellard | { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 }, |
1711 | aa0aa4fa | bellard | { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 }, |
1712 | aa0aa4fa | bellard | { "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1713 | aa0aa4fa | bellard | { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 }, |
1714 | aa0aa4fa | bellard | { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 }, |
1715 | aa0aa4fa | bellard | |
1716 | aa0aa4fa | bellard | { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */ |
1717 | aa0aa4fa | bellard | { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */ |
1718 | aa0aa4fa | bellard | |
1719 | aa0aa4fa | bellard | { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */ |
1720 | aa0aa4fa | bellard | { "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */ |
1721 | aa0aa4fa | bellard | |
1722 | aa0aa4fa | bellard | /* FPop1 and FPop2 are not instructions. Don't accept them. */
|
1723 | aa0aa4fa | bellard | |
1724 | aa0aa4fa | bellard | { "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 }, |
1725 | aa0aa4fa | bellard | { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, |
1726 | aa0aa4fa | bellard | { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, |
1727 | aa0aa4fa | bellard | |
1728 | aa0aa4fa | bellard | { "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 }, |
1729 | aa0aa4fa | bellard | { "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 }, |
1730 | aa0aa4fa | bellard | { "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 }, |
1731 | aa0aa4fa | bellard | |
1732 | aa0aa4fa | bellard | { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, |
1733 | aa0aa4fa | bellard | { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, |
1734 | aa0aa4fa | bellard | { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, |
1735 | aa0aa4fa | bellard | |
1736 | aa0aa4fa | bellard | { "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 }, |
1737 | aa0aa4fa | bellard | { "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 }, |
1738 | aa0aa4fa | bellard | { "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 }, |
1739 | aa0aa4fa | bellard | |
1740 | aa0aa4fa | bellard | { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, |
1741 | aa0aa4fa | bellard | { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, |
1742 | aa0aa4fa | bellard | { "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 }, |
1743 | aa0aa4fa | bellard | { "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 }, |
1744 | aa0aa4fa | bellard | { "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 }, |
1745 | aa0aa4fa | bellard | { "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 }, |
1746 | aa0aa4fa | bellard | |
1747 | aa0aa4fa | bellard | { "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 }, |
1748 | aa0aa4fa | bellard | { "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 }, |
1749 | aa0aa4fa | bellard | { "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
1750 | aa0aa4fa | bellard | { "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 }, |
1751 | aa0aa4fa | bellard | { "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 }, |
1752 | aa0aa4fa | bellard | { "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 }, |
1753 | aa0aa4fa | bellard | { "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
1754 | aa0aa4fa | bellard | { "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 }, |
1755 | aa0aa4fa | bellard | |
1756 | aa0aa4fa | bellard | { "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 }, |
1757 | aa0aa4fa | bellard | { "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 }, |
1758 | aa0aa4fa | bellard | { "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 }, |
1759 | aa0aa4fa | bellard | |
1760 | aa0aa4fa | bellard | { "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 }, |
1761 | aa0aa4fa | bellard | { "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 }, |
1762 | aa0aa4fa | bellard | { "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 }, |
1763 | aa0aa4fa | bellard | { "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 }, |
1764 | aa0aa4fa | bellard | |
1765 | aa0aa4fa | bellard | { "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 }, |
1766 | aa0aa4fa | bellard | { "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 }, |
1767 | aa0aa4fa | bellard | { "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, |
1768 | aa0aa4fa | bellard | { "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 }, |
1769 | aa0aa4fa | bellard | { "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 }, |
1770 | aa0aa4fa | bellard | { "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 }, |
1771 | aa0aa4fa | bellard | { "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, |
1772 | aa0aa4fa | bellard | { "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 }, |
1773 | aa0aa4fa | bellard | { "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 }, |
1774 | aa0aa4fa | bellard | { "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 }, |
1775 | aa0aa4fa | bellard | { "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, |
1776 | aa0aa4fa | bellard | { "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 }, |
1777 | aa0aa4fa | bellard | |
1778 | aa0aa4fa | bellard | { "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 }, |
1779 | aa0aa4fa | bellard | { "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 }, |
1780 | aa0aa4fa | bellard | { "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
1781 | aa0aa4fa | bellard | { "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 }, |
1782 | aa0aa4fa | bellard | { "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 }, |
1783 | aa0aa4fa | bellard | { "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 }, |
1784 | aa0aa4fa | bellard | { "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
1785 | aa0aa4fa | bellard | { "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 }, |
1786 | aa0aa4fa | bellard | |
1787 | aa0aa4fa | bellard | #define CMPFCC(x) (((x)&0x3)<<25) |
1788 | aa0aa4fa | bellard | |
1789 | aa0aa4fa | bellard | { "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 }, |
1790 | aa0aa4fa | bellard | { "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 }, |
1791 | aa0aa4fa | bellard | { "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 }, |
1792 | aa0aa4fa | bellard | { "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 }, |
1793 | aa0aa4fa | bellard | { "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 }, |
1794 | aa0aa4fa | bellard | { "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 }, |
1795 | aa0aa4fa | bellard | { "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 }, |
1796 | aa0aa4fa | bellard | { "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 }, |
1797 | aa0aa4fa | bellard | { "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 }, |
1798 | aa0aa4fa | bellard | { "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 }, |
1799 | aa0aa4fa | bellard | { "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 }, |
1800 | aa0aa4fa | bellard | { "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 }, |
1801 | aa0aa4fa | bellard | { "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 }, |
1802 | aa0aa4fa | bellard | { "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 }, |
1803 | aa0aa4fa | bellard | { "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 }, |
1804 | aa0aa4fa | bellard | { "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 }, |
1805 | aa0aa4fa | bellard | { "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 }, |
1806 | aa0aa4fa | bellard | { "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 }, |
1807 | aa0aa4fa | bellard | { "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 }, |
1808 | aa0aa4fa | bellard | { "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 }, |
1809 | aa0aa4fa | bellard | { "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, |
1810 | aa0aa4fa | bellard | { "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 }, |
1811 | aa0aa4fa | bellard | { "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 }, |
1812 | aa0aa4fa | bellard | { "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 }, |
1813 | aa0aa4fa | bellard | { "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 }, |
1814 | aa0aa4fa | bellard | { "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, |
1815 | aa0aa4fa | bellard | { "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 }, |
1816 | aa0aa4fa | bellard | { "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 }, |
1817 | aa0aa4fa | bellard | { "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 }, |
1818 | aa0aa4fa | bellard | { "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 }, |
1819 | aa0aa4fa | bellard | { "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 }, |
1820 | aa0aa4fa | bellard | { "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 }, |
1821 | aa0aa4fa | bellard | { "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 }, |
1822 | aa0aa4fa | bellard | { "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 }, |
1823 | aa0aa4fa | bellard | { "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 }, |
1824 | aa0aa4fa | bellard | { "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 }, |
1825 | aa0aa4fa | bellard | { "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 }, |
1826 | aa0aa4fa | bellard | { "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 }, |
1827 | aa0aa4fa | bellard | { "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 }, |
1828 | aa0aa4fa | bellard | { "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 }, |
1829 | aa0aa4fa | bellard | |
1830 | aa0aa4fa | bellard | /* These Extended FPop (FIFO) instructions are new in the Fujitsu
|
1831 | aa0aa4fa | bellard | MB86934, replacing the CPop instructions from v6 and later
|
1832 | aa0aa4fa | bellard | processors. */
|
1833 | aa0aa4fa | bellard | |
1834 | aa0aa4fa | bellard | #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite } |
1835 | aa0aa4fa | bellard | #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite } |
1836 | aa0aa4fa | bellard | #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite } |
1837 | aa0aa4fa | bellard | |
1838 | aa0aa4fa | bellard | EFPOP1_2 ("efitod", 0x0c8, "f,H"), |
1839 | aa0aa4fa | bellard | EFPOP1_2 ("efitos", 0x0c4, "f,g"), |
1840 | aa0aa4fa | bellard | EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), |
1841 | aa0aa4fa | bellard | EFPOP1_2 ("efstoi", 0x0d1, "f,g"), |
1842 | aa0aa4fa | bellard | EFPOP1_2 ("efstod", 0x0c9, "f,H"), |
1843 | aa0aa4fa | bellard | EFPOP1_2 ("efdtos", 0x0c6, "B,g"), |
1844 | aa0aa4fa | bellard | EFPOP1_2 ("efmovs", 0x001, "f,g"), |
1845 | aa0aa4fa | bellard | EFPOP1_2 ("efnegs", 0x005, "f,g"), |
1846 | aa0aa4fa | bellard | EFPOP1_2 ("efabss", 0x009, "f,g"), |
1847 | aa0aa4fa | bellard | EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), |
1848 | aa0aa4fa | bellard | EFPOP1_2 ("efsqrts", 0x029, "f,g"), |
1849 | aa0aa4fa | bellard | EFPOP1_3 ("efaddd", 0x042, "v,B,H"), |
1850 | aa0aa4fa | bellard | EFPOP1_3 ("efadds", 0x041, "e,f,g"), |
1851 | aa0aa4fa | bellard | EFPOP1_3 ("efsubd", 0x046, "v,B,H"), |
1852 | aa0aa4fa | bellard | EFPOP1_3 ("efsubs", 0x045, "e,f,g"), |
1853 | aa0aa4fa | bellard | EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), |
1854 | aa0aa4fa | bellard | EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), |
1855 | aa0aa4fa | bellard | EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), |
1856 | aa0aa4fa | bellard | EFPOP1_3 ("efmuls", 0x049, "e,f,g"), |
1857 | aa0aa4fa | bellard | EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), |
1858 | aa0aa4fa | bellard | EFPOP2_2 ("efcmpd", 0x052, "v,B"), |
1859 | aa0aa4fa | bellard | EFPOP2_2 ("efcmped", 0x056, "v,B"), |
1860 | aa0aa4fa | bellard | EFPOP2_2 ("efcmps", 0x051, "e,f"), |
1861 | aa0aa4fa | bellard | EFPOP2_2 ("efcmpes", 0x055, "e,f"), |
1862 | aa0aa4fa | bellard | |
1863 | aa0aa4fa | bellard | #undef EFPOP1_2
|
1864 | aa0aa4fa | bellard | #undef EFPOP1_3
|
1865 | aa0aa4fa | bellard | #undef EFPOP2_2
|
1866 | aa0aa4fa | bellard | |
1867 | aa0aa4fa | bellard | /* These are marked F_ALIAS, so that they won't conflict with sparclite insns
|
1868 | aa0aa4fa | bellard | present. Otherwise, the F_ALIAS flag is ignored. */
|
1869 | aa0aa4fa | bellard | { "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 }, |
1870 | aa0aa4fa | bellard | { "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 }, |
1871 | aa0aa4fa | bellard | |
1872 | aa0aa4fa | bellard | /* sparclet specific insns */
|
1873 | aa0aa4fa | bellard | |
1874 | aa0aa4fa | bellard | COMMUTEOP ("umac", 0x3e, sparclet), |
1875 | aa0aa4fa | bellard | COMMUTEOP ("smac", 0x3f, sparclet), |
1876 | aa0aa4fa | bellard | COMMUTEOP ("umacd", 0x2e, sparclet), |
1877 | aa0aa4fa | bellard | COMMUTEOP ("smacd", 0x2f, sparclet), |
1878 | aa0aa4fa | bellard | COMMUTEOP ("umuld", 0x09, sparclet), |
1879 | aa0aa4fa | bellard | COMMUTEOP ("smuld", 0x0d, sparclet), |
1880 | aa0aa4fa | bellard | |
1881 | aa0aa4fa | bellard | { "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet }, |
1882 | aa0aa4fa | bellard | { "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet }, |
1883 | aa0aa4fa | bellard | |
1884 | aa0aa4fa | bellard | /* The manual isn't completely accurate on these insns. The `rs2' field is
|
1885 | aa0aa4fa | bellard | treated as being 6 bits to account for 6 bit immediates to cpush. It is
|
1886 | aa0aa4fa | bellard | assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
|
1887 | aa0aa4fa | bellard | #define BIT5 (1<<5) |
1888 | aa0aa4fa | bellard | { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet }, |
1889 | aa0aa4fa | bellard | { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet }, |
1890 | aa0aa4fa | bellard | { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet }, |
1891 | aa0aa4fa | bellard | { "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet }, |
1892 | aa0aa4fa | bellard | { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet }, |
1893 | aa0aa4fa | bellard | { "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet }, |
1894 | aa0aa4fa | bellard | { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet }, |
1895 | aa0aa4fa | bellard | #undef BIT5
|
1896 | aa0aa4fa | bellard | |
1897 | aa0aa4fa | bellard | /* sparclet coprocessor branch insns */
|
1898 | aa0aa4fa | bellard | #define SLCBCC2(opcode, mask, lose) \
|
1899 | aa0aa4fa | bellard | { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \
|
1900 | aa0aa4fa | bellard | { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
|
1901 | aa0aa4fa | bellard | #define SLCBCC(opcode, mask) \
|
1902 | aa0aa4fa | bellard | SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) |
1903 | aa0aa4fa | bellard | |
1904 | aa0aa4fa | bellard | /* cbn,cba can't be defined here because they're defined elsewhere and GAS
|
1905 | aa0aa4fa | bellard | requires all mnemonics of the same name to be consecutive. */
|
1906 | aa0aa4fa | bellard | /*SLCBCC("cbn", 0), - already defined */
|
1907 | aa0aa4fa | bellard | SLCBCC("cbe", 1), |
1908 | aa0aa4fa | bellard | SLCBCC("cbf", 2), |
1909 | aa0aa4fa | bellard | SLCBCC("cbef", 3), |
1910 | aa0aa4fa | bellard | SLCBCC("cbr", 4), |
1911 | aa0aa4fa | bellard | SLCBCC("cber", 5), |
1912 | aa0aa4fa | bellard | SLCBCC("cbfr", 6), |
1913 | aa0aa4fa | bellard | SLCBCC("cbefr", 7), |
1914 | aa0aa4fa | bellard | /*SLCBCC("cba", 8), - already defined */
|
1915 | aa0aa4fa | bellard | SLCBCC("cbne", 9), |
1916 | aa0aa4fa | bellard | SLCBCC("cbnf", 10), |
1917 | aa0aa4fa | bellard | SLCBCC("cbnef", 11), |
1918 | aa0aa4fa | bellard | SLCBCC("cbnr", 12), |
1919 | aa0aa4fa | bellard | SLCBCC("cbner", 13), |
1920 | aa0aa4fa | bellard | SLCBCC("cbnfr", 14), |
1921 | aa0aa4fa | bellard | SLCBCC("cbnefr", 15), |
1922 | aa0aa4fa | bellard | |
1923 | aa0aa4fa | bellard | #undef SLCBCC2
|
1924 | aa0aa4fa | bellard | #undef SLCBCC
|
1925 | aa0aa4fa | bellard | |
1926 | aa0aa4fa | bellard | { "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 }, |
1927 | aa0aa4fa | bellard | { "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 }, |
1928 | aa0aa4fa | bellard | { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 }, |
1929 | aa0aa4fa | bellard | { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 }, |
1930 | aa0aa4fa | bellard | |
1931 | aa0aa4fa | bellard | /* v9 synthetic insns */
|
1932 | aa0aa4fa | bellard | { "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */ |
1933 | aa0aa4fa | bellard | { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */ |
1934 | aa0aa4fa | bellard | { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */ |
1935 | aa0aa4fa | bellard | { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */ |
1936 | aa0aa4fa | bellard | { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */ |
1937 | aa0aa4fa | bellard | { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ |
1938 | aa0aa4fa | bellard | { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ |
1939 | aa0aa4fa | bellard | { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ |
1940 | aa0aa4fa | bellard | { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ |
1941 | aa0aa4fa | bellard | |
1942 | aa0aa4fa | bellard | /* Ultrasparc extensions */
|
1943 | aa0aa4fa | bellard | { "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a }, |
1944 | aa0aa4fa | bellard | |
1945 | aa0aa4fa | bellard | /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
|
1946 | aa0aa4fa | bellard | { "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a }, |
1947 | aa0aa4fa | bellard | { "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a }, |
1948 | aa0aa4fa | bellard | { "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a }, |
1949 | aa0aa4fa | bellard | { "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a }, |
1950 | aa0aa4fa | bellard | { "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a }, |
1951 | aa0aa4fa | bellard | { "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a }, |
1952 | aa0aa4fa | bellard | { "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a }, |
1953 | aa0aa4fa | bellard | { "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a }, |
1954 | aa0aa4fa | bellard | |
1955 | aa0aa4fa | bellard | { "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a }, |
1956 | aa0aa4fa | bellard | { "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a }, |
1957 | aa0aa4fa | bellard | { "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a }, |
1958 | aa0aa4fa | bellard | { "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a }, |
1959 | aa0aa4fa | bellard | { "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a }, |
1960 | aa0aa4fa | bellard | |
1961 | aa0aa4fa | bellard | /* Note that the mixing of 32/64 bit regs is intentional. */
|
1962 | aa0aa4fa | bellard | { "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a }, |
1963 | aa0aa4fa | bellard | { "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a }, |
1964 | aa0aa4fa | bellard | { "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a }, |
1965 | aa0aa4fa | bellard | { "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a }, |
1966 | aa0aa4fa | bellard | { "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a }, |
1967 | aa0aa4fa | bellard | { "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a }, |
1968 | aa0aa4fa | bellard | { "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a }, |
1969 | aa0aa4fa | bellard | |
1970 | aa0aa4fa | bellard | { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a }, |
1971 | aa0aa4fa | bellard | { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a }, |
1972 | aa0aa4fa | bellard | { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a }, |
1973 | aa0aa4fa | bellard | |
1974 | aa0aa4fa | bellard | { "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a }, |
1975 | aa0aa4fa | bellard | { "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a }, |
1976 | aa0aa4fa | bellard | { "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a }, |
1977 | aa0aa4fa | bellard | { "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a }, |
1978 | aa0aa4fa | bellard | { "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a }, |
1979 | aa0aa4fa | bellard | { "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a }, |
1980 | aa0aa4fa | bellard | { "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a }, |
1981 | aa0aa4fa | bellard | { "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a }, |
1982 | aa0aa4fa | bellard | { "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a }, |
1983 | aa0aa4fa | bellard | { "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a }, |
1984 | aa0aa4fa | bellard | { "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a }, |
1985 | aa0aa4fa | bellard | { "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a }, |
1986 | aa0aa4fa | bellard | { "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a }, |
1987 | aa0aa4fa | bellard | { "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a }, |
1988 | aa0aa4fa | bellard | { "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a }, |
1989 | aa0aa4fa | bellard | { "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a }, |
1990 | aa0aa4fa | bellard | { "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a }, |
1991 | aa0aa4fa | bellard | { "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a }, |
1992 | aa0aa4fa | bellard | { "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a }, |
1993 | aa0aa4fa | bellard | { "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a }, |
1994 | aa0aa4fa | bellard | { "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a }, |
1995 | aa0aa4fa | bellard | { "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a }, |
1996 | aa0aa4fa | bellard | { "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a }, |
1997 | aa0aa4fa | bellard | { "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a }, |
1998 | aa0aa4fa | bellard | { "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a }, |
1999 | aa0aa4fa | bellard | { "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a }, |
2000 | aa0aa4fa | bellard | { "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a }, |
2001 | aa0aa4fa | bellard | { "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a }, |
2002 | aa0aa4fa | bellard | { "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a }, |
2003 | aa0aa4fa | bellard | { "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a }, |
2004 | aa0aa4fa | bellard | { "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a }, |
2005 | aa0aa4fa | bellard | { "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a }, |
2006 | aa0aa4fa | bellard | |
2007 | aa0aa4fa | bellard | { "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a }, |
2008 | aa0aa4fa | bellard | { "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a }, |
2009 | aa0aa4fa | bellard | { "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a }, |
2010 | aa0aa4fa | bellard | { "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a }, |
2011 | aa0aa4fa | bellard | { "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a }, |
2012 | aa0aa4fa | bellard | { "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a }, |
2013 | aa0aa4fa | bellard | { "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a }, |
2014 | aa0aa4fa | bellard | { "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a }, |
2015 | aa0aa4fa | bellard | |
2016 | aa0aa4fa | bellard | { "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a }, |
2017 | aa0aa4fa | bellard | { "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a }, |
2018 | aa0aa4fa | bellard | { "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a }, |
2019 | aa0aa4fa | bellard | { "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a }, |
2020 | aa0aa4fa | bellard | { "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a }, |
2021 | aa0aa4fa | bellard | { "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a }, |
2022 | aa0aa4fa | bellard | |
2023 | aa0aa4fa | bellard | { "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a }, |
2024 | aa0aa4fa | bellard | |
2025 | aa0aa4fa | bellard | { "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a }, |
2026 | aa0aa4fa | bellard | { "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a }, |
2027 | aa0aa4fa | bellard | { "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a }, |
2028 | aa0aa4fa | bellard | |
2029 | aa0aa4fa | bellard | /* Cheetah instructions */
|
2030 | aa0aa4fa | bellard | { "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b }, |
2031 | aa0aa4fa | bellard | { "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b }, |
2032 | aa0aa4fa | bellard | { "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b }, |
2033 | aa0aa4fa | bellard | { "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b }, |
2034 | aa0aa4fa | bellard | { "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b }, |
2035 | aa0aa4fa | bellard | { "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b }, |
2036 | aa0aa4fa | bellard | |
2037 | aa0aa4fa | bellard | { "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b }, |
2038 | aa0aa4fa | bellard | { "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b }, |
2039 | aa0aa4fa | bellard | |
2040 | aa0aa4fa | bellard | { "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b }, |
2041 | aa0aa4fa | bellard | |
2042 | aa0aa4fa | bellard | /* More v9 specific insns, these need to come last so they do not clash
|
2043 | aa0aa4fa | bellard | with v9a instructions such as "edge8" which looks like impdep1. */
|
2044 | aa0aa4fa | bellard | |
2045 | aa0aa4fa | bellard | #define IMPDEP(name, code) \
|
2046 | aa0aa4fa | bellard | { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \ |
2047 | aa0aa4fa | bellard | { name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \ |
2048 | aa0aa4fa | bellard | { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \ |
2049 | aa0aa4fa | bellard | { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a } |
2050 | aa0aa4fa | bellard | |
2051 | aa0aa4fa | bellard | IMPDEP ("impdep1", 0x36), |
2052 | aa0aa4fa | bellard | IMPDEP ("impdep2", 0x37), |
2053 | aa0aa4fa | bellard | |
2054 | aa0aa4fa | bellard | #undef IMPDEP
|
2055 | aa0aa4fa | bellard | |
2056 | aa0aa4fa | bellard | }; |
2057 | aa0aa4fa | bellard | |
2058 | aa0aa4fa | bellard | const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); |
2059 | aa0aa4fa | bellard | |
2060 | aa0aa4fa | bellard | /* Utilities for argument parsing. */
|
2061 | aa0aa4fa | bellard | |
2062 | aa0aa4fa | bellard | typedef struct |
2063 | aa0aa4fa | bellard | { |
2064 | aa0aa4fa | bellard | int value;
|
2065 | aa0aa4fa | bellard | const char *name; |
2066 | aa0aa4fa | bellard | } arg; |
2067 | aa0aa4fa | bellard | |
2068 | aa0aa4fa | bellard | /* Look up NAME in TABLE. */
|
2069 | aa0aa4fa | bellard | |
2070 | aa0aa4fa | bellard | static int lookup_name PARAMS ((const arg *, const char *)); |
2071 | aa0aa4fa | bellard | static const char *lookup_value PARAMS ((const arg *, int)); |
2072 | aa0aa4fa | bellard | |
2073 | aa0aa4fa | bellard | static int |
2074 | aa0aa4fa | bellard | lookup_name (table, name) |
2075 | aa0aa4fa | bellard | const arg *table;
|
2076 | aa0aa4fa | bellard | const char *name; |
2077 | aa0aa4fa | bellard | { |
2078 | aa0aa4fa | bellard | const arg *p;
|
2079 | aa0aa4fa | bellard | |
2080 | aa0aa4fa | bellard | for (p = table; p->name; ++p)
|
2081 | aa0aa4fa | bellard | if (strcmp (name, p->name) == 0) |
2082 | aa0aa4fa | bellard | return p->value;
|
2083 | aa0aa4fa | bellard | |
2084 | aa0aa4fa | bellard | return -1; |
2085 | aa0aa4fa | bellard | } |
2086 | aa0aa4fa | bellard | |
2087 | aa0aa4fa | bellard | /* Look up VALUE in TABLE. */
|
2088 | aa0aa4fa | bellard | |
2089 | aa0aa4fa | bellard | static const char * |
2090 | aa0aa4fa | bellard | lookup_value (table, value) |
2091 | aa0aa4fa | bellard | const arg *table;
|
2092 | aa0aa4fa | bellard | int value;
|
2093 | aa0aa4fa | bellard | { |
2094 | aa0aa4fa | bellard | const arg *p;
|
2095 | aa0aa4fa | bellard | |
2096 | aa0aa4fa | bellard | for (p = table; p->name; ++p)
|
2097 | aa0aa4fa | bellard | if (value == p->value)
|
2098 | aa0aa4fa | bellard | return p->name;
|
2099 | aa0aa4fa | bellard | |
2100 | aa0aa4fa | bellard | return (char *) 0; |
2101 | aa0aa4fa | bellard | } |
2102 | aa0aa4fa | bellard | |
2103 | aa0aa4fa | bellard | /* Handle ASI's. */
|
2104 | aa0aa4fa | bellard | |
2105 | aa0aa4fa | bellard | static arg asi_table[] =
|
2106 | aa0aa4fa | bellard | { |
2107 | aa0aa4fa | bellard | /* These are in the v9 architecture manual. */
|
2108 | aa0aa4fa | bellard | /* The shorter versions appear first, they're here because Sun's as has them.
|
2109 | aa0aa4fa | bellard | Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
|
2110 | aa0aa4fa | bellard | UltraSPARC architecture manual). */
|
2111 | aa0aa4fa | bellard | { 0x04, "#ASI_N" }, |
2112 | aa0aa4fa | bellard | { 0x0c, "#ASI_N_L" }, |
2113 | aa0aa4fa | bellard | { 0x10, "#ASI_AIUP" }, |
2114 | aa0aa4fa | bellard | { 0x11, "#ASI_AIUS" }, |
2115 | aa0aa4fa | bellard | { 0x18, "#ASI_AIUP_L" }, |
2116 | aa0aa4fa | bellard | { 0x19, "#ASI_AIUS_L" }, |
2117 | aa0aa4fa | bellard | { 0x80, "#ASI_P" }, |
2118 | aa0aa4fa | bellard | { 0x81, "#ASI_S" }, |
2119 | aa0aa4fa | bellard | { 0x82, "#ASI_PNF" }, |
2120 | aa0aa4fa | bellard | { 0x83, "#ASI_SNF" }, |
2121 | aa0aa4fa | bellard | { 0x88, "#ASI_P_L" }, |
2122 | aa0aa4fa | bellard | { 0x89, "#ASI_S_L" }, |
2123 | aa0aa4fa | bellard | { 0x8a, "#ASI_PNF_L" }, |
2124 | aa0aa4fa | bellard | { 0x8b, "#ASI_SNF_L" }, |
2125 | aa0aa4fa | bellard | { 0x04, "#ASI_NUCLEUS" }, |
2126 | aa0aa4fa | bellard | { 0x0c, "#ASI_NUCLEUS_LITTLE" }, |
2127 | aa0aa4fa | bellard | { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, |
2128 | aa0aa4fa | bellard | { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, |
2129 | aa0aa4fa | bellard | { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, |
2130 | aa0aa4fa | bellard | { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, |
2131 | aa0aa4fa | bellard | { 0x80, "#ASI_PRIMARY" }, |
2132 | aa0aa4fa | bellard | { 0x81, "#ASI_SECONDARY" }, |
2133 | aa0aa4fa | bellard | { 0x82, "#ASI_PRIMARY_NOFAULT" }, |
2134 | aa0aa4fa | bellard | { 0x83, "#ASI_SECONDARY_NOFAULT" }, |
2135 | aa0aa4fa | bellard | { 0x88, "#ASI_PRIMARY_LITTLE" }, |
2136 | aa0aa4fa | bellard | { 0x89, "#ASI_SECONDARY_LITTLE" }, |
2137 | aa0aa4fa | bellard | { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, |
2138 | aa0aa4fa | bellard | { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, |
2139 | aa0aa4fa | bellard | /* These are UltraSPARC extensions. */
|
2140 | aa0aa4fa | bellard | /* FIXME: There are dozens of them. Not sure we want them all.
|
2141 | aa0aa4fa | bellard | Most are for kernel building but some are for vis type stuff. */
|
2142 | aa0aa4fa | bellard | { 0, 0 } |
2143 | aa0aa4fa | bellard | }; |
2144 | aa0aa4fa | bellard | |
2145 | aa0aa4fa | bellard | /* Return the value for ASI NAME, or -1 if not found. */
|
2146 | aa0aa4fa | bellard | |
2147 | aa0aa4fa | bellard | int
|
2148 | aa0aa4fa | bellard | sparc_encode_asi (name) |
2149 | aa0aa4fa | bellard | const char *name; |
2150 | aa0aa4fa | bellard | { |
2151 | aa0aa4fa | bellard | return lookup_name (asi_table, name);
|
2152 | aa0aa4fa | bellard | } |
2153 | aa0aa4fa | bellard | |
2154 | aa0aa4fa | bellard | /* Return the name for ASI value VALUE or NULL if not found. */
|
2155 | aa0aa4fa | bellard | |
2156 | aa0aa4fa | bellard | const char * |
2157 | aa0aa4fa | bellard | sparc_decode_asi (value) |
2158 | aa0aa4fa | bellard | int value;
|
2159 | aa0aa4fa | bellard | { |
2160 | aa0aa4fa | bellard | return lookup_value (asi_table, value);
|
2161 | aa0aa4fa | bellard | } |
2162 | aa0aa4fa | bellard | |
2163 | aa0aa4fa | bellard | /* Handle membar masks. */
|
2164 | aa0aa4fa | bellard | |
2165 | aa0aa4fa | bellard | static arg membar_table[] =
|
2166 | aa0aa4fa | bellard | { |
2167 | aa0aa4fa | bellard | { 0x40, "#Sync" }, |
2168 | aa0aa4fa | bellard | { 0x20, "#MemIssue" }, |
2169 | aa0aa4fa | bellard | { 0x10, "#Lookaside" }, |
2170 | aa0aa4fa | bellard | { 0x08, "#StoreStore" }, |
2171 | aa0aa4fa | bellard | { 0x04, "#LoadStore" }, |
2172 | aa0aa4fa | bellard | { 0x02, "#StoreLoad" }, |
2173 | aa0aa4fa | bellard | { 0x01, "#LoadLoad" }, |
2174 | aa0aa4fa | bellard | { 0, 0 } |
2175 | aa0aa4fa | bellard | }; |
2176 | aa0aa4fa | bellard | |
2177 | aa0aa4fa | bellard | /* Return the value for membar arg NAME, or -1 if not found. */
|
2178 | aa0aa4fa | bellard | |
2179 | aa0aa4fa | bellard | int
|
2180 | aa0aa4fa | bellard | sparc_encode_membar (name) |
2181 | aa0aa4fa | bellard | const char *name; |
2182 | aa0aa4fa | bellard | { |
2183 | aa0aa4fa | bellard | return lookup_name (membar_table, name);
|
2184 | aa0aa4fa | bellard | } |
2185 | aa0aa4fa | bellard | |
2186 | aa0aa4fa | bellard | /* Return the name for membar value VALUE or NULL if not found. */
|
2187 | aa0aa4fa | bellard | |
2188 | aa0aa4fa | bellard | const char * |
2189 | aa0aa4fa | bellard | sparc_decode_membar (value) |
2190 | aa0aa4fa | bellard | int value;
|
2191 | aa0aa4fa | bellard | { |
2192 | aa0aa4fa | bellard | return lookup_value (membar_table, value);
|
2193 | aa0aa4fa | bellard | } |
2194 | aa0aa4fa | bellard | |
2195 | aa0aa4fa | bellard | /* Handle prefetch args. */
|
2196 | aa0aa4fa | bellard | |
2197 | aa0aa4fa | bellard | static arg prefetch_table[] =
|
2198 | aa0aa4fa | bellard | { |
2199 | aa0aa4fa | bellard | { 0, "#n_reads" }, |
2200 | aa0aa4fa | bellard | { 1, "#one_read" }, |
2201 | aa0aa4fa | bellard | { 2, "#n_writes" }, |
2202 | aa0aa4fa | bellard | { 3, "#one_write" }, |
2203 | aa0aa4fa | bellard | { 4, "#page" }, |
2204 | aa0aa4fa | bellard | { 16, "#invalidate" }, |
2205 | aa0aa4fa | bellard | { 0, 0 } |
2206 | aa0aa4fa | bellard | }; |
2207 | aa0aa4fa | bellard | |
2208 | aa0aa4fa | bellard | /* Return the value for prefetch arg NAME, or -1 if not found. */
|
2209 | aa0aa4fa | bellard | |
2210 | aa0aa4fa | bellard | int
|
2211 | aa0aa4fa | bellard | sparc_encode_prefetch (name) |
2212 | aa0aa4fa | bellard | const char *name; |
2213 | aa0aa4fa | bellard | { |
2214 | aa0aa4fa | bellard | return lookup_name (prefetch_table, name);
|
2215 | aa0aa4fa | bellard | } |
2216 | aa0aa4fa | bellard | |
2217 | aa0aa4fa | bellard | /* Return the name for prefetch value VALUE or NULL if not found. */
|
2218 | aa0aa4fa | bellard | |
2219 | aa0aa4fa | bellard | const char * |
2220 | aa0aa4fa | bellard | sparc_decode_prefetch (value) |
2221 | aa0aa4fa | bellard | int value;
|
2222 | aa0aa4fa | bellard | { |
2223 | aa0aa4fa | bellard | return lookup_value (prefetch_table, value);
|
2224 | aa0aa4fa | bellard | } |
2225 | aa0aa4fa | bellard | |
2226 | aa0aa4fa | bellard | /* Handle sparclet coprocessor registers. */
|
2227 | aa0aa4fa | bellard | |
2228 | aa0aa4fa | bellard | static arg sparclet_cpreg_table[] =
|
2229 | aa0aa4fa | bellard | { |
2230 | aa0aa4fa | bellard | { 0, "%ccsr" }, |
2231 | aa0aa4fa | bellard | { 1, "%ccfr" }, |
2232 | aa0aa4fa | bellard | { 2, "%cccrcr" }, |
2233 | aa0aa4fa | bellard | { 3, "%ccpr" }, |
2234 | aa0aa4fa | bellard | { 4, "%ccsr2" }, |
2235 | aa0aa4fa | bellard | { 5, "%cccrr" }, |
2236 | aa0aa4fa | bellard | { 6, "%ccrstr" }, |
2237 | aa0aa4fa | bellard | { 0, 0 } |
2238 | aa0aa4fa | bellard | }; |
2239 | aa0aa4fa | bellard | |
2240 | aa0aa4fa | bellard | /* Return the value for sparclet cpreg arg NAME, or -1 if not found. */
|
2241 | aa0aa4fa | bellard | |
2242 | aa0aa4fa | bellard | int
|
2243 | aa0aa4fa | bellard | sparc_encode_sparclet_cpreg (name) |
2244 | aa0aa4fa | bellard | const char *name; |
2245 | aa0aa4fa | bellard | { |
2246 | aa0aa4fa | bellard | return lookup_name (sparclet_cpreg_table, name);
|
2247 | aa0aa4fa | bellard | } |
2248 | aa0aa4fa | bellard | |
2249 | aa0aa4fa | bellard | /* Return the name for sparclet cpreg value VALUE or NULL if not found. */
|
2250 | aa0aa4fa | bellard | |
2251 | aa0aa4fa | bellard | const char * |
2252 | aa0aa4fa | bellard | sparc_decode_sparclet_cpreg (value) |
2253 | aa0aa4fa | bellard | int value;
|
2254 | aa0aa4fa | bellard | { |
2255 | aa0aa4fa | bellard | return lookup_value (sparclet_cpreg_table, value);
|
2256 | aa0aa4fa | bellard | } |
2257 | aa0aa4fa | bellard | |
2258 | aa0aa4fa | bellard | #undef MASK_V9
|
2259 | aa0aa4fa | bellard | |
2260 | aa0aa4fa | bellard | /* Bitmask of v9 architectures. */
|
2261 | aa0aa4fa | bellard | #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ |
2262 | aa0aa4fa | bellard | | (1 << SPARC_OPCODE_ARCH_V9A) \
|
2263 | aa0aa4fa | bellard | | (1 << SPARC_OPCODE_ARCH_V9B))
|
2264 | aa0aa4fa | bellard | /* 1 if INSN is for v9 only. */
|
2265 | aa0aa4fa | bellard | #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
|
2266 | aa0aa4fa | bellard | /* 1 if INSN is for v9. */
|
2267 | aa0aa4fa | bellard | #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) |
2268 | aa0aa4fa | bellard | |
2269 | aa0aa4fa | bellard | /* The sorted opcode table. */
|
2270 | aa0aa4fa | bellard | static const struct sparc_opcode **sorted_opcodes; |
2271 | aa0aa4fa | bellard | |
2272 | aa0aa4fa | bellard | /* For faster lookup, after insns are sorted they are hashed. */
|
2273 | aa0aa4fa | bellard | /* ??? I think there is room for even more improvement. */
|
2274 | aa0aa4fa | bellard | |
2275 | aa0aa4fa | bellard | #define HASH_SIZE 256 |
2276 | aa0aa4fa | bellard | /* It is important that we only look at insn code bits as that is how the
|
2277 | aa0aa4fa | bellard | opcode table is hashed. OPCODE_BITS is a table of valid bits for each
|
2278 | aa0aa4fa | bellard | of the main types (0,1,2,3). */
|
2279 | aa0aa4fa | bellard | static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; |
2280 | aa0aa4fa | bellard | #define HASH_INSN(INSN) \
|
2281 | aa0aa4fa | bellard | ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) |
2282 | aa0aa4fa | bellard | struct opcode_hash {
|
2283 | aa0aa4fa | bellard | struct opcode_hash *next;
|
2284 | aa0aa4fa | bellard | const struct sparc_opcode *opcode; |
2285 | aa0aa4fa | bellard | }; |
2286 | aa0aa4fa | bellard | static struct opcode_hash *opcode_hash_table[HASH_SIZE]; |
2287 | aa0aa4fa | bellard | |
2288 | aa0aa4fa | bellard | static void build_hash_table |
2289 | aa0aa4fa | bellard | PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int)); |
2290 | aa0aa4fa | bellard | static int is_delayed_branch PARAMS ((unsigned long)); |
2291 | aa0aa4fa | bellard | static int compare_opcodes PARAMS ((const void *, const void *)); |
2292 | aa0aa4fa | bellard | static int compute_arch_mask PARAMS ((unsigned long)); |
2293 | aa0aa4fa | bellard | |
2294 | aa0aa4fa | bellard | /* Sign-extend a value which is N bits long. */
|
2295 | aa0aa4fa | bellard | #define SEX(value, bits) \
|
2296 | aa0aa4fa | bellard | ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ |
2297 | aa0aa4fa | bellard | >> ((8 * sizeof (int)) - bits) ) |
2298 | aa0aa4fa | bellard | |
2299 | aa0aa4fa | bellard | static char *reg_names[] = |
2300 | aa0aa4fa | bellard | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
2301 | aa0aa4fa | bellard | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
2302 | aa0aa4fa | bellard | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
2303 | aa0aa4fa | bellard | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
2304 | aa0aa4fa | bellard | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
2305 | aa0aa4fa | bellard | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
2306 | aa0aa4fa | bellard | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
2307 | aa0aa4fa | bellard | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
2308 | aa0aa4fa | bellard | "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
2309 | aa0aa4fa | bellard | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", |
2310 | aa0aa4fa | bellard | "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", |
2311 | aa0aa4fa | bellard | "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", |
2312 | aa0aa4fa | bellard | /* psr, wim, tbr, fpsr, cpsr are v8 only. */
|
2313 | aa0aa4fa | bellard | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" |
2314 | aa0aa4fa | bellard | }; |
2315 | aa0aa4fa | bellard | |
2316 | aa0aa4fa | bellard | #define freg_names (®_names[4 * 8]) |
2317 | aa0aa4fa | bellard | |
2318 | aa0aa4fa | bellard | /* These are ordered according to there register number in
|
2319 | aa0aa4fa | bellard | rdpr and wrpr insns. */
|
2320 | aa0aa4fa | bellard | static char *v9_priv_reg_names[] = |
2321 | aa0aa4fa | bellard | { |
2322 | aa0aa4fa | bellard | "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", |
2323 | aa0aa4fa | bellard | "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", |
2324 | aa0aa4fa | bellard | "wstate", "fq" |
2325 | aa0aa4fa | bellard | /* "ver" - special cased */
|
2326 | aa0aa4fa | bellard | }; |
2327 | aa0aa4fa | bellard | |
2328 | aa0aa4fa | bellard | /* These are ordered according to there register number in
|
2329 | aa0aa4fa | bellard | rd and wr insns (-16). */
|
2330 | aa0aa4fa | bellard | static char *v9a_asr_reg_names[] = |
2331 | aa0aa4fa | bellard | { |
2332 | aa0aa4fa | bellard | "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", |
2333 | aa0aa4fa | bellard | "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr" |
2334 | aa0aa4fa | bellard | }; |
2335 | aa0aa4fa | bellard | |
2336 | aa0aa4fa | bellard | /* Macros used to extract instruction fields. Not all fields have
|
2337 | aa0aa4fa | bellard | macros defined here, only those which are actually used. */
|
2338 | aa0aa4fa | bellard | |
2339 | aa0aa4fa | bellard | #define X_RD(i) (((i) >> 25) & 0x1f) |
2340 | aa0aa4fa | bellard | #define X_RS1(i) (((i) >> 14) & 0x1f) |
2341 | aa0aa4fa | bellard | #define X_LDST_I(i) (((i) >> 13) & 1) |
2342 | aa0aa4fa | bellard | #define X_ASI(i) (((i) >> 5) & 0xff) |
2343 | aa0aa4fa | bellard | #define X_RS2(i) (((i) >> 0) & 0x1f) |
2344 | aa0aa4fa | bellard | #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) |
2345 | aa0aa4fa | bellard | #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
|
2346 | aa0aa4fa | bellard | #define X_DISP22(i) (((i) >> 0) & 0x3fffff) |
2347 | aa0aa4fa | bellard | #define X_IMM22(i) X_DISP22 (i)
|
2348 | aa0aa4fa | bellard | #define X_DISP30(i) (((i) >> 0) & 0x3fffffff) |
2349 | aa0aa4fa | bellard | |
2350 | aa0aa4fa | bellard | /* These are for v9. */
|
2351 | aa0aa4fa | bellard | #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) |
2352 | aa0aa4fa | bellard | #define X_DISP19(i) (((i) >> 0) & 0x7ffff) |
2353 | aa0aa4fa | bellard | #define X_MEMBAR(i) ((i) & 0x7f) |
2354 | aa0aa4fa | bellard | |
2355 | aa0aa4fa | bellard | /* Here is the union which was used to extract instruction fields
|
2356 | aa0aa4fa | bellard | before the shift and mask macros were written.
|
2357 | aa0aa4fa | bellard | |
2358 | aa0aa4fa | bellard | union sparc_insn
|
2359 | aa0aa4fa | bellard | {
|
2360 | aa0aa4fa | bellard | unsigned long int code;
|
2361 | aa0aa4fa | bellard | struct
|
2362 | aa0aa4fa | bellard | {
|
2363 | aa0aa4fa | bellard | unsigned int anop:2;
|
2364 | aa0aa4fa | bellard | #define op ldst.anop
|
2365 | aa0aa4fa | bellard | unsigned int anrd:5;
|
2366 | aa0aa4fa | bellard | #define rd ldst.anrd
|
2367 | aa0aa4fa | bellard | unsigned int op3:6;
|
2368 | aa0aa4fa | bellard | unsigned int anrs1:5;
|
2369 | aa0aa4fa | bellard | #define rs1 ldst.anrs1
|
2370 | aa0aa4fa | bellard | unsigned int i:1;
|
2371 | aa0aa4fa | bellard | unsigned int anasi:8;
|
2372 | aa0aa4fa | bellard | #define asi ldst.anasi
|
2373 | aa0aa4fa | bellard | unsigned int anrs2:5;
|
2374 | aa0aa4fa | bellard | #define rs2 ldst.anrs2
|
2375 | aa0aa4fa | bellard | #define shcnt rs2
|
2376 | aa0aa4fa | bellard | } ldst;
|
2377 | aa0aa4fa | bellard | struct
|
2378 | aa0aa4fa | bellard | {
|
2379 | aa0aa4fa | bellard | unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
|
2380 | aa0aa4fa | bellard | unsigned int IMM13:13;
|
2381 | aa0aa4fa | bellard | #define imm13 IMM13.IMM13
|
2382 | aa0aa4fa | bellard | } IMM13;
|
2383 | aa0aa4fa | bellard | struct
|
2384 | aa0aa4fa | bellard | {
|
2385 | aa0aa4fa | bellard | unsigned int anop:2;
|
2386 | aa0aa4fa | bellard | unsigned int a:1;
|
2387 | aa0aa4fa | bellard | unsigned int cond:4;
|
2388 | aa0aa4fa | bellard | unsigned int op2:3;
|
2389 | aa0aa4fa | bellard | unsigned int DISP22:22;
|
2390 | aa0aa4fa | bellard | #define disp22 branch.DISP22
|
2391 | aa0aa4fa | bellard | #define imm22 disp22
|
2392 | aa0aa4fa | bellard | } branch;
|
2393 | aa0aa4fa | bellard | struct
|
2394 | aa0aa4fa | bellard | {
|
2395 | aa0aa4fa | bellard | unsigned int anop:2;
|
2396 | aa0aa4fa | bellard | unsigned int a:1;
|
2397 | aa0aa4fa | bellard | unsigned int z:1;
|
2398 | aa0aa4fa | bellard | unsigned int rcond:3;
|
2399 | aa0aa4fa | bellard | unsigned int op2:3;
|
2400 | aa0aa4fa | bellard | unsigned int DISP16HI:2;
|
2401 | aa0aa4fa | bellard | unsigned int p:1;
|
2402 | aa0aa4fa | bellard | unsigned int _rs1:5;
|
2403 | aa0aa4fa | bellard | unsigned int DISP16LO:14;
|
2404 | aa0aa4fa | bellard | } branch16;
|
2405 | aa0aa4fa | bellard | struct
|
2406 | aa0aa4fa | bellard | {
|
2407 | aa0aa4fa | bellard | unsigned int anop:2;
|
2408 | aa0aa4fa | bellard | unsigned int adisp30:30;
|
2409 | aa0aa4fa | bellard | #define disp30 call.adisp30
|
2410 | aa0aa4fa | bellard | } call;
|
2411 | aa0aa4fa | bellard | };
|
2412 | aa0aa4fa | bellard | |
2413 | aa0aa4fa | bellard | */
|
2414 | aa0aa4fa | bellard | |
2415 | aa0aa4fa | bellard | /* Nonzero if INSN is the opcode for a delayed branch. */
|
2416 | aa0aa4fa | bellard | static int |
2417 | aa0aa4fa | bellard | is_delayed_branch (insn) |
2418 | aa0aa4fa | bellard | unsigned long insn; |
2419 | aa0aa4fa | bellard | { |
2420 | aa0aa4fa | bellard | struct opcode_hash *op;
|
2421 | aa0aa4fa | bellard | |
2422 | aa0aa4fa | bellard | for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
|
2423 | aa0aa4fa | bellard | { |
2424 | aa0aa4fa | bellard | const struct sparc_opcode *opcode = op->opcode; |
2425 | aa0aa4fa | bellard | if ((opcode->match & insn) == opcode->match
|
2426 | aa0aa4fa | bellard | && (opcode->lose & insn) == 0)
|
2427 | aa0aa4fa | bellard | return (opcode->flags & F_DELAYED);
|
2428 | aa0aa4fa | bellard | } |
2429 | aa0aa4fa | bellard | return 0; |
2430 | aa0aa4fa | bellard | } |
2431 | aa0aa4fa | bellard | |
2432 | aa0aa4fa | bellard | /* extern void qsort (); */
|
2433 | aa0aa4fa | bellard | |
2434 | aa0aa4fa | bellard | /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
|
2435 | aa0aa4fa | bellard | to compare_opcodes. */
|
2436 | aa0aa4fa | bellard | static unsigned int current_arch_mask; |
2437 | aa0aa4fa | bellard | |
2438 | aa0aa4fa | bellard | /* Print one instruction from MEMADDR on INFO->STREAM.
|
2439 | aa0aa4fa | bellard | |
2440 | aa0aa4fa | bellard | We suffix the instruction with a comment that gives the absolute
|
2441 | aa0aa4fa | bellard | address involved, as well as its symbolic form, if the instruction
|
2442 | aa0aa4fa | bellard | is preceded by a findable `sethi' and it either adds an immediate
|
2443 | aa0aa4fa | bellard | displacement to that register, or it is an `add' or `or' instruction
|
2444 | aa0aa4fa | bellard | on that register. */
|
2445 | aa0aa4fa | bellard | |
2446 | aa0aa4fa | bellard | int
|
2447 | aa0aa4fa | bellard | print_insn_sparc (memaddr, info) |
2448 | aa0aa4fa | bellard | bfd_vma memaddr; |
2449 | aa0aa4fa | bellard | disassemble_info *info; |
2450 | aa0aa4fa | bellard | { |
2451 | aa0aa4fa | bellard | FILE *stream = info->stream; |
2452 | aa0aa4fa | bellard | bfd_byte buffer[4];
|
2453 | aa0aa4fa | bellard | unsigned long insn; |
2454 | aa0aa4fa | bellard | register struct opcode_hash *op; |
2455 | aa0aa4fa | bellard | /* Nonzero of opcode table has been initialized. */
|
2456 | aa0aa4fa | bellard | static int opcodes_initialized = 0; |
2457 | aa0aa4fa | bellard | /* bfd mach number of last call. */
|
2458 | aa0aa4fa | bellard | static unsigned long current_mach = 0; |
2459 | aa0aa4fa | bellard | bfd_vma (*getword) PARAMS ((const unsigned char *)); |
2460 | aa0aa4fa | bellard | |
2461 | aa0aa4fa | bellard | if (!opcodes_initialized
|
2462 | aa0aa4fa | bellard | || info->mach != current_mach) |
2463 | aa0aa4fa | bellard | { |
2464 | aa0aa4fa | bellard | int i;
|
2465 | aa0aa4fa | bellard | |
2466 | aa0aa4fa | bellard | current_arch_mask = compute_arch_mask (info->mach); |
2467 | aa0aa4fa | bellard | |
2468 | aa0aa4fa | bellard | if (!opcodes_initialized)
|
2469 | aa0aa4fa | bellard | sorted_opcodes = (const struct sparc_opcode **) |
2470 | aa0aa4fa | bellard | malloc (sparc_num_opcodes * sizeof (struct sparc_opcode *)); |
2471 | aa0aa4fa | bellard | /* Reset the sorted table so we can resort it. */
|
2472 | aa0aa4fa | bellard | for (i = 0; i < sparc_num_opcodes; ++i) |
2473 | aa0aa4fa | bellard | sorted_opcodes[i] = &sparc_opcodes[i]; |
2474 | aa0aa4fa | bellard | qsort ((char *) sorted_opcodes, sparc_num_opcodes,
|
2475 | aa0aa4fa | bellard | sizeof (sorted_opcodes[0]), compare_opcodes); |
2476 | aa0aa4fa | bellard | |
2477 | aa0aa4fa | bellard | build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); |
2478 | aa0aa4fa | bellard | current_mach = info->mach; |
2479 | aa0aa4fa | bellard | opcodes_initialized = 1;
|
2480 | aa0aa4fa | bellard | } |
2481 | aa0aa4fa | bellard | |
2482 | aa0aa4fa | bellard | { |
2483 | aa0aa4fa | bellard | int status =
|
2484 | aa0aa4fa | bellard | (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
|
2485 | aa0aa4fa | bellard | if (status != 0) |
2486 | aa0aa4fa | bellard | { |
2487 | aa0aa4fa | bellard | (*info->memory_error_func) (status, memaddr, info); |
2488 | aa0aa4fa | bellard | return -1; |
2489 | aa0aa4fa | bellard | } |
2490 | aa0aa4fa | bellard | } |
2491 | aa0aa4fa | bellard | |
2492 | aa0aa4fa | bellard | /* On SPARClite variants such as DANlite (sparc86x), instructions
|
2493 | aa0aa4fa | bellard | are always big-endian even when the machine is in little-endian mode. */
|
2494 | aa0aa4fa | bellard | if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
|
2495 | aa0aa4fa | bellard | getword = bfd_getb32; |
2496 | aa0aa4fa | bellard | else
|
2497 | aa0aa4fa | bellard | getword = bfd_getl32; |
2498 | aa0aa4fa | bellard | |
2499 | aa0aa4fa | bellard | insn = getword (buffer); |
2500 | aa0aa4fa | bellard | |
2501 | aa0aa4fa | bellard | info->insn_info_valid = 1; /* We do return this info */ |
2502 | aa0aa4fa | bellard | info->insn_type = dis_nonbranch; /* Assume non branch insn */
|
2503 | aa0aa4fa | bellard | info->branch_delay_insns = 0; /* Assume no delay */ |
2504 | aa0aa4fa | bellard | info->target = 0; /* Assume no target known */ |
2505 | aa0aa4fa | bellard | |
2506 | aa0aa4fa | bellard | for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
|
2507 | aa0aa4fa | bellard | { |
2508 | aa0aa4fa | bellard | const struct sparc_opcode *opcode = op->opcode; |
2509 | aa0aa4fa | bellard | |
2510 | aa0aa4fa | bellard | /* If the insn isn't supported by the current architecture, skip it. */
|
2511 | aa0aa4fa | bellard | if (! (opcode->architecture & current_arch_mask))
|
2512 | aa0aa4fa | bellard | continue;
|
2513 | aa0aa4fa | bellard | |
2514 | aa0aa4fa | bellard | if ((opcode->match & insn) == opcode->match
|
2515 | aa0aa4fa | bellard | && (opcode->lose & insn) == 0)
|
2516 | aa0aa4fa | bellard | { |
2517 | aa0aa4fa | bellard | /* Nonzero means that we have found an instruction which has
|
2518 | aa0aa4fa | bellard | the effect of adding or or'ing the imm13 field to rs1. */
|
2519 | aa0aa4fa | bellard | int imm_added_to_rs1 = 0; |
2520 | aa0aa4fa | bellard | int imm_ored_to_rs1 = 0; |
2521 | aa0aa4fa | bellard | |
2522 | aa0aa4fa | bellard | /* Nonzero means that we have found a plus sign in the args
|
2523 | aa0aa4fa | bellard | field of the opcode table. */
|
2524 | aa0aa4fa | bellard | int found_plus = 0; |
2525 | aa0aa4fa | bellard | |
2526 | aa0aa4fa | bellard | /* Nonzero means we have an annulled branch. */
|
2527 | aa0aa4fa | bellard | int is_annulled = 0; |
2528 | aa0aa4fa | bellard | |
2529 | aa0aa4fa | bellard | /* Do we have an `add' or `or' instruction combining an
|
2530 | aa0aa4fa | bellard | immediate with rs1? */
|
2531 | aa0aa4fa | bellard | if (opcode->match == 0x80102000) /* or */ |
2532 | aa0aa4fa | bellard | imm_ored_to_rs1 = 1;
|
2533 | aa0aa4fa | bellard | if (opcode->match == 0x80002000) /* add */ |
2534 | aa0aa4fa | bellard | imm_added_to_rs1 = 1;
|
2535 | aa0aa4fa | bellard | |
2536 | aa0aa4fa | bellard | if (X_RS1 (insn) != X_RD (insn)
|
2537 | aa0aa4fa | bellard | && strchr (opcode->args, 'r') != 0) |
2538 | aa0aa4fa | bellard | /* Can't do simple format if source and dest are different. */
|
2539 | aa0aa4fa | bellard | continue;
|
2540 | aa0aa4fa | bellard | if (X_RS2 (insn) != X_RD (insn)
|
2541 | aa0aa4fa | bellard | && strchr (opcode->args, 'O') != 0) |
2542 | aa0aa4fa | bellard | /* Can't do simple format if source and dest are different. */
|
2543 | aa0aa4fa | bellard | continue;
|
2544 | aa0aa4fa | bellard | |
2545 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, opcode->name); |
2546 | aa0aa4fa | bellard | |
2547 | aa0aa4fa | bellard | { |
2548 | aa0aa4fa | bellard | register const char *s; |
2549 | aa0aa4fa | bellard | |
2550 | aa0aa4fa | bellard | if (opcode->args[0] != ',') |
2551 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, " ");
|
2552 | aa0aa4fa | bellard | for (s = opcode->args; *s != '\0'; ++s) |
2553 | aa0aa4fa | bellard | { |
2554 | aa0aa4fa | bellard | while (*s == ',') |
2555 | aa0aa4fa | bellard | { |
2556 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, ",");
|
2557 | aa0aa4fa | bellard | ++s; |
2558 | aa0aa4fa | bellard | switch (*s) {
|
2559 | aa0aa4fa | bellard | case 'a': |
2560 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "a");
|
2561 | aa0aa4fa | bellard | is_annulled = 1;
|
2562 | aa0aa4fa | bellard | ++s; |
2563 | aa0aa4fa | bellard | continue;
|
2564 | aa0aa4fa | bellard | case 'N': |
2565 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "pn");
|
2566 | aa0aa4fa | bellard | ++s; |
2567 | aa0aa4fa | bellard | continue;
|
2568 | aa0aa4fa | bellard | |
2569 | aa0aa4fa | bellard | case 'T': |
2570 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "pt");
|
2571 | aa0aa4fa | bellard | ++s; |
2572 | aa0aa4fa | bellard | continue;
|
2573 | aa0aa4fa | bellard | |
2574 | aa0aa4fa | bellard | default:
|
2575 | aa0aa4fa | bellard | break;
|
2576 | aa0aa4fa | bellard | } /* switch on arg */
|
2577 | aa0aa4fa | bellard | } /* while there are comma started args */
|
2578 | aa0aa4fa | bellard | |
2579 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, " ");
|
2580 | aa0aa4fa | bellard | |
2581 | aa0aa4fa | bellard | switch (*s)
|
2582 | aa0aa4fa | bellard | { |
2583 | aa0aa4fa | bellard | case '+': |
2584 | aa0aa4fa | bellard | found_plus = 1;
|
2585 | aa0aa4fa | bellard | |
2586 | aa0aa4fa | bellard | /* note fall-through */
|
2587 | aa0aa4fa | bellard | default:
|
2588 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%c", *s);
|
2589 | aa0aa4fa | bellard | break;
|
2590 | aa0aa4fa | bellard | |
2591 | aa0aa4fa | bellard | case '#': |
2592 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "0");
|
2593 | aa0aa4fa | bellard | break;
|
2594 | aa0aa4fa | bellard | |
2595 | aa0aa4fa | bellard | #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) |
2596 | aa0aa4fa | bellard | case '1': |
2597 | aa0aa4fa | bellard | case 'r': |
2598 | aa0aa4fa | bellard | reg (X_RS1 (insn)); |
2599 | aa0aa4fa | bellard | break;
|
2600 | aa0aa4fa | bellard | |
2601 | aa0aa4fa | bellard | case '2': |
2602 | aa0aa4fa | bellard | case 'O': |
2603 | aa0aa4fa | bellard | reg (X_RS2 (insn)); |
2604 | aa0aa4fa | bellard | break;
|
2605 | aa0aa4fa | bellard | |
2606 | aa0aa4fa | bellard | case 'd': |
2607 | aa0aa4fa | bellard | reg (X_RD (insn)); |
2608 | aa0aa4fa | bellard | break;
|
2609 | aa0aa4fa | bellard | #undef reg
|
2610 | aa0aa4fa | bellard | |
2611 | aa0aa4fa | bellard | #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) |
2612 | aa0aa4fa | bellard | #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) |
2613 | aa0aa4fa | bellard | case 'e': |
2614 | aa0aa4fa | bellard | freg (X_RS1 (insn)); |
2615 | aa0aa4fa | bellard | break;
|
2616 | aa0aa4fa | bellard | case 'v': /* double/even */ |
2617 | aa0aa4fa | bellard | case 'V': /* quad/multiple of 4 */ |
2618 | aa0aa4fa | bellard | fregx (X_RS1 (insn)); |
2619 | aa0aa4fa | bellard | break;
|
2620 | aa0aa4fa | bellard | |
2621 | aa0aa4fa | bellard | case 'f': |
2622 | aa0aa4fa | bellard | freg (X_RS2 (insn)); |
2623 | aa0aa4fa | bellard | break;
|
2624 | aa0aa4fa | bellard | case 'B': /* double/even */ |
2625 | aa0aa4fa | bellard | case 'R': /* quad/multiple of 4 */ |
2626 | aa0aa4fa | bellard | fregx (X_RS2 (insn)); |
2627 | aa0aa4fa | bellard | break;
|
2628 | aa0aa4fa | bellard | |
2629 | aa0aa4fa | bellard | case 'g': |
2630 | aa0aa4fa | bellard | freg (X_RD (insn)); |
2631 | aa0aa4fa | bellard | break;
|
2632 | aa0aa4fa | bellard | case 'H': /* double/even */ |
2633 | aa0aa4fa | bellard | case 'J': /* quad/multiple of 4 */ |
2634 | aa0aa4fa | bellard | fregx (X_RD (insn)); |
2635 | aa0aa4fa | bellard | break;
|
2636 | aa0aa4fa | bellard | #undef freg
|
2637 | aa0aa4fa | bellard | #undef fregx
|
2638 | aa0aa4fa | bellard | |
2639 | aa0aa4fa | bellard | #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) |
2640 | aa0aa4fa | bellard | case 'b': |
2641 | aa0aa4fa | bellard | creg (X_RS1 (insn)); |
2642 | aa0aa4fa | bellard | break;
|
2643 | aa0aa4fa | bellard | |
2644 | aa0aa4fa | bellard | case 'c': |
2645 | aa0aa4fa | bellard | creg (X_RS2 (insn)); |
2646 | aa0aa4fa | bellard | break;
|
2647 | aa0aa4fa | bellard | |
2648 | aa0aa4fa | bellard | case 'D': |
2649 | aa0aa4fa | bellard | creg (X_RD (insn)); |
2650 | aa0aa4fa | bellard | break;
|
2651 | aa0aa4fa | bellard | #undef creg
|
2652 | aa0aa4fa | bellard | |
2653 | aa0aa4fa | bellard | case 'h': |
2654 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%hi(%#x)",
|
2655 | aa0aa4fa | bellard | ((unsigned) 0xFFFFFFFF |
2656 | aa0aa4fa | bellard | & ((int) X_IMM22 (insn) << 10))); |
2657 | aa0aa4fa | bellard | break;
|
2658 | aa0aa4fa | bellard | |
2659 | aa0aa4fa | bellard | case 'i': /* 13 bit immediate */ |
2660 | aa0aa4fa | bellard | case 'I': /* 11 bit immediate */ |
2661 | aa0aa4fa | bellard | case 'j': /* 10 bit immediate */ |
2662 | aa0aa4fa | bellard | { |
2663 | aa0aa4fa | bellard | int imm;
|
2664 | aa0aa4fa | bellard | |
2665 | aa0aa4fa | bellard | if (*s == 'i') |
2666 | aa0aa4fa | bellard | imm = X_SIMM (insn, 13);
|
2667 | aa0aa4fa | bellard | else if (*s == 'I') |
2668 | aa0aa4fa | bellard | imm = X_SIMM (insn, 11);
|
2669 | aa0aa4fa | bellard | else
|
2670 | aa0aa4fa | bellard | imm = X_SIMM (insn, 10);
|
2671 | aa0aa4fa | bellard | |
2672 | aa0aa4fa | bellard | /* Check to see whether we have a 1+i, and take
|
2673 | aa0aa4fa | bellard | note of that fact.
|
2674 | aa0aa4fa | bellard | |
2675 | aa0aa4fa | bellard | Note: because of the way we sort the table,
|
2676 | aa0aa4fa | bellard | we will be matching 1+i rather than i+1,
|
2677 | aa0aa4fa | bellard | so it is OK to assume that i is after +,
|
2678 | aa0aa4fa | bellard | not before it. */
|
2679 | aa0aa4fa | bellard | if (found_plus)
|
2680 | aa0aa4fa | bellard | imm_added_to_rs1 = 1;
|
2681 | aa0aa4fa | bellard | |
2682 | aa0aa4fa | bellard | if (imm <= 9) |
2683 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%d", imm);
|
2684 | aa0aa4fa | bellard | else
|
2685 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%#x", imm);
|
2686 | aa0aa4fa | bellard | } |
2687 | aa0aa4fa | bellard | break;
|
2688 | aa0aa4fa | bellard | |
2689 | aa0aa4fa | bellard | case 'X': /* 5 bit unsigned immediate */ |
2690 | aa0aa4fa | bellard | case 'Y': /* 6 bit unsigned immediate */ |
2691 | aa0aa4fa | bellard | { |
2692 | aa0aa4fa | bellard | int imm = X_IMM (insn, *s == 'X' ? 5 : 6); |
2693 | aa0aa4fa | bellard | |
2694 | aa0aa4fa | bellard | if (imm <= 9) |
2695 | aa0aa4fa | bellard | (info->fprintf_func) (stream, "%d", imm);
|
2696 | aa0aa4fa | bellard | else
|
2697 | aa0aa4fa | bellard | (info->fprintf_func) (stream, "%#x", (unsigned) imm); |
2698 | aa0aa4fa | bellard | } |
2699 | aa0aa4fa | bellard | break;
|
2700 | aa0aa4fa | bellard | |
2701 | aa0aa4fa | bellard | case '3': |
2702 | aa0aa4fa | bellard | (info->fprintf_func) (stream, "%d", X_IMM (insn, 3)); |
2703 | aa0aa4fa | bellard | break;
|
2704 | aa0aa4fa | bellard | |
2705 | aa0aa4fa | bellard | case 'K': |
2706 | aa0aa4fa | bellard | { |
2707 | aa0aa4fa | bellard | int mask = X_MEMBAR (insn);
|
2708 | aa0aa4fa | bellard | int bit = 0x40, printed_one = 0; |
2709 | aa0aa4fa | bellard | const char *name; |
2710 | aa0aa4fa | bellard | |
2711 | aa0aa4fa | bellard | if (mask == 0) |
2712 | aa0aa4fa | bellard | (info->fprintf_func) (stream, "0");
|
2713 | aa0aa4fa | bellard | else
|
2714 | aa0aa4fa | bellard | while (bit)
|
2715 | aa0aa4fa | bellard | { |
2716 | aa0aa4fa | bellard | if (mask & bit)
|
2717 | aa0aa4fa | bellard | { |
2718 | aa0aa4fa | bellard | if (printed_one)
|
2719 | aa0aa4fa | bellard | (info->fprintf_func) (stream, "|");
|
2720 | aa0aa4fa | bellard | name = sparc_decode_membar (bit); |
2721 | aa0aa4fa | bellard | (info->fprintf_func) (stream, "%s", name);
|
2722 | aa0aa4fa | bellard | printed_one = 1;
|
2723 | aa0aa4fa | bellard | } |
2724 | aa0aa4fa | bellard | bit >>= 1;
|
2725 | aa0aa4fa | bellard | } |
2726 | aa0aa4fa | bellard | break;
|
2727 | aa0aa4fa | bellard | } |
2728 | aa0aa4fa | bellard | |
2729 | aa0aa4fa | bellard | case 'k': |
2730 | aa0aa4fa | bellard | info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; |
2731 | aa0aa4fa | bellard | (*info->print_address_func) (info->target, info); |
2732 | aa0aa4fa | bellard | break;
|
2733 | aa0aa4fa | bellard | |
2734 | aa0aa4fa | bellard | case 'G': |
2735 | aa0aa4fa | bellard | info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; |
2736 | aa0aa4fa | bellard | (*info->print_address_func) (info->target, info); |
2737 | aa0aa4fa | bellard | break;
|
2738 | aa0aa4fa | bellard | |
2739 | aa0aa4fa | bellard | case '6': |
2740 | aa0aa4fa | bellard | case '7': |
2741 | aa0aa4fa | bellard | case '8': |
2742 | aa0aa4fa | bellard | case '9': |
2743 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); |
2744 | aa0aa4fa | bellard | break;
|
2745 | aa0aa4fa | bellard | |
2746 | aa0aa4fa | bellard | case 'z': |
2747 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%icc");
|
2748 | aa0aa4fa | bellard | break;
|
2749 | aa0aa4fa | bellard | |
2750 | aa0aa4fa | bellard | case 'Z': |
2751 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%xcc");
|
2752 | aa0aa4fa | bellard | break;
|
2753 | aa0aa4fa | bellard | |
2754 | aa0aa4fa | bellard | case 'E': |
2755 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%ccr");
|
2756 | aa0aa4fa | bellard | break;
|
2757 | aa0aa4fa | bellard | |
2758 | aa0aa4fa | bellard | case 's': |
2759 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%fprs");
|
2760 | aa0aa4fa | bellard | break;
|
2761 | aa0aa4fa | bellard | |
2762 | aa0aa4fa | bellard | case 'o': |
2763 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%asi");
|
2764 | aa0aa4fa | bellard | break;
|
2765 | aa0aa4fa | bellard | |
2766 | aa0aa4fa | bellard | case 'W': |
2767 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%tick");
|
2768 | aa0aa4fa | bellard | break;
|
2769 | aa0aa4fa | bellard | |
2770 | aa0aa4fa | bellard | case 'P': |
2771 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%pc");
|
2772 | aa0aa4fa | bellard | break;
|
2773 | aa0aa4fa | bellard | |
2774 | aa0aa4fa | bellard | case '?': |
2775 | aa0aa4fa | bellard | if (X_RS1 (insn) == 31) |
2776 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%ver");
|
2777 | aa0aa4fa | bellard | else if ((unsigned) X_RS1 (insn) < 16) |
2778 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%%s",
|
2779 | aa0aa4fa | bellard | v9_priv_reg_names[X_RS1 (insn)]); |
2780 | aa0aa4fa | bellard | else
|
2781 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%reserved");
|
2782 | aa0aa4fa | bellard | break;
|
2783 | aa0aa4fa | bellard | |
2784 | aa0aa4fa | bellard | case '!': |
2785 | aa0aa4fa | bellard | if ((unsigned) X_RD (insn) < 15) |
2786 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%%s",
|
2787 | aa0aa4fa | bellard | v9_priv_reg_names[X_RD (insn)]); |
2788 | aa0aa4fa | bellard | else
|
2789 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%reserved");
|
2790 | aa0aa4fa | bellard | break;
|
2791 | aa0aa4fa | bellard | |
2792 | aa0aa4fa | bellard | case '/': |
2793 | aa0aa4fa | bellard | if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) |
2794 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%reserved");
|
2795 | aa0aa4fa | bellard | else
|
2796 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%%s",
|
2797 | aa0aa4fa | bellard | v9a_asr_reg_names[X_RS1 (insn)-16]);
|
2798 | aa0aa4fa | bellard | break;
|
2799 | aa0aa4fa | bellard | |
2800 | aa0aa4fa | bellard | case '_': |
2801 | aa0aa4fa | bellard | if (X_RD (insn) < 16 || X_RD (insn) > 25) |
2802 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%reserved");
|
2803 | aa0aa4fa | bellard | else
|
2804 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%%s",
|
2805 | aa0aa4fa | bellard | v9a_asr_reg_names[X_RD (insn)-16]);
|
2806 | aa0aa4fa | bellard | break;
|
2807 | aa0aa4fa | bellard | |
2808 | aa0aa4fa | bellard | case '*': |
2809 | aa0aa4fa | bellard | { |
2810 | aa0aa4fa | bellard | const char *name = sparc_decode_prefetch (X_RD (insn)); |
2811 | aa0aa4fa | bellard | |
2812 | aa0aa4fa | bellard | if (name)
|
2813 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%s", name);
|
2814 | aa0aa4fa | bellard | else
|
2815 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%d", X_RD (insn));
|
2816 | aa0aa4fa | bellard | break;
|
2817 | aa0aa4fa | bellard | } |
2818 | aa0aa4fa | bellard | |
2819 | aa0aa4fa | bellard | case 'M': |
2820 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
|
2821 | aa0aa4fa | bellard | break;
|
2822 | aa0aa4fa | bellard | |
2823 | aa0aa4fa | bellard | case 'm': |
2824 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
|
2825 | aa0aa4fa | bellard | break;
|
2826 | aa0aa4fa | bellard | |
2827 | aa0aa4fa | bellard | case 'L': |
2828 | aa0aa4fa | bellard | info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; |
2829 | aa0aa4fa | bellard | (*info->print_address_func) (info->target, info); |
2830 | aa0aa4fa | bellard | break;
|
2831 | aa0aa4fa | bellard | |
2832 | aa0aa4fa | bellard | case 'n': |
2833 | aa0aa4fa | bellard | (*info->fprintf_func) |
2834 | aa0aa4fa | bellard | (stream, "%#x", SEX (X_DISP22 (insn), 22)); |
2835 | aa0aa4fa | bellard | break;
|
2836 | aa0aa4fa | bellard | |
2837 | aa0aa4fa | bellard | case 'l': |
2838 | aa0aa4fa | bellard | info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; |
2839 | aa0aa4fa | bellard | (*info->print_address_func) (info->target, info); |
2840 | aa0aa4fa | bellard | break;
|
2841 | aa0aa4fa | bellard | |
2842 | aa0aa4fa | bellard | case 'A': |
2843 | aa0aa4fa | bellard | { |
2844 | aa0aa4fa | bellard | const char *name = sparc_decode_asi (X_ASI (insn)); |
2845 | aa0aa4fa | bellard | |
2846 | aa0aa4fa | bellard | if (name)
|
2847 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%s", name);
|
2848 | aa0aa4fa | bellard | else
|
2849 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
|
2850 | aa0aa4fa | bellard | break;
|
2851 | aa0aa4fa | bellard | } |
2852 | aa0aa4fa | bellard | |
2853 | aa0aa4fa | bellard | case 'C': |
2854 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%csr");
|
2855 | aa0aa4fa | bellard | break;
|
2856 | aa0aa4fa | bellard | |
2857 | aa0aa4fa | bellard | case 'F': |
2858 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%fsr");
|
2859 | aa0aa4fa | bellard | break;
|
2860 | aa0aa4fa | bellard | |
2861 | aa0aa4fa | bellard | case 'p': |
2862 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%psr");
|
2863 | aa0aa4fa | bellard | break;
|
2864 | aa0aa4fa | bellard | |
2865 | aa0aa4fa | bellard | case 'q': |
2866 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%fq");
|
2867 | aa0aa4fa | bellard | break;
|
2868 | aa0aa4fa | bellard | |
2869 | aa0aa4fa | bellard | case 'Q': |
2870 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%cq");
|
2871 | aa0aa4fa | bellard | break;
|
2872 | aa0aa4fa | bellard | |
2873 | aa0aa4fa | bellard | case 't': |
2874 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%tbr");
|
2875 | aa0aa4fa | bellard | break;
|
2876 | aa0aa4fa | bellard | |
2877 | aa0aa4fa | bellard | case 'w': |
2878 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%wim");
|
2879 | aa0aa4fa | bellard | break;
|
2880 | aa0aa4fa | bellard | |
2881 | aa0aa4fa | bellard | case 'x': |
2882 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%d",
|
2883 | aa0aa4fa | bellard | ((X_LDST_I (insn) << 8)
|
2884 | aa0aa4fa | bellard | + X_ASI (insn))); |
2885 | aa0aa4fa | bellard | break;
|
2886 | aa0aa4fa | bellard | |
2887 | aa0aa4fa | bellard | case 'y': |
2888 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%y");
|
2889 | aa0aa4fa | bellard | break;
|
2890 | aa0aa4fa | bellard | |
2891 | aa0aa4fa | bellard | case 'u': |
2892 | aa0aa4fa | bellard | case 'U': |
2893 | aa0aa4fa | bellard | { |
2894 | aa0aa4fa | bellard | int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); |
2895 | aa0aa4fa | bellard | const char *name = sparc_decode_sparclet_cpreg (val); |
2896 | aa0aa4fa | bellard | |
2897 | aa0aa4fa | bellard | if (name)
|
2898 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%s", name);
|
2899 | aa0aa4fa | bellard | else
|
2900 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
|
2901 | aa0aa4fa | bellard | break;
|
2902 | aa0aa4fa | bellard | } |
2903 | aa0aa4fa | bellard | } |
2904 | aa0aa4fa | bellard | } |
2905 | aa0aa4fa | bellard | } |
2906 | aa0aa4fa | bellard | |
2907 | aa0aa4fa | bellard | /* If we are adding or or'ing something to rs1, then
|
2908 | aa0aa4fa | bellard | check to see whether the previous instruction was
|
2909 | aa0aa4fa | bellard | a sethi to the same register as in the sethi.
|
2910 | aa0aa4fa | bellard | If so, attempt to print the result of the add or
|
2911 | aa0aa4fa | bellard | or (in this context add and or do the same thing)
|
2912 | aa0aa4fa | bellard | and its symbolic value. */
|
2913 | aa0aa4fa | bellard | if (imm_ored_to_rs1 || imm_added_to_rs1)
|
2914 | aa0aa4fa | bellard | { |
2915 | aa0aa4fa | bellard | unsigned long prev_insn; |
2916 | aa0aa4fa | bellard | int errcode;
|
2917 | aa0aa4fa | bellard | |
2918 | aa0aa4fa | bellard | errcode = |
2919 | aa0aa4fa | bellard | (*info->read_memory_func) |
2920 | aa0aa4fa | bellard | (memaddr - 4, buffer, sizeof (buffer), info); |
2921 | aa0aa4fa | bellard | prev_insn = getword (buffer); |
2922 | aa0aa4fa | bellard | |
2923 | aa0aa4fa | bellard | if (errcode == 0) |
2924 | aa0aa4fa | bellard | { |
2925 | aa0aa4fa | bellard | /* If it is a delayed branch, we need to look at the
|
2926 | aa0aa4fa | bellard | instruction before the delayed branch. This handles
|
2927 | aa0aa4fa | bellard | sequences such as
|
2928 | aa0aa4fa | bellard | |
2929 | aa0aa4fa | bellard | sethi %o1, %hi(_foo), %o1
|
2930 | aa0aa4fa | bellard | call _printf
|
2931 | aa0aa4fa | bellard | or %o1, %lo(_foo), %o1
|
2932 | aa0aa4fa | bellard | */
|
2933 | aa0aa4fa | bellard | |
2934 | aa0aa4fa | bellard | if (is_delayed_branch (prev_insn))
|
2935 | aa0aa4fa | bellard | { |
2936 | aa0aa4fa | bellard | errcode = (*info->read_memory_func) |
2937 | aa0aa4fa | bellard | (memaddr - 8, buffer, sizeof (buffer), info); |
2938 | aa0aa4fa | bellard | prev_insn = getword (buffer); |
2939 | aa0aa4fa | bellard | } |
2940 | aa0aa4fa | bellard | } |
2941 | aa0aa4fa | bellard | |
2942 | aa0aa4fa | bellard | /* If there was a problem reading memory, then assume
|
2943 | aa0aa4fa | bellard | the previous instruction was not sethi. */
|
2944 | aa0aa4fa | bellard | if (errcode == 0) |
2945 | aa0aa4fa | bellard | { |
2946 | aa0aa4fa | bellard | /* Is it sethi to the same register? */
|
2947 | aa0aa4fa | bellard | if ((prev_insn & 0xc1c00000) == 0x01000000 |
2948 | aa0aa4fa | bellard | && X_RD (prev_insn) == X_RS1 (insn)) |
2949 | aa0aa4fa | bellard | { |
2950 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, "\t! ");
|
2951 | aa0aa4fa | bellard | info->target = |
2952 | aa0aa4fa | bellard | ((unsigned) 0xFFFFFFFF |
2953 | aa0aa4fa | bellard | & ((int) X_IMM22 (prev_insn) << 10)); |
2954 | aa0aa4fa | bellard | if (imm_added_to_rs1)
|
2955 | aa0aa4fa | bellard | info->target += X_SIMM (insn, 13);
|
2956 | aa0aa4fa | bellard | else
|
2957 | aa0aa4fa | bellard | info->target |= X_SIMM (insn, 13);
|
2958 | aa0aa4fa | bellard | (*info->print_address_func) (info->target, info); |
2959 | aa0aa4fa | bellard | info->insn_type = dis_dref; |
2960 | aa0aa4fa | bellard | info->data_size = 4; /* FIXME!!! */ |
2961 | aa0aa4fa | bellard | } |
2962 | aa0aa4fa | bellard | } |
2963 | aa0aa4fa | bellard | } |
2964 | aa0aa4fa | bellard | |
2965 | aa0aa4fa | bellard | if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
|
2966 | aa0aa4fa | bellard | { |
2967 | aa0aa4fa | bellard | /* FIXME -- check is_annulled flag */
|
2968 | aa0aa4fa | bellard | if (opcode->flags & F_UNBR)
|
2969 | aa0aa4fa | bellard | info->insn_type = dis_branch; |
2970 | aa0aa4fa | bellard | if (opcode->flags & F_CONDBR)
|
2971 | aa0aa4fa | bellard | info->insn_type = dis_condbranch; |
2972 | aa0aa4fa | bellard | if (opcode->flags & F_JSR)
|
2973 | aa0aa4fa | bellard | info->insn_type = dis_jsr; |
2974 | aa0aa4fa | bellard | if (opcode->flags & F_DELAYED)
|
2975 | aa0aa4fa | bellard | info->branch_delay_insns = 1;
|
2976 | aa0aa4fa | bellard | } |
2977 | aa0aa4fa | bellard | |
2978 | aa0aa4fa | bellard | return sizeof (buffer); |
2979 | aa0aa4fa | bellard | } |
2980 | aa0aa4fa | bellard | } |
2981 | aa0aa4fa | bellard | |
2982 | aa0aa4fa | bellard | info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
|
2983 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, _("unknown"));
|
2984 | aa0aa4fa | bellard | return sizeof (buffer); |
2985 | aa0aa4fa | bellard | } |
2986 | aa0aa4fa | bellard | |
2987 | aa0aa4fa | bellard | /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
|
2988 | aa0aa4fa | bellard | |
2989 | aa0aa4fa | bellard | static int |
2990 | aa0aa4fa | bellard | compute_arch_mask (mach) |
2991 | aa0aa4fa | bellard | unsigned long mach; |
2992 | aa0aa4fa | bellard | { |
2993 | aa0aa4fa | bellard | switch (mach)
|
2994 | aa0aa4fa | bellard | { |
2995 | aa0aa4fa | bellard | case 0 : |
2996 | aa0aa4fa | bellard | case bfd_mach_sparc :
|
2997 | aa0aa4fa | bellard | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
|
2998 | aa0aa4fa | bellard | case bfd_mach_sparc_sparclet :
|
2999 | aa0aa4fa | bellard | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
|
3000 | aa0aa4fa | bellard | case bfd_mach_sparc_sparclite :
|
3001 | aa0aa4fa | bellard | case bfd_mach_sparc_sparclite_le :
|
3002 | aa0aa4fa | bellard | /* sparclites insns are recognized by default (because that's how
|
3003 | aa0aa4fa | bellard | they've always been treated, for better or worse). Kludge this by
|
3004 | aa0aa4fa | bellard | indicating generic v8 is also selected. */
|
3005 | aa0aa4fa | bellard | return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
|
3006 | aa0aa4fa | bellard | | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); |
3007 | aa0aa4fa | bellard | case bfd_mach_sparc_v8plus :
|
3008 | aa0aa4fa | bellard | case bfd_mach_sparc_v9 :
|
3009 | aa0aa4fa | bellard | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
|
3010 | aa0aa4fa | bellard | case bfd_mach_sparc_v8plusa :
|
3011 | aa0aa4fa | bellard | case bfd_mach_sparc_v9a :
|
3012 | aa0aa4fa | bellard | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
|
3013 | aa0aa4fa | bellard | case bfd_mach_sparc_v8plusb :
|
3014 | aa0aa4fa | bellard | case bfd_mach_sparc_v9b :
|
3015 | aa0aa4fa | bellard | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
|
3016 | aa0aa4fa | bellard | } |
3017 | aa0aa4fa | bellard | abort (); |
3018 | aa0aa4fa | bellard | } |
3019 | aa0aa4fa | bellard | |
3020 | aa0aa4fa | bellard | /* Compare opcodes A and B. */
|
3021 | aa0aa4fa | bellard | |
3022 | aa0aa4fa | bellard | static int |
3023 | aa0aa4fa | bellard | compare_opcodes (const void *a, const void *b) |
3024 | aa0aa4fa | bellard | { |
3025 | aa0aa4fa | bellard | struct sparc_opcode *op0 = * (struct sparc_opcode **) a; |
3026 | aa0aa4fa | bellard | struct sparc_opcode *op1 = * (struct sparc_opcode **) b; |
3027 | aa0aa4fa | bellard | unsigned long int match0 = op0->match, match1 = op1->match; |
3028 | aa0aa4fa | bellard | unsigned long int lose0 = op0->lose, lose1 = op1->lose; |
3029 | aa0aa4fa | bellard | register unsigned int i; |
3030 | aa0aa4fa | bellard | |
3031 | aa0aa4fa | bellard | /* If one (and only one) insn isn't supported by the current architecture,
|
3032 | aa0aa4fa | bellard | prefer the one that is. If neither are supported, but they're both for
|
3033 | aa0aa4fa | bellard | the same architecture, continue processing. Otherwise (both unsupported
|
3034 | aa0aa4fa | bellard | and for different architectures), prefer lower numbered arch's (fudged
|
3035 | aa0aa4fa | bellard | by comparing the bitmasks). */
|
3036 | aa0aa4fa | bellard | if (op0->architecture & current_arch_mask)
|
3037 | aa0aa4fa | bellard | { |
3038 | aa0aa4fa | bellard | if (! (op1->architecture & current_arch_mask))
|
3039 | aa0aa4fa | bellard | return -1; |
3040 | aa0aa4fa | bellard | } |
3041 | aa0aa4fa | bellard | else
|
3042 | aa0aa4fa | bellard | { |
3043 | aa0aa4fa | bellard | if (op1->architecture & current_arch_mask)
|
3044 | aa0aa4fa | bellard | return 1; |
3045 | aa0aa4fa | bellard | else if (op0->architecture != op1->architecture) |
3046 | aa0aa4fa | bellard | return op0->architecture - op1->architecture;
|
3047 | aa0aa4fa | bellard | } |
3048 | aa0aa4fa | bellard | |
3049 | aa0aa4fa | bellard | /* If a bit is set in both match and lose, there is something
|
3050 | aa0aa4fa | bellard | wrong with the opcode table. */
|
3051 | aa0aa4fa | bellard | if (match0 & lose0)
|
3052 | aa0aa4fa | bellard | { |
3053 | aa0aa4fa | bellard | fprintf |
3054 | aa0aa4fa | bellard | (stderr, |
3055 | aa0aa4fa | bellard | /* xgettext:c-format */
|
3056 | aa0aa4fa | bellard | _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
|
3057 | aa0aa4fa | bellard | op0->name, match0, lose0); |
3058 | aa0aa4fa | bellard | op0->lose &= ~op0->match; |
3059 | aa0aa4fa | bellard | lose0 = op0->lose; |
3060 | aa0aa4fa | bellard | } |
3061 | aa0aa4fa | bellard | |
3062 | aa0aa4fa | bellard | if (match1 & lose1)
|
3063 | aa0aa4fa | bellard | { |
3064 | aa0aa4fa | bellard | fprintf |
3065 | aa0aa4fa | bellard | (stderr, |
3066 | aa0aa4fa | bellard | /* xgettext:c-format */
|
3067 | aa0aa4fa | bellard | _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
|
3068 | aa0aa4fa | bellard | op1->name, match1, lose1); |
3069 | aa0aa4fa | bellard | op1->lose &= ~op1->match; |
3070 | aa0aa4fa | bellard | lose1 = op1->lose; |
3071 | aa0aa4fa | bellard | } |
3072 | aa0aa4fa | bellard | |
3073 | aa0aa4fa | bellard | /* Because the bits that are variable in one opcode are constant in
|
3074 | aa0aa4fa | bellard | another, it is important to order the opcodes in the right order. */
|
3075 | aa0aa4fa | bellard | for (i = 0; i < 32; ++i) |
3076 | aa0aa4fa | bellard | { |
3077 | aa0aa4fa | bellard | unsigned long int x = 1 << i; |
3078 | aa0aa4fa | bellard | int x0 = (match0 & x) != 0; |
3079 | aa0aa4fa | bellard | int x1 = (match1 & x) != 0; |
3080 | aa0aa4fa | bellard | |
3081 | aa0aa4fa | bellard | if (x0 != x1)
|
3082 | aa0aa4fa | bellard | return x1 - x0;
|
3083 | aa0aa4fa | bellard | } |
3084 | aa0aa4fa | bellard | |
3085 | aa0aa4fa | bellard | for (i = 0; i < 32; ++i) |
3086 | aa0aa4fa | bellard | { |
3087 | aa0aa4fa | bellard | unsigned long int x = 1 << i; |
3088 | aa0aa4fa | bellard | int x0 = (lose0 & x) != 0; |
3089 | aa0aa4fa | bellard | int x1 = (lose1 & x) != 0; |
3090 | aa0aa4fa | bellard | |
3091 | aa0aa4fa | bellard | if (x0 != x1)
|
3092 | aa0aa4fa | bellard | return x1 - x0;
|
3093 | aa0aa4fa | bellard | } |
3094 | aa0aa4fa | bellard | |
3095 | aa0aa4fa | bellard | /* They are functionally equal. So as long as the opcode table is
|
3096 | aa0aa4fa | bellard | valid, we can put whichever one first we want, on aesthetic grounds. */
|
3097 | aa0aa4fa | bellard | |
3098 | aa0aa4fa | bellard | /* Our first aesthetic ground is that aliases defer to real insns. */
|
3099 | aa0aa4fa | bellard | { |
3100 | aa0aa4fa | bellard | int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
|
3101 | aa0aa4fa | bellard | if (alias_diff != 0) |
3102 | aa0aa4fa | bellard | /* Put the one that isn't an alias first. */
|
3103 | aa0aa4fa | bellard | return alias_diff;
|
3104 | aa0aa4fa | bellard | } |
3105 | aa0aa4fa | bellard | |
3106 | aa0aa4fa | bellard | /* Except for aliases, two "identical" instructions had
|
3107 | aa0aa4fa | bellard | better have the same opcode. This is a sanity check on the table. */
|
3108 | aa0aa4fa | bellard | i = strcmp (op0->name, op1->name); |
3109 | aa0aa4fa | bellard | if (i)
|
3110 | aa0aa4fa | bellard | { |
3111 | aa0aa4fa | bellard | if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ |
3112 | aa0aa4fa | bellard | return i;
|
3113 | aa0aa4fa | bellard | else
|
3114 | aa0aa4fa | bellard | fprintf (stderr, |
3115 | aa0aa4fa | bellard | /* xgettext:c-format */
|
3116 | aa0aa4fa | bellard | _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
|
3117 | aa0aa4fa | bellard | op0->name, op1->name); |
3118 | aa0aa4fa | bellard | } |
3119 | aa0aa4fa | bellard | |
3120 | aa0aa4fa | bellard | /* Fewer arguments are preferred. */
|
3121 | aa0aa4fa | bellard | { |
3122 | aa0aa4fa | bellard | int length_diff = strlen (op0->args) - strlen (op1->args);
|
3123 | aa0aa4fa | bellard | if (length_diff != 0) |
3124 | aa0aa4fa | bellard | /* Put the one with fewer arguments first. */
|
3125 | aa0aa4fa | bellard | return length_diff;
|
3126 | aa0aa4fa | bellard | } |
3127 | aa0aa4fa | bellard | |
3128 | aa0aa4fa | bellard | /* Put 1+i before i+1. */
|
3129 | aa0aa4fa | bellard | { |
3130 | aa0aa4fa | bellard | char *p0 = (char *) strchr (op0->args, '+'); |
3131 | aa0aa4fa | bellard | char *p1 = (char *) strchr (op1->args, '+'); |
3132 | aa0aa4fa | bellard | |
3133 | aa0aa4fa | bellard | if (p0 && p1)
|
3134 | aa0aa4fa | bellard | { |
3135 | aa0aa4fa | bellard | /* There is a plus in both operands. Note that a plus
|
3136 | aa0aa4fa | bellard | sign cannot be the first character in args,
|
3137 | aa0aa4fa | bellard | so the following [-1]'s are valid. */
|
3138 | aa0aa4fa | bellard | if (p0[-1] == 'i' && p1[1] == 'i') |
3139 | aa0aa4fa | bellard | /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
|
3140 | aa0aa4fa | bellard | return 1; |
3141 | aa0aa4fa | bellard | if (p0[1] == 'i' && p1[-1] == 'i') |
3142 | aa0aa4fa | bellard | /* op0 is 1+i and op1 is i+1, so op0 goes first. */
|
3143 | aa0aa4fa | bellard | return -1; |
3144 | aa0aa4fa | bellard | } |
3145 | aa0aa4fa | bellard | } |
3146 | aa0aa4fa | bellard | |
3147 | aa0aa4fa | bellard | /* Put 1,i before i,1. */
|
3148 | aa0aa4fa | bellard | { |
3149 | aa0aa4fa | bellard | int i0 = strncmp (op0->args, "i,1", 3) == 0; |
3150 | aa0aa4fa | bellard | int i1 = strncmp (op1->args, "i,1", 3) == 0; |
3151 | aa0aa4fa | bellard | |
3152 | aa0aa4fa | bellard | if (i0 ^ i1)
|
3153 | aa0aa4fa | bellard | return i0 - i1;
|
3154 | aa0aa4fa | bellard | } |
3155 | aa0aa4fa | bellard | |
3156 | aa0aa4fa | bellard | /* They are, as far as we can tell, identical.
|
3157 | aa0aa4fa | bellard | Since qsort may have rearranged the table partially, there is
|
3158 | aa0aa4fa | bellard | no way to tell which one was first in the opcode table as
|
3159 | aa0aa4fa | bellard | written, so just say there are equal. */
|
3160 | aa0aa4fa | bellard | /* ??? This is no longer true now that we sort a vector of pointers,
|
3161 | aa0aa4fa | bellard | not the table itself. */
|
3162 | aa0aa4fa | bellard | return 0; |
3163 | aa0aa4fa | bellard | } |
3164 | aa0aa4fa | bellard | |
3165 | aa0aa4fa | bellard | /* Build a hash table from the opcode table.
|
3166 | aa0aa4fa | bellard | OPCODE_TABLE is a sorted list of pointers into the opcode table. */
|
3167 | aa0aa4fa | bellard | |
3168 | aa0aa4fa | bellard | static void |
3169 | aa0aa4fa | bellard | build_hash_table (opcode_table, hash_table, num_opcodes) |
3170 | aa0aa4fa | bellard | const struct sparc_opcode **opcode_table; |
3171 | aa0aa4fa | bellard | struct opcode_hash **hash_table;
|
3172 | aa0aa4fa | bellard | int num_opcodes;
|
3173 | aa0aa4fa | bellard | { |
3174 | aa0aa4fa | bellard | register int i; |
3175 | aa0aa4fa | bellard | int hash_count[HASH_SIZE];
|
3176 | aa0aa4fa | bellard | static struct opcode_hash *hash_buf = NULL; |
3177 | aa0aa4fa | bellard | |
3178 | aa0aa4fa | bellard | /* Start at the end of the table and work backwards so that each
|
3179 | aa0aa4fa | bellard | chain is sorted. */
|
3180 | aa0aa4fa | bellard | |
3181 | aa0aa4fa | bellard | memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); |
3182 | aa0aa4fa | bellard | memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); |
3183 | aa0aa4fa | bellard | if (hash_buf != NULL) |
3184 | aa0aa4fa | bellard | free (hash_buf); |
3185 | aa0aa4fa | bellard | hash_buf = (struct opcode_hash *) malloc (sizeof (struct opcode_hash) * num_opcodes); |
3186 | aa0aa4fa | bellard | for (i = num_opcodes - 1; i >= 0; --i) |
3187 | aa0aa4fa | bellard | { |
3188 | aa0aa4fa | bellard | register int hash = HASH_INSN (opcode_table[i]->match); |
3189 | aa0aa4fa | bellard | register struct opcode_hash *h = &hash_buf[i]; |
3190 | aa0aa4fa | bellard | h->next = hash_table[hash]; |
3191 | aa0aa4fa | bellard | h->opcode = opcode_table[i]; |
3192 | aa0aa4fa | bellard | hash_table[hash] = h; |
3193 | aa0aa4fa | bellard | ++hash_count[hash]; |
3194 | aa0aa4fa | bellard | } |
3195 | aa0aa4fa | bellard | |
3196 | aa0aa4fa | bellard | #if 0 /* for debugging */
|
3197 | aa0aa4fa | bellard | {
|
3198 | aa0aa4fa | bellard | int min_count = num_opcodes, max_count = 0;
|
3199 | aa0aa4fa | bellard | int total;
|
3200 | aa0aa4fa | bellard | |
3201 | aa0aa4fa | bellard | for (i = 0; i < HASH_SIZE; ++i)
|
3202 | aa0aa4fa | bellard | {
|
3203 | aa0aa4fa | bellard | if (hash_count[i] < min_count)
|
3204 | aa0aa4fa | bellard | min_count = hash_count[i];
|
3205 | aa0aa4fa | bellard | if (hash_count[i] > max_count)
|
3206 | aa0aa4fa | bellard | max_count = hash_count[i];
|
3207 | aa0aa4fa | bellard | total += hash_count[i];
|
3208 | aa0aa4fa | bellard | }
|
3209 | aa0aa4fa | bellard | |
3210 | aa0aa4fa | bellard | printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
|
3211 | aa0aa4fa | bellard | min_count, max_count, (double) total / HASH_SIZE);
|
3212 | aa0aa4fa | bellard | }
|
3213 | aa0aa4fa | bellard | #endif
|
3214 | aa0aa4fa | bellard | } |