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1	2c0262af	bellard	/*
2	2c0262af	bellard	* i386 translation
3	2c0262af	bellard	*
4	2c0262af	bellard	* Copyright (c) 2003 Fabrice Bellard
5	2c0262af	bellard	*
6	2c0262af	bellard	* This library is free software; you can redistribute it and/or
7	2c0262af	bellard	* modify it under the terms of the GNU Lesser General Public
8	2c0262af	bellard	* License as published by the Free Software Foundation; either
9	2c0262af	bellard	* version 2 of the License, or (at your option) any later version.
10	2c0262af	bellard	*
11	2c0262af	bellard	* This library is distributed in the hope that it will be useful,
12	2c0262af	bellard	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	2c0262af	bellard	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	2c0262af	bellard	* Lesser General Public License for more details.
15	2c0262af	bellard	*
16	2c0262af	bellard	* You should have received a copy of the GNU Lesser General Public
17	2c0262af	bellard	* License along with this library; if not, write to the Free Software
18	2c0262af	bellard	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	2c0262af	bellard	*/
20	2c0262af	bellard	#include <stdarg.h>
21	2c0262af	bellard	#include <stdlib.h>
22	2c0262af	bellard	#include <stdio.h>
23	2c0262af	bellard	#include <string.h>
24	2c0262af	bellard	#include <inttypes.h>
25	2c0262af	bellard	#include <signal.h>
26	2c0262af	bellard	#include <assert.h>
27	2c0262af	bellard
28	2c0262af	bellard	#include "cpu.h"
29	2c0262af	bellard	#include "exec-all.h"
30	2c0262af	bellard	#include "disas.h"
31	2c0262af	bellard
32	2c0262af	bellard	/* XXX: move that elsewhere */
33	2c0262af	bellard	static uint16_t *gen_opc_ptr;
34	2c0262af	bellard	static uint32_t *gen_opparam_ptr;
35	2c0262af	bellard
36	2c0262af	bellard	#define PREFIX_REPZ 0x01
37	2c0262af	bellard	#define PREFIX_REPNZ 0x02
38	2c0262af	bellard	#define PREFIX_LOCK 0x04
39	2c0262af	bellard	#define PREFIX_DATA 0x08
40	2c0262af	bellard	#define PREFIX_ADR 0x10
41	2c0262af	bellard
42	14ce26e7	bellard	#ifdef TARGET_X86_64
43	14ce26e7	bellard	#define X86_64_ONLY(x) x
44	14ce26e7	bellard	#define X86_64_DEF(x...) x
45	14ce26e7	bellard	#define CODE64(s) ((s)->code64)
46	14ce26e7	bellard	#define REX_X(s) ((s)->rex_x)
47	14ce26e7	bellard	#define REX_B(s) ((s)->rex_b)
48	14ce26e7	bellard	/* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
49	14ce26e7	bellard	#if 1
50	14ce26e7	bellard	#define BUGGY_64(x) NULL
51	14ce26e7	bellard	#endif
52	14ce26e7	bellard	#else
53	14ce26e7	bellard	#define X86_64_ONLY(x) NULL
54	14ce26e7	bellard	#define X86_64_DEF(x...)
55	14ce26e7	bellard	#define CODE64(s) 0
56	14ce26e7	bellard	#define REX_X(s) 0
57	14ce26e7	bellard	#define REX_B(s) 0
58	14ce26e7	bellard	#endif
59	14ce26e7	bellard
60	14ce26e7	bellard	#ifdef TARGET_X86_64
61	14ce26e7	bellard	static int x86_64_hregs;
62	14ce26e7	bellard	#endif
63	14ce26e7	bellard
64	ae063a68	bellard	#ifdef USE_DIRECT_JUMP
65	ae063a68	bellard	#define TBPARAM(x)
66	ae063a68	bellard	#else
67	ae063a68	bellard	#define TBPARAM(x) (long)(x)
68	ae063a68	bellard	#endif
69	ae063a68	bellard
70	2c0262af	bellard	typedef struct DisasContext {
71	2c0262af	bellard	/* current insn context */
72	2c0262af	bellard	int override; /* -1 if no override */
73	2c0262af	bellard	int prefix;
74	2c0262af	bellard	int aflag, dflag;
75	14ce26e7	bellard	target_ulong pc; /* pc = eip + cs_base */
76	2c0262af	bellard	int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
77	2c0262af	bellard	static state change (stop translation) */
78	2c0262af	bellard	/* current block context */
79	14ce26e7	bellard	target_ulong cs_base; /* base of CS segment */
80	2c0262af	bellard	int pe; /* protected mode */
81	2c0262af	bellard	int code32; /* 32 bit code segment */
82	14ce26e7	bellard	#ifdef TARGET_X86_64
83	14ce26e7	bellard	int lma; /* long mode active */
84	14ce26e7	bellard	int code64; /* 64 bit code segment */
85	14ce26e7	bellard	int rex_x, rex_b;
86	14ce26e7	bellard	#endif
87	2c0262af	bellard	int ss32; /* 32 bit stack segment */
88	2c0262af	bellard	int cc_op; /* current CC operation */
89	2c0262af	bellard	int addseg; /* non zero if either DS/ES/SS have a non zero base */
90	2c0262af	bellard	int f_st; /* currently unused */
91	2c0262af	bellard	int vm86; /* vm86 mode */
92	2c0262af	bellard	int cpl;
93	2c0262af	bellard	int iopl;
94	2c0262af	bellard	int tf; /* TF cpu flag */
95	34865134	bellard	int singlestep_enabled; /* "hardware" single step enabled */
96	2c0262af	bellard	int jmp_opt; /* use direct block chaining for direct jumps */
97	2c0262af	bellard	int mem_index; /* select memory access functions */
98	7eee2a50	bellard	int flags; /* all execution flags */
99	2c0262af	bellard	struct TranslationBlock *tb;
100	2c0262af	bellard	int popl_esp_hack; /* for correct popl with esp base handling */
101	14ce26e7	bellard	int rip_offset; /* only used in x86_64, but left for simplicity */
102	14ce26e7	bellard	int cpuid_features;
103	2c0262af	bellard	} DisasContext;
104	2c0262af	bellard
105	2c0262af	bellard	static void gen_eob(DisasContext *s);
106	14ce26e7	bellard	static void gen_jmp(DisasContext *s, target_ulong eip);
107	14ce26e7	bellard	static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
108	2c0262af	bellard
109	2c0262af	bellard	/* i386 arith/logic operations */
110	2c0262af	bellard	enum {
111	2c0262af	bellard	OP_ADDL,
112	2c0262af	bellard	OP_ORL,
113	2c0262af	bellard	OP_ADCL,
114	2c0262af	bellard	OP_SBBL,
115	2c0262af	bellard	OP_ANDL,
116	2c0262af	bellard	OP_SUBL,
117	2c0262af	bellard	OP_XORL,
118	2c0262af	bellard	OP_CMPL,
119	2c0262af	bellard	};
120	2c0262af	bellard
121	2c0262af	bellard	/* i386 shift ops */
122	2c0262af	bellard	enum {
123	2c0262af	bellard	OP_ROL,
124	2c0262af	bellard	OP_ROR,
125	2c0262af	bellard	OP_RCL,
126	2c0262af	bellard	OP_RCR,
127	2c0262af	bellard	OP_SHL,
128	2c0262af	bellard	OP_SHR,
129	2c0262af	bellard	OP_SHL1, /* undocumented */
130	2c0262af	bellard	OP_SAR = 7,
131	2c0262af	bellard	};
132	2c0262af	bellard
133	2c0262af	bellard	enum {
134	2c0262af	bellard	#define DEF(s, n, copy_size) INDEX_op_ ## s,
135	2c0262af	bellard	#include "opc.h"
136	2c0262af	bellard	#undef DEF
137	2c0262af	bellard	NB_OPS,
138	2c0262af	bellard	};
139	2c0262af	bellard
140	2c0262af	bellard	#include "gen-op.h"
141	2c0262af	bellard
142	2c0262af	bellard	/* operand size */
143	2c0262af	bellard	enum {
144	2c0262af	bellard	OT_BYTE = 0,
145	2c0262af	bellard	OT_WORD,
146	2c0262af	bellard	OT_LONG,
147	2c0262af	bellard	OT_QUAD,
148	2c0262af	bellard	};
149	2c0262af	bellard
150	2c0262af	bellard	enum {
151	2c0262af	bellard	/* I386 int registers */
152	2c0262af	bellard	OR_EAX, /* MUST be even numbered */
153	2c0262af	bellard	OR_ECX,
154	2c0262af	bellard	OR_EDX,
155	2c0262af	bellard	OR_EBX,
156	2c0262af	bellard	OR_ESP,
157	2c0262af	bellard	OR_EBP,
158	2c0262af	bellard	OR_ESI,
159	2c0262af	bellard	OR_EDI,
160	14ce26e7	bellard
161	14ce26e7	bellard	OR_TMP0 = 16, /* temporary operand register */
162	2c0262af	bellard	OR_TMP1,
163	2c0262af	bellard	OR_A0, /* temporary register used when doing address evaluation */
164	2c0262af	bellard	};
165	2c0262af	bellard
166	14ce26e7	bellard	#ifdef TARGET_X86_64
167	14ce26e7	bellard
168	14ce26e7	bellard	#define NB_OP_SIZES 4
169	14ce26e7	bellard
170	14ce26e7	bellard	#define DEF_REGS(prefix, suffix) \
171	14ce26e7	bellard	prefix ## EAX ## suffix,\
172	14ce26e7	bellard	prefix ## ECX ## suffix,\
173	14ce26e7	bellard	prefix ## EDX ## suffix,\
174	14ce26e7	bellard	prefix ## EBX ## suffix,\
175	14ce26e7	bellard	prefix ## ESP ## suffix,\
176	14ce26e7	bellard	prefix ## EBP ## suffix,\
177	14ce26e7	bellard	prefix ## ESI ## suffix,\
178	14ce26e7	bellard	prefix ## EDI ## suffix,\
179	14ce26e7	bellard	prefix ## R8 ## suffix,\
180	14ce26e7	bellard	prefix ## R9 ## suffix,\
181	14ce26e7	bellard	prefix ## R10 ## suffix,\
182	14ce26e7	bellard	prefix ## R11 ## suffix,\
183	14ce26e7	bellard	prefix ## R12 ## suffix,\
184	14ce26e7	bellard	prefix ## R13 ## suffix,\
185	14ce26e7	bellard	prefix ## R14 ## suffix,\
186	14ce26e7	bellard	prefix ## R15 ## suffix,
187	14ce26e7	bellard
188	14ce26e7	bellard	#define DEF_BREGS(prefixb, prefixh, suffix) \
189	14ce26e7	bellard	\
190	14ce26e7	bellard	static void prefixb ## ESP ## suffix ## _wrapper(void) \
191	14ce26e7	bellard	{ \
192	14ce26e7	bellard	if (x86_64_hregs) \
193	14ce26e7	bellard	prefixb ## ESP ## suffix (); \
194	14ce26e7	bellard	else \
195	14ce26e7	bellard	prefixh ## EAX ## suffix (); \
196	14ce26e7	bellard	} \
197	14ce26e7	bellard	\
198	14ce26e7	bellard	static void prefixb ## EBP ## suffix ## _wrapper(void) \
199	14ce26e7	bellard	{ \
200	14ce26e7	bellard	if (x86_64_hregs) \
201	14ce26e7	bellard	prefixb ## EBP ## suffix (); \
202	14ce26e7	bellard	else \
203	14ce26e7	bellard	prefixh ## ECX ## suffix (); \
204	14ce26e7	bellard	} \
205	14ce26e7	bellard	\
206	14ce26e7	bellard	static void prefixb ## ESI ## suffix ## _wrapper(void) \
207	14ce26e7	bellard	{ \
208	14ce26e7	bellard	if (x86_64_hregs) \
209	14ce26e7	bellard	prefixb ## ESI ## suffix (); \
210	14ce26e7	bellard	else \
211	14ce26e7	bellard	prefixh ## EDX ## suffix (); \
212	14ce26e7	bellard	} \
213	14ce26e7	bellard	\
214	14ce26e7	bellard	static void prefixb ## EDI ## suffix ## _wrapper(void) \
215	14ce26e7	bellard	{ \
216	14ce26e7	bellard	if (x86_64_hregs) \
217	14ce26e7	bellard	prefixb ## EDI ## suffix (); \
218	14ce26e7	bellard	else \
219	14ce26e7	bellard	prefixh ## EBX ## suffix (); \
220	14ce26e7	bellard	}
221	14ce26e7	bellard
222	14ce26e7	bellard	DEF_BREGS(gen_op_movb_, gen_op_movh_, _T0)
223	14ce26e7	bellard	DEF_BREGS(gen_op_movb_, gen_op_movh_, _T1)
224	14ce26e7	bellard	DEF_BREGS(gen_op_movl_T0_, gen_op_movh_T0_, )
225	14ce26e7	bellard	DEF_BREGS(gen_op_movl_T1_, gen_op_movh_T1_, )
226	14ce26e7	bellard
227	14ce26e7	bellard	#else /* !TARGET_X86_64 */
228	14ce26e7	bellard
229	14ce26e7	bellard	#define NB_OP_SIZES 3
230	14ce26e7	bellard
231	14ce26e7	bellard	#define DEF_REGS(prefix, suffix) \
232	14ce26e7	bellard	prefix ## EAX ## suffix,\
233	14ce26e7	bellard	prefix ## ECX ## suffix,\
234	14ce26e7	bellard	prefix ## EDX ## suffix,\
235	14ce26e7	bellard	prefix ## EBX ## suffix,\
236	14ce26e7	bellard	prefix ## ESP ## suffix,\
237	14ce26e7	bellard	prefix ## EBP ## suffix,\
238	14ce26e7	bellard	prefix ## ESI ## suffix,\
239	14ce26e7	bellard	prefix ## EDI ## suffix,
240	14ce26e7	bellard
241	14ce26e7	bellard	#endif /* !TARGET_X86_64 */
242	14ce26e7	bellard
243	14ce26e7	bellard	static GenOpFunc *gen_op_mov_reg_T0[NB_OP_SIZES][CPU_NB_REGS] = {
244	2c0262af	bellard	[OT_BYTE] = {
245	2c0262af	bellard	gen_op_movb_EAX_T0,
246	2c0262af	bellard	gen_op_movb_ECX_T0,
247	2c0262af	bellard	gen_op_movb_EDX_T0,
248	2c0262af	bellard	gen_op_movb_EBX_T0,
249	14ce26e7	bellard	#ifdef TARGET_X86_64
250	14ce26e7	bellard	gen_op_movb_ESP_T0_wrapper,
251	14ce26e7	bellard	gen_op_movb_EBP_T0_wrapper,
252	14ce26e7	bellard	gen_op_movb_ESI_T0_wrapper,
253	14ce26e7	bellard	gen_op_movb_EDI_T0_wrapper,
254	14ce26e7	bellard	gen_op_movb_R8_T0,
255	14ce26e7	bellard	gen_op_movb_R9_T0,
256	14ce26e7	bellard	gen_op_movb_R10_T0,
257	14ce26e7	bellard	gen_op_movb_R11_T0,
258	14ce26e7	bellard	gen_op_movb_R12_T0,
259	14ce26e7	bellard	gen_op_movb_R13_T0,
260	14ce26e7	bellard	gen_op_movb_R14_T0,
261	14ce26e7	bellard	gen_op_movb_R15_T0,
262	14ce26e7	bellard	#else
263	2c0262af	bellard	gen_op_movh_EAX_T0,
264	2c0262af	bellard	gen_op_movh_ECX_T0,
265	2c0262af	bellard	gen_op_movh_EDX_T0,
266	2c0262af	bellard	gen_op_movh_EBX_T0,
267	14ce26e7	bellard	#endif
268	2c0262af	bellard	},
269	2c0262af	bellard	[OT_WORD] = {
270	14ce26e7	bellard	DEF_REGS(gen_op_movw_, _T0)
271	2c0262af	bellard	},
272	2c0262af	bellard	[OT_LONG] = {
273	14ce26e7	bellard	DEF_REGS(gen_op_movl_, _T0)
274	2c0262af	bellard	},
275	14ce26e7	bellard	#ifdef TARGET_X86_64
276	14ce26e7	bellard	[OT_QUAD] = {
277	14ce26e7	bellard	DEF_REGS(gen_op_movq_, _T0)
278	14ce26e7	bellard	},
279	14ce26e7	bellard	#endif
280	2c0262af	bellard	};
281	2c0262af	bellard
282	14ce26e7	bellard	static GenOpFunc *gen_op_mov_reg_T1[NB_OP_SIZES][CPU_NB_REGS] = {
283	2c0262af	bellard	[OT_BYTE] = {
284	2c0262af	bellard	gen_op_movb_EAX_T1,
285	2c0262af	bellard	gen_op_movb_ECX_T1,
286	2c0262af	bellard	gen_op_movb_EDX_T1,
287	2c0262af	bellard	gen_op_movb_EBX_T1,
288	14ce26e7	bellard	#ifdef TARGET_X86_64
289	14ce26e7	bellard	gen_op_movb_ESP_T1_wrapper,
290	14ce26e7	bellard	gen_op_movb_EBP_T1_wrapper,
291	14ce26e7	bellard	gen_op_movb_ESI_T1_wrapper,
292	14ce26e7	bellard	gen_op_movb_EDI_T1_wrapper,
293	14ce26e7	bellard	gen_op_movb_R8_T1,
294	14ce26e7	bellard	gen_op_movb_R9_T1,
295	14ce26e7	bellard	gen_op_movb_R10_T1,
296	14ce26e7	bellard	gen_op_movb_R11_T1,
297	14ce26e7	bellard	gen_op_movb_R12_T1,
298	14ce26e7	bellard	gen_op_movb_R13_T1,
299	14ce26e7	bellard	gen_op_movb_R14_T1,
300	14ce26e7	bellard	gen_op_movb_R15_T1,
301	14ce26e7	bellard	#else
302	2c0262af	bellard	gen_op_movh_EAX_T1,
303	2c0262af	bellard	gen_op_movh_ECX_T1,
304	2c0262af	bellard	gen_op_movh_EDX_T1,
305	2c0262af	bellard	gen_op_movh_EBX_T1,
306	14ce26e7	bellard	#endif
307	2c0262af	bellard	},
308	2c0262af	bellard	[OT_WORD] = {
309	14ce26e7	bellard	DEF_REGS(gen_op_movw_, _T1)
310	2c0262af	bellard	},
311	2c0262af	bellard	[OT_LONG] = {
312	14ce26e7	bellard	DEF_REGS(gen_op_movl_, _T1)
313	14ce26e7	bellard	},
314	14ce26e7	bellard	#ifdef TARGET_X86_64
315	14ce26e7	bellard	[OT_QUAD] = {
316	14ce26e7	bellard	DEF_REGS(gen_op_movq_, _T1)
317	2c0262af	bellard	},
318	14ce26e7	bellard	#endif
319	2c0262af	bellard	};
320	2c0262af	bellard
321	14ce26e7	bellard	static GenOpFunc *gen_op_mov_reg_A0[NB_OP_SIZES - 1][CPU_NB_REGS] = {
322	2c0262af	bellard	[0] = {
323	14ce26e7	bellard	DEF_REGS(gen_op_movw_, _A0)
324	2c0262af	bellard	},
325	2c0262af	bellard	[1] = {
326	14ce26e7	bellard	DEF_REGS(gen_op_movl_, _A0)
327	14ce26e7	bellard	},
328	14ce26e7	bellard	#ifdef TARGET_X86_64
329	14ce26e7	bellard	[2] = {
330	14ce26e7	bellard	DEF_REGS(gen_op_movq_, _A0)
331	2c0262af	bellard	},
332	14ce26e7	bellard	#endif
333	2c0262af	bellard	};
334	2c0262af	bellard
335	14ce26e7	bellard	static GenOpFunc *gen_op_mov_TN_reg[NB_OP_SIZES][2][CPU_NB_REGS] =
336	2c0262af	bellard	{
337	2c0262af	bellard	[OT_BYTE] = {
338	2c0262af	bellard	{
339	2c0262af	bellard	gen_op_movl_T0_EAX,
340	2c0262af	bellard	gen_op_movl_T0_ECX,
341	2c0262af	bellard	gen_op_movl_T0_EDX,
342	2c0262af	bellard	gen_op_movl_T0_EBX,
343	14ce26e7	bellard	#ifdef TARGET_X86_64
344	14ce26e7	bellard	gen_op_movl_T0_ESP_wrapper,
345	14ce26e7	bellard	gen_op_movl_T0_EBP_wrapper,
346	14ce26e7	bellard	gen_op_movl_T0_ESI_wrapper,
347	14ce26e7	bellard	gen_op_movl_T0_EDI_wrapper,
348	14ce26e7	bellard	gen_op_movl_T0_R8,
349	14ce26e7	bellard	gen_op_movl_T0_R9,
350	14ce26e7	bellard	gen_op_movl_T0_R10,
351	14ce26e7	bellard	gen_op_movl_T0_R11,
352	14ce26e7	bellard	gen_op_movl_T0_R12,
353	14ce26e7	bellard	gen_op_movl_T0_R13,
354	14ce26e7	bellard	gen_op_movl_T0_R14,
355	14ce26e7	bellard	gen_op_movl_T0_R15,
356	14ce26e7	bellard	#else
357	2c0262af	bellard	gen_op_movh_T0_EAX,
358	2c0262af	bellard	gen_op_movh_T0_ECX,
359	2c0262af	bellard	gen_op_movh_T0_EDX,
360	2c0262af	bellard	gen_op_movh_T0_EBX,
361	14ce26e7	bellard	#endif
362	2c0262af	bellard	},
363	2c0262af	bellard	{
364	2c0262af	bellard	gen_op_movl_T1_EAX,
365	2c0262af	bellard	gen_op_movl_T1_ECX,
366	2c0262af	bellard	gen_op_movl_T1_EDX,
367	2c0262af	bellard	gen_op_movl_T1_EBX,
368	14ce26e7	bellard	#ifdef TARGET_X86_64
369	14ce26e7	bellard	gen_op_movl_T1_ESP_wrapper,
370	14ce26e7	bellard	gen_op_movl_T1_EBP_wrapper,
371	14ce26e7	bellard	gen_op_movl_T1_ESI_wrapper,
372	14ce26e7	bellard	gen_op_movl_T1_EDI_wrapper,
373	14ce26e7	bellard	gen_op_movl_T1_R8,
374	14ce26e7	bellard	gen_op_movl_T1_R9,
375	14ce26e7	bellard	gen_op_movl_T1_R10,
376	14ce26e7	bellard	gen_op_movl_T1_R11,
377	14ce26e7	bellard	gen_op_movl_T1_R12,
378	14ce26e7	bellard	gen_op_movl_T1_R13,
379	14ce26e7	bellard	gen_op_movl_T1_R14,
380	14ce26e7	bellard	gen_op_movl_T1_R15,
381	14ce26e7	bellard	#else
382	2c0262af	bellard	gen_op_movh_T1_EAX,
383	2c0262af	bellard	gen_op_movh_T1_ECX,
384	2c0262af	bellard	gen_op_movh_T1_EDX,
385	2c0262af	bellard	gen_op_movh_T1_EBX,
386	14ce26e7	bellard	#endif
387	2c0262af	bellard	},
388	2c0262af	bellard	},
389	2c0262af	bellard	[OT_WORD] = {
390	2c0262af	bellard	{
391	14ce26e7	bellard	DEF_REGS(gen_op_movl_T0_, )
392	2c0262af	bellard	},
393	2c0262af	bellard	{
394	14ce26e7	bellard	DEF_REGS(gen_op_movl_T1_, )
395	2c0262af	bellard	},
396	2c0262af	bellard	},
397	2c0262af	bellard	[OT_LONG] = {
398	2c0262af	bellard	{
399	14ce26e7	bellard	DEF_REGS(gen_op_movl_T0_, )
400	2c0262af	bellard	},
401	2c0262af	bellard	{
402	14ce26e7	bellard	DEF_REGS(gen_op_movl_T1_, )
403	2c0262af	bellard	},
404	2c0262af	bellard	},
405	14ce26e7	bellard	#ifdef TARGET_X86_64
406	14ce26e7	bellard	[OT_QUAD] = {
407	14ce26e7	bellard	{
408	14ce26e7	bellard	DEF_REGS(gen_op_movl_T0_, )
409	14ce26e7	bellard	},
410	14ce26e7	bellard	{
411	14ce26e7	bellard	DEF_REGS(gen_op_movl_T1_, )
412	14ce26e7	bellard	},
413	14ce26e7	bellard	},
414	14ce26e7	bellard	#endif
415	2c0262af	bellard	};
416	2c0262af	bellard
417	14ce26e7	bellard	static GenOpFunc *gen_op_movl_A0_reg[CPU_NB_REGS] = {
418	14ce26e7	bellard	DEF_REGS(gen_op_movl_A0_, )
419	2c0262af	bellard	};
420	2c0262af	bellard
421	14ce26e7	bellard	static GenOpFunc *gen_op_addl_A0_reg_sN[4][CPU_NB_REGS] = {
422	2c0262af	bellard	[0] = {
423	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, )
424	2c0262af	bellard	},
425	2c0262af	bellard	[1] = {
426	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, _s1)
427	2c0262af	bellard	},
428	2c0262af	bellard	[2] = {
429	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, _s2)
430	2c0262af	bellard	},
431	2c0262af	bellard	[3] = {
432	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, _s3)
433	2c0262af	bellard	},
434	2c0262af	bellard	};
435	2c0262af	bellard
436	14ce26e7	bellard	#ifdef TARGET_X86_64
437	14ce26e7	bellard	static GenOpFunc *gen_op_movq_A0_reg[CPU_NB_REGS] = {
438	14ce26e7	bellard	DEF_REGS(gen_op_movq_A0_, )
439	14ce26e7	bellard	};
440	14ce26e7	bellard
441	14ce26e7	bellard	static GenOpFunc *gen_op_addq_A0_reg_sN[4][CPU_NB_REGS] = {
442	2c0262af	bellard	[0] = {
443	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, )
444	2c0262af	bellard	},
445	2c0262af	bellard	[1] = {
446	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, _s1)
447	14ce26e7	bellard	},
448	14ce26e7	bellard	[2] = {
449	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, _s2)
450	14ce26e7	bellard	},
451	14ce26e7	bellard	[3] = {
452	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, _s3)
453	2c0262af	bellard	},
454	2c0262af	bellard	};
455	14ce26e7	bellard	#endif
456	14ce26e7	bellard
457	14ce26e7	bellard	static GenOpFunc *gen_op_cmov_reg_T1_T0[NB_OP_SIZES - 1][CPU_NB_REGS] = {
458	14ce26e7	bellard	[0] = {
459	14ce26e7	bellard	DEF_REGS(gen_op_cmovw_, _T1_T0)
460	14ce26e7	bellard	},
461	14ce26e7	bellard	[1] = {
462	14ce26e7	bellard	DEF_REGS(gen_op_cmovl_, _T1_T0)
463	14ce26e7	bellard	},
464	14ce26e7	bellard	#ifdef TARGET_X86_64
465	14ce26e7	bellard	[2] = {
466	14ce26e7	bellard	DEF_REGS(gen_op_cmovq_, _T1_T0)
467	14ce26e7	bellard	},
468	14ce26e7	bellard	#endif
469	14ce26e7	bellard	};
470	2c0262af	bellard
471	2c0262af	bellard	static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
472	2c0262af	bellard	NULL,
473	2c0262af	bellard	gen_op_orl_T0_T1,
474	2c0262af	bellard	NULL,
475	2c0262af	bellard	NULL,
476	2c0262af	bellard	gen_op_andl_T0_T1,
477	2c0262af	bellard	NULL,
478	2c0262af	bellard	gen_op_xorl_T0_T1,
479	2c0262af	bellard	NULL,
480	2c0262af	bellard	};
481	2c0262af	bellard
482	4f31916f	bellard	#define DEF_ARITHC(SUFFIX)\
483	4f31916f	bellard	{\
484	4f31916f	bellard	gen_op_adcb ## SUFFIX ## _T0_T1_cc,\
485	4f31916f	bellard	gen_op_sbbb ## SUFFIX ## _T0_T1_cc,\
486	4f31916f	bellard	},\
487	4f31916f	bellard	{\
488	4f31916f	bellard	gen_op_adcw ## SUFFIX ## _T0_T1_cc,\
489	4f31916f	bellard	gen_op_sbbw ## SUFFIX ## _T0_T1_cc,\
490	4f31916f	bellard	},\
491	4f31916f	bellard	{\
492	4f31916f	bellard	gen_op_adcl ## SUFFIX ## _T0_T1_cc,\
493	4f31916f	bellard	gen_op_sbbl ## SUFFIX ## _T0_T1_cc,\
494	14ce26e7	bellard	},\
495	14ce26e7	bellard	{\
496	14ce26e7	bellard	X86_64_ONLY(gen_op_adcq ## SUFFIX ## _T0_T1_cc),\
497	14ce26e7	bellard	X86_64_ONLY(gen_op_sbbq ## SUFFIX ## _T0_T1_cc),\
498	2c0262af	bellard	},
499	4f31916f	bellard
500	14ce26e7	bellard	static GenOpFunc *gen_op_arithc_T0_T1_cc[4][2] = {
501	4bb2fcc7	bellard	DEF_ARITHC( )
502	2c0262af	bellard	};
503	2c0262af	bellard
504	14ce26e7	bellard	static GenOpFunc gen_op_arithc_mem_T0_T1_cc[3 4][2] = {
505	4f31916f	bellard	DEF_ARITHC(_raw)
506	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
507	4f31916f	bellard	DEF_ARITHC(_kernel)
508	4f31916f	bellard	DEF_ARITHC(_user)
509	4f31916f	bellard	#endif
510	2c0262af	bellard	};
511	2c0262af	bellard
512	2c0262af	bellard	static const int cc_op_arithb[8] = {
513	2c0262af	bellard	CC_OP_ADDB,
514	2c0262af	bellard	CC_OP_LOGICB,
515	2c0262af	bellard	CC_OP_ADDB,
516	2c0262af	bellard	CC_OP_SUBB,
517	2c0262af	bellard	CC_OP_LOGICB,
518	2c0262af	bellard	CC_OP_SUBB,
519	2c0262af	bellard	CC_OP_LOGICB,
520	2c0262af	bellard	CC_OP_SUBB,
521	2c0262af	bellard	};
522	2c0262af	bellard
523	4f31916f	bellard	#define DEF_CMPXCHG(SUFFIX)\
524	4f31916f	bellard	gen_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc,\
525	4f31916f	bellard	gen_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc,\
526	14ce26e7	bellard	gen_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc,\
527	14ce26e7	bellard	X86_64_ONLY(gen_op_cmpxchgq ## SUFFIX ## _T0_T1_EAX_cc),
528	4f31916f	bellard
529	14ce26e7	bellard	static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[4] = {
530	4bb2fcc7	bellard	DEF_CMPXCHG( )
531	2c0262af	bellard	};
532	2c0262af	bellard
533	14ce26e7	bellard	static GenOpFunc gen_op_cmpxchg_mem_T0_T1_EAX_cc[3 4] = {
534	4f31916f	bellard	DEF_CMPXCHG(_raw)
535	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
536	4f31916f	bellard	DEF_CMPXCHG(_kernel)
537	4f31916f	bellard	DEF_CMPXCHG(_user)
538	4f31916f	bellard	#endif
539	2c0262af	bellard	};
540	2c0262af	bellard
541	4f31916f	bellard	#define DEF_SHIFT(SUFFIX)\
542	4f31916f	bellard	{\
543	4f31916f	bellard	gen_op_rolb ## SUFFIX ## _T0_T1_cc,\
544	4f31916f	bellard	gen_op_rorb ## SUFFIX ## _T0_T1_cc,\
545	4f31916f	bellard	gen_op_rclb ## SUFFIX ## _T0_T1_cc,\
546	4f31916f	bellard	gen_op_rcrb ## SUFFIX ## _T0_T1_cc,\
547	4f31916f	bellard	gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
548	4f31916f	bellard	gen_op_shrb ## SUFFIX ## _T0_T1_cc,\
549	4f31916f	bellard	gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
550	4f31916f	bellard	gen_op_sarb ## SUFFIX ## _T0_T1_cc,\
551	4f31916f	bellard	},\
552	4f31916f	bellard	{\
553	4f31916f	bellard	gen_op_rolw ## SUFFIX ## _T0_T1_cc,\
554	4f31916f	bellard	gen_op_rorw ## SUFFIX ## _T0_T1_cc,\
555	4f31916f	bellard	gen_op_rclw ## SUFFIX ## _T0_T1_cc,\
556	4f31916f	bellard	gen_op_rcrw ## SUFFIX ## _T0_T1_cc,\
557	4f31916f	bellard	gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
558	4f31916f	bellard	gen_op_shrw ## SUFFIX ## _T0_T1_cc,\
559	4f31916f	bellard	gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
560	4f31916f	bellard	gen_op_sarw ## SUFFIX ## _T0_T1_cc,\
561	4f31916f	bellard	},\
562	4f31916f	bellard	{\
563	4f31916f	bellard	gen_op_roll ## SUFFIX ## _T0_T1_cc,\
564	4f31916f	bellard	gen_op_rorl ## SUFFIX ## _T0_T1_cc,\
565	4f31916f	bellard	gen_op_rcll ## SUFFIX ## _T0_T1_cc,\
566	4f31916f	bellard	gen_op_rcrl ## SUFFIX ## _T0_T1_cc,\
567	4f31916f	bellard	gen_op_shll ## SUFFIX ## _T0_T1_cc,\
568	4f31916f	bellard	gen_op_shrl ## SUFFIX ## _T0_T1_cc,\
569	4f31916f	bellard	gen_op_shll ## SUFFIX ## _T0_T1_cc,\
570	4f31916f	bellard	gen_op_sarl ## SUFFIX ## _T0_T1_cc,\
571	14ce26e7	bellard	},\
572	14ce26e7	bellard	{\
573	14ce26e7	bellard	X86_64_ONLY(gen_op_rolq ## SUFFIX ## _T0_T1_cc),\
574	14ce26e7	bellard	X86_64_ONLY(gen_op_rorq ## SUFFIX ## _T0_T1_cc),\
575	14ce26e7	bellard	X86_64_ONLY(gen_op_rclq ## SUFFIX ## _T0_T1_cc),\
576	14ce26e7	bellard	X86_64_ONLY(gen_op_rcrq ## SUFFIX ## _T0_T1_cc),\
577	14ce26e7	bellard	X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\
578	14ce26e7	bellard	X86_64_ONLY(gen_op_shrq ## SUFFIX ## _T0_T1_cc),\
579	14ce26e7	bellard	X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\
580	14ce26e7	bellard	X86_64_ONLY(gen_op_sarq ## SUFFIX ## _T0_T1_cc),\
581	2c0262af	bellard	},
582	4f31916f	bellard
583	14ce26e7	bellard	static GenOpFunc *gen_op_shift_T0_T1_cc[4][8] = {
584	4bb2fcc7	bellard	DEF_SHIFT( )
585	2c0262af	bellard	};
586	2c0262af	bellard
587	14ce26e7	bellard	static GenOpFunc gen_op_shift_mem_T0_T1_cc[3 4][8] = {
588	4f31916f	bellard	DEF_SHIFT(_raw)
589	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
590	4f31916f	bellard	DEF_SHIFT(_kernel)
591	4f31916f	bellard	DEF_SHIFT(_user)
592	4f31916f	bellard	#endif
593	2c0262af	bellard	};
594	2c0262af	bellard
595	4f31916f	bellard	#define DEF_SHIFTD(SUFFIX, op)\
596	4f31916f	bellard	{\
597	4f31916f	bellard	NULL,\
598	4f31916f	bellard	NULL,\
599	4f31916f	bellard	},\
600	4f31916f	bellard	{\
601	4f31916f	bellard	gen_op_shldw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
602	4f31916f	bellard	gen_op_shrdw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
603	4f31916f	bellard	},\
604	4f31916f	bellard	{\
605	4f31916f	bellard	gen_op_shldl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
606	4f31916f	bellard	gen_op_shrdl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
607	14ce26e7	bellard	},\
608	14ce26e7	bellard	{\
609	2c0262af	bellard	},
610	4f31916f	bellard
611	14ce26e7	bellard	static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[4][2] = {
612	4f31916f	bellard	DEF_SHIFTD(, im)
613	2c0262af	bellard	};
614	2c0262af	bellard
615	14ce26e7	bellard	static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[4][2] = {
616	4f31916f	bellard	DEF_SHIFTD(, ECX)
617	2c0262af	bellard	};
618	2c0262af	bellard
619	14ce26e7	bellard	static GenOpFunc1 gen_op_shiftd_mem_T0_T1_im_cc[3 4][2] = {
620	4f31916f	bellard	DEF_SHIFTD(_raw, im)
621	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
622	4f31916f	bellard	DEF_SHIFTD(_kernel, im)
623	4f31916f	bellard	DEF_SHIFTD(_user, im)
624	4f31916f	bellard	#endif
625	2c0262af	bellard	};
626	2c0262af	bellard
627	14ce26e7	bellard	static GenOpFunc gen_op_shiftd_mem_T0_T1_ECX_cc[3 4][2] = {
628	4f31916f	bellard	DEF_SHIFTD(_raw, ECX)
629	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
630	4f31916f	bellard	DEF_SHIFTD(_kernel, ECX)
631	4f31916f	bellard	DEF_SHIFTD(_user, ECX)
632	4f31916f	bellard	#endif
633	2c0262af	bellard	};
634	2c0262af	bellard
635	14ce26e7	bellard	static GenOpFunc *gen_op_btx_T0_T1_cc[3][4] = {
636	2c0262af	bellard	[0] = {
637	2c0262af	bellard	gen_op_btw_T0_T1_cc,
638	2c0262af	bellard	gen_op_btsw_T0_T1_cc,
639	2c0262af	bellard	gen_op_btrw_T0_T1_cc,
640	2c0262af	bellard	gen_op_btcw_T0_T1_cc,
641	2c0262af	bellard	},
642	2c0262af	bellard	[1] = {
643	2c0262af	bellard	gen_op_btl_T0_T1_cc,
644	2c0262af	bellard	gen_op_btsl_T0_T1_cc,
645	2c0262af	bellard	gen_op_btrl_T0_T1_cc,
646	2c0262af	bellard	gen_op_btcl_T0_T1_cc,
647	2c0262af	bellard	},
648	14ce26e7	bellard	#ifdef TARGET_X86_64
649	14ce26e7	bellard	[2] = {
650	14ce26e7	bellard	gen_op_btq_T0_T1_cc,
651	14ce26e7	bellard	gen_op_btsq_T0_T1_cc,
652	14ce26e7	bellard	gen_op_btrq_T0_T1_cc,
653	14ce26e7	bellard	gen_op_btcq_T0_T1_cc,
654	14ce26e7	bellard	},
655	14ce26e7	bellard	#endif
656	14ce26e7	bellard	};
657	14ce26e7	bellard
658	14ce26e7	bellard	static GenOpFunc *gen_op_add_bit_A0_T1[3] = {
659	14ce26e7	bellard	gen_op_add_bitw_A0_T1,
660	14ce26e7	bellard	gen_op_add_bitl_A0_T1,
661	14ce26e7	bellard	X86_64_ONLY(gen_op_add_bitq_A0_T1),
662	2c0262af	bellard	};
663	2c0262af	bellard
664	14ce26e7	bellard	static GenOpFunc *gen_op_bsx_T0_cc[3][2] = {
665	2c0262af	bellard	[0] = {
666	2c0262af	bellard	gen_op_bsfw_T0_cc,
667	2c0262af	bellard	gen_op_bsrw_T0_cc,
668	2c0262af	bellard	},
669	2c0262af	bellard	[1] = {
670	2c0262af	bellard	gen_op_bsfl_T0_cc,
671	2c0262af	bellard	gen_op_bsrl_T0_cc,
672	2c0262af	bellard	},
673	14ce26e7	bellard	#ifdef TARGET_X86_64
674	14ce26e7	bellard	[2] = {
675	14ce26e7	bellard	gen_op_bsfq_T0_cc,
676	14ce26e7	bellard	gen_op_bsrq_T0_cc,
677	14ce26e7	bellard	},
678	14ce26e7	bellard	#endif
679	2c0262af	bellard	};
680	2c0262af	bellard
681	14ce26e7	bellard	static GenOpFunc gen_op_lds_T0_A0[3 4] = {
682	61382a50	bellard	gen_op_ldsb_raw_T0_A0,
683	61382a50	bellard	gen_op_ldsw_raw_T0_A0,
684	14ce26e7	bellard	X86_64_ONLY(gen_op_ldsl_raw_T0_A0),
685	2c0262af	bellard	NULL,
686	61382a50	bellard	#ifndef CONFIG_USER_ONLY
687	2c0262af	bellard	gen_op_ldsb_kernel_T0_A0,
688	2c0262af	bellard	gen_op_ldsw_kernel_T0_A0,
689	14ce26e7	bellard	X86_64_ONLY(gen_op_ldsl_kernel_T0_A0),
690	2c0262af	bellard	NULL,
691	2c0262af	bellard
692	2c0262af	bellard	gen_op_ldsb_user_T0_A0,
693	2c0262af	bellard	gen_op_ldsw_user_T0_A0,
694	14ce26e7	bellard	X86_64_ONLY(gen_op_ldsl_user_T0_A0),
695	2c0262af	bellard	NULL,
696	61382a50	bellard	#endif
697	2c0262af	bellard	};
698	2c0262af	bellard
699	14ce26e7	bellard	static GenOpFunc gen_op_ldu_T0_A0[3 4] = {
700	61382a50	bellard	gen_op_ldub_raw_T0_A0,
701	61382a50	bellard	gen_op_lduw_raw_T0_A0,
702	2c0262af	bellard	NULL,
703	14ce26e7	bellard	NULL,
704	2c0262af	bellard
705	61382a50	bellard	#ifndef CONFIG_USER_ONLY
706	2c0262af	bellard	gen_op_ldub_kernel_T0_A0,
707	2c0262af	bellard	gen_op_lduw_kernel_T0_A0,
708	2c0262af	bellard	NULL,
709	14ce26e7	bellard	NULL,
710	2c0262af	bellard
711	2c0262af	bellard	gen_op_ldub_user_T0_A0,
712	2c0262af	bellard	gen_op_lduw_user_T0_A0,
713	2c0262af	bellard	NULL,
714	14ce26e7	bellard	NULL,
715	61382a50	bellard	#endif
716	2c0262af	bellard	};
717	2c0262af	bellard
718	2c0262af	bellard	/* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
719	14ce26e7	bellard	static GenOpFunc gen_op_ld_T0_A0[3 4] = {
720	61382a50	bellard	gen_op_ldub_raw_T0_A0,
721	61382a50	bellard	gen_op_lduw_raw_T0_A0,
722	61382a50	bellard	gen_op_ldl_raw_T0_A0,
723	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_raw_T0_A0),
724	2c0262af	bellard
725	61382a50	bellard	#ifndef CONFIG_USER_ONLY
726	2c0262af	bellard	gen_op_ldub_kernel_T0_A0,
727	2c0262af	bellard	gen_op_lduw_kernel_T0_A0,
728	2c0262af	bellard	gen_op_ldl_kernel_T0_A0,
729	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_kernel_T0_A0),
730	2c0262af	bellard
731	2c0262af	bellard	gen_op_ldub_user_T0_A0,
732	2c0262af	bellard	gen_op_lduw_user_T0_A0,
733	2c0262af	bellard	gen_op_ldl_user_T0_A0,
734	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_user_T0_A0),
735	61382a50	bellard	#endif
736	2c0262af	bellard	};
737	2c0262af	bellard
738	14ce26e7	bellard	static GenOpFunc gen_op_ld_T1_A0[3 4] = {
739	61382a50	bellard	gen_op_ldub_raw_T1_A0,
740	61382a50	bellard	gen_op_lduw_raw_T1_A0,
741	61382a50	bellard	gen_op_ldl_raw_T1_A0,
742	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_raw_T1_A0),
743	2c0262af	bellard
744	61382a50	bellard	#ifndef CONFIG_USER_ONLY
745	2c0262af	bellard	gen_op_ldub_kernel_T1_A0,
746	2c0262af	bellard	gen_op_lduw_kernel_T1_A0,
747	2c0262af	bellard	gen_op_ldl_kernel_T1_A0,
748	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_kernel_T1_A0),
749	2c0262af	bellard
750	2c0262af	bellard	gen_op_ldub_user_T1_A0,
751	2c0262af	bellard	gen_op_lduw_user_T1_A0,
752	2c0262af	bellard	gen_op_ldl_user_T1_A0,
753	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_user_T1_A0),
754	61382a50	bellard	#endif
755	2c0262af	bellard	};
756	2c0262af	bellard
757	14ce26e7	bellard	static GenOpFunc gen_op_st_T0_A0[3 4] = {
758	61382a50	bellard	gen_op_stb_raw_T0_A0,
759	61382a50	bellard	gen_op_stw_raw_T0_A0,
760	61382a50	bellard	gen_op_stl_raw_T0_A0,
761	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_raw_T0_A0),
762	2c0262af	bellard
763	61382a50	bellard	#ifndef CONFIG_USER_ONLY
764	2c0262af	bellard	gen_op_stb_kernel_T0_A0,
765	2c0262af	bellard	gen_op_stw_kernel_T0_A0,
766	2c0262af	bellard	gen_op_stl_kernel_T0_A0,
767	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_kernel_T0_A0),
768	2c0262af	bellard
769	2c0262af	bellard	gen_op_stb_user_T0_A0,
770	2c0262af	bellard	gen_op_stw_user_T0_A0,
771	2c0262af	bellard	gen_op_stl_user_T0_A0,
772	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_user_T0_A0),
773	61382a50	bellard	#endif
774	2c0262af	bellard	};
775	2c0262af	bellard
776	14ce26e7	bellard	static GenOpFunc gen_op_st_T1_A0[3 4] = {
777	4f31916f	bellard	NULL,
778	4f31916f	bellard	gen_op_stw_raw_T1_A0,
779	4f31916f	bellard	gen_op_stl_raw_T1_A0,
780	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_raw_T1_A0),
781	4f31916f	bellard
782	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
783	4f31916f	bellard	NULL,
784	4f31916f	bellard	gen_op_stw_kernel_T1_A0,
785	4f31916f	bellard	gen_op_stl_kernel_T1_A0,
786	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_kernel_T1_A0),
787	4f31916f	bellard
788	4f31916f	bellard	NULL,
789	4f31916f	bellard	gen_op_stw_user_T1_A0,
790	4f31916f	bellard	gen_op_stl_user_T1_A0,
791	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_user_T1_A0),
792	4f31916f	bellard	#endif
793	4f31916f	bellard	};
794	4f31916f	bellard
795	14ce26e7	bellard	static inline void gen_jmp_im(target_ulong pc)
796	14ce26e7	bellard	{
797	14ce26e7	bellard	#ifdef TARGET_X86_64
798	14ce26e7	bellard	if (pc == (uint32_t)pc) {
799	14ce26e7	bellard	gen_op_movl_eip_im(pc);
800	14ce26e7	bellard	} else if (pc == (int32_t)pc) {
801	14ce26e7	bellard	gen_op_movq_eip_im(pc);
802	14ce26e7	bellard	} else {
803	14ce26e7	bellard	gen_op_movq_eip_im64(pc >> 32, pc);
804	14ce26e7	bellard	}
805	14ce26e7	bellard	#else
806	14ce26e7	bellard	gen_op_movl_eip_im(pc);
807	14ce26e7	bellard	#endif
808	14ce26e7	bellard	}
809	14ce26e7	bellard
810	2c0262af	bellard	static inline void gen_string_movl_A0_ESI(DisasContext *s)
811	2c0262af	bellard	{
812	2c0262af	bellard	int override;
813	2c0262af	bellard
814	2c0262af	bellard	override = s->override;
815	14ce26e7	bellard	#ifdef TARGET_X86_64
816	14ce26e7	bellard	if (s->aflag == 2) {
817	14ce26e7	bellard	if (override >= 0) {
818	14ce26e7	bellard	gen_op_movq_A0_seg(offsetof(CPUX86State,segs[override].base));
819	14ce26e7	bellard	gen_op_addq_A0_reg_sN[0][R_ESI]();
820	14ce26e7	bellard	} else {
821	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESI]();
822	14ce26e7	bellard	}
823	14ce26e7	bellard	} else
824	14ce26e7	bellard	#endif
825	2c0262af	bellard	if (s->aflag) {
826	2c0262af	bellard	/* 32 bit address */
827	2c0262af	bellard	if (s->addseg && override < 0)
828	2c0262af	bellard	override = R_DS;
829	2c0262af	bellard	if (override >= 0) {
830	2c0262af	bellard	gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
831	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_ESI]();
832	2c0262af	bellard	} else {
833	2c0262af	bellard	gen_op_movl_A0_reg[R_ESI]();
834	2c0262af	bellard	}
835	2c0262af	bellard	} else {
836	2c0262af	bellard	/* 16 address, always override */
837	2c0262af	bellard	if (override < 0)
838	2c0262af	bellard	override = R_DS;
839	2c0262af	bellard	gen_op_movl_A0_reg[R_ESI]();
840	2c0262af	bellard	gen_op_andl_A0_ffff();
841	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
842	2c0262af	bellard	}
843	2c0262af	bellard	}
844	2c0262af	bellard
845	2c0262af	bellard	static inline void gen_string_movl_A0_EDI(DisasContext *s)
846	2c0262af	bellard	{
847	14ce26e7	bellard	#ifdef TARGET_X86_64
848	14ce26e7	bellard	if (s->aflag == 2) {
849	14ce26e7	bellard	gen_op_movq_A0_reg[R_EDI]();
850	14ce26e7	bellard	} else
851	14ce26e7	bellard	#endif
852	2c0262af	bellard	if (s->aflag) {
853	2c0262af	bellard	if (s->addseg) {
854	2c0262af	bellard	gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
855	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_EDI]();
856	2c0262af	bellard	} else {
857	2c0262af	bellard	gen_op_movl_A0_reg[R_EDI]();
858	2c0262af	bellard	}
859	2c0262af	bellard	} else {
860	2c0262af	bellard	gen_op_movl_A0_reg[R_EDI]();
861	2c0262af	bellard	gen_op_andl_A0_ffff();
862	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
863	2c0262af	bellard	}
864	2c0262af	bellard	}
865	2c0262af	bellard
866	14ce26e7	bellard	static GenOpFunc *gen_op_movl_T0_Dshift[4] = {
867	2c0262af	bellard	gen_op_movl_T0_Dshiftb,
868	2c0262af	bellard	gen_op_movl_T0_Dshiftw,
869	2c0262af	bellard	gen_op_movl_T0_Dshiftl,
870	14ce26e7	bellard	X86_64_ONLY(gen_op_movl_T0_Dshiftq),
871	2c0262af	bellard	};
872	2c0262af	bellard
873	14ce26e7	bellard	static GenOpFunc1 *gen_op_jnz_ecx[3] = {
874	14ce26e7	bellard	gen_op_jnz_ecxw,
875	14ce26e7	bellard	gen_op_jnz_ecxl,
876	14ce26e7	bellard	X86_64_ONLY(gen_op_jnz_ecxq),
877	2c0262af	bellard	};
878	2c0262af	bellard
879	14ce26e7	bellard	static GenOpFunc1 *gen_op_jz_ecx[3] = {
880	14ce26e7	bellard	gen_op_jz_ecxw,
881	14ce26e7	bellard	gen_op_jz_ecxl,
882	14ce26e7	bellard	X86_64_ONLY(gen_op_jz_ecxq),
883	2c0262af	bellard	};
884	2c0262af	bellard
885	14ce26e7	bellard	static GenOpFunc *gen_op_dec_ECX[3] = {
886	2c0262af	bellard	gen_op_decw_ECX,
887	2c0262af	bellard	gen_op_decl_ECX,
888	14ce26e7	bellard	X86_64_ONLY(gen_op_decq_ECX),
889	2c0262af	bellard	};
890	2c0262af	bellard
891	14ce26e7	bellard	static GenOpFunc1 *gen_op_string_jnz_sub[2][4] = {
892	2c0262af	bellard	{
893	14ce26e7	bellard	gen_op_jnz_subb,
894	14ce26e7	bellard	gen_op_jnz_subw,
895	14ce26e7	bellard	gen_op_jnz_subl,
896	14ce26e7	bellard	X86_64_ONLY(gen_op_jnz_subq),
897	2c0262af	bellard	},
898	2c0262af	bellard	{
899	14ce26e7	bellard	gen_op_jz_subb,
900	14ce26e7	bellard	gen_op_jz_subw,
901	14ce26e7	bellard	gen_op_jz_subl,
902	14ce26e7	bellard	X86_64_ONLY(gen_op_jz_subq),
903	2c0262af	bellard	},
904	2c0262af	bellard	};
905	2c0262af	bellard
906	2c0262af	bellard	static GenOpFunc *gen_op_in_DX_T0[3] = {
907	2c0262af	bellard	gen_op_inb_DX_T0,
908	2c0262af	bellard	gen_op_inw_DX_T0,
909	2c0262af	bellard	gen_op_inl_DX_T0,
910	2c0262af	bellard	};
911	2c0262af	bellard
912	2c0262af	bellard	static GenOpFunc *gen_op_out_DX_T0[3] = {
913	2c0262af	bellard	gen_op_outb_DX_T0,
914	2c0262af	bellard	gen_op_outw_DX_T0,
915	2c0262af	bellard	gen_op_outl_DX_T0,
916	2c0262af	bellard	};
917	2c0262af	bellard
918	f115e911	bellard	static GenOpFunc *gen_op_in[3] = {
919	f115e911	bellard	gen_op_inb_T0_T1,
920	f115e911	bellard	gen_op_inw_T0_T1,
921	f115e911	bellard	gen_op_inl_T0_T1,
922	f115e911	bellard	};
923	f115e911	bellard
924	f115e911	bellard	static GenOpFunc *gen_op_out[3] = {
925	f115e911	bellard	gen_op_outb_T0_T1,
926	f115e911	bellard	gen_op_outw_T0_T1,
927	f115e911	bellard	gen_op_outl_T0_T1,
928	f115e911	bellard	};
929	f115e911	bellard
930	f115e911	bellard	static GenOpFunc *gen_check_io_T0[3] = {
931	f115e911	bellard	gen_op_check_iob_T0,
932	f115e911	bellard	gen_op_check_iow_T0,
933	f115e911	bellard	gen_op_check_iol_T0,
934	f115e911	bellard	};
935	f115e911	bellard
936	f115e911	bellard	static GenOpFunc *gen_check_io_DX[3] = {
937	f115e911	bellard	gen_op_check_iob_DX,
938	f115e911	bellard	gen_op_check_iow_DX,
939	f115e911	bellard	gen_op_check_iol_DX,
940	f115e911	bellard	};
941	f115e911	bellard
942	14ce26e7	bellard	static void gen_check_io(DisasContext *s, int ot, int use_dx, target_ulong cur_eip)
943	f115e911	bellard	{
944	f115e911	bellard	if (s->pe && (s->cpl > s->iopl \|\| s->vm86)) {
945	f115e911	bellard	if (s->cc_op != CC_OP_DYNAMIC)
946	f115e911	bellard	gen_op_set_cc_op(s->cc_op);
947	14ce26e7	bellard	gen_jmp_im(cur_eip);
948	f115e911	bellard	if (use_dx)
949	f115e911	bellard	gen_check_io_DX[ot]();
950	f115e911	bellard	else
951	f115e911	bellard	gen_check_io_T0[ot]();
952	f115e911	bellard	}
953	f115e911	bellard	}
954	f115e911	bellard
955	2c0262af	bellard	static inline void gen_movs(DisasContext *s, int ot)
956	2c0262af	bellard	{
957	2c0262af	bellard	gen_string_movl_A0_ESI(s);
958	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
959	2c0262af	bellard	gen_string_movl_A0_EDI(s);
960	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
961	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
962	14ce26e7	bellard	#ifdef TARGET_X86_64
963	14ce26e7	bellard	if (s->aflag == 2) {
964	14ce26e7	bellard	gen_op_addq_ESI_T0();
965	14ce26e7	bellard	gen_op_addq_EDI_T0();
966	14ce26e7	bellard	} else
967	14ce26e7	bellard	#endif
968	2c0262af	bellard	if (s->aflag) {
969	2c0262af	bellard	gen_op_addl_ESI_T0();
970	2c0262af	bellard	gen_op_addl_EDI_T0();
971	2c0262af	bellard	} else {
972	2c0262af	bellard	gen_op_addw_ESI_T0();
973	2c0262af	bellard	gen_op_addw_EDI_T0();
974	2c0262af	bellard	}
975	2c0262af	bellard	}
976	2c0262af	bellard
977	2c0262af	bellard	static inline void gen_update_cc_op(DisasContext *s)
978	2c0262af	bellard	{
979	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
980	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
981	2c0262af	bellard	s->cc_op = CC_OP_DYNAMIC;
982	2c0262af	bellard	}
983	2c0262af	bellard	}
984	2c0262af	bellard
985	14ce26e7	bellard	/* XXX: does not work with gdbstub "ice" single step - not a
986	14ce26e7	bellard	serious problem */
987	14ce26e7	bellard	static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
988	2c0262af	bellard	{
989	14ce26e7	bellard	int l1, l2;
990	14ce26e7	bellard
991	14ce26e7	bellard	l1 = gen_new_label();
992	14ce26e7	bellard	l2 = gen_new_label();
993	14ce26e7	bellard	gen_op_jnz_ecx[s->aflag](l1);
994	14ce26e7	bellard	gen_set_label(l2);
995	14ce26e7	bellard	gen_jmp_tb(s, next_eip, 1);
996	14ce26e7	bellard	gen_set_label(l1);
997	14ce26e7	bellard	return l2;
998	2c0262af	bellard	}
999	2c0262af	bellard
1000	2c0262af	bellard	static inline void gen_stos(DisasContext *s, int ot)
1001	2c0262af	bellard	{
1002	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
1003	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1004	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1005	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1006	14ce26e7	bellard	#ifdef TARGET_X86_64
1007	14ce26e7	bellard	if (s->aflag == 2) {
1008	14ce26e7	bellard	gen_op_addq_EDI_T0();
1009	14ce26e7	bellard	} else
1010	14ce26e7	bellard	#endif
1011	2c0262af	bellard	if (s->aflag) {
1012	2c0262af	bellard	gen_op_addl_EDI_T0();
1013	2c0262af	bellard	} else {
1014	2c0262af	bellard	gen_op_addw_EDI_T0();
1015	2c0262af	bellard	}
1016	2c0262af	bellard	}
1017	2c0262af	bellard
1018	2c0262af	bellard	static inline void gen_lods(DisasContext *s, int ot)
1019	2c0262af	bellard	{
1020	2c0262af	bellard	gen_string_movl_A0_ESI(s);
1021	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1022	2c0262af	bellard	gen_op_mov_reg_T0[ot][R_EAX]();
1023	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1024	14ce26e7	bellard	#ifdef TARGET_X86_64
1025	14ce26e7	bellard	if (s->aflag == 2) {
1026	14ce26e7	bellard	gen_op_addq_ESI_T0();
1027	14ce26e7	bellard	} else
1028	14ce26e7	bellard	#endif
1029	2c0262af	bellard	if (s->aflag) {
1030	2c0262af	bellard	gen_op_addl_ESI_T0();
1031	2c0262af	bellard	} else {
1032	2c0262af	bellard	gen_op_addw_ESI_T0();
1033	2c0262af	bellard	}
1034	2c0262af	bellard	}
1035	2c0262af	bellard
1036	2c0262af	bellard	static inline void gen_scas(DisasContext *s, int ot)
1037	2c0262af	bellard	{
1038	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
1039	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1040	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
1041	2c0262af	bellard	gen_op_cmpl_T0_T1_cc();
1042	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1043	14ce26e7	bellard	#ifdef TARGET_X86_64
1044	14ce26e7	bellard	if (s->aflag == 2) {
1045	14ce26e7	bellard	gen_op_addq_EDI_T0();
1046	14ce26e7	bellard	} else
1047	14ce26e7	bellard	#endif
1048	2c0262af	bellard	if (s->aflag) {
1049	2c0262af	bellard	gen_op_addl_EDI_T0();
1050	2c0262af	bellard	} else {
1051	2c0262af	bellard	gen_op_addw_EDI_T0();
1052	2c0262af	bellard	}
1053	2c0262af	bellard	}
1054	2c0262af	bellard
1055	2c0262af	bellard	static inline void gen_cmps(DisasContext *s, int ot)
1056	2c0262af	bellard	{
1057	2c0262af	bellard	gen_string_movl_A0_ESI(s);
1058	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1059	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1060	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
1061	2c0262af	bellard	gen_op_cmpl_T0_T1_cc();
1062	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1063	14ce26e7	bellard	#ifdef TARGET_X86_64
1064	14ce26e7	bellard	if (s->aflag == 2) {
1065	14ce26e7	bellard	gen_op_addq_ESI_T0();
1066	14ce26e7	bellard	gen_op_addq_EDI_T0();
1067	14ce26e7	bellard	} else
1068	14ce26e7	bellard	#endif
1069	2c0262af	bellard	if (s->aflag) {
1070	2c0262af	bellard	gen_op_addl_ESI_T0();
1071	2c0262af	bellard	gen_op_addl_EDI_T0();
1072	2c0262af	bellard	} else {
1073	2c0262af	bellard	gen_op_addw_ESI_T0();
1074	2c0262af	bellard	gen_op_addw_EDI_T0();
1075	2c0262af	bellard	}
1076	2c0262af	bellard	}
1077	2c0262af	bellard
1078	2c0262af	bellard	static inline void gen_ins(DisasContext *s, int ot)
1079	2c0262af	bellard	{
1080	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1081	9772c73b	bellard	gen_op_movl_T0_0();
1082	9772c73b	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1083	9772c73b	bellard	gen_op_in_DX_T0[ot]();
1084	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1085	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1086	14ce26e7	bellard	#ifdef TARGET_X86_64
1087	14ce26e7	bellard	if (s->aflag == 2) {
1088	14ce26e7	bellard	gen_op_addq_EDI_T0();
1089	14ce26e7	bellard	} else
1090	14ce26e7	bellard	#endif
1091	2c0262af	bellard	if (s->aflag) {
1092	2c0262af	bellard	gen_op_addl_EDI_T0();
1093	2c0262af	bellard	} else {
1094	2c0262af	bellard	gen_op_addw_EDI_T0();
1095	2c0262af	bellard	}
1096	2c0262af	bellard	}
1097	2c0262af	bellard
1098	2c0262af	bellard	static inline void gen_outs(DisasContext *s, int ot)
1099	2c0262af	bellard	{
1100	2c0262af	bellard	gen_string_movl_A0_ESI(s);
1101	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1102	2c0262af	bellard	gen_op_out_DX_T0[ot]();
1103	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1104	14ce26e7	bellard	#ifdef TARGET_X86_64
1105	14ce26e7	bellard	if (s->aflag == 2) {
1106	14ce26e7	bellard	gen_op_addq_ESI_T0();
1107	14ce26e7	bellard	} else
1108	14ce26e7	bellard	#endif
1109	2c0262af	bellard	if (s->aflag) {
1110	2c0262af	bellard	gen_op_addl_ESI_T0();
1111	2c0262af	bellard	} else {
1112	2c0262af	bellard	gen_op_addw_ESI_T0();
1113	2c0262af	bellard	}
1114	2c0262af	bellard	}
1115	2c0262af	bellard
1116	2c0262af	bellard	/* same method as Valgrind : we generate jumps to current or next
1117	2c0262af	bellard	instruction */
1118	2c0262af	bellard	#define GEN_REPZ(op) \
1119	2c0262af	bellard	static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1120	14ce26e7	bellard	target_ulong cur_eip, target_ulong next_eip) \
1121	2c0262af	bellard	{ \
1122	14ce26e7	bellard	int l2;\
1123	2c0262af	bellard	gen_update_cc_op(s); \
1124	14ce26e7	bellard	l2 = gen_jz_ecx_string(s, next_eip); \
1125	2c0262af	bellard	gen_ ## op(s, ot); \
1126	2c0262af	bellard	gen_op_dec_ECX[s->aflag](); \
1127	2c0262af	bellard	/* a loop would cause two single step exceptions if ECX = 1 \
1128	2c0262af	bellard	before rep string_insn */ \
1129	2c0262af	bellard	if (!s->jmp_opt) \
1130	14ce26e7	bellard	gen_op_jz_ecx[s->aflag](l2); \
1131	2c0262af	bellard	gen_jmp(s, cur_eip); \
1132	2c0262af	bellard	}
1133	2c0262af	bellard
1134	2c0262af	bellard	#define GEN_REPZ2(op) \
1135	2c0262af	bellard	static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1136	14ce26e7	bellard	target_ulong cur_eip, \
1137	14ce26e7	bellard	target_ulong next_eip, \
1138	2c0262af	bellard	int nz) \
1139	2c0262af	bellard	{ \
1140	14ce26e7	bellard	int l2;\
1141	2c0262af	bellard	gen_update_cc_op(s); \
1142	14ce26e7	bellard	l2 = gen_jz_ecx_string(s, next_eip); \
1143	2c0262af	bellard	gen_ ## op(s, ot); \
1144	2c0262af	bellard	gen_op_dec_ECX[s->aflag](); \
1145	2c0262af	bellard	gen_op_set_cc_op(CC_OP_SUBB + ot); \
1146	14ce26e7	bellard	gen_op_string_jnz_sub[nz][ot](l2);\
1147	2c0262af	bellard	if (!s->jmp_opt) \
1148	14ce26e7	bellard	gen_op_jz_ecx[s->aflag](l2); \
1149	2c0262af	bellard	gen_jmp(s, cur_eip); \
1150	2c0262af	bellard	}
1151	2c0262af	bellard
1152	2c0262af	bellard	GEN_REPZ(movs)
1153	2c0262af	bellard	GEN_REPZ(stos)
1154	2c0262af	bellard	GEN_REPZ(lods)
1155	2c0262af	bellard	GEN_REPZ(ins)
1156	2c0262af	bellard	GEN_REPZ(outs)
1157	2c0262af	bellard	GEN_REPZ2(scas)
1158	2c0262af	bellard	GEN_REPZ2(cmps)
1159	2c0262af	bellard
1160	2c0262af	bellard	enum {
1161	2c0262af	bellard	JCC_O,
1162	2c0262af	bellard	JCC_B,
1163	2c0262af	bellard	JCC_Z,
1164	2c0262af	bellard	JCC_BE,
1165	2c0262af	bellard	JCC_S,
1166	2c0262af	bellard	JCC_P,
1167	2c0262af	bellard	JCC_L,
1168	2c0262af	bellard	JCC_LE,
1169	2c0262af	bellard	};
1170	2c0262af	bellard
1171	14ce26e7	bellard	static GenOpFunc1 *gen_jcc_sub[4][8] = {
1172	2c0262af	bellard	[OT_BYTE] = {
1173	2c0262af	bellard	NULL,
1174	2c0262af	bellard	gen_op_jb_subb,
1175	2c0262af	bellard	gen_op_jz_subb,
1176	2c0262af	bellard	gen_op_jbe_subb,
1177	2c0262af	bellard	gen_op_js_subb,
1178	2c0262af	bellard	NULL,
1179	2c0262af	bellard	gen_op_jl_subb,
1180	2c0262af	bellard	gen_op_jle_subb,
1181	2c0262af	bellard	},
1182	2c0262af	bellard	[OT_WORD] = {
1183	2c0262af	bellard	NULL,
1184	2c0262af	bellard	gen_op_jb_subw,
1185	2c0262af	bellard	gen_op_jz_subw,
1186	2c0262af	bellard	gen_op_jbe_subw,
1187	2c0262af	bellard	gen_op_js_subw,
1188	2c0262af	bellard	NULL,
1189	2c0262af	bellard	gen_op_jl_subw,
1190	2c0262af	bellard	gen_op_jle_subw,
1191	2c0262af	bellard	},
1192	2c0262af	bellard	[OT_LONG] = {
1193	2c0262af	bellard	NULL,
1194	2c0262af	bellard	gen_op_jb_subl,
1195	2c0262af	bellard	gen_op_jz_subl,
1196	2c0262af	bellard	gen_op_jbe_subl,
1197	2c0262af	bellard	gen_op_js_subl,
1198	2c0262af	bellard	NULL,
1199	2c0262af	bellard	gen_op_jl_subl,
1200	2c0262af	bellard	gen_op_jle_subl,
1201	2c0262af	bellard	},
1202	14ce26e7	bellard	#ifdef TARGET_X86_64
1203	14ce26e7	bellard	[OT_QUAD] = {
1204	14ce26e7	bellard	NULL,
1205	14ce26e7	bellard	BUGGY_64(gen_op_jb_subq),
1206	14ce26e7	bellard	gen_op_jz_subq,
1207	14ce26e7	bellard	BUGGY_64(gen_op_jbe_subq),
1208	14ce26e7	bellard	gen_op_js_subq,
1209	14ce26e7	bellard	NULL,
1210	14ce26e7	bellard	BUGGY_64(gen_op_jl_subq),
1211	14ce26e7	bellard	BUGGY_64(gen_op_jle_subq),
1212	14ce26e7	bellard	},
1213	14ce26e7	bellard	#endif
1214	2c0262af	bellard	};
1215	14ce26e7	bellard	static GenOpFunc1 *gen_op_loop[3][4] = {
1216	2c0262af	bellard	[0] = {
1217	2c0262af	bellard	gen_op_loopnzw,
1218	2c0262af	bellard	gen_op_loopzw,
1219	14ce26e7	bellard	gen_op_jnz_ecxw,
1220	2c0262af	bellard	},
1221	2c0262af	bellard	[1] = {
1222	2c0262af	bellard	gen_op_loopnzl,
1223	2c0262af	bellard	gen_op_loopzl,
1224	14ce26e7	bellard	gen_op_jnz_ecxl,
1225	14ce26e7	bellard	},
1226	14ce26e7	bellard	#ifdef TARGET_X86_64
1227	14ce26e7	bellard	[2] = {
1228	14ce26e7	bellard	gen_op_loopnzq,
1229	14ce26e7	bellard	gen_op_loopzq,
1230	14ce26e7	bellard	gen_op_jnz_ecxq,
1231	2c0262af	bellard	},
1232	14ce26e7	bellard	#endif
1233	2c0262af	bellard	};
1234	2c0262af	bellard
1235	2c0262af	bellard	static GenOpFunc *gen_setcc_slow[8] = {
1236	2c0262af	bellard	gen_op_seto_T0_cc,
1237	2c0262af	bellard	gen_op_setb_T0_cc,
1238	2c0262af	bellard	gen_op_setz_T0_cc,
1239	2c0262af	bellard	gen_op_setbe_T0_cc,
1240	2c0262af	bellard	gen_op_sets_T0_cc,
1241	2c0262af	bellard	gen_op_setp_T0_cc,
1242	2c0262af	bellard	gen_op_setl_T0_cc,
1243	2c0262af	bellard	gen_op_setle_T0_cc,
1244	2c0262af	bellard	};
1245	2c0262af	bellard
1246	14ce26e7	bellard	static GenOpFunc *gen_setcc_sub[4][8] = {
1247	2c0262af	bellard	[OT_BYTE] = {
1248	2c0262af	bellard	NULL,
1249	2c0262af	bellard	gen_op_setb_T0_subb,
1250	2c0262af	bellard	gen_op_setz_T0_subb,
1251	2c0262af	bellard	gen_op_setbe_T0_subb,
1252	2c0262af	bellard	gen_op_sets_T0_subb,
1253	2c0262af	bellard	NULL,
1254	2c0262af	bellard	gen_op_setl_T0_subb,
1255	2c0262af	bellard	gen_op_setle_T0_subb,
1256	2c0262af	bellard	},
1257	2c0262af	bellard	[OT_WORD] = {
1258	2c0262af	bellard	NULL,
1259	2c0262af	bellard	gen_op_setb_T0_subw,
1260	2c0262af	bellard	gen_op_setz_T0_subw,
1261	2c0262af	bellard	gen_op_setbe_T0_subw,
1262	2c0262af	bellard	gen_op_sets_T0_subw,
1263	2c0262af	bellard	NULL,
1264	2c0262af	bellard	gen_op_setl_T0_subw,
1265	2c0262af	bellard	gen_op_setle_T0_subw,
1266	2c0262af	bellard	},
1267	2c0262af	bellard	[OT_LONG] = {
1268	2c0262af	bellard	NULL,
1269	2c0262af	bellard	gen_op_setb_T0_subl,
1270	2c0262af	bellard	gen_op_setz_T0_subl,
1271	2c0262af	bellard	gen_op_setbe_T0_subl,
1272	2c0262af	bellard	gen_op_sets_T0_subl,
1273	2c0262af	bellard	NULL,
1274	2c0262af	bellard	gen_op_setl_T0_subl,
1275	2c0262af	bellard	gen_op_setle_T0_subl,
1276	2c0262af	bellard	},
1277	14ce26e7	bellard	#ifdef TARGET_X86_64
1278	14ce26e7	bellard	[OT_QUAD] = {
1279	14ce26e7	bellard	NULL,
1280	14ce26e7	bellard	gen_op_setb_T0_subq,
1281	14ce26e7	bellard	gen_op_setz_T0_subq,
1282	14ce26e7	bellard	gen_op_setbe_T0_subq,
1283	14ce26e7	bellard	gen_op_sets_T0_subq,
1284	14ce26e7	bellard	NULL,
1285	14ce26e7	bellard	gen_op_setl_T0_subq,
1286	14ce26e7	bellard	gen_op_setle_T0_subq,
1287	14ce26e7	bellard	},
1288	14ce26e7	bellard	#endif
1289	2c0262af	bellard	};
1290	2c0262af	bellard
1291	2c0262af	bellard	static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1292	2c0262af	bellard	gen_op_fadd_ST0_FT0,
1293	2c0262af	bellard	gen_op_fmul_ST0_FT0,
1294	2c0262af	bellard	gen_op_fcom_ST0_FT0,
1295	2c0262af	bellard	gen_op_fcom_ST0_FT0,
1296	2c0262af	bellard	gen_op_fsub_ST0_FT0,
1297	2c0262af	bellard	gen_op_fsubr_ST0_FT0,
1298	2c0262af	bellard	gen_op_fdiv_ST0_FT0,
1299	2c0262af	bellard	gen_op_fdivr_ST0_FT0,
1300	2c0262af	bellard	};
1301	2c0262af	bellard
1302	2c0262af	bellard	/* NOTE the exception in "r" op ordering */
1303	2c0262af	bellard	static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1304	2c0262af	bellard	gen_op_fadd_STN_ST0,
1305	2c0262af	bellard	gen_op_fmul_STN_ST0,
1306	2c0262af	bellard	NULL,
1307	2c0262af	bellard	NULL,
1308	2c0262af	bellard	gen_op_fsubr_STN_ST0,
1309	2c0262af	bellard	gen_op_fsub_STN_ST0,
1310	2c0262af	bellard	gen_op_fdivr_STN_ST0,
1311	2c0262af	bellard	gen_op_fdiv_STN_ST0,
1312	2c0262af	bellard	};
1313	2c0262af	bellard
1314	2c0262af	bellard	/* if d == OR_TMP0, it means memory operand (address in A0) */
1315	2c0262af	bellard	static void gen_op(DisasContext *s1, int op, int ot, int d)
1316	2c0262af	bellard	{
1317	2c0262af	bellard	GenOpFunc *gen_update_cc;
1318	2c0262af	bellard
1319	2c0262af	bellard	if (d != OR_TMP0) {
1320	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][d]();
1321	2c0262af	bellard	} else {
1322	2c0262af	bellard	gen_op_ld_T0_A0[ot + s1->mem_index]();
1323	2c0262af	bellard	}
1324	2c0262af	bellard	switch(op) {
1325	2c0262af	bellard	case OP_ADCL:
1326	2c0262af	bellard	case OP_SBBL:
1327	2c0262af	bellard	if (s1->cc_op != CC_OP_DYNAMIC)
1328	2c0262af	bellard	gen_op_set_cc_op(s1->cc_op);
1329	2c0262af	bellard	if (d != OR_TMP0) {
1330	2c0262af	bellard	gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1331	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1332	2c0262af	bellard	} else {
1333	4f31916f	bellard	gen_op_arithc_mem_T0_T1_cc[ot + s1->mem_index][op - OP_ADCL]();
1334	2c0262af	bellard	}
1335	2c0262af	bellard	s1->cc_op = CC_OP_DYNAMIC;
1336	2c0262af	bellard	goto the_end;
1337	2c0262af	bellard	case OP_ADDL:
1338	2c0262af	bellard	gen_op_addl_T0_T1();
1339	2c0262af	bellard	s1->cc_op = CC_OP_ADDB + ot;
1340	2c0262af	bellard	gen_update_cc = gen_op_update2_cc;
1341	2c0262af	bellard	break;
1342	2c0262af	bellard	case OP_SUBL:
1343	2c0262af	bellard	gen_op_subl_T0_T1();
1344	2c0262af	bellard	s1->cc_op = CC_OP_SUBB + ot;
1345	2c0262af	bellard	gen_update_cc = gen_op_update2_cc;
1346	2c0262af	bellard	break;
1347	2c0262af	bellard	default:
1348	2c0262af	bellard	case OP_ANDL:
1349	2c0262af	bellard	case OP_ORL:
1350	2c0262af	bellard	case OP_XORL:
1351	2c0262af	bellard	gen_op_arith_T0_T1_cc[op]();
1352	2c0262af	bellard	s1->cc_op = CC_OP_LOGICB + ot;
1353	2c0262af	bellard	gen_update_cc = gen_op_update1_cc;
1354	2c0262af	bellard	break;
1355	2c0262af	bellard	case OP_CMPL:
1356	2c0262af	bellard	gen_op_cmpl_T0_T1_cc();
1357	2c0262af	bellard	s1->cc_op = CC_OP_SUBB + ot;
1358	2c0262af	bellard	gen_update_cc = NULL;
1359	2c0262af	bellard	break;
1360	2c0262af	bellard	}
1361	2c0262af	bellard	if (op != OP_CMPL) {
1362	2c0262af	bellard	if (d != OR_TMP0)
1363	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1364	2c0262af	bellard	else
1365	2c0262af	bellard	gen_op_st_T0_A0[ot + s1->mem_index]();
1366	2c0262af	bellard	}
1367	2c0262af	bellard	/* the flags update must happen after the memory write (precise
1368	2c0262af	bellard	exception support) */
1369	2c0262af	bellard	if (gen_update_cc)
1370	2c0262af	bellard	gen_update_cc();
1371	2c0262af	bellard	the_end: ;
1372	2c0262af	bellard	}
1373	2c0262af	bellard
1374	2c0262af	bellard	/* if d == OR_TMP0, it means memory operand (address in A0) */
1375	2c0262af	bellard	static void gen_inc(DisasContext *s1, int ot, int d, int c)
1376	2c0262af	bellard	{
1377	2c0262af	bellard	if (d != OR_TMP0)
1378	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][d]();
1379	2c0262af	bellard	else
1380	2c0262af	bellard	gen_op_ld_T0_A0[ot + s1->mem_index]();
1381	2c0262af	bellard	if (s1->cc_op != CC_OP_DYNAMIC)
1382	2c0262af	bellard	gen_op_set_cc_op(s1->cc_op);
1383	2c0262af	bellard	if (c > 0) {
1384	2c0262af	bellard	gen_op_incl_T0();
1385	2c0262af	bellard	s1->cc_op = CC_OP_INCB + ot;
1386	2c0262af	bellard	} else {
1387	2c0262af	bellard	gen_op_decl_T0();
1388	2c0262af	bellard	s1->cc_op = CC_OP_DECB + ot;
1389	2c0262af	bellard	}
1390	2c0262af	bellard	if (d != OR_TMP0)
1391	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1392	2c0262af	bellard	else
1393	2c0262af	bellard	gen_op_st_T0_A0[ot + s1->mem_index]();
1394	2c0262af	bellard	gen_op_update_inc_cc();
1395	2c0262af	bellard	}
1396	2c0262af	bellard
1397	2c0262af	bellard	static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1398	2c0262af	bellard	{
1399	2c0262af	bellard	if (d != OR_TMP0)
1400	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][d]();
1401	2c0262af	bellard	else
1402	2c0262af	bellard	gen_op_ld_T0_A0[ot + s1->mem_index]();
1403	2c0262af	bellard	if (s != OR_TMP1)
1404	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][s]();
1405	2c0262af	bellard	/* for zero counts, flags are not updated, so must do it dynamically */
1406	2c0262af	bellard	if (s1->cc_op != CC_OP_DYNAMIC)
1407	2c0262af	bellard	gen_op_set_cc_op(s1->cc_op);
1408	2c0262af	bellard
1409	2c0262af	bellard	if (d != OR_TMP0)
1410	2c0262af	bellard	gen_op_shift_T0_T1_cc[ot][op]();
1411	2c0262af	bellard	else
1412	4f31916f	bellard	gen_op_shift_mem_T0_T1_cc[ot + s1->mem_index][op]();
1413	2c0262af	bellard	if (d != OR_TMP0)
1414	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1415	2c0262af	bellard	s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1416	2c0262af	bellard	}
1417	2c0262af	bellard
1418	2c0262af	bellard	static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1419	2c0262af	bellard	{
1420	2c0262af	bellard	/* currently not optimized */
1421	2c0262af	bellard	gen_op_movl_T1_im(c);
1422	2c0262af	bellard	gen_shift(s1, op, ot, d, OR_TMP1);
1423	2c0262af	bellard	}
1424	2c0262af	bellard
1425	2c0262af	bellard	static void gen_lea_modrm(DisasContext s, int modrm, int reg_ptr, int *offset_ptr)
1426	2c0262af	bellard	{
1427	14ce26e7	bellard	target_long disp;
1428	2c0262af	bellard	int havesib;
1429	14ce26e7	bellard	int base;
1430	2c0262af	bellard	int index;
1431	2c0262af	bellard	int scale;
1432	2c0262af	bellard	int opreg;
1433	2c0262af	bellard	int mod, rm, code, override, must_add_seg;
1434	2c0262af	bellard
1435	2c0262af	bellard	override = s->override;
1436	2c0262af	bellard	must_add_seg = s->addseg;
1437	2c0262af	bellard	if (override >= 0)
1438	2c0262af	bellard	must_add_seg = 1;
1439	2c0262af	bellard	mod = (modrm >> 6) & 3;
1440	2c0262af	bellard	rm = modrm & 7;
1441	2c0262af	bellard
1442	2c0262af	bellard	if (s->aflag) {
1443	2c0262af	bellard
1444	2c0262af	bellard	havesib = 0;
1445	2c0262af	bellard	base = rm;
1446	2c0262af	bellard	index = 0;
1447	2c0262af	bellard	scale = 0;
1448	2c0262af	bellard
1449	2c0262af	bellard	if (base == 4) {
1450	2c0262af	bellard	havesib = 1;
1451	61382a50	bellard	code = ldub_code(s->pc++);
1452	2c0262af	bellard	scale = (code >> 6) & 3;
1453	14ce26e7	bellard	index = ((code >> 3) & 7) \| REX_X(s);
1454	14ce26e7	bellard	base = (code & 7);
1455	2c0262af	bellard	}
1456	14ce26e7	bellard	base \|= REX_B(s);
1457	2c0262af	bellard
1458	2c0262af	bellard	switch (mod) {
1459	2c0262af	bellard	case 0:
1460	14ce26e7	bellard	if ((base & 7) == 5) {
1461	2c0262af	bellard	base = -1;
1462	14ce26e7	bellard	disp = (int32_t)ldl_code(s->pc);
1463	2c0262af	bellard	s->pc += 4;
1464	14ce26e7	bellard	if (CODE64(s) && !havesib) {
1465	14ce26e7	bellard	disp += s->pc + s->rip_offset;
1466	14ce26e7	bellard	}
1467	2c0262af	bellard	} else {
1468	2c0262af	bellard	disp = 0;
1469	2c0262af	bellard	}
1470	2c0262af	bellard	break;
1471	2c0262af	bellard	case 1:
1472	61382a50	bellard	disp = (int8_t)ldub_code(s->pc++);
1473	2c0262af	bellard	break;
1474	2c0262af	bellard	default:
1475	2c0262af	bellard	case 2:
1476	61382a50	bellard	disp = ldl_code(s->pc);
1477	2c0262af	bellard	s->pc += 4;
1478	2c0262af	bellard	break;
1479	2c0262af	bellard	}
1480	2c0262af	bellard
1481	2c0262af	bellard	if (base >= 0) {
1482	2c0262af	bellard	/* for correct popl handling with esp */
1483	2c0262af	bellard	if (base == 4 && s->popl_esp_hack)
1484	2c0262af	bellard	disp += s->popl_esp_hack;
1485	14ce26e7	bellard	#ifdef TARGET_X86_64
1486	14ce26e7	bellard	if (s->aflag == 2) {
1487	14ce26e7	bellard	gen_op_movq_A0_reg[base]();
1488	14ce26e7	bellard	if (disp != 0) {
1489	14ce26e7	bellard	if ((int32_t)disp == disp)
1490	14ce26e7	bellard	gen_op_addq_A0_im(disp);
1491	14ce26e7	bellard	else
1492	14ce26e7	bellard	gen_op_addq_A0_im64(disp >> 32, disp);
1493	14ce26e7	bellard	}
1494	14ce26e7	bellard	} else
1495	14ce26e7	bellard	#endif
1496	14ce26e7	bellard	{
1497	14ce26e7	bellard	gen_op_movl_A0_reg[base]();
1498	14ce26e7	bellard	if (disp != 0)
1499	14ce26e7	bellard	gen_op_addl_A0_im(disp);
1500	14ce26e7	bellard	}
1501	2c0262af	bellard	} else {
1502	14ce26e7	bellard	#ifdef TARGET_X86_64
1503	14ce26e7	bellard	if (s->aflag == 2) {
1504	14ce26e7	bellard	if ((int32_t)disp == disp)
1505	14ce26e7	bellard	gen_op_movq_A0_im(disp);
1506	14ce26e7	bellard	else
1507	14ce26e7	bellard	gen_op_movq_A0_im64(disp >> 32, disp);
1508	14ce26e7	bellard	} else
1509	14ce26e7	bellard	#endif
1510	14ce26e7	bellard	{
1511	14ce26e7	bellard	gen_op_movl_A0_im(disp);
1512	14ce26e7	bellard	}
1513	2c0262af	bellard	}
1514	2c0262af	bellard	/* XXX: index == 4 is always invalid */
1515	2c0262af	bellard	if (havesib && (index != 4 \|\| scale != 0)) {
1516	14ce26e7	bellard	#ifdef TARGET_X86_64
1517	14ce26e7	bellard	if (s->aflag == 2) {
1518	14ce26e7	bellard	gen_op_addq_A0_reg_sN[scale][index]();
1519	14ce26e7	bellard	} else
1520	14ce26e7	bellard	#endif
1521	14ce26e7	bellard	{
1522	14ce26e7	bellard	gen_op_addl_A0_reg_sN[scale][index]();
1523	14ce26e7	bellard	}
1524	2c0262af	bellard	}
1525	2c0262af	bellard	if (must_add_seg) {
1526	2c0262af	bellard	if (override < 0) {
1527	2c0262af	bellard	if (base == R_EBP \|\| base == R_ESP)
1528	2c0262af	bellard	override = R_SS;
1529	2c0262af	bellard	else
1530	2c0262af	bellard	override = R_DS;
1531	2c0262af	bellard	}
1532	14ce26e7	bellard	#ifdef TARGET_X86_64
1533	14ce26e7	bellard	if (s->aflag == 2) {
1534	14ce26e7	bellard	gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
1535	14ce26e7	bellard	} else
1536	14ce26e7	bellard	#endif
1537	14ce26e7	bellard	{
1538	14ce26e7	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1539	14ce26e7	bellard	}
1540	2c0262af	bellard	}
1541	2c0262af	bellard	} else {
1542	2c0262af	bellard	switch (mod) {
1543	2c0262af	bellard	case 0:
1544	2c0262af	bellard	if (rm == 6) {
1545	61382a50	bellard	disp = lduw_code(s->pc);
1546	2c0262af	bellard	s->pc += 2;
1547	2c0262af	bellard	gen_op_movl_A0_im(disp);
1548	2c0262af	bellard	rm = 0; /* avoid SS override */
1549	2c0262af	bellard	goto no_rm;
1550	2c0262af	bellard	} else {
1551	2c0262af	bellard	disp = 0;
1552	2c0262af	bellard	}
1553	2c0262af	bellard	break;
1554	2c0262af	bellard	case 1:
1555	61382a50	bellard	disp = (int8_t)ldub_code(s->pc++);
1556	2c0262af	bellard	break;
1557	2c0262af	bellard	default:
1558	2c0262af	bellard	case 2:
1559	61382a50	bellard	disp = lduw_code(s->pc);
1560	2c0262af	bellard	s->pc += 2;
1561	2c0262af	bellard	break;
1562	2c0262af	bellard	}
1563	2c0262af	bellard	switch(rm) {
1564	2c0262af	bellard	case 0:
1565	2c0262af	bellard	gen_op_movl_A0_reg[R_EBX]();
1566	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_ESI]();
1567	2c0262af	bellard	break;
1568	2c0262af	bellard	case 1:
1569	2c0262af	bellard	gen_op_movl_A0_reg[R_EBX]();
1570	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_EDI]();
1571	2c0262af	bellard	break;
1572	2c0262af	bellard	case 2:
1573	2c0262af	bellard	gen_op_movl_A0_reg[R_EBP]();
1574	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_ESI]();
1575	2c0262af	bellard	break;
1576	2c0262af	bellard	case 3:
1577	2c0262af	bellard	gen_op_movl_A0_reg[R_EBP]();
1578	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_EDI]();
1579	2c0262af	bellard	break;
1580	2c0262af	bellard	case 4:
1581	2c0262af	bellard	gen_op_movl_A0_reg[R_ESI]();
1582	2c0262af	bellard	break;
1583	2c0262af	bellard	case 5:
1584	2c0262af	bellard	gen_op_movl_A0_reg[R_EDI]();
1585	2c0262af	bellard	break;
1586	2c0262af	bellard	case 6:
1587	2c0262af	bellard	gen_op_movl_A0_reg[R_EBP]();
1588	2c0262af	bellard	break;
1589	2c0262af	bellard	default:
1590	2c0262af	bellard	case 7:
1591	2c0262af	bellard	gen_op_movl_A0_reg[R_EBX]();
1592	2c0262af	bellard	break;
1593	2c0262af	bellard	}
1594	2c0262af	bellard	if (disp != 0)
1595	2c0262af	bellard	gen_op_addl_A0_im(disp);
1596	2c0262af	bellard	gen_op_andl_A0_ffff();
1597	2c0262af	bellard	no_rm:
1598	2c0262af	bellard	if (must_add_seg) {
1599	2c0262af	bellard	if (override < 0) {
1600	2c0262af	bellard	if (rm == 2 \|\| rm == 3 \|\| rm == 6)
1601	2c0262af	bellard	override = R_SS;
1602	2c0262af	bellard	else
1603	2c0262af	bellard	override = R_DS;
1604	2c0262af	bellard	}
1605	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1606	2c0262af	bellard	}
1607	2c0262af	bellard	}
1608	2c0262af	bellard
1609	2c0262af	bellard	opreg = OR_A0;
1610	2c0262af	bellard	disp = 0;
1611	2c0262af	bellard	*reg_ptr = opreg;
1612	2c0262af	bellard	*offset_ptr = disp;
1613	2c0262af	bellard	}
1614	2c0262af	bellard
1615	664e0f19	bellard	/* used for LEA and MOV AX, mem */
1616	664e0f19	bellard	static void gen_add_A0_ds_seg(DisasContext *s)
1617	664e0f19	bellard	{
1618	664e0f19	bellard	int override, must_add_seg;
1619	664e0f19	bellard	must_add_seg = s->addseg;
1620	664e0f19	bellard	override = R_DS;
1621	664e0f19	bellard	if (s->override >= 0) {
1622	664e0f19	bellard	override = s->override;
1623	664e0f19	bellard	must_add_seg = 1;
1624	664e0f19	bellard	} else {
1625	664e0f19	bellard	override = R_DS;
1626	664e0f19	bellard	}
1627	664e0f19	bellard	if (must_add_seg) {
1628	664e0f19	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1629	664e0f19	bellard	}
1630	664e0f19	bellard	}
1631	664e0f19	bellard
1632	2c0262af	bellard	/* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1633	2c0262af	bellard	OR_TMP0 */
1634	2c0262af	bellard	static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1635	2c0262af	bellard	{
1636	2c0262af	bellard	int mod, rm, opreg, disp;
1637	2c0262af	bellard
1638	2c0262af	bellard	mod = (modrm >> 6) & 3;
1639	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
1640	2c0262af	bellard	if (mod == 3) {
1641	2c0262af	bellard	if (is_store) {
1642	2c0262af	bellard	if (reg != OR_TMP0)
1643	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
1644	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
1645	2c0262af	bellard	} else {
1646	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
1647	2c0262af	bellard	if (reg != OR_TMP0)
1648	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
1649	2c0262af	bellard	}
1650	2c0262af	bellard	} else {
1651	2c0262af	bellard	gen_lea_modrm(s, modrm, &opreg, &disp);
1652	2c0262af	bellard	if (is_store) {
1653	2c0262af	bellard	if (reg != OR_TMP0)
1654	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
1655	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1656	2c0262af	bellard	} else {
1657	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1658	2c0262af	bellard	if (reg != OR_TMP0)
1659	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
1660	2c0262af	bellard	}
1661	2c0262af	bellard	}
1662	2c0262af	bellard	}
1663	2c0262af	bellard
1664	2c0262af	bellard	static inline uint32_t insn_get(DisasContext *s, int ot)
1665	2c0262af	bellard	{
1666	2c0262af	bellard	uint32_t ret;
1667	2c0262af	bellard
1668	2c0262af	bellard	switch(ot) {
1669	2c0262af	bellard	case OT_BYTE:
1670	61382a50	bellard	ret = ldub_code(s->pc);
1671	2c0262af	bellard	s->pc++;
1672	2c0262af	bellard	break;
1673	2c0262af	bellard	case OT_WORD:
1674	61382a50	bellard	ret = lduw_code(s->pc);
1675	2c0262af	bellard	s->pc += 2;
1676	2c0262af	bellard	break;
1677	2c0262af	bellard	default:
1678	2c0262af	bellard	case OT_LONG:
1679	61382a50	bellard	ret = ldl_code(s->pc);
1680	2c0262af	bellard	s->pc += 4;
1681	2c0262af	bellard	break;
1682	2c0262af	bellard	}
1683	2c0262af	bellard	return ret;
1684	2c0262af	bellard	}
1685	2c0262af	bellard
1686	14ce26e7	bellard	static inline int insn_const_size(unsigned int ot)
1687	14ce26e7	bellard	{
1688	14ce26e7	bellard	if (ot <= OT_LONG)
1689	14ce26e7	bellard	return 1 << ot;
1690	14ce26e7	bellard	else
1691	14ce26e7	bellard	return 4;
1692	14ce26e7	bellard	}
1693	14ce26e7	bellard
1694	14ce26e7	bellard	static inline void gen_jcc(DisasContext *s, int b,
1695	14ce26e7	bellard	target_ulong val, target_ulong next_eip)
1696	2c0262af	bellard	{
1697	2c0262af	bellard	TranslationBlock *tb;
1698	2c0262af	bellard	int inv, jcc_op;
1699	14ce26e7	bellard	GenOpFunc1 *func;
1700	14ce26e7	bellard	target_ulong tmp;
1701	14ce26e7	bellard	int l1, l2;
1702	2c0262af	bellard
1703	2c0262af	bellard	inv = b & 1;
1704	2c0262af	bellard	jcc_op = (b >> 1) & 7;
1705	2c0262af	bellard
1706	2c0262af	bellard	if (s->jmp_opt) {
1707	2c0262af	bellard	switch(s->cc_op) {
1708	2c0262af	bellard	/* we optimize the cmp/jcc case */
1709	2c0262af	bellard	case CC_OP_SUBB:
1710	2c0262af	bellard	case CC_OP_SUBW:
1711	2c0262af	bellard	case CC_OP_SUBL:
1712	14ce26e7	bellard	case CC_OP_SUBQ:
1713	2c0262af	bellard	func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1714	2c0262af	bellard	break;
1715	2c0262af	bellard
1716	2c0262af	bellard	/* some jumps are easy to compute */
1717	2c0262af	bellard	case CC_OP_ADDB:
1718	2c0262af	bellard	case CC_OP_ADDW:
1719	2c0262af	bellard	case CC_OP_ADDL:
1720	14ce26e7	bellard	case CC_OP_ADDQ:
1721	14ce26e7	bellard
1722	2c0262af	bellard	case CC_OP_ADCB:
1723	2c0262af	bellard	case CC_OP_ADCW:
1724	2c0262af	bellard	case CC_OP_ADCL:
1725	14ce26e7	bellard	case CC_OP_ADCQ:
1726	14ce26e7	bellard
1727	2c0262af	bellard	case CC_OP_SBBB:
1728	2c0262af	bellard	case CC_OP_SBBW:
1729	2c0262af	bellard	case CC_OP_SBBL:
1730	14ce26e7	bellard	case CC_OP_SBBQ:
1731	14ce26e7	bellard
1732	2c0262af	bellard	case CC_OP_LOGICB:
1733	2c0262af	bellard	case CC_OP_LOGICW:
1734	2c0262af	bellard	case CC_OP_LOGICL:
1735	14ce26e7	bellard	case CC_OP_LOGICQ:
1736	14ce26e7	bellard
1737	2c0262af	bellard	case CC_OP_INCB:
1738	2c0262af	bellard	case CC_OP_INCW:
1739	2c0262af	bellard	case CC_OP_INCL:
1740	14ce26e7	bellard	case CC_OP_INCQ:
1741	14ce26e7	bellard
1742	2c0262af	bellard	case CC_OP_DECB:
1743	2c0262af	bellard	case CC_OP_DECW:
1744	2c0262af	bellard	case CC_OP_DECL:
1745	14ce26e7	bellard	case CC_OP_DECQ:
1746	14ce26e7	bellard
1747	2c0262af	bellard	case CC_OP_SHLB:
1748	2c0262af	bellard	case CC_OP_SHLW:
1749	2c0262af	bellard	case CC_OP_SHLL:
1750	14ce26e7	bellard	case CC_OP_SHLQ:
1751	14ce26e7	bellard
1752	2c0262af	bellard	case CC_OP_SARB:
1753	2c0262af	bellard	case CC_OP_SARW:
1754	2c0262af	bellard	case CC_OP_SARL:
1755	14ce26e7	bellard	case CC_OP_SARQ:
1756	2c0262af	bellard	switch(jcc_op) {
1757	2c0262af	bellard	case JCC_Z:
1758	14ce26e7	bellard	func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1759	2c0262af	bellard	break;
1760	2c0262af	bellard	case JCC_S:
1761	14ce26e7	bellard	func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1762	2c0262af	bellard	break;
1763	2c0262af	bellard	default:
1764	2c0262af	bellard	func = NULL;
1765	2c0262af	bellard	break;
1766	2c0262af	bellard	}
1767	2c0262af	bellard	break;
1768	2c0262af	bellard	default:
1769	2c0262af	bellard	func = NULL;
1770	2c0262af	bellard	break;
1771	2c0262af	bellard	}
1772	2c0262af	bellard
1773	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
1774	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
1775	2c0262af	bellard
1776	2c0262af	bellard	if (!func) {
1777	2c0262af	bellard	gen_setcc_slow[jcc_op]();
1778	14ce26e7	bellard	func = gen_op_jnz_T0_label;
1779	2c0262af	bellard	}
1780	2c0262af	bellard
1781	14ce26e7	bellard	if (inv) {
1782	14ce26e7	bellard	tmp = val;
1783	14ce26e7	bellard	val = next_eip;
1784	14ce26e7	bellard	next_eip = tmp;
1785	2c0262af	bellard	}
1786	14ce26e7	bellard	tb = s->tb;
1787	14ce26e7	bellard
1788	14ce26e7	bellard	l1 = gen_new_label();
1789	14ce26e7	bellard	func(l1);
1790	14ce26e7	bellard
1791	ae063a68	bellard	gen_op_goto_tb0(TBPARAM(tb));
1792	14ce26e7	bellard	gen_jmp_im(next_eip);
1793	14ce26e7	bellard	gen_op_movl_T0_im((long)tb + 0);
1794	14ce26e7	bellard	gen_op_exit_tb();
1795	14ce26e7	bellard
1796	14ce26e7	bellard	gen_set_label(l1);
1797	ae063a68	bellard	gen_op_goto_tb1(TBPARAM(tb));
1798	14ce26e7	bellard	gen_jmp_im(val);
1799	14ce26e7	bellard	gen_op_movl_T0_im((long)tb + 1);
1800	14ce26e7	bellard	gen_op_exit_tb();
1801	14ce26e7	bellard
1802	2c0262af	bellard	s->is_jmp = 3;
1803	2c0262af	bellard	} else {
1804	14ce26e7	bellard
1805	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
1806	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
1807	2c0262af	bellard	s->cc_op = CC_OP_DYNAMIC;
1808	2c0262af	bellard	}
1809	2c0262af	bellard	gen_setcc_slow[jcc_op]();
1810	14ce26e7	bellard	if (inv) {
1811	14ce26e7	bellard	tmp = val;
1812	14ce26e7	bellard	val = next_eip;
1813	14ce26e7	bellard	next_eip = tmp;
1814	2c0262af	bellard	}
1815	14ce26e7	bellard	l1 = gen_new_label();
1816	14ce26e7	bellard	l2 = gen_new_label();
1817	14ce26e7	bellard	gen_op_jnz_T0_label(l1);
1818	14ce26e7	bellard	gen_jmp_im(next_eip);
1819	14ce26e7	bellard	gen_op_jmp_label(l2);
1820	14ce26e7	bellard	gen_set_label(l1);
1821	14ce26e7	bellard	gen_jmp_im(val);
1822	14ce26e7	bellard	gen_set_label(l2);
1823	2c0262af	bellard	gen_eob(s);
1824	2c0262af	bellard	}
1825	2c0262af	bellard	}
1826	2c0262af	bellard
1827	2c0262af	bellard	static void gen_setcc(DisasContext *s, int b)
1828	2c0262af	bellard	{
1829	2c0262af	bellard	int inv, jcc_op;
1830	2c0262af	bellard	GenOpFunc *func;
1831	2c0262af	bellard
1832	2c0262af	bellard	inv = b & 1;
1833	2c0262af	bellard	jcc_op = (b >> 1) & 7;
1834	2c0262af	bellard	switch(s->cc_op) {
1835	2c0262af	bellard	/* we optimize the cmp/jcc case */
1836	2c0262af	bellard	case CC_OP_SUBB:
1837	2c0262af	bellard	case CC_OP_SUBW:
1838	2c0262af	bellard	case CC_OP_SUBL:
1839	14ce26e7	bellard	case CC_OP_SUBQ:
1840	2c0262af	bellard	func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1841	2c0262af	bellard	if (!func)
1842	2c0262af	bellard	goto slow_jcc;
1843	2c0262af	bellard	break;
1844	2c0262af	bellard
1845	2c0262af	bellard	/* some jumps are easy to compute */
1846	2c0262af	bellard	case CC_OP_ADDB:
1847	2c0262af	bellard	case CC_OP_ADDW:
1848	2c0262af	bellard	case CC_OP_ADDL:
1849	14ce26e7	bellard	case CC_OP_ADDQ:
1850	14ce26e7	bellard
1851	2c0262af	bellard	case CC_OP_LOGICB:
1852	2c0262af	bellard	case CC_OP_LOGICW:
1853	2c0262af	bellard	case CC_OP_LOGICL:
1854	14ce26e7	bellard	case CC_OP_LOGICQ:
1855	14ce26e7	bellard
1856	2c0262af	bellard	case CC_OP_INCB:
1857	2c0262af	bellard	case CC_OP_INCW:
1858	2c0262af	bellard	case CC_OP_INCL:
1859	14ce26e7	bellard	case CC_OP_INCQ:
1860	14ce26e7	bellard
1861	2c0262af	bellard	case CC_OP_DECB:
1862	2c0262af	bellard	case CC_OP_DECW:
1863	2c0262af	bellard	case CC_OP_DECL:
1864	14ce26e7	bellard	case CC_OP_DECQ:
1865	14ce26e7	bellard
1866	2c0262af	bellard	case CC_OP_SHLB:
1867	2c0262af	bellard	case CC_OP_SHLW:
1868	2c0262af	bellard	case CC_OP_SHLL:
1869	14ce26e7	bellard	case CC_OP_SHLQ:
1870	2c0262af	bellard	switch(jcc_op) {
1871	2c0262af	bellard	case JCC_Z:
1872	14ce26e7	bellard	func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1873	2c0262af	bellard	break;
1874	2c0262af	bellard	case JCC_S:
1875	14ce26e7	bellard	func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1876	2c0262af	bellard	break;
1877	2c0262af	bellard	default:
1878	2c0262af	bellard	goto slow_jcc;
1879	2c0262af	bellard	}
1880	2c0262af	bellard	break;
1881	2c0262af	bellard	default:
1882	2c0262af	bellard	slow_jcc:
1883	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
1884	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
1885	2c0262af	bellard	func = gen_setcc_slow[jcc_op];
1886	2c0262af	bellard	break;
1887	2c0262af	bellard	}
1888	2c0262af	bellard	func();
1889	2c0262af	bellard	if (inv) {
1890	2c0262af	bellard	gen_op_xor_T0_1();
1891	2c0262af	bellard	}
1892	2c0262af	bellard	}
1893	2c0262af	bellard
1894	2c0262af	bellard	/* move T0 to seg_reg and compute if the CPU state may change. Never
1895	2c0262af	bellard	call this function with seg_reg == R_CS */
1896	14ce26e7	bellard	static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
1897	2c0262af	bellard	{
1898	3415a4dd	bellard	if (s->pe && !s->vm86) {
1899	3415a4dd	bellard	/* XXX: optimize by finding processor state dynamically */
1900	3415a4dd	bellard	if (s->cc_op != CC_OP_DYNAMIC)
1901	3415a4dd	bellard	gen_op_set_cc_op(s->cc_op);
1902	14ce26e7	bellard	gen_jmp_im(cur_eip);
1903	3415a4dd	bellard	gen_op_movl_seg_T0(seg_reg);
1904	dc196a57	bellard	/* abort translation because the addseg value may change or
1905	dc196a57	bellard	because ss32 may change. For R_SS, translation must always
1906	dc196a57	bellard	stop as a special handling must be done to disable hardware
1907	dc196a57	bellard	interrupts for the next instruction */
1908	dc196a57	bellard	if (seg_reg == R_SS \|\| (s->code32 && seg_reg < R_FS))
1909	dc196a57	bellard	s->is_jmp = 3;
1910	3415a4dd	bellard	} else {
1911	2c0262af	bellard	gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
1912	dc196a57	bellard	if (seg_reg == R_SS)
1913	dc196a57	bellard	s->is_jmp = 3;
1914	3415a4dd	bellard	}
1915	2c0262af	bellard	}
1916	2c0262af	bellard
1917	4f31916f	bellard	static inline void gen_stack_update(DisasContext *s, int addend)
1918	4f31916f	bellard	{
1919	14ce26e7	bellard	#ifdef TARGET_X86_64
1920	14ce26e7	bellard	if (CODE64(s)) {
1921	14ce26e7	bellard	if (addend == 8)
1922	14ce26e7	bellard	gen_op_addq_ESP_8();
1923	14ce26e7	bellard	else
1924	14ce26e7	bellard	gen_op_addq_ESP_im(addend);
1925	14ce26e7	bellard	} else
1926	14ce26e7	bellard	#endif
1927	4f31916f	bellard	if (s->ss32) {
1928	4f31916f	bellard	if (addend == 2)
1929	4f31916f	bellard	gen_op_addl_ESP_2();
1930	4f31916f	bellard	else if (addend == 4)
1931	4f31916f	bellard	gen_op_addl_ESP_4();
1932	4f31916f	bellard	else
1933	4f31916f	bellard	gen_op_addl_ESP_im(addend);
1934	4f31916f	bellard	} else {
1935	4f31916f	bellard	if (addend == 2)
1936	4f31916f	bellard	gen_op_addw_ESP_2();
1937	4f31916f	bellard	else if (addend == 4)
1938	4f31916f	bellard	gen_op_addw_ESP_4();
1939	4f31916f	bellard	else
1940	4f31916f	bellard	gen_op_addw_ESP_im(addend);
1941	4f31916f	bellard	}
1942	4f31916f	bellard	}
1943	4f31916f	bellard
1944	2c0262af	bellard	/* generate a push. It depends on ss32, addseg and dflag */
1945	2c0262af	bellard	static void gen_push_T0(DisasContext *s)
1946	2c0262af	bellard	{
1947	14ce26e7	bellard	#ifdef TARGET_X86_64
1948	14ce26e7	bellard	if (CODE64(s)) {
1949	14ce26e7	bellard	/* XXX: check 16 bit behaviour */
1950	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESP]();
1951	14ce26e7	bellard	gen_op_subq_A0_8();
1952	14ce26e7	bellard	gen_op_st_T0_A0[OT_QUAD + s->mem_index]();
1953	14ce26e7	bellard	gen_op_movq_ESP_A0();
1954	14ce26e7	bellard	} else
1955	14ce26e7	bellard	#endif
1956	14ce26e7	bellard	{
1957	14ce26e7	bellard	gen_op_movl_A0_reg[R_ESP]();
1958	14ce26e7	bellard	if (!s->dflag)
1959	14ce26e7	bellard	gen_op_subl_A0_2();
1960	14ce26e7	bellard	else
1961	14ce26e7	bellard	gen_op_subl_A0_4();
1962	14ce26e7	bellard	if (s->ss32) {
1963	14ce26e7	bellard	if (s->addseg) {
1964	14ce26e7	bellard	gen_op_movl_T1_A0();
1965	14ce26e7	bellard	gen_op_addl_A0_SS();
1966	14ce26e7	bellard	}
1967	14ce26e7	bellard	} else {
1968	14ce26e7	bellard	gen_op_andl_A0_ffff();
1969	4f31916f	bellard	gen_op_movl_T1_A0();
1970	4f31916f	bellard	gen_op_addl_A0_SS();
1971	2c0262af	bellard	}
1972	14ce26e7	bellard	gen_op_st_T0_A0[s->dflag + 1 + s->mem_index]();
1973	14ce26e7	bellard	if (s->ss32 && !s->addseg)
1974	14ce26e7	bellard	gen_op_movl_ESP_A0();
1975	14ce26e7	bellard	else
1976	14ce26e7	bellard	gen_op_mov_reg_T1[s->ss32 + 1][R_ESP]();
1977	2c0262af	bellard	}
1978	2c0262af	bellard	}
1979	2c0262af	bellard
1980	4f31916f	bellard	/* generate a push. It depends on ss32, addseg and dflag */
1981	4f31916f	bellard	/* slower version for T1, only used for call Ev */
1982	4f31916f	bellard	static void gen_push_T1(DisasContext *s)
1983	2c0262af	bellard	{
1984	14ce26e7	bellard	#ifdef TARGET_X86_64
1985	14ce26e7	bellard	if (CODE64(s)) {
1986	14ce26e7	bellard	/* XXX: check 16 bit behaviour */
1987	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESP]();
1988	14ce26e7	bellard	gen_op_subq_A0_8();
1989	14ce26e7	bellard	gen_op_st_T1_A0[OT_QUAD + s->mem_index]();
1990	14ce26e7	bellard	gen_op_movq_ESP_A0();
1991	14ce26e7	bellard	} else
1992	14ce26e7	bellard	#endif
1993	14ce26e7	bellard	{
1994	14ce26e7	bellard	gen_op_movl_A0_reg[R_ESP]();
1995	14ce26e7	bellard	if (!s->dflag)
1996	14ce26e7	bellard	gen_op_subl_A0_2();
1997	14ce26e7	bellard	else
1998	14ce26e7	bellard	gen_op_subl_A0_4();
1999	14ce26e7	bellard	if (s->ss32) {
2000	14ce26e7	bellard	if (s->addseg) {
2001	14ce26e7	bellard	gen_op_addl_A0_SS();
2002	14ce26e7	bellard	}
2003	14ce26e7	bellard	} else {
2004	14ce26e7	bellard	gen_op_andl_A0_ffff();
2005	4f31916f	bellard	gen_op_addl_A0_SS();
2006	2c0262af	bellard	}
2007	14ce26e7	bellard	gen_op_st_T1_A0[s->dflag + 1 + s->mem_index]();
2008	14ce26e7	bellard
2009	14ce26e7	bellard	if (s->ss32 && !s->addseg)
2010	14ce26e7	bellard	gen_op_movl_ESP_A0();
2011	14ce26e7	bellard	else
2012	14ce26e7	bellard	gen_stack_update(s, (-2) << s->dflag);
2013	2c0262af	bellard	}
2014	2c0262af	bellard	}
2015	2c0262af	bellard
2016	4f31916f	bellard	/* two step pop is necessary for precise exceptions */
2017	4f31916f	bellard	static void gen_pop_T0(DisasContext *s)
2018	2c0262af	bellard	{
2019	14ce26e7	bellard	#ifdef TARGET_X86_64
2020	14ce26e7	bellard	if (CODE64(s)) {
2021	14ce26e7	bellard	/* XXX: check 16 bit behaviour */
2022	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESP]();
2023	14ce26e7	bellard	gen_op_ld_T0_A0[OT_QUAD + s->mem_index]();
2024	14ce26e7	bellard	} else
2025	14ce26e7	bellard	#endif
2026	14ce26e7	bellard	{
2027	14ce26e7	bellard	gen_op_movl_A0_reg[R_ESP]();
2028	14ce26e7	bellard	if (s->ss32) {
2029	14ce26e7	bellard	if (s->addseg)
2030	14ce26e7	bellard	gen_op_addl_A0_SS();
2031	14ce26e7	bellard	} else {
2032	14ce26e7	bellard	gen_op_andl_A0_ffff();
2033	4f31916f	bellard	gen_op_addl_A0_SS();
2034	14ce26e7	bellard	}
2035	14ce26e7	bellard	gen_op_ld_T0_A0[s->dflag + 1 + s->mem_index]();
2036	2c0262af	bellard	}
2037	2c0262af	bellard	}
2038	2c0262af	bellard
2039	2c0262af	bellard	static void gen_pop_update(DisasContext *s)
2040	2c0262af	bellard	{
2041	14ce26e7	bellard	#ifdef TARGET_X86_64
2042	14ce26e7	bellard	if (CODE64(s)) {
2043	14ce26e7	bellard	gen_stack_update(s, 8);
2044	14ce26e7	bellard	} else
2045	14ce26e7	bellard	#endif
2046	14ce26e7	bellard	{
2047	14ce26e7	bellard	gen_stack_update(s, 2 << s->dflag);
2048	14ce26e7	bellard	}
2049	2c0262af	bellard	}
2050	2c0262af	bellard
2051	2c0262af	bellard	static void gen_stack_A0(DisasContext *s)
2052	2c0262af	bellard	{
2053	2c0262af	bellard	gen_op_movl_A0_ESP();
2054	2c0262af	bellard	if (!s->ss32)
2055	2c0262af	bellard	gen_op_andl_A0_ffff();
2056	2c0262af	bellard	gen_op_movl_T1_A0();
2057	2c0262af	bellard	if (s->addseg)
2058	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2059	2c0262af	bellard	}
2060	2c0262af	bellard
2061	2c0262af	bellard	/* NOTE: wrap around in 16 bit not fully handled */
2062	2c0262af	bellard	static void gen_pusha(DisasContext *s)
2063	2c0262af	bellard	{
2064	2c0262af	bellard	int i;
2065	2c0262af	bellard	gen_op_movl_A0_ESP();
2066	2c0262af	bellard	gen_op_addl_A0_im(-16 << s->dflag);
2067	2c0262af	bellard	if (!s->ss32)
2068	2c0262af	bellard	gen_op_andl_A0_ffff();
2069	2c0262af	bellard	gen_op_movl_T1_A0();
2070	2c0262af	bellard	if (s->addseg)
2071	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2072	2c0262af	bellard	for(i = 0;i < 8; i++) {
2073	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
2074	2c0262af	bellard	gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
2075	2c0262af	bellard	gen_op_addl_A0_im(2 << s->dflag);
2076	2c0262af	bellard	}
2077	90f11f95	bellard	gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2078	2c0262af	bellard	}
2079	2c0262af	bellard
2080	2c0262af	bellard	/* NOTE: wrap around in 16 bit not fully handled */
2081	2c0262af	bellard	static void gen_popa(DisasContext *s)
2082	2c0262af	bellard	{
2083	2c0262af	bellard	int i;
2084	2c0262af	bellard	gen_op_movl_A0_ESP();
2085	2c0262af	bellard	if (!s->ss32)
2086	2c0262af	bellard	gen_op_andl_A0_ffff();
2087	2c0262af	bellard	gen_op_movl_T1_A0();
2088	2c0262af	bellard	gen_op_addl_T1_im(16 << s->dflag);
2089	2c0262af	bellard	if (s->addseg)
2090	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2091	2c0262af	bellard	for(i = 0;i < 8; i++) {
2092	2c0262af	bellard	/* ESP is not reloaded */
2093	2c0262af	bellard	if (i != 3) {
2094	2c0262af	bellard	gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
2095	2c0262af	bellard	gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
2096	2c0262af	bellard	}
2097	2c0262af	bellard	gen_op_addl_A0_im(2 << s->dflag);
2098	2c0262af	bellard	}
2099	90f11f95	bellard	gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2100	2c0262af	bellard	}
2101	2c0262af	bellard
2102	2c0262af	bellard	static void gen_enter(DisasContext *s, int esp_addend, int level)
2103	2c0262af	bellard	{
2104	61a8c4ec	bellard	int ot, opsize;
2105	2c0262af	bellard
2106	2c0262af	bellard	ot = s->dflag + OT_WORD;
2107	2c0262af	bellard	level &= 0x1f;
2108	2c0262af	bellard	opsize = 2 << s->dflag;
2109	2c0262af	bellard
2110	2c0262af	bellard	gen_op_movl_A0_ESP();
2111	2c0262af	bellard	gen_op_addl_A0_im(-opsize);
2112	2c0262af	bellard	if (!s->ss32)
2113	2c0262af	bellard	gen_op_andl_A0_ffff();
2114	2c0262af	bellard	gen_op_movl_T1_A0();
2115	2c0262af	bellard	if (s->addseg)
2116	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2117	2c0262af	bellard	/* push bp */
2118	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2119	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
2120	2c0262af	bellard	if (level) {
2121	61a8c4ec	bellard	gen_op_enter_level(level, s->dflag);
2122	2c0262af	bellard	}
2123	2c0262af	bellard	gen_op_mov_reg_T1[ot][R_EBP]();
2124	61a8c4ec	bellard	gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2125	90f11f95	bellard	gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2126	2c0262af	bellard	}
2127	2c0262af	bellard
2128	14ce26e7	bellard	static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2129	2c0262af	bellard	{
2130	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2131	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2132	14ce26e7	bellard	gen_jmp_im(cur_eip);
2133	2c0262af	bellard	gen_op_raise_exception(trapno);
2134	2c0262af	bellard	s->is_jmp = 3;
2135	2c0262af	bellard	}
2136	2c0262af	bellard
2137	2c0262af	bellard	/* an interrupt is different from an exception because of the
2138	2c0262af	bellard	priviledge checks */
2139	2c0262af	bellard	static void gen_interrupt(DisasContext *s, int intno,
2140	14ce26e7	bellard	target_ulong cur_eip, target_ulong next_eip)
2141	2c0262af	bellard	{
2142	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2143	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2144	14ce26e7	bellard	gen_jmp_im(cur_eip);
2145	a8ede8ba	bellard	gen_op_raise_interrupt(intno, (int)(next_eip - cur_eip));
2146	2c0262af	bellard	s->is_jmp = 3;
2147	2c0262af	bellard	}
2148	2c0262af	bellard
2149	14ce26e7	bellard	static void gen_debug(DisasContext *s, target_ulong cur_eip)
2150	2c0262af	bellard	{
2151	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2152	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2153	14ce26e7	bellard	gen_jmp_im(cur_eip);
2154	2c0262af	bellard	gen_op_debug();
2155	2c0262af	bellard	s->is_jmp = 3;
2156	2c0262af	bellard	}
2157	2c0262af	bellard
2158	2c0262af	bellard	/* generate a generic end of block. Trace exception is also generated
2159	2c0262af	bellard	if needed */
2160	2c0262af	bellard	static void gen_eob(DisasContext *s)
2161	2c0262af	bellard	{
2162	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2163	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2164	a2cc3b24	bellard	if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2165	a2cc3b24	bellard	gen_op_reset_inhibit_irq();
2166	a2cc3b24	bellard	}
2167	34865134	bellard	if (s->singlestep_enabled) {
2168	34865134	bellard	gen_op_debug();
2169	34865134	bellard	} else if (s->tf) {
2170	2c0262af	bellard	gen_op_raise_exception(EXCP01_SSTP);
2171	2c0262af	bellard	} else {
2172	2c0262af	bellard	gen_op_movl_T0_0();
2173	2c0262af	bellard	gen_op_exit_tb();
2174	2c0262af	bellard	}
2175	2c0262af	bellard	s->is_jmp = 3;
2176	2c0262af	bellard	}
2177	2c0262af	bellard
2178	2c0262af	bellard	/* generate a jump to eip. No segment change must happen before as a
2179	2c0262af	bellard	direct call to the next block may occur */
2180	14ce26e7	bellard	static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2181	2c0262af	bellard	{
2182	2c0262af	bellard	TranslationBlock *tb = s->tb;
2183	2c0262af	bellard
2184	2c0262af	bellard	if (s->jmp_opt) {
2185	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2186	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2187	14ce26e7	bellard	if (tb_num)
2188	ae063a68	bellard	gen_op_goto_tb1(TBPARAM(tb));
2189	14ce26e7	bellard	else
2190	ae063a68	bellard	gen_op_goto_tb0(TBPARAM(tb));
2191	14ce26e7	bellard	gen_jmp_im(eip);
2192	14ce26e7	bellard	gen_op_movl_T0_im((long)tb + tb_num);
2193	14ce26e7	bellard	gen_op_exit_tb();
2194	2c0262af	bellard	s->is_jmp = 3;
2195	2c0262af	bellard	} else {
2196	14ce26e7	bellard	gen_jmp_im(eip);
2197	2c0262af	bellard	gen_eob(s);
2198	2c0262af	bellard	}
2199	2c0262af	bellard	}
2200	2c0262af	bellard
2201	14ce26e7	bellard	static void gen_jmp(DisasContext *s, target_ulong eip)
2202	14ce26e7	bellard	{
2203	14ce26e7	bellard	gen_jmp_tb(s, eip, 0);
2204	14ce26e7	bellard	}
2205	14ce26e7	bellard
2206	14ce26e7	bellard	static void gen_movtl_T0_im(target_ulong val)
2207	14ce26e7	bellard	{
2208	14ce26e7	bellard	#ifdef TARGET_X86_64
2209	14ce26e7	bellard	if ((int32_t)val == val) {
2210	14ce26e7	bellard	gen_op_movl_T0_im(val);
2211	14ce26e7	bellard	} else {
2212	14ce26e7	bellard	gen_op_movq_T0_im64(val >> 32, val);
2213	14ce26e7	bellard	}
2214	14ce26e7	bellard	#else
2215	14ce26e7	bellard	gen_op_movl_T0_im(val);
2216	14ce26e7	bellard	#endif
2217	14ce26e7	bellard	}
2218	14ce26e7	bellard
2219	1ef38687	bellard	static void gen_movtl_T1_im(target_ulong val)
2220	1ef38687	bellard	{
2221	1ef38687	bellard	#ifdef TARGET_X86_64
2222	1ef38687	bellard	if ((int32_t)val == val) {
2223	1ef38687	bellard	gen_op_movl_T1_im(val);
2224	1ef38687	bellard	} else {
2225	1ef38687	bellard	gen_op_movq_T1_im64(val >> 32, val);
2226	1ef38687	bellard	}
2227	1ef38687	bellard	#else
2228	1ef38687	bellard	gen_op_movl_T1_im(val);
2229	1ef38687	bellard	#endif
2230	1ef38687	bellard	}
2231	1ef38687	bellard
2232	664e0f19	bellard	static GenOpFunc1 *gen_ldq_env_A0[3] = {
2233	664e0f19	bellard	gen_op_ldq_raw_env_A0,
2234	664e0f19	bellard	#ifndef CONFIG_USER_ONLY
2235	664e0f19	bellard	gen_op_ldq_kernel_env_A0,
2236	664e0f19	bellard	gen_op_ldq_user_env_A0,
2237	664e0f19	bellard	#endif
2238	664e0f19	bellard	};
2239	664e0f19	bellard
2240	664e0f19	bellard	static GenOpFunc1 *gen_stq_env_A0[3] = {
2241	664e0f19	bellard	gen_op_stq_raw_env_A0,
2242	664e0f19	bellard	#ifndef CONFIG_USER_ONLY
2243	664e0f19	bellard	gen_op_stq_kernel_env_A0,
2244	664e0f19	bellard	gen_op_stq_user_env_A0,
2245	664e0f19	bellard	#endif
2246	664e0f19	bellard	};
2247	664e0f19	bellard
2248	14ce26e7	bellard	static GenOpFunc1 *gen_ldo_env_A0[3] = {
2249	14ce26e7	bellard	gen_op_ldo_raw_env_A0,
2250	14ce26e7	bellard	#ifndef CONFIG_USER_ONLY
2251	14ce26e7	bellard	gen_op_ldo_kernel_env_A0,
2252	14ce26e7	bellard	gen_op_ldo_user_env_A0,
2253	14ce26e7	bellard	#endif
2254	14ce26e7	bellard	};
2255	14ce26e7	bellard
2256	14ce26e7	bellard	static GenOpFunc1 *gen_sto_env_A0[3] = {
2257	14ce26e7	bellard	gen_op_sto_raw_env_A0,
2258	14ce26e7	bellard	#ifndef CONFIG_USER_ONLY
2259	14ce26e7	bellard	gen_op_sto_kernel_env_A0,
2260	14ce26e7	bellard	gen_op_sto_user_env_A0,
2261	14ce26e7	bellard	#endif
2262	14ce26e7	bellard	};
2263	14ce26e7	bellard
2264	664e0f19	bellard	#define SSE_SPECIAL ((GenOpFunc2 *)1)
2265	664e0f19	bellard
2266	664e0f19	bellard	#define MMX_OP2(x) { gen_op_ ## x ## _mmx, gen_op_ ## x ## _xmm }
2267	664e0f19	bellard	#define SSE_FOP(x) { gen_op_ ## x ## ps, gen_op_ ## x ## pd, \
2268	664e0f19	bellard	gen_op_ ## x ## ss, gen_op_ ## x ## sd, }
2269	664e0f19	bellard
2270	664e0f19	bellard	static GenOpFunc2 *sse_op_table1[256][4] = {
2271	664e0f19	bellard	/* pure SSE operations */
2272	664e0f19	bellard	[0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2273	664e0f19	bellard	[0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2274	664e0f19	bellard	[0x12] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2275	664e0f19	bellard	[0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2276	664e0f19	bellard	[0x14] = { gen_op_punpckldq_xmm, gen_op_punpcklqdq_xmm },
2277	664e0f19	bellard	[0x15] = { gen_op_punpckhdq_xmm, gen_op_punpckhqdq_xmm },
2278	664e0f19	bellard	[0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2279	664e0f19	bellard	[0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2280	664e0f19	bellard
2281	664e0f19	bellard	[0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2282	664e0f19	bellard	[0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2283	664e0f19	bellard	[0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2284	664e0f19	bellard	[0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2285	664e0f19	bellard	[0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2286	664e0f19	bellard	[0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2287	664e0f19	bellard	[0x2e] = { gen_op_ucomiss, gen_op_ucomisd },
2288	664e0f19	bellard	[0x2f] = { gen_op_comiss, gen_op_comisd },
2289	664e0f19	bellard	[0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2290	664e0f19	bellard	[0x51] = SSE_FOP(sqrt),
2291	664e0f19	bellard	[0x52] = { gen_op_rsqrtps, NULL, gen_op_rsqrtss, NULL },
2292	664e0f19	bellard	[0x53] = { gen_op_rcpps, NULL, gen_op_rcpss, NULL },
2293	664e0f19	bellard	[0x54] = { gen_op_pand_xmm, gen_op_pand_xmm }, /* andps, andpd */
2294	664e0f19	bellard	[0x55] = { gen_op_pandn_xmm, gen_op_pandn_xmm }, /* andnps, andnpd */
2295	664e0f19	bellard	[0x56] = { gen_op_por_xmm, gen_op_por_xmm }, /* orps, orpd */
2296	664e0f19	bellard	[0x57] = { gen_op_pxor_xmm, gen_op_pxor_xmm }, /* xorps, xorpd */
2297	664e0f19	bellard	[0x58] = SSE_FOP(add),
2298	664e0f19	bellard	[0x59] = SSE_FOP(mul),
2299	664e0f19	bellard	[0x5a] = { gen_op_cvtps2pd, gen_op_cvtpd2ps,
2300	664e0f19	bellard	gen_op_cvtss2sd, gen_op_cvtsd2ss },
2301	664e0f19	bellard	[0x5b] = { gen_op_cvtdq2ps, gen_op_cvtps2dq, gen_op_cvttps2dq },
2302	664e0f19	bellard	[0x5c] = SSE_FOP(sub),
2303	664e0f19	bellard	[0x5d] = SSE_FOP(min),
2304	664e0f19	bellard	[0x5e] = SSE_FOP(div),
2305	664e0f19	bellard	[0x5f] = SSE_FOP(max),
2306	664e0f19	bellard
2307	664e0f19	bellard	[0xc2] = SSE_FOP(cmpeq),
2308	d52cf7a6	bellard	[0xc6] = { (GenOpFunc2 )gen_op_shufps, (GenOpFunc2 )gen_op_shufpd },
2309	664e0f19	bellard
2310	664e0f19	bellard	/* MMX ops and their SSE extensions */
2311	664e0f19	bellard	[0x60] = MMX_OP2(punpcklbw),
2312	664e0f19	bellard	[0x61] = MMX_OP2(punpcklwd),
2313	664e0f19	bellard	[0x62] = MMX_OP2(punpckldq),
2314	664e0f19	bellard	[0x63] = MMX_OP2(packsswb),
2315	664e0f19	bellard	[0x64] = MMX_OP2(pcmpgtb),
2316	664e0f19	bellard	[0x65] = MMX_OP2(pcmpgtw),
2317	664e0f19	bellard	[0x66] = MMX_OP2(pcmpgtl),
2318	664e0f19	bellard	[0x67] = MMX_OP2(packuswb),
2319	664e0f19	bellard	[0x68] = MMX_OP2(punpckhbw),
2320	664e0f19	bellard	[0x69] = MMX_OP2(punpckhwd),
2321	664e0f19	bellard	[0x6a] = MMX_OP2(punpckhdq),
2322	664e0f19	bellard	[0x6b] = MMX_OP2(packssdw),
2323	664e0f19	bellard	[0x6c] = { NULL, gen_op_punpcklqdq_xmm },
2324	664e0f19	bellard	[0x6d] = { NULL, gen_op_punpckhqdq_xmm },
2325	664e0f19	bellard	[0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2326	664e0f19	bellard	[0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2327	664e0f19	bellard	[0x70] = { (GenOpFunc2 *)gen_op_pshufw_mmx,
2328	664e0f19	bellard	(GenOpFunc2 *)gen_op_pshufd_xmm,
2329	664e0f19	bellard	(GenOpFunc2 *)gen_op_pshufhw_xmm,
2330	664e0f19	bellard	(GenOpFunc2 *)gen_op_pshuflw_xmm },
2331	664e0f19	bellard	[0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2332	664e0f19	bellard	[0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2333	664e0f19	bellard	[0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2334	664e0f19	bellard	[0x74] = MMX_OP2(pcmpeqb),
2335	664e0f19	bellard	[0x75] = MMX_OP2(pcmpeqw),
2336	664e0f19	bellard	[0x76] = MMX_OP2(pcmpeql),
2337	664e0f19	bellard	[0x77] = { SSE_SPECIAL }, /* emms */
2338	664e0f19	bellard	[0x7c] = { NULL, gen_op_haddpd, NULL, gen_op_haddps },
2339	664e0f19	bellard	[0x7d] = { NULL, gen_op_hsubpd, NULL, gen_op_hsubps },
2340	664e0f19	bellard	[0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2341	664e0f19	bellard	[0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2342	664e0f19	bellard	[0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2343	664e0f19	bellard	[0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2344	664e0f19	bellard	[0xd0] = { NULL, gen_op_addsubpd, NULL, gen_op_addsubps },
2345	664e0f19	bellard	[0xd1] = MMX_OP2(psrlw),
2346	664e0f19	bellard	[0xd2] = MMX_OP2(psrld),
2347	664e0f19	bellard	[0xd3] = MMX_OP2(psrlq),
2348	664e0f19	bellard	[0xd4] = MMX_OP2(paddq),
2349	664e0f19	bellard	[0xd5] = MMX_OP2(pmullw),
2350	664e0f19	bellard	[0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2351	664e0f19	bellard	[0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2352	664e0f19	bellard	[0xd8] = MMX_OP2(psubusb),
2353	664e0f19	bellard	[0xd9] = MMX_OP2(psubusw),
2354	664e0f19	bellard	[0xda] = MMX_OP2(pminub),
2355	664e0f19	bellard	[0xdb] = MMX_OP2(pand),
2356	664e0f19	bellard	[0xdc] = MMX_OP2(paddusb),
2357	664e0f19	bellard	[0xdd] = MMX_OP2(paddusw),
2358	664e0f19	bellard	[0xde] = MMX_OP2(pmaxub),
2359	664e0f19	bellard	[0xdf] = MMX_OP2(pandn),
2360	664e0f19	bellard	[0xe0] = MMX_OP2(pavgb),
2361	664e0f19	bellard	[0xe1] = MMX_OP2(psraw),
2362	664e0f19	bellard	[0xe2] = MMX_OP2(psrad),
2363	664e0f19	bellard	[0xe3] = MMX_OP2(pavgw),
2364	664e0f19	bellard	[0xe4] = MMX_OP2(pmulhuw),
2365	664e0f19	bellard	[0xe5] = MMX_OP2(pmulhw),
2366	664e0f19	bellard	[0xe6] = { NULL, gen_op_cvttpd2dq, gen_op_cvtdq2pd, gen_op_cvtpd2dq },
2367	664e0f19	bellard	[0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2368	664e0f19	bellard	[0xe8] = MMX_OP2(psubsb),
2369	664e0f19	bellard	[0xe9] = MMX_OP2(psubsw),
2370	664e0f19	bellard	[0xea] = MMX_OP2(pminsw),
2371	664e0f19	bellard	[0xeb] = MMX_OP2(por),
2372	664e0f19	bellard	[0xec] = MMX_OP2(paddsb),
2373	664e0f19	bellard	[0xed] = MMX_OP2(paddsw),
2374	664e0f19	bellard	[0xee] = MMX_OP2(pmaxsw),
2375	664e0f19	bellard	[0xef] = MMX_OP2(pxor),
2376	664e0f19	bellard	[0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu (PNI) */
2377	664e0f19	bellard	[0xf1] = MMX_OP2(psllw),
2378	664e0f19	bellard	[0xf2] = MMX_OP2(pslld),
2379	664e0f19	bellard	[0xf3] = MMX_OP2(psllq),
2380	664e0f19	bellard	[0xf4] = MMX_OP2(pmuludq),
2381	664e0f19	bellard	[0xf5] = MMX_OP2(pmaddwd),
2382	664e0f19	bellard	[0xf6] = MMX_OP2(psadbw),
2383	664e0f19	bellard	[0xf7] = MMX_OP2(maskmov),
2384	664e0f19	bellard	[0xf8] = MMX_OP2(psubb),
2385	664e0f19	bellard	[0xf9] = MMX_OP2(psubw),
2386	664e0f19	bellard	[0xfa] = MMX_OP2(psubl),
2387	664e0f19	bellard	[0xfb] = MMX_OP2(psubq),
2388	664e0f19	bellard	[0xfc] = MMX_OP2(paddb),
2389	664e0f19	bellard	[0xfd] = MMX_OP2(paddw),
2390	664e0f19	bellard	[0xfe] = MMX_OP2(paddl),
2391	664e0f19	bellard	};
2392	664e0f19	bellard
2393	664e0f19	bellard	static GenOpFunc2 sse_op_table2[3 8][2] = {
2394	664e0f19	bellard	[0 + 2] = MMX_OP2(psrlw),
2395	664e0f19	bellard	[0 + 4] = MMX_OP2(psraw),
2396	664e0f19	bellard	[0 + 6] = MMX_OP2(psllw),
2397	664e0f19	bellard	[8 + 2] = MMX_OP2(psrld),
2398	664e0f19	bellard	[8 + 4] = MMX_OP2(psrad),
2399	664e0f19	bellard	[8 + 6] = MMX_OP2(pslld),
2400	664e0f19	bellard	[16 + 2] = MMX_OP2(psrlq),
2401	664e0f19	bellard	[16 + 3] = { NULL, gen_op_psrldq_xmm },
2402	664e0f19	bellard	[16 + 6] = MMX_OP2(psllq),
2403	664e0f19	bellard	[16 + 7] = { NULL, gen_op_pslldq_xmm },
2404	664e0f19	bellard	};
2405	664e0f19	bellard
2406	664e0f19	bellard	static GenOpFunc1 sse_op_table3[4 3] = {
2407	664e0f19	bellard	gen_op_cvtsi2ss,
2408	664e0f19	bellard	gen_op_cvtsi2sd,
2409	664e0f19	bellard	X86_64_ONLY(gen_op_cvtsq2ss),
2410	664e0f19	bellard	X86_64_ONLY(gen_op_cvtsq2sd),
2411	664e0f19	bellard
2412	664e0f19	bellard	gen_op_cvttss2si,
2413	664e0f19	bellard	gen_op_cvttsd2si,
2414	664e0f19	bellard	X86_64_ONLY(gen_op_cvttss2sq),
2415	664e0f19	bellard	X86_64_ONLY(gen_op_cvttsd2sq),
2416	664e0f19	bellard
2417	664e0f19	bellard	gen_op_cvtss2si,
2418	664e0f19	bellard	gen_op_cvtsd2si,
2419	664e0f19	bellard	X86_64_ONLY(gen_op_cvtss2sq),
2420	664e0f19	bellard	X86_64_ONLY(gen_op_cvtsd2sq),
2421	664e0f19	bellard	};
2422	664e0f19	bellard
2423	664e0f19	bellard	static GenOpFunc2 *sse_op_table4[8][4] = {
2424	664e0f19	bellard	SSE_FOP(cmpeq),
2425	664e0f19	bellard	SSE_FOP(cmplt),
2426	664e0f19	bellard	SSE_FOP(cmple),
2427	664e0f19	bellard	SSE_FOP(cmpunord),
2428	664e0f19	bellard	SSE_FOP(cmpneq),
2429	664e0f19	bellard	SSE_FOP(cmpnlt),
2430	664e0f19	bellard	SSE_FOP(cmpnle),
2431	664e0f19	bellard	SSE_FOP(cmpord),
2432	664e0f19	bellard	};
2433	664e0f19	bellard
2434	664e0f19	bellard	static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
2435	664e0f19	bellard	{
2436	664e0f19	bellard	int b1, op1_offset, op2_offset, is_xmm, val, ot;
2437	664e0f19	bellard	int modrm, mod, rm, reg, reg_addr, offset_addr;
2438	664e0f19	bellard	GenOpFunc2 *sse_op2;
2439	664e0f19	bellard	GenOpFunc3 *sse_op3;
2440	664e0f19	bellard
2441	664e0f19	bellard	b &= 0xff;
2442	664e0f19	bellard	if (s->prefix & PREFIX_DATA)
2443	664e0f19	bellard	b1 = 1;
2444	664e0f19	bellard	else if (s->prefix & PREFIX_REPZ)
2445	664e0f19	bellard	b1 = 2;
2446	664e0f19	bellard	else if (s->prefix & PREFIX_REPNZ)
2447	664e0f19	bellard	b1 = 3;
2448	664e0f19	bellard	else
2449	664e0f19	bellard	b1 = 0;
2450	664e0f19	bellard	sse_op2 = sse_op_table1[b][b1];
2451	664e0f19	bellard	if (!sse_op2)
2452	664e0f19	bellard	goto illegal_op;
2453	664e0f19	bellard	if (b <= 0x5f \|\| b == 0xc6 \|\| b == 0xc2) {
2454	664e0f19	bellard	is_xmm = 1;
2455	664e0f19	bellard	} else {
2456	664e0f19	bellard	if (b1 == 0) {
2457	664e0f19	bellard	/* MMX case */
2458	664e0f19	bellard	is_xmm = 0;
2459	664e0f19	bellard	} else {
2460	664e0f19	bellard	is_xmm = 1;
2461	664e0f19	bellard	}
2462	664e0f19	bellard	}
2463	664e0f19	bellard	/* simple MMX/SSE operation */
2464	664e0f19	bellard	if (s->flags & HF_TS_MASK) {
2465	664e0f19	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2466	664e0f19	bellard	return;
2467	664e0f19	bellard	}
2468	664e0f19	bellard	if (s->flags & HF_EM_MASK) {
2469	664e0f19	bellard	illegal_op:
2470	664e0f19	bellard	gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
2471	664e0f19	bellard	return;
2472	664e0f19	bellard	}
2473	664e0f19	bellard	if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
2474	664e0f19	bellard	goto illegal_op;
2475	664e0f19	bellard	if (b == 0x77) {
2476	664e0f19	bellard	/* emms */
2477	664e0f19	bellard	gen_op_emms();
2478	664e0f19	bellard	return;
2479	664e0f19	bellard	}
2480	664e0f19	bellard	/* prepare MMX state (XXX: optimize by storing fptt and fptags in
2481	664e0f19	bellard	the static cpu state) */
2482	664e0f19	bellard	if (!is_xmm) {
2483	664e0f19	bellard	gen_op_enter_mmx();
2484	664e0f19	bellard	}
2485	664e0f19	bellard
2486	664e0f19	bellard	modrm = ldub_code(s->pc++);
2487	664e0f19	bellard	reg = ((modrm >> 3) & 7);
2488	664e0f19	bellard	if (is_xmm)
2489	664e0f19	bellard	reg \|= rex_r;
2490	664e0f19	bellard	mod = (modrm >> 6) & 3;
2491	664e0f19	bellard	if (sse_op2 == SSE_SPECIAL) {
2492	664e0f19	bellard	b \|= (b1 << 8);
2493	664e0f19	bellard	switch(b) {
2494	664e0f19	bellard	case 0x0e7: /* movntq */
2495	664e0f19	bellard	if (mod == 3)
2496	664e0f19	bellard	goto illegal_op;
2497	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2498	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2499	664e0f19	bellard	break;
2500	664e0f19	bellard	case 0x1e7: /* movntdq */
2501	664e0f19	bellard	case 0x02b: /* movntps */
2502	664e0f19	bellard	case 0x12b: /* movntps */
2503	664e0f19	bellard	case 0x2f0: /* lddqu */
2504	664e0f19	bellard	if (mod == 3)
2505	664e0f19	bellard	goto illegal_op;
2506	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2507	664e0f19	bellard	gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2508	664e0f19	bellard	break;
2509	664e0f19	bellard	case 0x6e: /* movd mm, ea */
2510	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
2511	664e0f19	bellard	gen_op_movl_mm_T0_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
2512	664e0f19	bellard	break;
2513	664e0f19	bellard	case 0x16e: /* movd xmm, ea */
2514	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
2515	664e0f19	bellard	gen_op_movl_mm_T0_xmm(offsetof(CPUX86State,xmm_regs[reg]));
2516	664e0f19	bellard	break;
2517	664e0f19	bellard	case 0x6f: /* movq mm, ea */
2518	664e0f19	bellard	if (mod != 3) {
2519	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2520	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2521	664e0f19	bellard	} else {
2522	664e0f19	bellard	rm = (modrm & 7);
2523	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,fpregs[reg].mmx),
2524	664e0f19	bellard	offsetof(CPUX86State,fpregs[rm].mmx));
2525	664e0f19	bellard	}
2526	664e0f19	bellard	break;
2527	664e0f19	bellard	case 0x010: /* movups */
2528	664e0f19	bellard	case 0x110: /* movupd */
2529	664e0f19	bellard	case 0x028: /* movaps */
2530	664e0f19	bellard	case 0x128: /* movapd */
2531	664e0f19	bellard	case 0x16f: /* movdqa xmm, ea */
2532	664e0f19	bellard	case 0x26f: /* movdqu xmm, ea */
2533	664e0f19	bellard	if (mod != 3) {
2534	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2535	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2536	664e0f19	bellard	} else {
2537	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2538	664e0f19	bellard	gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
2539	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm]));
2540	664e0f19	bellard	}
2541	664e0f19	bellard	break;
2542	664e0f19	bellard	case 0x210: /* movss xmm, ea */
2543	664e0f19	bellard	if (mod != 3) {
2544	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2545	664e0f19	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2546	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2547	664e0f19	bellard	gen_op_movl_T0_0();
2548	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
2549	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
2550	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2551	664e0f19	bellard	} else {
2552	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2553	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
2554	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
2555	664e0f19	bellard	}
2556	664e0f19	bellard	break;
2557	664e0f19	bellard	case 0x310: /* movsd xmm, ea */
2558	664e0f19	bellard	if (mod != 3) {
2559	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2560	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2561	664e0f19	bellard	gen_op_movl_T0_0();
2562	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
2563	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2564	664e0f19	bellard	} else {
2565	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2566	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2567	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2568	664e0f19	bellard	}
2569	664e0f19	bellard	break;
2570	664e0f19	bellard	case 0x012: /* movlps */
2571	664e0f19	bellard	case 0x112: /* movlpd */
2572	664e0f19	bellard	if (mod != 3) {
2573	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2574	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2575	664e0f19	bellard	} else {
2576	664e0f19	bellard	/* movhlps */
2577	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2578	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2579	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2580	664e0f19	bellard	}
2581	664e0f19	bellard	break;
2582	664e0f19	bellard	case 0x016: /* movhps */
2583	664e0f19	bellard	case 0x116: /* movhpd */
2584	664e0f19	bellard	if (mod != 3) {
2585	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2586	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2587	664e0f19	bellard	} else {
2588	664e0f19	bellard	/* movlhps */
2589	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2590	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
2591	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2592	664e0f19	bellard	}
2593	664e0f19	bellard	break;
2594	664e0f19	bellard	case 0x216: /* movshdup */
2595	664e0f19	bellard	if (mod != 3) {
2596	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2597	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2598	664e0f19	bellard	} else {
2599	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2600	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
2601	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
2602	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
2603	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
2604	664e0f19	bellard	}
2605	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
2606	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
2607	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
2608	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2609	664e0f19	bellard	break;
2610	664e0f19	bellard	case 0x7e: /* movd ea, mm */
2611	664e0f19	bellard	gen_op_movl_T0_mm_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
2612	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
2613	664e0f19	bellard	break;
2614	664e0f19	bellard	case 0x17e: /* movd ea, xmm */
2615	664e0f19	bellard	gen_op_movl_T0_mm_xmm(offsetof(CPUX86State,xmm_regs[reg]));
2616	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
2617	664e0f19	bellard	break;
2618	664e0f19	bellard	case 0x27e: /* movq xmm, ea */
2619	664e0f19	bellard	if (mod != 3) {
2620	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2621	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2622	664e0f19	bellard	} else {
2623	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2624	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2625	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2626	664e0f19	bellard	}
2627	664e0f19	bellard	gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2628	664e0f19	bellard	break;
2629	664e0f19	bellard	case 0x7f: /* movq ea, mm */
2630	664e0f19	bellard	if (mod != 3) {
2631	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2632	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2633	664e0f19	bellard	} else {
2634	664e0f19	bellard	rm = (modrm & 7);
2635	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
2636	664e0f19	bellard	offsetof(CPUX86State,fpregs[reg].mmx));
2637	664e0f19	bellard	}
2638	664e0f19	bellard	break;
2639	664e0f19	bellard	case 0x011: /* movups */
2640	664e0f19	bellard	case 0x111: /* movupd */
2641	664e0f19	bellard	case 0x029: /* movaps */
2642	664e0f19	bellard	case 0x129: /* movapd */
2643	664e0f19	bellard	case 0x17f: /* movdqa ea, xmm */
2644	664e0f19	bellard	case 0x27f: /* movdqu ea, xmm */
2645	664e0f19	bellard	if (mod != 3) {
2646	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2647	664e0f19	bellard	gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2648	664e0f19	bellard	} else {
2649	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2650	664e0f19	bellard	gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
2651	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg]));
2652	664e0f19	bellard	}
2653	664e0f19	bellard	break;
2654	664e0f19	bellard	case 0x211: /* movss ea, xmm */
2655	664e0f19	bellard	if (mod != 3) {
2656	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2657	664e0f19	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2658	664e0f19	bellard	gen_op_st_T0_A0[OT_LONG + s->mem_index]();
2659	664e0f19	bellard	} else {
2660	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2661	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
2662	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2663	664e0f19	bellard	}
2664	664e0f19	bellard	break;
2665	664e0f19	bellard	case 0x311: /* movsd ea, xmm */
2666	664e0f19	bellard	if (mod != 3) {
2667	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2668	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2669	664e0f19	bellard	} else {
2670	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2671	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2672	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2673	664e0f19	bellard	}
2674	664e0f19	bellard	break;
2675	664e0f19	bellard	case 0x013: /* movlps */
2676	664e0f19	bellard	case 0x113: /* movlpd */
2677	664e0f19	bellard	if (mod != 3) {
2678	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2679	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2680	664e0f19	bellard	} else {
2681	664e0f19	bellard	goto illegal_op;
2682	664e0f19	bellard	}
2683	664e0f19	bellard	break;
2684	664e0f19	bellard	case 0x017: /* movhps */
2685	664e0f19	bellard	case 0x117: /* movhpd */
2686	664e0f19	bellard	if (mod != 3) {
2687	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2688	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2689	664e0f19	bellard	} else {
2690	664e0f19	bellard	goto illegal_op;
2691	664e0f19	bellard	}
2692	664e0f19	bellard	break;
2693	664e0f19	bellard	case 0x71: /* shift mm, im */
2694	664e0f19	bellard	case 0x72:
2695	664e0f19	bellard	case 0x73:
2696	664e0f19	bellard	case 0x171: /* shift xmm, im */
2697	664e0f19	bellard	case 0x172:
2698	664e0f19	bellard	case 0x173:
2699	664e0f19	bellard	val = ldub_code(s->pc++);
2700	664e0f19	bellard	if (is_xmm) {
2701	664e0f19	bellard	gen_op_movl_T0_im(val);
2702	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2703	664e0f19	bellard	gen_op_movl_T0_0();
2704	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(1)));
2705	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_t0);
2706	664e0f19	bellard	} else {
2707	664e0f19	bellard	gen_op_movl_T0_im(val);
2708	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(0)));
2709	664e0f19	bellard	gen_op_movl_T0_0();
2710	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(1)));
2711	664e0f19	bellard	op1_offset = offsetof(CPUX86State,mmx_t0);
2712	664e0f19	bellard	}
2713	664e0f19	bellard	sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
2714	664e0f19	bellard	if (!sse_op2)
2715	664e0f19	bellard	goto illegal_op;
2716	664e0f19	bellard	if (is_xmm) {
2717	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2718	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2719	664e0f19	bellard	} else {
2720	664e0f19	bellard	rm = (modrm & 7);
2721	664e0f19	bellard	op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
2722	664e0f19	bellard	}
2723	664e0f19	bellard	sse_op2(op2_offset, op1_offset);
2724	664e0f19	bellard	break;
2725	664e0f19	bellard	case 0x050: /* movmskps */
2726	664e0f19	bellard	gen_op_movmskps(offsetof(CPUX86State,xmm_regs[reg]));
2727	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2728	664e0f19	bellard	gen_op_mov_reg_T0[OT_LONG][rm]();
2729	664e0f19	bellard	break;
2730	664e0f19	bellard	case 0x150: /* movmskpd */
2731	664e0f19	bellard	gen_op_movmskpd(offsetof(CPUX86State,xmm_regs[reg]));
2732	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2733	664e0f19	bellard	gen_op_mov_reg_T0[OT_LONG][rm]();
2734	664e0f19	bellard	break;
2735	664e0f19	bellard	case 0x02a: /* cvtpi2ps */
2736	664e0f19	bellard	case 0x12a: /* cvtpi2pd */
2737	664e0f19	bellard	gen_op_enter_mmx();
2738	664e0f19	bellard	if (mod != 3) {
2739	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2740	664e0f19	bellard	op2_offset = offsetof(CPUX86State,mmx_t0);
2741	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](op2_offset);
2742	664e0f19	bellard	} else {
2743	664e0f19	bellard	rm = (modrm & 7);
2744	664e0f19	bellard	op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
2745	664e0f19	bellard	}
2746	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2747	664e0f19	bellard	switch(b >> 8) {
2748	664e0f19	bellard	case 0x0:
2749	664e0f19	bellard	gen_op_cvtpi2ps(op1_offset, op2_offset);
2750	664e0f19	bellard	break;
2751	664e0f19	bellard	default:
2752	664e0f19	bellard	case 0x1:
2753	664e0f19	bellard	gen_op_cvtpi2pd(op1_offset, op2_offset);
2754	664e0f19	bellard	break;
2755	664e0f19	bellard	}
2756	664e0f19	bellard	break;
2757	664e0f19	bellard	case 0x22a: /* cvtsi2ss */
2758	664e0f19	bellard	case 0x32a: /* cvtsi2sd */
2759	664e0f19	bellard	ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
2760	664e0f19	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2761	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2762	664e0f19	bellard	sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)](op1_offset);
2763	664e0f19	bellard	break;
2764	664e0f19	bellard	case 0x02c: /* cvttps2pi */
2765	664e0f19	bellard	case 0x12c: /* cvttpd2pi */
2766	664e0f19	bellard	case 0x02d: /* cvtps2pi */
2767	664e0f19	bellard	case 0x12d: /* cvtpd2pi */
2768	664e0f19	bellard	gen_op_enter_mmx();
2769	664e0f19	bellard	if (mod != 3) {
2770	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2771	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_t0);
2772	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](op2_offset);
2773	664e0f19	bellard	} else {
2774	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2775	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2776	664e0f19	bellard	}
2777	664e0f19	bellard	op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
2778	664e0f19	bellard	switch(b) {
2779	664e0f19	bellard	case 0x02c:
2780	664e0f19	bellard	gen_op_cvttps2pi(op1_offset, op2_offset);
2781	664e0f19	bellard	break;
2782	664e0f19	bellard	case 0x12c:
2783	664e0f19	bellard	gen_op_cvttpd2pi(op1_offset, op2_offset);
2784	664e0f19	bellard	break;
2785	664e0f19	bellard	case 0x02d:
2786	664e0f19	bellard	gen_op_cvtps2pi(op1_offset, op2_offset);
2787	664e0f19	bellard	break;
2788	664e0f19	bellard	case 0x12d:
2789	664e0f19	bellard	gen_op_cvtpd2pi(op1_offset, op2_offset);
2790	664e0f19	bellard	break;
2791	664e0f19	bellard	}
2792	664e0f19	bellard	break;
2793	664e0f19	bellard	case 0x22c: /* cvttss2si */
2794	664e0f19	bellard	case 0x32c: /* cvttsd2si */
2795	664e0f19	bellard	case 0x22d: /* cvtss2si */
2796	664e0f19	bellard	case 0x32d: /* cvtsd2si */
2797	664e0f19	bellard	ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
2798	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2799	664e0f19	bellard	sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
2800	664e0f19	bellard	(b & 1) * 4](op1_offset);
2801	664e0f19	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2802	664e0f19	bellard	break;
2803	664e0f19	bellard	case 0xc4: /* pinsrw */
2804	664e0f19	bellard	case 0x1c4:
2805	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2806	664e0f19	bellard	val = ldub_code(s->pc++);
2807	664e0f19	bellard	if (b1) {
2808	664e0f19	bellard	val &= 7;
2809	664e0f19	bellard	gen_op_pinsrw_xmm(offsetof(CPUX86State,xmm_regs[reg]), val);
2810	664e0f19	bellard	} else {
2811	664e0f19	bellard	val &= 3;
2812	664e0f19	bellard	gen_op_pinsrw_mmx(offsetof(CPUX86State,fpregs[reg].mmx), val);
2813	664e0f19	bellard	}
2814	664e0f19	bellard	break;
2815	664e0f19	bellard	case 0xc5: /* pextrw */
2816	664e0f19	bellard	case 0x1c5:
2817	664e0f19	bellard	if (mod != 3)
2818	664e0f19	bellard	goto illegal_op;
2819	664e0f19	bellard	val = ldub_code(s->pc++);
2820	664e0f19	bellard	if (b1) {
2821	664e0f19	bellard	val &= 7;
2822	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2823	664e0f19	bellard	gen_op_pextrw_xmm(offsetof(CPUX86State,xmm_regs[rm]), val);
2824	664e0f19	bellard	} else {
2825	664e0f19	bellard	val &= 3;
2826	664e0f19	bellard	rm = (modrm & 7);
2827	664e0f19	bellard	gen_op_pextrw_mmx(offsetof(CPUX86State,fpregs[rm].mmx), val);
2828	664e0f19	bellard	}
2829	664e0f19	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
2830	664e0f19	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
2831	664e0f19	bellard	break;
2832	664e0f19	bellard	case 0x1d6: /* movq ea, xmm */
2833	664e0f19	bellard	if (mod != 3) {
2834	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2835	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2836	664e0f19	bellard	} else {
2837	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2838	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2839	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2840	664e0f19	bellard	gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2841	664e0f19	bellard	}
2842	664e0f19	bellard	break;
2843	664e0f19	bellard	case 0x2d6: /* movq2dq */
2844	664e0f19	bellard	gen_op_enter_mmx();
2845	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2846	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2847	664e0f19	bellard	offsetof(CPUX86State,fpregs[reg & 7].mmx));
2848	664e0f19	bellard	gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2849	664e0f19	bellard	break;
2850	664e0f19	bellard	case 0x3d6: /* movdq2q */
2851	664e0f19	bellard	gen_op_enter_mmx();
2852	664e0f19	bellard	rm = (modrm & 7);
2853	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
2854	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2855	664e0f19	bellard	break;
2856	664e0f19	bellard	case 0xd7: /* pmovmskb */
2857	664e0f19	bellard	case 0x1d7:
2858	664e0f19	bellard	if (mod != 3)
2859	664e0f19	bellard	goto illegal_op;
2860	664e0f19	bellard	if (b1) {
2861	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2862	664e0f19	bellard	gen_op_pmovmskb_xmm(offsetof(CPUX86State,xmm_regs[rm]));
2863	664e0f19	bellard	} else {
2864	664e0f19	bellard	rm = (modrm & 7);
2865	664e0f19	bellard	gen_op_pmovmskb_mmx(offsetof(CPUX86State,fpregs[rm].mmx));
2866	664e0f19	bellard	}
2867	664e0f19	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
2868	664e0f19	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
2869	664e0f19	bellard	break;
2870	664e0f19	bellard	default:
2871	664e0f19	bellard	goto illegal_op;
2872	664e0f19	bellard	}
2873	664e0f19	bellard	} else {
2874	664e0f19	bellard	/* generic MMX or SSE operation */
2875	664e0f19	bellard	if (b == 0xf7) {
2876	664e0f19	bellard	/* maskmov : we must prepare A0 */
2877	664e0f19	bellard	if (mod != 3)
2878	664e0f19	bellard	goto illegal_op;
2879	664e0f19	bellard	#ifdef TARGET_X86_64
2880	664e0f19	bellard	if (CODE64(s)) {
2881	664e0f19	bellard	gen_op_movq_A0_reg[R_EDI]();
2882	664e0f19	bellard	} else
2883	664e0f19	bellard	#endif
2884	664e0f19	bellard	{
2885	664e0f19	bellard	gen_op_movl_A0_reg[R_EDI]();
2886	664e0f19	bellard	if (s->aflag == 0)
2887	664e0f19	bellard	gen_op_andl_A0_ffff();
2888	664e0f19	bellard	}
2889	664e0f19	bellard	gen_add_A0_ds_seg(s);
2890	664e0f19	bellard	}
2891	664e0f19	bellard	if (is_xmm) {
2892	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2893	664e0f19	bellard	if (mod != 3) {
2894	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2895	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_t0);
2896	664e0f19	bellard	if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f) \|\|
2897	664e0f19	bellard	b == 0xc2)) {
2898	664e0f19	bellard	/* specific case for SSE single instructions */
2899	664e0f19	bellard	if (b1 == 2) {
2900	664e0f19	bellard	/* 32 bit access */
2901	664e0f19	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2902	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2903	664e0f19	bellard	} else {
2904	664e0f19	bellard	/* 64 bit access */
2905	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_t0.XMM_D(0)));
2906	664e0f19	bellard	}
2907	664e0f19	bellard	} else {
2908	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](op2_offset);
2909	664e0f19	bellard	}
2910	664e0f19	bellard	} else {
2911	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2912	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2913	664e0f19	bellard	}
2914	664e0f19	bellard	} else {
2915	664e0f19	bellard	op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
2916	664e0f19	bellard	if (mod != 3) {
2917	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2918	664e0f19	bellard	op2_offset = offsetof(CPUX86State,mmx_t0);
2919	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](op2_offset);
2920	664e0f19	bellard	} else {
2921	664e0f19	bellard	rm = (modrm & 7);
2922	664e0f19	bellard	op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
2923	664e0f19	bellard	}
2924	664e0f19	bellard	}
2925	664e0f19	bellard	switch(b) {
2926	664e0f19	bellard	case 0x70: /* pshufx insn */
2927	664e0f19	bellard	case 0xc6: /* pshufx insn */
2928	664e0f19	bellard	val = ldub_code(s->pc++);
2929	664e0f19	bellard	sse_op3 = (GenOpFunc3 *)sse_op2;
2930	664e0f19	bellard	sse_op3(op1_offset, op2_offset, val);
2931	664e0f19	bellard	break;
2932	664e0f19	bellard	case 0xc2:
2933	664e0f19	bellard	/* compare insns */
2934	664e0f19	bellard	val = ldub_code(s->pc++);
2935	664e0f19	bellard	if (val >= 8)
2936	664e0f19	bellard	goto illegal_op;
2937	664e0f19	bellard	sse_op2 = sse_op_table4[val][b1];
2938	664e0f19	bellard	sse_op2(op1_offset, op2_offset);
2939	664e0f19	bellard	break;
2940	664e0f19	bellard	default:
2941	664e0f19	bellard	sse_op2(op1_offset, op2_offset);
2942	664e0f19	bellard	break;
2943	664e0f19	bellard	}
2944	664e0f19	bellard	if (b == 0x2e \|\| b == 0x2f) {
2945	664e0f19	bellard	s->cc_op = CC_OP_EFLAGS;
2946	664e0f19	bellard	}
2947	664e0f19	bellard	}
2948	664e0f19	bellard	}
2949	664e0f19	bellard
2950	664e0f19	bellard
2951	2c0262af	bellard	/* convert one instruction. s->is_jmp is set if the translation must
2952	2c0262af	bellard	be stopped. Return the next pc value */
2953	14ce26e7	bellard	static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
2954	2c0262af	bellard	{
2955	2c0262af	bellard	int b, prefixes, aflag, dflag;
2956	2c0262af	bellard	int shift, ot;
2957	2c0262af	bellard	int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
2958	14ce26e7	bellard	target_ulong next_eip, tval;
2959	14ce26e7	bellard	int rex_w, rex_r;
2960	2c0262af	bellard
2961	2c0262af	bellard	s->pc = pc_start;
2962	2c0262af	bellard	prefixes = 0;
2963	2c0262af	bellard	aflag = s->code32;
2964	2c0262af	bellard	dflag = s->code32;
2965	2c0262af	bellard	s->override = -1;
2966	14ce26e7	bellard	rex_w = -1;
2967	14ce26e7	bellard	rex_r = 0;
2968	14ce26e7	bellard	#ifdef TARGET_X86_64
2969	14ce26e7	bellard	s->rex_x = 0;
2970	14ce26e7	bellard	s->rex_b = 0;
2971	14ce26e7	bellard	x86_64_hregs = 0;
2972	14ce26e7	bellard	#endif
2973	14ce26e7	bellard	s->rip_offset = 0; /* for relative ip address */
2974	2c0262af	bellard	next_byte:
2975	61382a50	bellard	b = ldub_code(s->pc);
2976	2c0262af	bellard	s->pc++;
2977	2c0262af	bellard	/* check prefixes */
2978	14ce26e7	bellard	#ifdef TARGET_X86_64
2979	14ce26e7	bellard	if (CODE64(s)) {
2980	14ce26e7	bellard	switch (b) {
2981	14ce26e7	bellard	case 0xf3:
2982	14ce26e7	bellard	prefixes \|= PREFIX_REPZ;
2983	14ce26e7	bellard	goto next_byte;
2984	14ce26e7	bellard	case 0xf2:
2985	14ce26e7	bellard	prefixes \|= PREFIX_REPNZ;
2986	14ce26e7	bellard	goto next_byte;
2987	14ce26e7	bellard	case 0xf0:
2988	14ce26e7	bellard	prefixes \|= PREFIX_LOCK;
2989	14ce26e7	bellard	goto next_byte;
2990	14ce26e7	bellard	case 0x2e:
2991	14ce26e7	bellard	s->override = R_CS;
2992	14ce26e7	bellard	goto next_byte;
2993	14ce26e7	bellard	case 0x36:
2994	14ce26e7	bellard	s->override = R_SS;
2995	14ce26e7	bellard	goto next_byte;
2996	14ce26e7	bellard	case 0x3e:
2997	14ce26e7	bellard	s->override = R_DS;
2998	14ce26e7	bellard	goto next_byte;
2999	14ce26e7	bellard	case 0x26:
3000	14ce26e7	bellard	s->override = R_ES;
3001	14ce26e7	bellard	goto next_byte;
3002	14ce26e7	bellard	case 0x64:
3003	14ce26e7	bellard	s->override = R_FS;
3004	14ce26e7	bellard	goto next_byte;
3005	14ce26e7	bellard	case 0x65:
3006	14ce26e7	bellard	s->override = R_GS;
3007	14ce26e7	bellard	goto next_byte;
3008	14ce26e7	bellard	case 0x66:
3009	14ce26e7	bellard	prefixes \|= PREFIX_DATA;
3010	14ce26e7	bellard	goto next_byte;
3011	14ce26e7	bellard	case 0x67:
3012	14ce26e7	bellard	prefixes \|= PREFIX_ADR;
3013	14ce26e7	bellard	goto next_byte;
3014	14ce26e7	bellard	case 0x40 ... 0x4f:
3015	14ce26e7	bellard	/* REX prefix */
3016	14ce26e7	bellard	rex_w = (b >> 3) & 1;
3017	14ce26e7	bellard	rex_r = (b & 0x4) << 1;
3018	14ce26e7	bellard	s->rex_x = (b & 0x2) << 2;
3019	14ce26e7	bellard	REX_B(s) = (b & 0x1) << 3;
3020	14ce26e7	bellard	x86_64_hregs = 1; /* select uniform byte register addressing */
3021	14ce26e7	bellard	goto next_byte;
3022	14ce26e7	bellard	}
3023	14ce26e7	bellard	if (rex_w == 1) {
3024	14ce26e7	bellard	/* 0x66 is ignored if rex.w is set */
3025	14ce26e7	bellard	dflag = 2;
3026	14ce26e7	bellard	} else {
3027	14ce26e7	bellard	if (prefixes & PREFIX_DATA)
3028	14ce26e7	bellard	dflag ^= 1;
3029	14ce26e7	bellard	}
3030	14ce26e7	bellard	if (!(prefixes & PREFIX_ADR))
3031	14ce26e7	bellard	aflag = 2;
3032	14ce26e7	bellard	} else
3033	14ce26e7	bellard	#endif
3034	14ce26e7	bellard	{
3035	14ce26e7	bellard	switch (b) {
3036	14ce26e7	bellard	case 0xf3:
3037	14ce26e7	bellard	prefixes \|= PREFIX_REPZ;
3038	14ce26e7	bellard	goto next_byte;
3039	14ce26e7	bellard	case 0xf2:
3040	14ce26e7	bellard	prefixes \|= PREFIX_REPNZ;
3041	14ce26e7	bellard	goto next_byte;
3042	14ce26e7	bellard	case 0xf0:
3043	14ce26e7	bellard	prefixes \|= PREFIX_LOCK;
3044	14ce26e7	bellard	goto next_byte;
3045	14ce26e7	bellard	case 0x2e:
3046	14ce26e7	bellard	s->override = R_CS;
3047	14ce26e7	bellard	goto next_byte;
3048	14ce26e7	bellard	case 0x36:
3049	14ce26e7	bellard	s->override = R_SS;
3050	14ce26e7	bellard	goto next_byte;
3051	14ce26e7	bellard	case 0x3e:
3052	14ce26e7	bellard	s->override = R_DS;
3053	14ce26e7	bellard	goto next_byte;
3054	14ce26e7	bellard	case 0x26:
3055	14ce26e7	bellard	s->override = R_ES;
3056	14ce26e7	bellard	goto next_byte;
3057	14ce26e7	bellard	case 0x64:
3058	14ce26e7	bellard	s->override = R_FS;
3059	14ce26e7	bellard	goto next_byte;
3060	14ce26e7	bellard	case 0x65:
3061	14ce26e7	bellard	s->override = R_GS;
3062	14ce26e7	bellard	goto next_byte;
3063	14ce26e7	bellard	case 0x66:
3064	14ce26e7	bellard	prefixes \|= PREFIX_DATA;
3065	14ce26e7	bellard	goto next_byte;
3066	14ce26e7	bellard	case 0x67:
3067	14ce26e7	bellard	prefixes \|= PREFIX_ADR;
3068	14ce26e7	bellard	goto next_byte;
3069	14ce26e7	bellard	}
3070	14ce26e7	bellard	if (prefixes & PREFIX_DATA)
3071	14ce26e7	bellard	dflag ^= 1;
3072	14ce26e7	bellard	if (prefixes & PREFIX_ADR)
3073	14ce26e7	bellard	aflag ^= 1;
3074	2c0262af	bellard	}
3075	2c0262af	bellard
3076	2c0262af	bellard	s->prefix = prefixes;
3077	2c0262af	bellard	s->aflag = aflag;
3078	2c0262af	bellard	s->dflag = dflag;
3079	2c0262af	bellard
3080	2c0262af	bellard	/* lock generation */
3081	2c0262af	bellard	if (prefixes & PREFIX_LOCK)
3082	2c0262af	bellard	gen_op_lock();
3083	2c0262af	bellard
3084	2c0262af	bellard	/* now check op code */
3085	2c0262af	bellard	reswitch:
3086	2c0262af	bellard	switch(b) {
3087	2c0262af	bellard	case 0x0f:
3088	2c0262af	bellard	/**************************/
3089	2c0262af	bellard	/* extended op code */
3090	61382a50	bellard	b = ldub_code(s->pc++) \| 0x100;
3091	2c0262af	bellard	goto reswitch;
3092	2c0262af	bellard
3093	2c0262af	bellard	/**************************/
3094	2c0262af	bellard	/* arith & logic */
3095	2c0262af	bellard	case 0x00 ... 0x05:
3096	2c0262af	bellard	case 0x08 ... 0x0d:
3097	2c0262af	bellard	case 0x10 ... 0x15:
3098	2c0262af	bellard	case 0x18 ... 0x1d:
3099	2c0262af	bellard	case 0x20 ... 0x25:
3100	2c0262af	bellard	case 0x28 ... 0x2d:
3101	2c0262af	bellard	case 0x30 ... 0x35:
3102	2c0262af	bellard	case 0x38 ... 0x3d:
3103	2c0262af	bellard	{
3104	2c0262af	bellard	int op, f, val;
3105	2c0262af	bellard	op = (b >> 3) & 7;
3106	2c0262af	bellard	f = (b >> 1) & 3;
3107	2c0262af	bellard
3108	2c0262af	bellard	if ((b & 1) == 0)
3109	2c0262af	bellard	ot = OT_BYTE;
3110	2c0262af	bellard	else
3111	14ce26e7	bellard	ot = dflag + OT_WORD;
3112	2c0262af	bellard
3113	2c0262af	bellard	switch(f) {
3114	2c0262af	bellard	case 0: /* OP Ev, Gv */
3115	61382a50	bellard	modrm = ldub_code(s->pc++);
3116	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3117	2c0262af	bellard	mod = (modrm >> 6) & 3;
3118	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3119	2c0262af	bellard	if (mod != 3) {
3120	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3121	2c0262af	bellard	opreg = OR_TMP0;
3122	2c0262af	bellard	} else if (op == OP_XORL && rm == reg) {
3123	2c0262af	bellard	xor_zero:
3124	2c0262af	bellard	/* xor reg, reg optimisation */
3125	2c0262af	bellard	gen_op_movl_T0_0();
3126	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3127	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
3128	2c0262af	bellard	gen_op_update1_cc();
3129	2c0262af	bellard	break;
3130	2c0262af	bellard	} else {
3131	2c0262af	bellard	opreg = rm;
3132	2c0262af	bellard	}
3133	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3134	2c0262af	bellard	gen_op(s, op, ot, opreg);
3135	2c0262af	bellard	break;
3136	2c0262af	bellard	case 1: /* OP Gv, Ev */
3137	61382a50	bellard	modrm = ldub_code(s->pc++);
3138	2c0262af	bellard	mod = (modrm >> 6) & 3;
3139	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3140	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3141	2c0262af	bellard	if (mod != 3) {
3142	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3143	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3144	2c0262af	bellard	} else if (op == OP_XORL && rm == reg) {
3145	2c0262af	bellard	goto xor_zero;
3146	2c0262af	bellard	} else {
3147	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
3148	2c0262af	bellard	}
3149	2c0262af	bellard	gen_op(s, op, ot, reg);
3150	2c0262af	bellard	break;
3151	2c0262af	bellard	case 2: /* OP A, Iv */
3152	2c0262af	bellard	val = insn_get(s, ot);
3153	2c0262af	bellard	gen_op_movl_T1_im(val);
3154	2c0262af	bellard	gen_op(s, op, ot, OR_EAX);
3155	2c0262af	bellard	break;
3156	2c0262af	bellard	}
3157	2c0262af	bellard	}
3158	2c0262af	bellard	break;
3159	2c0262af	bellard
3160	2c0262af	bellard	case 0x80: /* GRP1 */
3161	2c0262af	bellard	case 0x81:
3162	d64477af	bellard	case 0x82:
3163	2c0262af	bellard	case 0x83:
3164	2c0262af	bellard	{
3165	2c0262af	bellard	int val;
3166	2c0262af	bellard
3167	2c0262af	bellard	if ((b & 1) == 0)
3168	2c0262af	bellard	ot = OT_BYTE;
3169	2c0262af	bellard	else
3170	14ce26e7	bellard	ot = dflag + OT_WORD;
3171	2c0262af	bellard
3172	61382a50	bellard	modrm = ldub_code(s->pc++);
3173	2c0262af	bellard	mod = (modrm >> 6) & 3;
3174	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3175	2c0262af	bellard	op = (modrm >> 3) & 7;
3176	2c0262af	bellard
3177	2c0262af	bellard	if (mod != 3) {
3178	14ce26e7	bellard	if (b == 0x83)
3179	14ce26e7	bellard	s->rip_offset = 1;
3180	14ce26e7	bellard	else
3181	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3182	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3183	2c0262af	bellard	opreg = OR_TMP0;
3184	2c0262af	bellard	} else {
3185	14ce26e7	bellard	opreg = rm;
3186	2c0262af	bellard	}
3187	2c0262af	bellard
3188	2c0262af	bellard	switch(b) {
3189	2c0262af	bellard	default:
3190	2c0262af	bellard	case 0x80:
3191	2c0262af	bellard	case 0x81:
3192	d64477af	bellard	case 0x82:
3193	2c0262af	bellard	val = insn_get(s, ot);
3194	2c0262af	bellard	break;
3195	2c0262af	bellard	case 0x83:
3196	2c0262af	bellard	val = (int8_t)insn_get(s, OT_BYTE);
3197	2c0262af	bellard	break;
3198	2c0262af	bellard	}
3199	2c0262af	bellard	gen_op_movl_T1_im(val);
3200	2c0262af	bellard	gen_op(s, op, ot, opreg);
3201	2c0262af	bellard	}
3202	2c0262af	bellard	break;
3203	2c0262af	bellard
3204	2c0262af	bellard	/**************************/
3205	2c0262af	bellard	/* inc, dec, and other misc arith */
3206	2c0262af	bellard	case 0x40 ... 0x47: /* inc Gv */
3207	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
3208	2c0262af	bellard	gen_inc(s, ot, OR_EAX + (b & 7), 1);
3209	2c0262af	bellard	break;
3210	2c0262af	bellard	case 0x48 ... 0x4f: /* dec Gv */
3211	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
3212	2c0262af	bellard	gen_inc(s, ot, OR_EAX + (b & 7), -1);
3213	2c0262af	bellard	break;
3214	2c0262af	bellard	case 0xf6: /* GRP3 */
3215	2c0262af	bellard	case 0xf7:
3216	2c0262af	bellard	if ((b & 1) == 0)
3217	2c0262af	bellard	ot = OT_BYTE;
3218	2c0262af	bellard	else
3219	14ce26e7	bellard	ot = dflag + OT_WORD;
3220	2c0262af	bellard
3221	61382a50	bellard	modrm = ldub_code(s->pc++);
3222	2c0262af	bellard	mod = (modrm >> 6) & 3;
3223	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3224	2c0262af	bellard	op = (modrm >> 3) & 7;
3225	2c0262af	bellard	if (mod != 3) {
3226	14ce26e7	bellard	if (op == 0)
3227	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3228	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3229	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3230	2c0262af	bellard	} else {
3231	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3232	2c0262af	bellard	}
3233	2c0262af	bellard
3234	2c0262af	bellard	switch(op) {
3235	2c0262af	bellard	case 0: /* test */
3236	2c0262af	bellard	val = insn_get(s, ot);
3237	2c0262af	bellard	gen_op_movl_T1_im(val);
3238	2c0262af	bellard	gen_op_testl_T0_T1_cc();
3239	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3240	2c0262af	bellard	break;
3241	2c0262af	bellard	case 2: /* not */
3242	2c0262af	bellard	gen_op_notl_T0();
3243	2c0262af	bellard	if (mod != 3) {
3244	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3245	2c0262af	bellard	} else {
3246	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
3247	2c0262af	bellard	}
3248	2c0262af	bellard	break;
3249	2c0262af	bellard	case 3: /* neg */
3250	2c0262af	bellard	gen_op_negl_T0();
3251	2c0262af	bellard	if (mod != 3) {
3252	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3253	2c0262af	bellard	} else {
3254	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
3255	2c0262af	bellard	}
3256	2c0262af	bellard	gen_op_update_neg_cc();
3257	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
3258	2c0262af	bellard	break;
3259	2c0262af	bellard	case 4: /* mul */
3260	2c0262af	bellard	switch(ot) {
3261	2c0262af	bellard	case OT_BYTE:
3262	2c0262af	bellard	gen_op_mulb_AL_T0();
3263	d36cd60e	bellard	s->cc_op = CC_OP_MULB;
3264	2c0262af	bellard	break;
3265	2c0262af	bellard	case OT_WORD:
3266	2c0262af	bellard	gen_op_mulw_AX_T0();
3267	d36cd60e	bellard	s->cc_op = CC_OP_MULW;
3268	2c0262af	bellard	break;
3269	2c0262af	bellard	default:
3270	2c0262af	bellard	case OT_LONG:
3271	2c0262af	bellard	gen_op_mull_EAX_T0();
3272	d36cd60e	bellard	s->cc_op = CC_OP_MULL;
3273	2c0262af	bellard	break;
3274	14ce26e7	bellard	#ifdef TARGET_X86_64
3275	14ce26e7	bellard	case OT_QUAD:
3276	14ce26e7	bellard	gen_op_mulq_EAX_T0();
3277	14ce26e7	bellard	s->cc_op = CC_OP_MULQ;
3278	14ce26e7	bellard	break;
3279	14ce26e7	bellard	#endif
3280	2c0262af	bellard	}
3281	2c0262af	bellard	break;
3282	2c0262af	bellard	case 5: /* imul */
3283	2c0262af	bellard	switch(ot) {
3284	2c0262af	bellard	case OT_BYTE:
3285	2c0262af	bellard	gen_op_imulb_AL_T0();
3286	d36cd60e	bellard	s->cc_op = CC_OP_MULB;
3287	2c0262af	bellard	break;
3288	2c0262af	bellard	case OT_WORD:
3289	2c0262af	bellard	gen_op_imulw_AX_T0();
3290	d36cd60e	bellard	s->cc_op = CC_OP_MULW;
3291	2c0262af	bellard	break;
3292	2c0262af	bellard	default:
3293	2c0262af	bellard	case OT_LONG:
3294	2c0262af	bellard	gen_op_imull_EAX_T0();
3295	d36cd60e	bellard	s->cc_op = CC_OP_MULL;
3296	2c0262af	bellard	break;
3297	14ce26e7	bellard	#ifdef TARGET_X86_64
3298	14ce26e7	bellard	case OT_QUAD:
3299	14ce26e7	bellard	gen_op_imulq_EAX_T0();
3300	14ce26e7	bellard	s->cc_op = CC_OP_MULQ;
3301	14ce26e7	bellard	break;
3302	14ce26e7	bellard	#endif
3303	2c0262af	bellard	}
3304	2c0262af	bellard	break;
3305	2c0262af	bellard	case 6: /* div */
3306	2c0262af	bellard	switch(ot) {
3307	2c0262af	bellard	case OT_BYTE:
3308	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3309	14ce26e7	bellard	gen_op_divb_AL_T0();
3310	2c0262af	bellard	break;
3311	2c0262af	bellard	case OT_WORD:
3312	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3313	14ce26e7	bellard	gen_op_divw_AX_T0();
3314	2c0262af	bellard	break;
3315	2c0262af	bellard	default:
3316	2c0262af	bellard	case OT_LONG:
3317	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3318	14ce26e7	bellard	gen_op_divl_EAX_T0();
3319	14ce26e7	bellard	break;
3320	14ce26e7	bellard	#ifdef TARGET_X86_64
3321	14ce26e7	bellard	case OT_QUAD:
3322	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3323	14ce26e7	bellard	gen_op_divq_EAX_T0();
3324	2c0262af	bellard	break;
3325	14ce26e7	bellard	#endif
3326	2c0262af	bellard	}
3327	2c0262af	bellard	break;
3328	2c0262af	bellard	case 7: /* idiv */
3329	2c0262af	bellard	switch(ot) {
3330	2c0262af	bellard	case OT_BYTE:
3331	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3332	14ce26e7	bellard	gen_op_idivb_AL_T0();
3333	2c0262af	bellard	break;
3334	2c0262af	bellard	case OT_WORD:
3335	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3336	14ce26e7	bellard	gen_op_idivw_AX_T0();
3337	2c0262af	bellard	break;
3338	2c0262af	bellard	default:
3339	2c0262af	bellard	case OT_LONG:
3340	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3341	14ce26e7	bellard	gen_op_idivl_EAX_T0();
3342	14ce26e7	bellard	break;
3343	14ce26e7	bellard	#ifdef TARGET_X86_64
3344	14ce26e7	bellard	case OT_QUAD:
3345	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3346	14ce26e7	bellard	gen_op_idivq_EAX_T0();
3347	2c0262af	bellard	break;
3348	14ce26e7	bellard	#endif
3349	2c0262af	bellard	}
3350	2c0262af	bellard	break;
3351	2c0262af	bellard	default:
3352	2c0262af	bellard	goto illegal_op;
3353	2c0262af	bellard	}
3354	2c0262af	bellard	break;
3355	2c0262af	bellard
3356	2c0262af	bellard	case 0xfe: /* GRP4 */
3357	2c0262af	bellard	case 0xff: /* GRP5 */
3358	2c0262af	bellard	if ((b & 1) == 0)
3359	2c0262af	bellard	ot = OT_BYTE;
3360	2c0262af	bellard	else
3361	14ce26e7	bellard	ot = dflag + OT_WORD;
3362	2c0262af	bellard
3363	61382a50	bellard	modrm = ldub_code(s->pc++);
3364	2c0262af	bellard	mod = (modrm >> 6) & 3;
3365	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3366	2c0262af	bellard	op = (modrm >> 3) & 7;
3367	2c0262af	bellard	if (op >= 2 && b == 0xfe) {
3368	2c0262af	bellard	goto illegal_op;
3369	2c0262af	bellard	}
3370	14ce26e7	bellard	if (CODE64(s)) {
3371	14ce26e7	bellard	if (op >= 2 && op <= 5) {
3372	14ce26e7	bellard	/* operand size for jumps is 64 bit */
3373	14ce26e7	bellard	ot = OT_QUAD;
3374	14ce26e7	bellard	} else if (op == 6) {
3375	14ce26e7	bellard	/* default push size is 64 bit */
3376	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3377	14ce26e7	bellard	}
3378	14ce26e7	bellard	}
3379	2c0262af	bellard	if (mod != 3) {
3380	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3381	2c0262af	bellard	if (op >= 2 && op != 3 && op != 5)
3382	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3383	2c0262af	bellard	} else {
3384	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3385	2c0262af	bellard	}
3386	2c0262af	bellard
3387	2c0262af	bellard	switch(op) {
3388	2c0262af	bellard	case 0: /* inc Ev */
3389	2c0262af	bellard	if (mod != 3)
3390	2c0262af	bellard	opreg = OR_TMP0;
3391	2c0262af	bellard	else
3392	2c0262af	bellard	opreg = rm;
3393	2c0262af	bellard	gen_inc(s, ot, opreg, 1);
3394	2c0262af	bellard	break;
3395	2c0262af	bellard	case 1: /* dec Ev */
3396	2c0262af	bellard	if (mod != 3)
3397	2c0262af	bellard	opreg = OR_TMP0;
3398	2c0262af	bellard	else
3399	2c0262af	bellard	opreg = rm;
3400	2c0262af	bellard	gen_inc(s, ot, opreg, -1);
3401	2c0262af	bellard	break;
3402	2c0262af	bellard	case 2: /* call Ev */
3403	4f31916f	bellard	/* XXX: optimize if memory (no 'and' is necessary) */
3404	2c0262af	bellard	if (s->dflag == 0)
3405	2c0262af	bellard	gen_op_andl_T0_ffff();
3406	2c0262af	bellard	next_eip = s->pc - s->cs_base;
3407	1ef38687	bellard	gen_movtl_T1_im(next_eip);
3408	4f31916f	bellard	gen_push_T1(s);
3409	4f31916f	bellard	gen_op_jmp_T0();
3410	2c0262af	bellard	gen_eob(s);
3411	2c0262af	bellard	break;
3412	61382a50	bellard	case 3: /* lcall Ev */
3413	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3414	2c0262af	bellard	gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
3415	61382a50	bellard	gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
3416	2c0262af	bellard	do_lcall:
3417	2c0262af	bellard	if (s->pe && !s->vm86) {
3418	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
3419	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
3420	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3421	2c0262af	bellard	gen_op_lcall_protected_T0_T1(dflag, s->pc - s->cs_base);
3422	2c0262af	bellard	} else {
3423	2c0262af	bellard	gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
3424	2c0262af	bellard	}
3425	2c0262af	bellard	gen_eob(s);
3426	2c0262af	bellard	break;
3427	2c0262af	bellard	case 4: /* jmp Ev */
3428	2c0262af	bellard	if (s->dflag == 0)
3429	2c0262af	bellard	gen_op_andl_T0_ffff();
3430	2c0262af	bellard	gen_op_jmp_T0();
3431	2c0262af	bellard	gen_eob(s);
3432	2c0262af	bellard	break;
3433	2c0262af	bellard	case 5: /* ljmp Ev */
3434	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3435	2c0262af	bellard	gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
3436	61382a50	bellard	gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
3437	2c0262af	bellard	do_ljmp:
3438	2c0262af	bellard	if (s->pe && !s->vm86) {
3439	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
3440	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
3441	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3442	08cea4ee	bellard	gen_op_ljmp_protected_T0_T1(s->pc - s->cs_base);
3443	2c0262af	bellard	} else {
3444	2c0262af	bellard	gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3445	2c0262af	bellard	gen_op_movl_T0_T1();
3446	2c0262af	bellard	gen_op_jmp_T0();
3447	2c0262af	bellard	}
3448	2c0262af	bellard	gen_eob(s);
3449	2c0262af	bellard	break;
3450	2c0262af	bellard	case 6: /* push Ev */
3451	2c0262af	bellard	gen_push_T0(s);
3452	2c0262af	bellard	break;
3453	2c0262af	bellard	default:
3454	2c0262af	bellard	goto illegal_op;
3455	2c0262af	bellard	}
3456	2c0262af	bellard	break;
3457	2c0262af	bellard
3458	2c0262af	bellard	case 0x84: /* test Ev, Gv */
3459	2c0262af	bellard	case 0x85:
3460	2c0262af	bellard	if ((b & 1) == 0)
3461	2c0262af	bellard	ot = OT_BYTE;
3462	2c0262af	bellard	else
3463	14ce26e7	bellard	ot = dflag + OT_WORD;
3464	2c0262af	bellard
3465	61382a50	bellard	modrm = ldub_code(s->pc++);
3466	2c0262af	bellard	mod = (modrm >> 6) & 3;
3467	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3468	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3469	2c0262af	bellard
3470	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3471	14ce26e7	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3472	2c0262af	bellard	gen_op_testl_T0_T1_cc();
3473	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3474	2c0262af	bellard	break;
3475	2c0262af	bellard
3476	2c0262af	bellard	case 0xa8: /* test eAX, Iv */
3477	2c0262af	bellard	case 0xa9:
3478	2c0262af	bellard	if ((b & 1) == 0)
3479	2c0262af	bellard	ot = OT_BYTE;
3480	2c0262af	bellard	else
3481	14ce26e7	bellard	ot = dflag + OT_WORD;
3482	2c0262af	bellard	val = insn_get(s, ot);
3483	2c0262af	bellard
3484	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][OR_EAX]();
3485	2c0262af	bellard	gen_op_movl_T1_im(val);
3486	2c0262af	bellard	gen_op_testl_T0_T1_cc();
3487	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3488	2c0262af	bellard	break;
3489	2c0262af	bellard
3490	2c0262af	bellard	case 0x98: /* CWDE/CBW */
3491	14ce26e7	bellard	#ifdef TARGET_X86_64
3492	14ce26e7	bellard	if (dflag == 2) {
3493	14ce26e7	bellard	gen_op_movslq_RAX_EAX();
3494	14ce26e7	bellard	} else
3495	14ce26e7	bellard	#endif
3496	14ce26e7	bellard	if (dflag == 1)
3497	2c0262af	bellard	gen_op_movswl_EAX_AX();
3498	2c0262af	bellard	else
3499	2c0262af	bellard	gen_op_movsbw_AX_AL();
3500	2c0262af	bellard	break;
3501	2c0262af	bellard	case 0x99: /* CDQ/CWD */
3502	14ce26e7	bellard	#ifdef TARGET_X86_64
3503	14ce26e7	bellard	if (dflag == 2) {
3504	14ce26e7	bellard	gen_op_movsqo_RDX_RAX();
3505	14ce26e7	bellard	} else
3506	14ce26e7	bellard	#endif
3507	14ce26e7	bellard	if (dflag == 1)
3508	2c0262af	bellard	gen_op_movslq_EDX_EAX();
3509	2c0262af	bellard	else
3510	2c0262af	bellard	gen_op_movswl_DX_AX();
3511	2c0262af	bellard	break;
3512	2c0262af	bellard	case 0x1af: /* imul Gv, Ev */
3513	2c0262af	bellard	case 0x69: /* imul Gv, Ev, I */
3514	2c0262af	bellard	case 0x6b:
3515	14ce26e7	bellard	ot = dflag + OT_WORD;
3516	61382a50	bellard	modrm = ldub_code(s->pc++);
3517	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3518	14ce26e7	bellard	if (b == 0x69)
3519	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3520	14ce26e7	bellard	else if (b == 0x6b)
3521	14ce26e7	bellard	s->rip_offset = 1;
3522	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3523	2c0262af	bellard	if (b == 0x69) {
3524	2c0262af	bellard	val = insn_get(s, ot);
3525	2c0262af	bellard	gen_op_movl_T1_im(val);
3526	2c0262af	bellard	} else if (b == 0x6b) {
3527	d64477af	bellard	val = (int8_t)insn_get(s, OT_BYTE);
3528	2c0262af	bellard	gen_op_movl_T1_im(val);
3529	2c0262af	bellard	} else {
3530	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3531	2c0262af	bellard	}
3532	2c0262af	bellard
3533	14ce26e7	bellard	#ifdef TARGET_X86_64
3534	14ce26e7	bellard	if (ot == OT_QUAD) {
3535	14ce26e7	bellard	gen_op_imulq_T0_T1();
3536	14ce26e7	bellard	} else
3537	14ce26e7	bellard	#endif
3538	2c0262af	bellard	if (ot == OT_LONG) {
3539	2c0262af	bellard	gen_op_imull_T0_T1();
3540	2c0262af	bellard	} else {
3541	2c0262af	bellard	gen_op_imulw_T0_T1();
3542	2c0262af	bellard	}
3543	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
3544	d36cd60e	bellard	s->cc_op = CC_OP_MULB + ot;
3545	2c0262af	bellard	break;
3546	2c0262af	bellard	case 0x1c0:
3547	2c0262af	bellard	case 0x1c1: /* xadd Ev, Gv */
3548	2c0262af	bellard	if ((b & 1) == 0)
3549	2c0262af	bellard	ot = OT_BYTE;
3550	2c0262af	bellard	else
3551	14ce26e7	bellard	ot = dflag + OT_WORD;
3552	61382a50	bellard	modrm = ldub_code(s->pc++);
3553	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3554	2c0262af	bellard	mod = (modrm >> 6) & 3;
3555	2c0262af	bellard	if (mod == 3) {
3556	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3557	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
3558	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
3559	2c0262af	bellard	gen_op_addl_T0_T1();
3560	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
3561	5a1388b6	bellard	gen_op_mov_reg_T0[ot][rm]();
3562	2c0262af	bellard	} else {
3563	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3564	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
3565	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3566	2c0262af	bellard	gen_op_addl_T0_T1();
3567	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3568	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
3569	2c0262af	bellard	}
3570	2c0262af	bellard	gen_op_update2_cc();
3571	2c0262af	bellard	s->cc_op = CC_OP_ADDB + ot;
3572	2c0262af	bellard	break;
3573	2c0262af	bellard	case 0x1b0:
3574	2c0262af	bellard	case 0x1b1: /* cmpxchg Ev, Gv */
3575	2c0262af	bellard	if ((b & 1) == 0)
3576	2c0262af	bellard	ot = OT_BYTE;
3577	2c0262af	bellard	else
3578	14ce26e7	bellard	ot = dflag + OT_WORD;
3579	61382a50	bellard	modrm = ldub_code(s->pc++);
3580	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3581	2c0262af	bellard	mod = (modrm >> 6) & 3;
3582	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3583	2c0262af	bellard	if (mod == 3) {
3584	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3585	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3586	2c0262af	bellard	gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
3587	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
3588	2c0262af	bellard	} else {
3589	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3590	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3591	4f31916f	bellard	gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot + s->mem_index]();
3592	2c0262af	bellard	}
3593	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
3594	2c0262af	bellard	break;
3595	2c0262af	bellard	case 0x1c7: /* cmpxchg8b */
3596	61382a50	bellard	modrm = ldub_code(s->pc++);
3597	2c0262af	bellard	mod = (modrm >> 6) & 3;
3598	2c0262af	bellard	if (mod == 3)
3599	2c0262af	bellard	goto illegal_op;
3600	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
3601	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
3602	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3603	2c0262af	bellard	gen_op_cmpxchg8b();
3604	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
3605	2c0262af	bellard	break;
3606	2c0262af	bellard
3607	2c0262af	bellard	/**************************/
3608	2c0262af	bellard	/* push/pop */
3609	2c0262af	bellard	case 0x50 ... 0x57: /* push */
3610	14ce26e7	bellard	gen_op_mov_TN_reg[OT_LONG][0][(b & 7) \| REX_B(s)]();
3611	2c0262af	bellard	gen_push_T0(s);
3612	2c0262af	bellard	break;
3613	2c0262af	bellard	case 0x58 ... 0x5f: /* pop */
3614	14ce26e7	bellard	if (CODE64(s)) {
3615	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3616	14ce26e7	bellard	} else {
3617	14ce26e7	bellard	ot = dflag + OT_WORD;
3618	14ce26e7	bellard	}
3619	2c0262af	bellard	gen_pop_T0(s);
3620	77729c24	bellard	/* NOTE: order is important for pop %sp */
3621	2c0262af	bellard	gen_pop_update(s);
3622	14ce26e7	bellard	gen_op_mov_reg_T0[ot][(b & 7) \| REX_B(s)]();
3623	2c0262af	bellard	break;
3624	2c0262af	bellard	case 0x60: /* pusha */
3625	14ce26e7	bellard	if (CODE64(s))
3626	14ce26e7	bellard	goto illegal_op;
3627	2c0262af	bellard	gen_pusha(s);
3628	2c0262af	bellard	break;
3629	2c0262af	bellard	case 0x61: /* popa */
3630	14ce26e7	bellard	if (CODE64(s))
3631	14ce26e7	bellard	goto illegal_op;
3632	2c0262af	bellard	gen_popa(s);
3633	2c0262af	bellard	break;
3634	2c0262af	bellard	case 0x68: /* push Iv */
3635	2c0262af	bellard	case 0x6a:
3636	14ce26e7	bellard	if (CODE64(s)) {
3637	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3638	14ce26e7	bellard	} else {
3639	14ce26e7	bellard	ot = dflag + OT_WORD;
3640	14ce26e7	bellard	}
3641	2c0262af	bellard	if (b == 0x68)
3642	2c0262af	bellard	val = insn_get(s, ot);
3643	2c0262af	bellard	else
3644	2c0262af	bellard	val = (int8_t)insn_get(s, OT_BYTE);
3645	2c0262af	bellard	gen_op_movl_T0_im(val);
3646	2c0262af	bellard	gen_push_T0(s);
3647	2c0262af	bellard	break;
3648	2c0262af	bellard	case 0x8f: /* pop Ev */
3649	14ce26e7	bellard	if (CODE64(s)) {
3650	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3651	14ce26e7	bellard	} else {
3652	14ce26e7	bellard	ot = dflag + OT_WORD;
3653	14ce26e7	bellard	}
3654	61382a50	bellard	modrm = ldub_code(s->pc++);
3655	77729c24	bellard	mod = (modrm >> 6) & 3;
3656	2c0262af	bellard	gen_pop_T0(s);
3657	77729c24	bellard	if (mod == 3) {
3658	77729c24	bellard	/* NOTE: order is important for pop %sp */
3659	77729c24	bellard	gen_pop_update(s);
3660	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3661	77729c24	bellard	gen_op_mov_reg_T0[ot][rm]();
3662	77729c24	bellard	} else {
3663	77729c24	bellard	/* NOTE: order is important too for MMU exceptions */
3664	14ce26e7	bellard	s->popl_esp_hack = 1 << ot;
3665	77729c24	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3666	77729c24	bellard	s->popl_esp_hack = 0;
3667	77729c24	bellard	gen_pop_update(s);
3668	77729c24	bellard	}
3669	2c0262af	bellard	break;
3670	2c0262af	bellard	case 0xc8: /* enter */
3671	2c0262af	bellard	{
3672	14ce26e7	bellard	/* XXX: long mode support */
3673	2c0262af	bellard	int level;
3674	61382a50	bellard	val = lduw_code(s->pc);
3675	2c0262af	bellard	s->pc += 2;
3676	61382a50	bellard	level = ldub_code(s->pc++);
3677	2c0262af	bellard	gen_enter(s, val, level);
3678	2c0262af	bellard	}
3679	2c0262af	bellard	break;
3680	2c0262af	bellard	case 0xc9: /* leave */
3681	2c0262af	bellard	/* XXX: exception not precise (ESP is updated before potential exception) */
3682	14ce26e7	bellard	/* XXX: may be invalid for 16 bit in long mode */
3683	14ce26e7	bellard	if (CODE64(s)) {
3684	14ce26e7	bellard	gen_op_mov_TN_reg[OT_QUAD][0][R_EBP]();
3685	14ce26e7	bellard	gen_op_mov_reg_T0[OT_QUAD][R_ESP]();
3686	14ce26e7	bellard	} else if (s->ss32) {
3687	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
3688	2c0262af	bellard	gen_op_mov_reg_T0[OT_LONG][R_ESP]();
3689	2c0262af	bellard	} else {
3690	2c0262af	bellard	gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
3691	2c0262af	bellard	gen_op_mov_reg_T0[OT_WORD][R_ESP]();
3692	2c0262af	bellard	}
3693	2c0262af	bellard	gen_pop_T0(s);
3694	14ce26e7	bellard	if (CODE64(s)) {
3695	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3696	14ce26e7	bellard	} else {
3697	14ce26e7	bellard	ot = dflag + OT_WORD;
3698	14ce26e7	bellard	}
3699	2c0262af	bellard	gen_op_mov_reg_T0[ot][R_EBP]();
3700	2c0262af	bellard	gen_pop_update(s);
3701	2c0262af	bellard	break;
3702	2c0262af	bellard	case 0x06: /* push es */
3703	2c0262af	bellard	case 0x0e: /* push cs */
3704	2c0262af	bellard	case 0x16: /* push ss */
3705	2c0262af	bellard	case 0x1e: /* push ds */
3706	14ce26e7	bellard	if (CODE64(s))
3707	14ce26e7	bellard	goto illegal_op;
3708	2c0262af	bellard	gen_op_movl_T0_seg(b >> 3);
3709	2c0262af	bellard	gen_push_T0(s);
3710	2c0262af	bellard	break;
3711	2c0262af	bellard	case 0x1a0: /* push fs */
3712	2c0262af	bellard	case 0x1a8: /* push gs */
3713	2c0262af	bellard	gen_op_movl_T0_seg((b >> 3) & 7);
3714	2c0262af	bellard	gen_push_T0(s);
3715	2c0262af	bellard	break;
3716	2c0262af	bellard	case 0x07: /* pop es */
3717	2c0262af	bellard	case 0x17: /* pop ss */
3718	2c0262af	bellard	case 0x1f: /* pop ds */
3719	14ce26e7	bellard	if (CODE64(s))
3720	14ce26e7	bellard	goto illegal_op;
3721	2c0262af	bellard	reg = b >> 3;
3722	2c0262af	bellard	gen_pop_T0(s);
3723	2c0262af	bellard	gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
3724	2c0262af	bellard	gen_pop_update(s);
3725	2c0262af	bellard	if (reg == R_SS) {
3726	a2cc3b24	bellard	/* if reg == SS, inhibit interrupts/trace. */
3727	a2cc3b24	bellard	/* If several instructions disable interrupts, only the
3728	a2cc3b24	bellard	_first_ does it */
3729	a2cc3b24	bellard	if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3730	a2cc3b24	bellard	gen_op_set_inhibit_irq();
3731	2c0262af	bellard	s->tf = 0;
3732	2c0262af	bellard	}
3733	2c0262af	bellard	if (s->is_jmp) {
3734	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
3735	2c0262af	bellard	gen_eob(s);
3736	2c0262af	bellard	}
3737	2c0262af	bellard	break;
3738	2c0262af	bellard	case 0x1a1: /* pop fs */
3739	2c0262af	bellard	case 0x1a9: /* pop gs */
3740	2c0262af	bellard	gen_pop_T0(s);
3741	2c0262af	bellard	gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
3742	2c0262af	bellard	gen_pop_update(s);
3743	2c0262af	bellard	if (s->is_jmp) {
3744	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
3745	2c0262af	bellard	gen_eob(s);
3746	2c0262af	bellard	}
3747	2c0262af	bellard	break;
3748	2c0262af	bellard
3749	2c0262af	bellard	/**************************/
3750	2c0262af	bellard	/* mov */
3751	2c0262af	bellard	case 0x88:
3752	2c0262af	bellard	case 0x89: /* mov Gv, Ev */
3753	2c0262af	bellard	if ((b & 1) == 0)
3754	2c0262af	bellard	ot = OT_BYTE;
3755	2c0262af	bellard	else
3756	14ce26e7	bellard	ot = dflag + OT_WORD;
3757	61382a50	bellard	modrm = ldub_code(s->pc++);
3758	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3759	2c0262af	bellard
3760	2c0262af	bellard	/* generate a generic store */
3761	14ce26e7	bellard	gen_ldst_modrm(s, modrm, ot, reg, 1);
3762	2c0262af	bellard	break;
3763	2c0262af	bellard	case 0xc6:
3764	2c0262af	bellard	case 0xc7: /* mov Ev, Iv */
3765	2c0262af	bellard	if ((b & 1) == 0)
3766	2c0262af	bellard	ot = OT_BYTE;
3767	2c0262af	bellard	else
3768	14ce26e7	bellard	ot = dflag + OT_WORD;
3769	61382a50	bellard	modrm = ldub_code(s->pc++);
3770	2c0262af	bellard	mod = (modrm >> 6) & 3;
3771	14ce26e7	bellard	if (mod != 3) {
3772	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3773	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3774	14ce26e7	bellard	}
3775	2c0262af	bellard	val = insn_get(s, ot);
3776	2c0262af	bellard	gen_op_movl_T0_im(val);
3777	2c0262af	bellard	if (mod != 3)
3778	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3779	2c0262af	bellard	else
3780	14ce26e7	bellard	gen_op_mov_reg_T0[ot][(modrm & 7) \| REX_B(s)]();
3781	2c0262af	bellard	break;
3782	2c0262af	bellard	case 0x8a:
3783	2c0262af	bellard	case 0x8b: /* mov Ev, Gv */
3784	2c0262af	bellard	if ((b & 1) == 0)
3785	2c0262af	bellard	ot = OT_BYTE;
3786	2c0262af	bellard	else
3787	14ce26e7	bellard	ot = OT_WORD + dflag;
3788	61382a50	bellard	modrm = ldub_code(s->pc++);
3789	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3790	2c0262af	bellard
3791	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3792	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
3793	2c0262af	bellard	break;
3794	2c0262af	bellard	case 0x8e: /* mov seg, Gv */
3795	61382a50	bellard	modrm = ldub_code(s->pc++);
3796	2c0262af	bellard	reg = (modrm >> 3) & 7;
3797	2c0262af	bellard	if (reg >= 6 \|\| reg == R_CS)
3798	2c0262af	bellard	goto illegal_op;
3799	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3800	2c0262af	bellard	gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
3801	2c0262af	bellard	if (reg == R_SS) {
3802	2c0262af	bellard	/* if reg == SS, inhibit interrupts/trace */
3803	a2cc3b24	bellard	/* If several instructions disable interrupts, only the
3804	a2cc3b24	bellard	_first_ does it */
3805	a2cc3b24	bellard	if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3806	a2cc3b24	bellard	gen_op_set_inhibit_irq();
3807	2c0262af	bellard	s->tf = 0;
3808	2c0262af	bellard	}
3809	2c0262af	bellard	if (s->is_jmp) {
3810	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
3811	2c0262af	bellard	gen_eob(s);
3812	2c0262af	bellard	}
3813	2c0262af	bellard	break;
3814	2c0262af	bellard	case 0x8c: /* mov Gv, seg */
3815	61382a50	bellard	modrm = ldub_code(s->pc++);
3816	2c0262af	bellard	reg = (modrm >> 3) & 7;
3817	2c0262af	bellard	mod = (modrm >> 6) & 3;
3818	2c0262af	bellard	if (reg >= 6)
3819	2c0262af	bellard	goto illegal_op;
3820	2c0262af	bellard	gen_op_movl_T0_seg(reg);
3821	14ce26e7	bellard	if (mod == 3)
3822	14ce26e7	bellard	ot = OT_WORD + dflag;
3823	14ce26e7	bellard	else
3824	14ce26e7	bellard	ot = OT_WORD;
3825	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3826	2c0262af	bellard	break;
3827	2c0262af	bellard
3828	2c0262af	bellard	case 0x1b6: /* movzbS Gv, Eb */
3829	2c0262af	bellard	case 0x1b7: /* movzwS Gv, Eb */
3830	2c0262af	bellard	case 0x1be: /* movsbS Gv, Eb */
3831	2c0262af	bellard	case 0x1bf: /* movswS Gv, Eb */
3832	2c0262af	bellard	{
3833	2c0262af	bellard	int d_ot;
3834	2c0262af	bellard	/* d_ot is the size of destination */
3835	2c0262af	bellard	d_ot = dflag + OT_WORD;
3836	2c0262af	bellard	/* ot is the size of source */
3837	2c0262af	bellard	ot = (b & 1) + OT_BYTE;
3838	61382a50	bellard	modrm = ldub_code(s->pc++);
3839	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3840	2c0262af	bellard	mod = (modrm >> 6) & 3;
3841	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3842	2c0262af	bellard
3843	2c0262af	bellard	if (mod == 3) {
3844	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3845	2c0262af	bellard	switch(ot \| (b & 8)) {
3846	2c0262af	bellard	case OT_BYTE:
3847	2c0262af	bellard	gen_op_movzbl_T0_T0();
3848	2c0262af	bellard	break;
3849	2c0262af	bellard	case OT_BYTE \| 8:
3850	2c0262af	bellard	gen_op_movsbl_T0_T0();
3851	2c0262af	bellard	break;
3852	2c0262af	bellard	case OT_WORD:
3853	2c0262af	bellard	gen_op_movzwl_T0_T0();
3854	2c0262af	bellard	break;
3855	2c0262af	bellard	default:
3856	2c0262af	bellard	case OT_WORD \| 8:
3857	2c0262af	bellard	gen_op_movswl_T0_T0();
3858	2c0262af	bellard	break;
3859	2c0262af	bellard	}
3860	2c0262af	bellard	gen_op_mov_reg_T0[d_ot][reg]();
3861	2c0262af	bellard	} else {
3862	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3863	2c0262af	bellard	if (b & 8) {
3864	2c0262af	bellard	gen_op_lds_T0_A0[ot + s->mem_index]();
3865	2c0262af	bellard	} else {
3866	2c0262af	bellard	gen_op_ldu_T0_A0[ot + s->mem_index]();
3867	2c0262af	bellard	}
3868	2c0262af	bellard	gen_op_mov_reg_T0[d_ot][reg]();
3869	2c0262af	bellard	}
3870	2c0262af	bellard	}
3871	2c0262af	bellard	break;
3872	2c0262af	bellard
3873	2c0262af	bellard	case 0x8d: /* lea */
3874	14ce26e7	bellard	ot = dflag + OT_WORD;
3875	61382a50	bellard	modrm = ldub_code(s->pc++);
3876	3a1d9b8b	bellard	mod = (modrm >> 6) & 3;
3877	3a1d9b8b	bellard	if (mod == 3)
3878	3a1d9b8b	bellard	goto illegal_op;
3879	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3880	2c0262af	bellard	/* we must ensure that no segment is added */
3881	2c0262af	bellard	s->override = -1;
3882	2c0262af	bellard	val = s->addseg;
3883	2c0262af	bellard	s->addseg = 0;
3884	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3885	2c0262af	bellard	s->addseg = val;
3886	2c0262af	bellard	gen_op_mov_reg_A0[ot - OT_WORD][reg]();
3887	2c0262af	bellard	break;
3888	2c0262af	bellard
3889	2c0262af	bellard	case 0xa0: /* mov EAX, Ov */
3890	2c0262af	bellard	case 0xa1:
3891	2c0262af	bellard	case 0xa2: /* mov Ov, EAX */
3892	2c0262af	bellard	case 0xa3:
3893	2c0262af	bellard	{
3894	14ce26e7	bellard	target_ulong offset_addr;
3895	14ce26e7	bellard
3896	14ce26e7	bellard	if ((b & 1) == 0)
3897	14ce26e7	bellard	ot = OT_BYTE;
3898	14ce26e7	bellard	else
3899	14ce26e7	bellard	ot = dflag + OT_WORD;
3900	14ce26e7	bellard	#ifdef TARGET_X86_64
3901	14ce26e7	bellard	if (CODE64(s)) {
3902	14ce26e7	bellard	offset_addr = ldq_code(s->pc);
3903	14ce26e7	bellard	s->pc += 8;
3904	14ce26e7	bellard	if (offset_addr == (int32_t)offset_addr)
3905	14ce26e7	bellard	gen_op_movq_A0_im(offset_addr);
3906	14ce26e7	bellard	else
3907	14ce26e7	bellard	gen_op_movq_A0_im64(offset_addr >> 32, offset_addr);
3908	14ce26e7	bellard	} else
3909	14ce26e7	bellard	#endif
3910	14ce26e7	bellard	{
3911	14ce26e7	bellard	if (s->aflag) {
3912	14ce26e7	bellard	offset_addr = insn_get(s, OT_LONG);
3913	14ce26e7	bellard	} else {
3914	14ce26e7	bellard	offset_addr = insn_get(s, OT_WORD);
3915	14ce26e7	bellard	}
3916	14ce26e7	bellard	gen_op_movl_A0_im(offset_addr);
3917	14ce26e7	bellard	}
3918	664e0f19	bellard	gen_add_A0_ds_seg(s);
3919	14ce26e7	bellard	if ((b & 2) == 0) {
3920	14ce26e7	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3921	14ce26e7	bellard	gen_op_mov_reg_T0[ot][R_EAX]();
3922	14ce26e7	bellard	} else {
3923	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][R_EAX]();
3924	14ce26e7	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3925	2c0262af	bellard	}
3926	2c0262af	bellard	}
3927	2c0262af	bellard	break;
3928	2c0262af	bellard	case 0xd7: /* xlat */
3929	14ce26e7	bellard	#ifdef TARGET_X86_64
3930	14ce26e7	bellard	if (CODE64(s)) {
3931	14ce26e7	bellard	gen_op_movq_A0_reg[R_EBX]();
3932	14ce26e7	bellard	gen_op_addq_A0_AL();
3933	14ce26e7	bellard	} else
3934	14ce26e7	bellard	#endif
3935	14ce26e7	bellard	{
3936	14ce26e7	bellard	gen_op_movl_A0_reg[R_EBX]();
3937	14ce26e7	bellard	gen_op_addl_A0_AL();
3938	14ce26e7	bellard	if (s->aflag == 0)
3939	14ce26e7	bellard	gen_op_andl_A0_ffff();
3940	14ce26e7	bellard	}
3941	664e0f19	bellard	gen_add_A0_ds_seg(s);
3942	2c0262af	bellard	gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
3943	2c0262af	bellard	gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
3944	2c0262af	bellard	break;
3945	2c0262af	bellard	case 0xb0 ... 0xb7: /* mov R, Ib */
3946	2c0262af	bellard	val = insn_get(s, OT_BYTE);
3947	2c0262af	bellard	gen_op_movl_T0_im(val);
3948	14ce26e7	bellard	gen_op_mov_reg_T0[OT_BYTE][(b & 7) \| REX_B(s)]();
3949	2c0262af	bellard	break;
3950	2c0262af	bellard	case 0xb8 ... 0xbf: /* mov R, Iv */
3951	14ce26e7	bellard	#ifdef TARGET_X86_64
3952	14ce26e7	bellard	if (dflag == 2) {
3953	14ce26e7	bellard	uint64_t tmp;
3954	14ce26e7	bellard	/* 64 bit case */
3955	14ce26e7	bellard	tmp = ldq_code(s->pc);
3956	14ce26e7	bellard	s->pc += 8;
3957	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
3958	14ce26e7	bellard	gen_movtl_T0_im(tmp);
3959	14ce26e7	bellard	gen_op_mov_reg_T0[OT_QUAD][reg]();
3960	14ce26e7	bellard	} else
3961	14ce26e7	bellard	#endif
3962	14ce26e7	bellard	{
3963	14ce26e7	bellard	ot = dflag ? OT_LONG : OT_WORD;
3964	14ce26e7	bellard	val = insn_get(s, ot);
3965	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
3966	14ce26e7	bellard	gen_op_movl_T0_im(val);
3967	14ce26e7	bellard	gen_op_mov_reg_T0[ot][reg]();
3968	14ce26e7	bellard	}
3969	2c0262af	bellard	break;
3970	2c0262af	bellard
3971	2c0262af	bellard	case 0x91 ... 0x97: /* xchg R, EAX */
3972	14ce26e7	bellard	ot = dflag + OT_WORD;
3973	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
3974	2c0262af	bellard	rm = R_EAX;
3975	2c0262af	bellard	goto do_xchg_reg;
3976	2c0262af	bellard	case 0x86:
3977	2c0262af	bellard	case 0x87: /* xchg Ev, Gv */
3978	2c0262af	bellard	if ((b & 1) == 0)
3979	2c0262af	bellard	ot = OT_BYTE;
3980	2c0262af	bellard	else
3981	14ce26e7	bellard	ot = dflag + OT_WORD;
3982	61382a50	bellard	modrm = ldub_code(s->pc++);
3983	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3984	2c0262af	bellard	mod = (modrm >> 6) & 3;
3985	2c0262af	bellard	if (mod == 3) {
3986	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3987	2c0262af	bellard	do_xchg_reg:
3988	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
3989	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
3990	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
3991	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
3992	2c0262af	bellard	} else {
3993	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3994	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
3995	2c0262af	bellard	/* for xchg, lock is implicit */
3996	2c0262af	bellard	if (!(prefixes & PREFIX_LOCK))
3997	2c0262af	bellard	gen_op_lock();
3998	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3999	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
4000	2c0262af	bellard	if (!(prefixes & PREFIX_LOCK))
4001	2c0262af	bellard	gen_op_unlock();
4002	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
4003	2c0262af	bellard	}
4004	2c0262af	bellard	break;
4005	2c0262af	bellard	case 0xc4: /* les Gv */
4006	14ce26e7	bellard	if (CODE64(s))
4007	14ce26e7	bellard	goto illegal_op;
4008	2c0262af	bellard	op = R_ES;
4009	2c0262af	bellard	goto do_lxx;
4010	2c0262af	bellard	case 0xc5: /* lds Gv */
4011	14ce26e7	bellard	if (CODE64(s))
4012	14ce26e7	bellard	goto illegal_op;
4013	2c0262af	bellard	op = R_DS;
4014	2c0262af	bellard	goto do_lxx;
4015	2c0262af	bellard	case 0x1b2: /* lss Gv */
4016	2c0262af	bellard	op = R_SS;
4017	2c0262af	bellard	goto do_lxx;
4018	2c0262af	bellard	case 0x1b4: /* lfs Gv */
4019	2c0262af	bellard	op = R_FS;
4020	2c0262af	bellard	goto do_lxx;
4021	2c0262af	bellard	case 0x1b5: /* lgs Gv */
4022	2c0262af	bellard	op = R_GS;
4023	2c0262af	bellard	do_lxx:
4024	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
4025	61382a50	bellard	modrm = ldub_code(s->pc++);
4026	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
4027	2c0262af	bellard	mod = (modrm >> 6) & 3;
4028	2c0262af	bellard	if (mod == 3)
4029	2c0262af	bellard	goto illegal_op;
4030	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4031	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
4032	2c0262af	bellard	gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
4033	2c0262af	bellard	/* load the segment first to handle exceptions properly */
4034	61382a50	bellard	gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
4035	2c0262af	bellard	gen_movl_seg_T0(s, op, pc_start - s->cs_base);
4036	2c0262af	bellard	/* then put the data */
4037	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
4038	2c0262af	bellard	if (s->is_jmp) {
4039	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
4040	2c0262af	bellard	gen_eob(s);
4041	2c0262af	bellard	}
4042	2c0262af	bellard	break;
4043	2c0262af	bellard
4044	2c0262af	bellard	/************************/
4045	2c0262af	bellard	/* shifts */
4046	2c0262af	bellard	case 0xc0:
4047	2c0262af	bellard	case 0xc1:
4048	2c0262af	bellard	/* shift Ev,Ib */
4049	2c0262af	bellard	shift = 2;
4050	2c0262af	bellard	grp2:
4051	2c0262af	bellard	{
4052	2c0262af	bellard	if ((b & 1) == 0)
4053	2c0262af	bellard	ot = OT_BYTE;
4054	2c0262af	bellard	else
4055	14ce26e7	bellard	ot = dflag + OT_WORD;
4056	2c0262af	bellard
4057	61382a50	bellard	modrm = ldub_code(s->pc++);
4058	2c0262af	bellard	mod = (modrm >> 6) & 3;
4059	2c0262af	bellard	op = (modrm >> 3) & 7;
4060	2c0262af	bellard
4061	2c0262af	bellard	if (mod != 3) {
4062	14ce26e7	bellard	if (shift == 2) {
4063	14ce26e7	bellard	s->rip_offset = 1;
4064	14ce26e7	bellard	}
4065	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4066	2c0262af	bellard	opreg = OR_TMP0;
4067	2c0262af	bellard	} else {
4068	14ce26e7	bellard	opreg = (modrm & 7) \| REX_B(s);
4069	2c0262af	bellard	}
4070	2c0262af	bellard
4071	2c0262af	bellard	/* simpler op */
4072	2c0262af	bellard	if (shift == 0) {
4073	2c0262af	bellard	gen_shift(s, op, ot, opreg, OR_ECX);
4074	2c0262af	bellard	} else {
4075	2c0262af	bellard	if (shift == 2) {
4076	61382a50	bellard	shift = ldub_code(s->pc++);
4077	2c0262af	bellard	}
4078	2c0262af	bellard	gen_shifti(s, op, ot, opreg, shift);
4079	2c0262af	bellard	}
4080	2c0262af	bellard	}
4081	2c0262af	bellard	break;
4082	2c0262af	bellard	case 0xd0:
4083	2c0262af	bellard	case 0xd1:
4084	2c0262af	bellard	/* shift Ev,1 */
4085	2c0262af	bellard	shift = 1;
4086	2c0262af	bellard	goto grp2;
4087	2c0262af	bellard	case 0xd2:
4088	2c0262af	bellard	case 0xd3:
4089	2c0262af	bellard	/* shift Ev,cl */
4090	2c0262af	bellard	shift = 0;
4091	2c0262af	bellard	goto grp2;
4092	2c0262af	bellard
4093	2c0262af	bellard	case 0x1a4: /* shld imm */
4094	2c0262af	bellard	op = 0;
4095	2c0262af	bellard	shift = 1;
4096	2c0262af	bellard	goto do_shiftd;
4097	2c0262af	bellard	case 0x1a5: /* shld cl */
4098	2c0262af	bellard	op = 0;
4099	2c0262af	bellard	shift = 0;
4100	2c0262af	bellard	goto do_shiftd;
4101	2c0262af	bellard	case 0x1ac: /* shrd imm */
4102	2c0262af	bellard	op = 1;
4103	2c0262af	bellard	shift = 1;
4104	2c0262af	bellard	goto do_shiftd;
4105	2c0262af	bellard	case 0x1ad: /* shrd cl */
4106	2c0262af	bellard	op = 1;
4107	2c0262af	bellard	shift = 0;
4108	2c0262af	bellard	do_shiftd:
4109	14ce26e7	bellard	ot = dflag + OT_WORD;
4110	61382a50	bellard	modrm = ldub_code(s->pc++);
4111	2c0262af	bellard	mod = (modrm >> 6) & 3;
4112	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
4113	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
4114	2c0262af	bellard
4115	2c0262af	bellard	if (mod != 3) {
4116	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4117	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
4118	2c0262af	bellard	} else {
4119	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
4120	2c0262af	bellard	}
4121	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
4122	2c0262af	bellard
4123	2c0262af	bellard	if (shift) {
4124	61382a50	bellard	val = ldub_code(s->pc++);
4125	14ce26e7	bellard	if (ot == OT_QUAD)
4126	14ce26e7	bellard	val &= 0x3f;
4127	14ce26e7	bellard	else
4128	14ce26e7	bellard	val &= 0x1f;
4129	2c0262af	bellard	if (val) {
4130	2c0262af	bellard	if (mod == 3)
4131	4f31916f	bellard	gen_op_shiftd_T0_T1_im_cc[ot][op](val);
4132	2c0262af	bellard	else
4133	4f31916f	bellard	gen_op_shiftd_mem_T0_T1_im_cc[ot + s->mem_index][op](val);
4134	2c0262af	bellard	if (op == 0 && ot != OT_WORD)
4135	2c0262af	bellard	s->cc_op = CC_OP_SHLB + ot;
4136	2c0262af	bellard	else
4137	2c0262af	bellard	s->cc_op = CC_OP_SARB + ot;
4138	2c0262af	bellard	}
4139	2c0262af	bellard	} else {
4140	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4141	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4142	2c0262af	bellard	if (mod == 3)
4143	4f31916f	bellard	gen_op_shiftd_T0_T1_ECX_cc[ot][op]();
4144	2c0262af	bellard	else
4145	4f31916f	bellard	gen_op_shiftd_mem_T0_T1_ECX_cc[ot + s->mem_index][op]();
4146	2c0262af	bellard	s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
4147	2c0262af	bellard	}
4148	2c0262af	bellard	if (mod == 3) {
4149	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
4150	2c0262af	bellard	}
4151	2c0262af	bellard	break;
4152	2c0262af	bellard
4153	2c0262af	bellard	/************************/
4154	2c0262af	bellard	/* floats */
4155	2c0262af	bellard	case 0xd8 ... 0xdf:
4156	7eee2a50	bellard	if (s->flags & (HF_EM_MASK \| HF_TS_MASK)) {
4157	7eee2a50	bellard	/* if CR0.EM or CR0.TS are set, generate an FPU exception */
4158	7eee2a50	bellard	/* XXX: what to do if illegal op ? */
4159	7eee2a50	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
4160	7eee2a50	bellard	break;
4161	7eee2a50	bellard	}
4162	61382a50	bellard	modrm = ldub_code(s->pc++);
4163	2c0262af	bellard	mod = (modrm >> 6) & 3;
4164	2c0262af	bellard	rm = modrm & 7;
4165	2c0262af	bellard	op = ((b & 7) << 3) \| ((modrm >> 3) & 7);
4166	2c0262af	bellard	if (mod != 3) {
4167	2c0262af	bellard	/* memory op */
4168	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4169	2c0262af	bellard	switch(op) {
4170	2c0262af	bellard	case 0x00 ... 0x07: /* fxxxs */
4171	2c0262af	bellard	case 0x10 ... 0x17: /* fixxxl */
4172	2c0262af	bellard	case 0x20 ... 0x27: /* fxxxl */
4173	2c0262af	bellard	case 0x30 ... 0x37: /* fixxx */
4174	2c0262af	bellard	{
4175	2c0262af	bellard	int op1;
4176	2c0262af	bellard	op1 = op & 7;
4177	2c0262af	bellard
4178	2c0262af	bellard	switch(op >> 4) {
4179	2c0262af	bellard	case 0:
4180	2c0262af	bellard	gen_op_flds_FT0_A0();
4181	2c0262af	bellard	break;
4182	2c0262af	bellard	case 1:
4183	2c0262af	bellard	gen_op_fildl_FT0_A0();
4184	2c0262af	bellard	break;
4185	2c0262af	bellard	case 2:
4186	2c0262af	bellard	gen_op_fldl_FT0_A0();
4187	2c0262af	bellard	break;
4188	2c0262af	bellard	case 3:
4189	2c0262af	bellard	default:
4190	2c0262af	bellard	gen_op_fild_FT0_A0();
4191	2c0262af	bellard	break;
4192	2c0262af	bellard	}
4193	2c0262af	bellard
4194	2c0262af	bellard	gen_op_fp_arith_ST0_FT0[op1]();
4195	2c0262af	bellard	if (op1 == 3) {
4196	2c0262af	bellard	/* fcomp needs pop */
4197	2c0262af	bellard	gen_op_fpop();
4198	2c0262af	bellard	}
4199	2c0262af	bellard	}
4200	2c0262af	bellard	break;
4201	2c0262af	bellard	case 0x08: /* flds */
4202	2c0262af	bellard	case 0x0a: /* fsts */
4203	2c0262af	bellard	case 0x0b: /* fstps */
4204	2c0262af	bellard	case 0x18: /* fildl */
4205	2c0262af	bellard	case 0x1a: /* fistl */
4206	2c0262af	bellard	case 0x1b: /* fistpl */
4207	2c0262af	bellard	case 0x28: /* fldl */
4208	2c0262af	bellard	case 0x2a: /* fstl */
4209	2c0262af	bellard	case 0x2b: /* fstpl */
4210	2c0262af	bellard	case 0x38: /* filds */
4211	2c0262af	bellard	case 0x3a: /* fists */
4212	2c0262af	bellard	case 0x3b: /* fistps */
4213	2c0262af	bellard
4214	2c0262af	bellard	switch(op & 7) {
4215	2c0262af	bellard	case 0:
4216	2c0262af	bellard	switch(op >> 4) {
4217	2c0262af	bellard	case 0:
4218	2c0262af	bellard	gen_op_flds_ST0_A0();
4219	2c0262af	bellard	break;
4220	2c0262af	bellard	case 1:
4221	2c0262af	bellard	gen_op_fildl_ST0_A0();
4222	2c0262af	bellard	break;
4223	2c0262af	bellard	case 2:
4224	2c0262af	bellard	gen_op_fldl_ST0_A0();
4225	2c0262af	bellard	break;
4226	2c0262af	bellard	case 3:
4227	2c0262af	bellard	default:
4228	2c0262af	bellard	gen_op_fild_ST0_A0();
4229	2c0262af	bellard	break;
4230	2c0262af	bellard	}
4231	2c0262af	bellard	break;
4232	2c0262af	bellard	default:
4233	2c0262af	bellard	switch(op >> 4) {
4234	2c0262af	bellard	case 0:
4235	2c0262af	bellard	gen_op_fsts_ST0_A0();
4236	2c0262af	bellard	break;
4237	2c0262af	bellard	case 1:
4238	2c0262af	bellard	gen_op_fistl_ST0_A0();
4239	2c0262af	bellard	break;
4240	2c0262af	bellard	case 2:
4241	2c0262af	bellard	gen_op_fstl_ST0_A0();
4242	2c0262af	bellard	break;
4243	2c0262af	bellard	case 3:
4244	2c0262af	bellard	default:
4245	2c0262af	bellard	gen_op_fist_ST0_A0();
4246	2c0262af	bellard	break;
4247	2c0262af	bellard	}
4248	2c0262af	bellard	if ((op & 7) == 3)
4249	2c0262af	bellard	gen_op_fpop();
4250	2c0262af	bellard	break;
4251	2c0262af	bellard	}
4252	2c0262af	bellard	break;
4253	2c0262af	bellard	case 0x0c: /* fldenv mem */
4254	2c0262af	bellard	gen_op_fldenv_A0(s->dflag);
4255	2c0262af	bellard	break;
4256	2c0262af	bellard	case 0x0d: /* fldcw mem */
4257	2c0262af	bellard	gen_op_fldcw_A0();
4258	2c0262af	bellard	break;
4259	2c0262af	bellard	case 0x0e: /* fnstenv mem */
4260	2c0262af	bellard	gen_op_fnstenv_A0(s->dflag);
4261	2c0262af	bellard	break;
4262	2c0262af	bellard	case 0x0f: /* fnstcw mem */
4263	2c0262af	bellard	gen_op_fnstcw_A0();
4264	2c0262af	bellard	break;
4265	2c0262af	bellard	case 0x1d: /* fldt mem */
4266	2c0262af	bellard	gen_op_fldt_ST0_A0();
4267	2c0262af	bellard	break;
4268	2c0262af	bellard	case 0x1f: /* fstpt mem */
4269	2c0262af	bellard	gen_op_fstt_ST0_A0();
4270	2c0262af	bellard	gen_op_fpop();
4271	2c0262af	bellard	break;
4272	2c0262af	bellard	case 0x2c: /* frstor mem */
4273	2c0262af	bellard	gen_op_frstor_A0(s->dflag);
4274	2c0262af	bellard	break;
4275	2c0262af	bellard	case 0x2e: /* fnsave mem */
4276	2c0262af	bellard	gen_op_fnsave_A0(s->dflag);
4277	2c0262af	bellard	break;
4278	2c0262af	bellard	case 0x2f: /* fnstsw mem */
4279	2c0262af	bellard	gen_op_fnstsw_A0();
4280	2c0262af	bellard	break;
4281	2c0262af	bellard	case 0x3c: /* fbld */
4282	2c0262af	bellard	gen_op_fbld_ST0_A0();
4283	2c0262af	bellard	break;
4284	2c0262af	bellard	case 0x3e: /* fbstp */
4285	2c0262af	bellard	gen_op_fbst_ST0_A0();
4286	2c0262af	bellard	gen_op_fpop();
4287	2c0262af	bellard	break;
4288	2c0262af	bellard	case 0x3d: /* fildll */
4289	2c0262af	bellard	gen_op_fildll_ST0_A0();
4290	2c0262af	bellard	break;
4291	2c0262af	bellard	case 0x3f: /* fistpll */
4292	2c0262af	bellard	gen_op_fistll_ST0_A0();
4293	2c0262af	bellard	gen_op_fpop();
4294	2c0262af	bellard	break;
4295	2c0262af	bellard	default:
4296	2c0262af	bellard	goto illegal_op;
4297	2c0262af	bellard	}
4298	2c0262af	bellard	} else {
4299	2c0262af	bellard	/* register float ops */
4300	2c0262af	bellard	opreg = rm;
4301	2c0262af	bellard
4302	2c0262af	bellard	switch(op) {
4303	2c0262af	bellard	case 0x08: /* fld sti */
4304	2c0262af	bellard	gen_op_fpush();
4305	2c0262af	bellard	gen_op_fmov_ST0_STN((opreg + 1) & 7);
4306	2c0262af	bellard	break;
4307	2c0262af	bellard	case 0x09: /* fxchg sti */
4308	c169c906	bellard	case 0x29: /* fxchg4 sti, undocumented op */
4309	c169c906	bellard	case 0x39: /* fxchg7 sti, undocumented op */
4310	2c0262af	bellard	gen_op_fxchg_ST0_STN(opreg);
4311	2c0262af	bellard	break;
4312	2c0262af	bellard	case 0x0a: /* grp d9/2 */
4313	2c0262af	bellard	switch(rm) {
4314	2c0262af	bellard	case 0: /* fnop */
4315	023fe10d	bellard	/* check exceptions (FreeBSD FPU probe) */
4316	023fe10d	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4317	023fe10d	bellard	gen_op_set_cc_op(s->cc_op);
4318	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
4319	023fe10d	bellard	gen_op_fwait();
4320	2c0262af	bellard	break;
4321	2c0262af	bellard	default:
4322	2c0262af	bellard	goto illegal_op;
4323	2c0262af	bellard	}
4324	2c0262af	bellard	break;
4325	2c0262af	bellard	case 0x0c: /* grp d9/4 */
4326	2c0262af	bellard	switch(rm) {
4327	2c0262af	bellard	case 0: /* fchs */
4328	2c0262af	bellard	gen_op_fchs_ST0();
4329	2c0262af	bellard	break;
4330	2c0262af	bellard	case 1: /* fabs */
4331	2c0262af	bellard	gen_op_fabs_ST0();
4332	2c0262af	bellard	break;
4333	2c0262af	bellard	case 4: /* ftst */
4334	2c0262af	bellard	gen_op_fldz_FT0();
4335	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4336	2c0262af	bellard	break;
4337	2c0262af	bellard	case 5: /* fxam */
4338	2c0262af	bellard	gen_op_fxam_ST0();
4339	2c0262af	bellard	break;
4340	2c0262af	bellard	default:
4341	2c0262af	bellard	goto illegal_op;
4342	2c0262af	bellard	}
4343	2c0262af	bellard	break;
4344	2c0262af	bellard	case 0x0d: /* grp d9/5 */
4345	2c0262af	bellard	{
4346	2c0262af	bellard	switch(rm) {
4347	2c0262af	bellard	case 0:
4348	2c0262af	bellard	gen_op_fpush();
4349	2c0262af	bellard	gen_op_fld1_ST0();
4350	2c0262af	bellard	break;
4351	2c0262af	bellard	case 1:
4352	2c0262af	bellard	gen_op_fpush();
4353	2c0262af	bellard	gen_op_fldl2t_ST0();
4354	2c0262af	bellard	break;
4355	2c0262af	bellard	case 2:
4356	2c0262af	bellard	gen_op_fpush();
4357	2c0262af	bellard	gen_op_fldl2e_ST0();
4358	2c0262af	bellard	break;
4359	2c0262af	bellard	case 3:
4360	2c0262af	bellard	gen_op_fpush();
4361	2c0262af	bellard	gen_op_fldpi_ST0();
4362	2c0262af	bellard	break;
4363	2c0262af	bellard	case 4:
4364	2c0262af	bellard	gen_op_fpush();
4365	2c0262af	bellard	gen_op_fldlg2_ST0();
4366	2c0262af	bellard	break;
4367	2c0262af	bellard	case 5:
4368	2c0262af	bellard	gen_op_fpush();
4369	2c0262af	bellard	gen_op_fldln2_ST0();
4370	2c0262af	bellard	break;
4371	2c0262af	bellard	case 6:
4372	2c0262af	bellard	gen_op_fpush();
4373	2c0262af	bellard	gen_op_fldz_ST0();
4374	2c0262af	bellard	break;
4375	2c0262af	bellard	default:
4376	2c0262af	bellard	goto illegal_op;
4377	2c0262af	bellard	}
4378	2c0262af	bellard	}
4379	2c0262af	bellard	break;
4380	2c0262af	bellard	case 0x0e: /* grp d9/6 */
4381	2c0262af	bellard	switch(rm) {
4382	2c0262af	bellard	case 0: /* f2xm1 */
4383	2c0262af	bellard	gen_op_f2xm1();
4384	2c0262af	bellard	break;
4385	2c0262af	bellard	case 1: /* fyl2x */
4386	2c0262af	bellard	gen_op_fyl2x();
4387	2c0262af	bellard	break;
4388	2c0262af	bellard	case 2: /* fptan */
4389	2c0262af	bellard	gen_op_fptan();
4390	2c0262af	bellard	break;
4391	2c0262af	bellard	case 3: /* fpatan */
4392	2c0262af	bellard	gen_op_fpatan();
4393	2c0262af	bellard	break;
4394	2c0262af	bellard	case 4: /* fxtract */
4395	2c0262af	bellard	gen_op_fxtract();
4396	2c0262af	bellard	break;
4397	2c0262af	bellard	case 5: /* fprem1 */
4398	2c0262af	bellard	gen_op_fprem1();
4399	2c0262af	bellard	break;
4400	2c0262af	bellard	case 6: /* fdecstp */
4401	2c0262af	bellard	gen_op_fdecstp();
4402	2c0262af	bellard	break;
4403	2c0262af	bellard	default:
4404	2c0262af	bellard	case 7: /* fincstp */
4405	2c0262af	bellard	gen_op_fincstp();
4406	2c0262af	bellard	break;
4407	2c0262af	bellard	}
4408	2c0262af	bellard	break;
4409	2c0262af	bellard	case 0x0f: /* grp d9/7 */
4410	2c0262af	bellard	switch(rm) {
4411	2c0262af	bellard	case 0: /* fprem */
4412	2c0262af	bellard	gen_op_fprem();
4413	2c0262af	bellard	break;
4414	2c0262af	bellard	case 1: /* fyl2xp1 */
4415	2c0262af	bellard	gen_op_fyl2xp1();
4416	2c0262af	bellard	break;
4417	2c0262af	bellard	case 2: /* fsqrt */
4418	2c0262af	bellard	gen_op_fsqrt();
4419	2c0262af	bellard	break;
4420	2c0262af	bellard	case 3: /* fsincos */
4421	2c0262af	bellard	gen_op_fsincos();
4422	2c0262af	bellard	break;
4423	2c0262af	bellard	case 5: /* fscale */
4424	2c0262af	bellard	gen_op_fscale();
4425	2c0262af	bellard	break;
4426	2c0262af	bellard	case 4: /* frndint */
4427	2c0262af	bellard	gen_op_frndint();
4428	2c0262af	bellard	break;
4429	2c0262af	bellard	case 6: /* fsin */
4430	2c0262af	bellard	gen_op_fsin();
4431	2c0262af	bellard	break;
4432	2c0262af	bellard	default:
4433	2c0262af	bellard	case 7: /* fcos */
4434	2c0262af	bellard	gen_op_fcos();
4435	2c0262af	bellard	break;
4436	2c0262af	bellard	}
4437	2c0262af	bellard	break;
4438	2c0262af	bellard	case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
4439	2c0262af	bellard	case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
4440	2c0262af	bellard	case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
4441	2c0262af	bellard	{
4442	2c0262af	bellard	int op1;
4443	2c0262af	bellard
4444	2c0262af	bellard	op1 = op & 7;
4445	2c0262af	bellard	if (op >= 0x20) {
4446	2c0262af	bellard	gen_op_fp_arith_STN_ST0[op1](opreg);
4447	2c0262af	bellard	if (op >= 0x30)
4448	2c0262af	bellard	gen_op_fpop();
4449	2c0262af	bellard	} else {
4450	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4451	2c0262af	bellard	gen_op_fp_arith_ST0_FT0[op1]();
4452	2c0262af	bellard	}
4453	2c0262af	bellard	}
4454	2c0262af	bellard	break;
4455	2c0262af	bellard	case 0x02: /* fcom */
4456	c169c906	bellard	case 0x22: /* fcom2, undocumented op */
4457	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4458	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4459	2c0262af	bellard	break;
4460	2c0262af	bellard	case 0x03: /* fcomp */
4461	c169c906	bellard	case 0x23: /* fcomp3, undocumented op */
4462	c169c906	bellard	case 0x32: /* fcomp5, undocumented op */
4463	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4464	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4465	2c0262af	bellard	gen_op_fpop();
4466	2c0262af	bellard	break;
4467	2c0262af	bellard	case 0x15: /* da/5 */
4468	2c0262af	bellard	switch(rm) {
4469	2c0262af	bellard	case 1: /* fucompp */
4470	2c0262af	bellard	gen_op_fmov_FT0_STN(1);
4471	2c0262af	bellard	gen_op_fucom_ST0_FT0();
4472	2c0262af	bellard	gen_op_fpop();
4473	2c0262af	bellard	gen_op_fpop();
4474	2c0262af	bellard	break;
4475	2c0262af	bellard	default:
4476	2c0262af	bellard	goto illegal_op;
4477	2c0262af	bellard	}
4478	2c0262af	bellard	break;
4479	2c0262af	bellard	case 0x1c:
4480	2c0262af	bellard	switch(rm) {
4481	2c0262af	bellard	case 0: /* feni (287 only, just do nop here) */
4482	2c0262af	bellard	break;
4483	2c0262af	bellard	case 1: /* fdisi (287 only, just do nop here) */
4484	2c0262af	bellard	break;
4485	2c0262af	bellard	case 2: /* fclex */
4486	2c0262af	bellard	gen_op_fclex();
4487	2c0262af	bellard	break;
4488	2c0262af	bellard	case 3: /* fninit */
4489	2c0262af	bellard	gen_op_fninit();
4490	2c0262af	bellard	break;
4491	2c0262af	bellard	case 4: /* fsetpm (287 only, just do nop here) */
4492	2c0262af	bellard	break;
4493	2c0262af	bellard	default:
4494	2c0262af	bellard	goto illegal_op;
4495	2c0262af	bellard	}
4496	2c0262af	bellard	break;
4497	2c0262af	bellard	case 0x1d: /* fucomi */
4498	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4499	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4500	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4501	2c0262af	bellard	gen_op_fucomi_ST0_FT0();
4502	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4503	2c0262af	bellard	break;
4504	2c0262af	bellard	case 0x1e: /* fcomi */
4505	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4506	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4507	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4508	2c0262af	bellard	gen_op_fcomi_ST0_FT0();
4509	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4510	2c0262af	bellard	break;
4511	658c8bda	bellard	case 0x28: /* ffree sti */
4512	658c8bda	bellard	gen_op_ffree_STN(opreg);
4513	658c8bda	bellard	break;
4514	2c0262af	bellard	case 0x2a: /* fst sti */
4515	2c0262af	bellard	gen_op_fmov_STN_ST0(opreg);
4516	2c0262af	bellard	break;
4517	2c0262af	bellard	case 0x2b: /* fstp sti */
4518	c169c906	bellard	case 0x0b: /* fstp1 sti, undocumented op */
4519	c169c906	bellard	case 0x3a: /* fstp8 sti, undocumented op */
4520	c169c906	bellard	case 0x3b: /* fstp9 sti, undocumented op */
4521	2c0262af	bellard	gen_op_fmov_STN_ST0(opreg);
4522	2c0262af	bellard	gen_op_fpop();
4523	2c0262af	bellard	break;
4524	2c0262af	bellard	case 0x2c: /* fucom st(i) */
4525	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4526	2c0262af	bellard	gen_op_fucom_ST0_FT0();
4527	2c0262af	bellard	break;
4528	2c0262af	bellard	case 0x2d: /* fucomp st(i) */
4529	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4530	2c0262af	bellard	gen_op_fucom_ST0_FT0();
4531	2c0262af	bellard	gen_op_fpop();
4532	2c0262af	bellard	break;
4533	2c0262af	bellard	case 0x33: /* de/3 */
4534	2c0262af	bellard	switch(rm) {
4535	2c0262af	bellard	case 1: /* fcompp */
4536	2c0262af	bellard	gen_op_fmov_FT0_STN(1);
4537	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4538	2c0262af	bellard	gen_op_fpop();
4539	2c0262af	bellard	gen_op_fpop();
4540	2c0262af	bellard	break;
4541	2c0262af	bellard	default:
4542	2c0262af	bellard	goto illegal_op;
4543	2c0262af	bellard	}
4544	2c0262af	bellard	break;
4545	c169c906	bellard	case 0x38: /* ffreep sti, undocumented op */
4546	c169c906	bellard	gen_op_ffree_STN(opreg);
4547	c169c906	bellard	gen_op_fpop();
4548	c169c906	bellard	break;
4549	2c0262af	bellard	case 0x3c: /* df/4 */
4550	2c0262af	bellard	switch(rm) {
4551	2c0262af	bellard	case 0:
4552	2c0262af	bellard	gen_op_fnstsw_EAX();
4553	2c0262af	bellard	break;
4554	2c0262af	bellard	default:
4555	2c0262af	bellard	goto illegal_op;
4556	2c0262af	bellard	}
4557	2c0262af	bellard	break;
4558	2c0262af	bellard	case 0x3d: /* fucomip */
4559	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4560	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4561	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4562	2c0262af	bellard	gen_op_fucomi_ST0_FT0();
4563	2c0262af	bellard	gen_op_fpop();
4564	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4565	2c0262af	bellard	break;
4566	2c0262af	bellard	case 0x3e: /* fcomip */
4567	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4568	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4569	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4570	2c0262af	bellard	gen_op_fcomi_ST0_FT0();
4571	2c0262af	bellard	gen_op_fpop();
4572	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4573	2c0262af	bellard	break;
4574	a2cc3b24	bellard	case 0x10 ... 0x13: /* fcmovxx */
4575	a2cc3b24	bellard	case 0x18 ... 0x1b:
4576	a2cc3b24	bellard	{
4577	a2cc3b24	bellard	int op1;
4578	a2cc3b24	bellard	const static uint8_t fcmov_cc[8] = {
4579	a2cc3b24	bellard	(JCC_B << 1),
4580	a2cc3b24	bellard	(JCC_Z << 1),
4581	a2cc3b24	bellard	(JCC_BE << 1),
4582	a2cc3b24	bellard	(JCC_P << 1),
4583	a2cc3b24	bellard	};
4584	a2cc3b24	bellard	op1 = fcmov_cc[op & 3] \| ((op >> 3) & 1);
4585	a2cc3b24	bellard	gen_setcc(s, op1);
4586	a2cc3b24	bellard	gen_op_fcmov_ST0_STN_T0(opreg);
4587	a2cc3b24	bellard	}
4588	a2cc3b24	bellard	break;
4589	2c0262af	bellard	default:
4590	2c0262af	bellard	goto illegal_op;
4591	2c0262af	bellard	}
4592	2c0262af	bellard	}
4593	7eee2a50	bellard	#ifdef USE_CODE_COPY
4594	7eee2a50	bellard	s->tb->cflags \|= CF_TB_FP_USED;
4595	7eee2a50	bellard	#endif
4596	2c0262af	bellard	break;
4597	2c0262af	bellard	/************************/
4598	2c0262af	bellard	/* string ops */
4599	2c0262af	bellard
4600	2c0262af	bellard	case 0xa4: /* movsS */
4601	2c0262af	bellard	case 0xa5:
4602	2c0262af	bellard	if ((b & 1) == 0)
4603	2c0262af	bellard	ot = OT_BYTE;
4604	2c0262af	bellard	else
4605	14ce26e7	bellard	ot = dflag + OT_WORD;
4606	2c0262af	bellard
4607	2c0262af	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4608	2c0262af	bellard	gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4609	2c0262af	bellard	} else {
4610	2c0262af	bellard	gen_movs(s, ot);
4611	2c0262af	bellard	}
4612	2c0262af	bellard	break;
4613	2c0262af	bellard
4614	2c0262af	bellard	case 0xaa: /* stosS */
4615	2c0262af	bellard	case 0xab:
4616	2c0262af	bellard	if ((b & 1) == 0)
4617	2c0262af	bellard	ot = OT_BYTE;
4618	2c0262af	bellard	else
4619	14ce26e7	bellard	ot = dflag + OT_WORD;
4620	2c0262af	bellard
4621	2c0262af	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4622	2c0262af	bellard	gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4623	2c0262af	bellard	} else {
4624	2c0262af	bellard	gen_stos(s, ot);
4625	2c0262af	bellard	}
4626	2c0262af	bellard	break;
4627	2c0262af	bellard	case 0xac: /* lodsS */
4628	2c0262af	bellard	case 0xad:
4629	2c0262af	bellard	if ((b & 1) == 0)
4630	2c0262af	bellard	ot = OT_BYTE;
4631	2c0262af	bellard	else
4632	14ce26e7	bellard	ot = dflag + OT_WORD;
4633	2c0262af	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4634	2c0262af	bellard	gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4635	2c0262af	bellard	} else {
4636	2c0262af	bellard	gen_lods(s, ot);
4637	2c0262af	bellard	}
4638	2c0262af	bellard	break;
4639	2c0262af	bellard	case 0xae: /* scasS */
4640	2c0262af	bellard	case 0xaf:
4641	2c0262af	bellard	if ((b & 1) == 0)
4642	2c0262af	bellard	ot = OT_BYTE;
4643	2c0262af	bellard	else
4644	14ce26e7	bellard	ot = dflag + OT_WORD;
4645	2c0262af	bellard	if (prefixes & PREFIX_REPNZ) {
4646	2c0262af	bellard	gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
4647	2c0262af	bellard	} else if (prefixes & PREFIX_REPZ) {
4648	2c0262af	bellard	gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
4649	2c0262af	bellard	} else {
4650	2c0262af	bellard	gen_scas(s, ot);
4651	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
4652	2c0262af	bellard	}
4653	2c0262af	bellard	break;
4654	2c0262af	bellard
4655	2c0262af	bellard	case 0xa6: /* cmpsS */
4656	2c0262af	bellard	case 0xa7:
4657	2c0262af	bellard	if ((b & 1) == 0)
4658	2c0262af	bellard	ot = OT_BYTE;
4659	2c0262af	bellard	else
4660	14ce26e7	bellard	ot = dflag + OT_WORD;
4661	2c0262af	bellard	if (prefixes & PREFIX_REPNZ) {
4662	2c0262af	bellard	gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
4663	2c0262af	bellard	} else if (prefixes & PREFIX_REPZ) {
4664	2c0262af	bellard	gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
4665	2c0262af	bellard	} else {
4666	2c0262af	bellard	gen_cmps(s, ot);
4667	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
4668	2c0262af	bellard	}
4669	2c0262af	bellard	break;
4670	2c0262af	bellard	case 0x6c: /* insS */
4671	2c0262af	bellard	case 0x6d:
4672	f115e911	bellard	if ((b & 1) == 0)
4673	f115e911	bellard	ot = OT_BYTE;
4674	f115e911	bellard	else
4675	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4676	f115e911	bellard	gen_check_io(s, ot, 1, pc_start - s->cs_base);
4677	f115e911	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4678	f115e911	bellard	gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4679	2c0262af	bellard	} else {
4680	f115e911	bellard	gen_ins(s, ot);
4681	2c0262af	bellard	}
4682	2c0262af	bellard	break;
4683	2c0262af	bellard	case 0x6e: /* outsS */
4684	2c0262af	bellard	case 0x6f:
4685	f115e911	bellard	if ((b & 1) == 0)
4686	f115e911	bellard	ot = OT_BYTE;
4687	f115e911	bellard	else
4688	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4689	f115e911	bellard	gen_check_io(s, ot, 1, pc_start - s->cs_base);
4690	f115e911	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4691	f115e911	bellard	gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4692	2c0262af	bellard	} else {
4693	f115e911	bellard	gen_outs(s, ot);
4694	2c0262af	bellard	}
4695	2c0262af	bellard	break;
4696	2c0262af	bellard
4697	2c0262af	bellard	/************************/
4698	2c0262af	bellard	/* port I/O */
4699	2c0262af	bellard	case 0xe4:
4700	2c0262af	bellard	case 0xe5:
4701	f115e911	bellard	if ((b & 1) == 0)
4702	f115e911	bellard	ot = OT_BYTE;
4703	f115e911	bellard	else
4704	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4705	f115e911	bellard	val = ldub_code(s->pc++);
4706	f115e911	bellard	gen_op_movl_T0_im(val);
4707	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4708	f115e911	bellard	gen_op_in[ot]();
4709	f115e911	bellard	gen_op_mov_reg_T1[ot][R_EAX]();
4710	2c0262af	bellard	break;
4711	2c0262af	bellard	case 0xe6:
4712	2c0262af	bellard	case 0xe7:
4713	f115e911	bellard	if ((b & 1) == 0)
4714	f115e911	bellard	ot = OT_BYTE;
4715	f115e911	bellard	else
4716	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4717	f115e911	bellard	val = ldub_code(s->pc++);
4718	f115e911	bellard	gen_op_movl_T0_im(val);
4719	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4720	f115e911	bellard	gen_op_mov_TN_reg[ot][1][R_EAX]();
4721	f115e911	bellard	gen_op_out[ot]();
4722	2c0262af	bellard	break;
4723	2c0262af	bellard	case 0xec:
4724	2c0262af	bellard	case 0xed:
4725	f115e911	bellard	if ((b & 1) == 0)
4726	f115e911	bellard	ot = OT_BYTE;
4727	f115e911	bellard	else
4728	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4729	f115e911	bellard	gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
4730	4f31916f	bellard	gen_op_andl_T0_ffff();
4731	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4732	f115e911	bellard	gen_op_in[ot]();
4733	f115e911	bellard	gen_op_mov_reg_T1[ot][R_EAX]();
4734	2c0262af	bellard	break;
4735	2c0262af	bellard	case 0xee:
4736	2c0262af	bellard	case 0xef:
4737	f115e911	bellard	if ((b & 1) == 0)
4738	f115e911	bellard	ot = OT_BYTE;
4739	f115e911	bellard	else
4740	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4741	f115e911	bellard	gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
4742	4f31916f	bellard	gen_op_andl_T0_ffff();
4743	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4744	f115e911	bellard	gen_op_mov_TN_reg[ot][1][R_EAX]();
4745	f115e911	bellard	gen_op_out[ot]();
4746	2c0262af	bellard	break;
4747	2c0262af	bellard
4748	2c0262af	bellard	/************************/
4749	2c0262af	bellard	/* control */
4750	2c0262af	bellard	case 0xc2: /* ret im */
4751	61382a50	bellard	val = ldsw_code(s->pc);
4752	2c0262af	bellard	s->pc += 2;
4753	2c0262af	bellard	gen_pop_T0(s);
4754	2c0262af	bellard	gen_stack_update(s, val + (2 << s->dflag));
4755	2c0262af	bellard	if (s->dflag == 0)
4756	2c0262af	bellard	gen_op_andl_T0_ffff();
4757	2c0262af	bellard	gen_op_jmp_T0();
4758	2c0262af	bellard	gen_eob(s);
4759	2c0262af	bellard	break;
4760	2c0262af	bellard	case 0xc3: /* ret */
4761	2c0262af	bellard	gen_pop_T0(s);
4762	2c0262af	bellard	gen_pop_update(s);
4763	2c0262af	bellard	if (s->dflag == 0)
4764	2c0262af	bellard	gen_op_andl_T0_ffff();
4765	2c0262af	bellard	gen_op_jmp_T0();
4766	2c0262af	bellard	gen_eob(s);
4767	2c0262af	bellard	break;
4768	2c0262af	bellard	case 0xca: /* lret im */
4769	61382a50	bellard	val = ldsw_code(s->pc);
4770	2c0262af	bellard	s->pc += 2;
4771	2c0262af	bellard	do_lret:
4772	2c0262af	bellard	if (s->pe && !s->vm86) {
4773	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4774	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4775	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
4776	2c0262af	bellard	gen_op_lret_protected(s->dflag, val);
4777	2c0262af	bellard	} else {
4778	2c0262af	bellard	gen_stack_A0(s);
4779	2c0262af	bellard	/* pop offset */
4780	2c0262af	bellard	gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
4781	2c0262af	bellard	if (s->dflag == 0)
4782	2c0262af	bellard	gen_op_andl_T0_ffff();
4783	2c0262af	bellard	/* NOTE: keeping EIP updated is not a problem in case of
4784	2c0262af	bellard	exception */
4785	2c0262af	bellard	gen_op_jmp_T0();
4786	2c0262af	bellard	/* pop selector */
4787	2c0262af	bellard	gen_op_addl_A0_im(2 << s->dflag);
4788	2c0262af	bellard	gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
4789	2c0262af	bellard	gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
4790	2c0262af	bellard	/* add stack offset */
4791	2c0262af	bellard	gen_stack_update(s, val + (4 << s->dflag));
4792	2c0262af	bellard	}
4793	2c0262af	bellard	gen_eob(s);
4794	2c0262af	bellard	break;
4795	2c0262af	bellard	case 0xcb: /* lret */
4796	2c0262af	bellard	val = 0;
4797	2c0262af	bellard	goto do_lret;
4798	2c0262af	bellard	case 0xcf: /* iret */
4799	2c0262af	bellard	if (!s->pe) {
4800	2c0262af	bellard	/* real mode */
4801	2c0262af	bellard	gen_op_iret_real(s->dflag);
4802	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4803	f115e911	bellard	} else if (s->vm86) {
4804	f115e911	bellard	if (s->iopl != 3) {
4805	f115e911	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4806	f115e911	bellard	} else {
4807	f115e911	bellard	gen_op_iret_real(s->dflag);
4808	f115e911	bellard	s->cc_op = CC_OP_EFLAGS;
4809	f115e911	bellard	}
4810	2c0262af	bellard	} else {
4811	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4812	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4813	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
4814	08cea4ee	bellard	gen_op_iret_protected(s->dflag, s->pc - s->cs_base);
4815	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4816	2c0262af	bellard	}
4817	2c0262af	bellard	gen_eob(s);
4818	2c0262af	bellard	break;
4819	2c0262af	bellard	case 0xe8: /* call im */
4820	2c0262af	bellard	{
4821	14ce26e7	bellard	if (dflag)
4822	14ce26e7	bellard	tval = (int32_t)insn_get(s, OT_LONG);
4823	14ce26e7	bellard	else
4824	14ce26e7	bellard	tval = (int16_t)insn_get(s, OT_WORD);
4825	2c0262af	bellard	next_eip = s->pc - s->cs_base;
4826	14ce26e7	bellard	tval += next_eip;
4827	2c0262af	bellard	if (s->dflag == 0)
4828	14ce26e7	bellard	tval &= 0xffff;
4829	14ce26e7	bellard	gen_movtl_T0_im(next_eip);
4830	2c0262af	bellard	gen_push_T0(s);
4831	14ce26e7	bellard	gen_jmp(s, tval);
4832	2c0262af	bellard	}
4833	2c0262af	bellard	break;
4834	2c0262af	bellard	case 0x9a: /* lcall im */
4835	2c0262af	bellard	{
4836	2c0262af	bellard	unsigned int selector, offset;
4837	14ce26e7	bellard
4838	14ce26e7	bellard	if (CODE64(s))
4839	14ce26e7	bellard	goto illegal_op;
4840	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
4841	2c0262af	bellard	offset = insn_get(s, ot);
4842	2c0262af	bellard	selector = insn_get(s, OT_WORD);
4843	2c0262af	bellard
4844	2c0262af	bellard	gen_op_movl_T0_im(selector);
4845	14ce26e7	bellard	gen_op_movl_T1_imu(offset);
4846	2c0262af	bellard	}
4847	2c0262af	bellard	goto do_lcall;
4848	2c0262af	bellard	case 0xe9: /* jmp */
4849	14ce26e7	bellard	if (dflag)
4850	14ce26e7	bellard	tval = (int32_t)insn_get(s, OT_LONG);
4851	14ce26e7	bellard	else
4852	14ce26e7	bellard	tval = (int16_t)insn_get(s, OT_WORD);
4853	14ce26e7	bellard	tval += s->pc - s->cs_base;
4854	2c0262af	bellard	if (s->dflag == 0)
4855	14ce26e7	bellard	tval &= 0xffff;
4856	14ce26e7	bellard	gen_jmp(s, tval);
4857	2c0262af	bellard	break;
4858	2c0262af	bellard	case 0xea: /* ljmp im */
4859	2c0262af	bellard	{
4860	2c0262af	bellard	unsigned int selector, offset;
4861	2c0262af	bellard
4862	14ce26e7	bellard	if (CODE64(s))
4863	14ce26e7	bellard	goto illegal_op;
4864	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
4865	2c0262af	bellard	offset = insn_get(s, ot);
4866	2c0262af	bellard	selector = insn_get(s, OT_WORD);
4867	2c0262af	bellard
4868	2c0262af	bellard	gen_op_movl_T0_im(selector);
4869	14ce26e7	bellard	gen_op_movl_T1_imu(offset);
4870	2c0262af	bellard	}
4871	2c0262af	bellard	goto do_ljmp;
4872	2c0262af	bellard	case 0xeb: /* jmp Jb */
4873	14ce26e7	bellard	tval = (int8_t)insn_get(s, OT_BYTE);
4874	14ce26e7	bellard	tval += s->pc - s->cs_base;
4875	2c0262af	bellard	if (s->dflag == 0)
4876	14ce26e7	bellard	tval &= 0xffff;
4877	14ce26e7	bellard	gen_jmp(s, tval);
4878	2c0262af	bellard	break;
4879	2c0262af	bellard	case 0x70 ... 0x7f: /* jcc Jb */
4880	14ce26e7	bellard	tval = (int8_t)insn_get(s, OT_BYTE);
4881	2c0262af	bellard	goto do_jcc;
4882	2c0262af	bellard	case 0x180 ... 0x18f: /* jcc Jv */
4883	2c0262af	bellard	if (dflag) {
4884	14ce26e7	bellard	tval = (int32_t)insn_get(s, OT_LONG);
4885	2c0262af	bellard	} else {
4886	14ce26e7	bellard	tval = (int16_t)insn_get(s, OT_WORD);
4887	2c0262af	bellard	}
4888	2c0262af	bellard	do_jcc:
4889	2c0262af	bellard	next_eip = s->pc - s->cs_base;
4890	14ce26e7	bellard	tval += next_eip;
4891	2c0262af	bellard	if (s->dflag == 0)
4892	14ce26e7	bellard	tval &= 0xffff;
4893	14ce26e7	bellard	gen_jcc(s, b, tval, next_eip);
4894	2c0262af	bellard	break;
4895	2c0262af	bellard
4896	2c0262af	bellard	case 0x190 ... 0x19f: /* setcc Gv */
4897	61382a50	bellard	modrm = ldub_code(s->pc++);
4898	2c0262af	bellard	gen_setcc(s, b);
4899	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
4900	2c0262af	bellard	break;
4901	2c0262af	bellard	case 0x140 ... 0x14f: /* cmov Gv, Ev */
4902	14ce26e7	bellard	ot = dflag + OT_WORD;
4903	61382a50	bellard	modrm = ldub_code(s->pc++);
4904	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
4905	2c0262af	bellard	mod = (modrm >> 6) & 3;
4906	2c0262af	bellard	gen_setcc(s, b);
4907	2c0262af	bellard	if (mod != 3) {
4908	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4909	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
4910	2c0262af	bellard	} else {
4911	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
4912	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
4913	2c0262af	bellard	}
4914	2c0262af	bellard	gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
4915	2c0262af	bellard	break;
4916	2c0262af	bellard
4917	2c0262af	bellard	/************************/
4918	2c0262af	bellard	/* flags */
4919	2c0262af	bellard	case 0x9c: /* pushf */
4920	2c0262af	bellard	if (s->vm86 && s->iopl != 3) {
4921	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4922	2c0262af	bellard	} else {
4923	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4924	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4925	2c0262af	bellard	gen_op_movl_T0_eflags();
4926	2c0262af	bellard	gen_push_T0(s);
4927	2c0262af	bellard	}
4928	2c0262af	bellard	break;
4929	2c0262af	bellard	case 0x9d: /* popf */
4930	2c0262af	bellard	if (s->vm86 && s->iopl != 3) {
4931	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4932	2c0262af	bellard	} else {
4933	2c0262af	bellard	gen_pop_T0(s);
4934	2c0262af	bellard	if (s->cpl == 0) {
4935	2c0262af	bellard	if (s->dflag) {
4936	2c0262af	bellard	gen_op_movl_eflags_T0_cpl0();
4937	2c0262af	bellard	} else {
4938	2c0262af	bellard	gen_op_movw_eflags_T0_cpl0();
4939	2c0262af	bellard	}
4940	2c0262af	bellard	} else {
4941	4136f33c	bellard	if (s->cpl <= s->iopl) {
4942	4136f33c	bellard	if (s->dflag) {
4943	4136f33c	bellard	gen_op_movl_eflags_T0_io();
4944	4136f33c	bellard	} else {
4945	4136f33c	bellard	gen_op_movw_eflags_T0_io();
4946	4136f33c	bellard	}
4947	2c0262af	bellard	} else {
4948	4136f33c	bellard	if (s->dflag) {
4949	4136f33c	bellard	gen_op_movl_eflags_T0();
4950	4136f33c	bellard	} else {
4951	4136f33c	bellard	gen_op_movw_eflags_T0();
4952	4136f33c	bellard	}
4953	2c0262af	bellard	}
4954	2c0262af	bellard	}
4955	2c0262af	bellard	gen_pop_update(s);
4956	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4957	2c0262af	bellard	/* abort translation because TF flag may change */
4958	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
4959	2c0262af	bellard	gen_eob(s);
4960	2c0262af	bellard	}
4961	2c0262af	bellard	break;
4962	2c0262af	bellard	case 0x9e: /* sahf */
4963	14ce26e7	bellard	if (CODE64(s))
4964	14ce26e7	bellard	goto illegal_op;
4965	2c0262af	bellard	gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
4966	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4967	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4968	2c0262af	bellard	gen_op_movb_eflags_T0();
4969	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4970	2c0262af	bellard	break;
4971	2c0262af	bellard	case 0x9f: /* lahf */
4972	14ce26e7	bellard	if (CODE64(s))
4973	14ce26e7	bellard	goto illegal_op;
4974	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4975	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4976	2c0262af	bellard	gen_op_movl_T0_eflags();
4977	2c0262af	bellard	gen_op_mov_reg_T0[OT_BYTE][R_AH]();
4978	2c0262af	bellard	break;
4979	2c0262af	bellard	case 0xf5: /* cmc */
4980	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4981	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4982	2c0262af	bellard	gen_op_cmc();
4983	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4984	2c0262af	bellard	break;
4985	2c0262af	bellard	case 0xf8: /* clc */
4986	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4987	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4988	2c0262af	bellard	gen_op_clc();
4989	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4990	2c0262af	bellard	break;
4991	2c0262af	bellard	case 0xf9: /* stc */
4992	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4993	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4994	2c0262af	bellard	gen_op_stc();
4995	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4996	2c0262af	bellard	break;
4997	2c0262af	bellard	case 0xfc: /* cld */
4998	2c0262af	bellard	gen_op_cld();
4999	2c0262af	bellard	break;
5000	2c0262af	bellard	case 0xfd: /* std */
5001	2c0262af	bellard	gen_op_std();
5002	2c0262af	bellard	break;
5003	2c0262af	bellard
5004	2c0262af	bellard	/************************/
5005	2c0262af	bellard	/* bit operations */
5006	2c0262af	bellard	case 0x1ba: /* bt/bts/btr/btc Gv, im */
5007	14ce26e7	bellard	ot = dflag + OT_WORD;
5008	61382a50	bellard	modrm = ldub_code(s->pc++);
5009	14ce26e7	bellard	op = ((modrm >> 3) & 7) \| rex_r;
5010	2c0262af	bellard	mod = (modrm >> 6) & 3;
5011	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5012	2c0262af	bellard	if (mod != 3) {
5013	14ce26e7	bellard	s->rip_offset = 1;
5014	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5015	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
5016	2c0262af	bellard	} else {
5017	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5018	2c0262af	bellard	}
5019	2c0262af	bellard	/* load shift */
5020	61382a50	bellard	val = ldub_code(s->pc++);
5021	2c0262af	bellard	gen_op_movl_T1_im(val);
5022	2c0262af	bellard	if (op < 4)
5023	2c0262af	bellard	goto illegal_op;
5024	2c0262af	bellard	op -= 4;
5025	2c0262af	bellard	gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
5026	2c0262af	bellard	s->cc_op = CC_OP_SARB + ot;
5027	2c0262af	bellard	if (op != 0) {
5028	2c0262af	bellard	if (mod != 3)
5029	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
5030	2c0262af	bellard	else
5031	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
5032	2c0262af	bellard	gen_op_update_bt_cc();
5033	2c0262af	bellard	}
5034	2c0262af	bellard	break;
5035	2c0262af	bellard	case 0x1a3: /* bt Gv, Ev */
5036	2c0262af	bellard	op = 0;
5037	2c0262af	bellard	goto do_btx;
5038	2c0262af	bellard	case 0x1ab: /* bts */
5039	2c0262af	bellard	op = 1;
5040	2c0262af	bellard	goto do_btx;
5041	2c0262af	bellard	case 0x1b3: /* btr */
5042	2c0262af	bellard	op = 2;
5043	2c0262af	bellard	goto do_btx;
5044	2c0262af	bellard	case 0x1bb: /* btc */
5045	2c0262af	bellard	op = 3;
5046	2c0262af	bellard	do_btx:
5047	14ce26e7	bellard	ot = dflag + OT_WORD;
5048	61382a50	bellard	modrm = ldub_code(s->pc++);
5049	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5050	2c0262af	bellard	mod = (modrm >> 6) & 3;
5051	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5052	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][1][reg]();
5053	2c0262af	bellard	if (mod != 3) {
5054	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5055	2c0262af	bellard	/* specific case: we need to add a displacement */
5056	14ce26e7	bellard	gen_op_add_bit_A0_T1[ot - OT_WORD]();
5057	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
5058	2c0262af	bellard	} else {
5059	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5060	2c0262af	bellard	}
5061	2c0262af	bellard	gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
5062	2c0262af	bellard	s->cc_op = CC_OP_SARB + ot;
5063	2c0262af	bellard	if (op != 0) {
5064	2c0262af	bellard	if (mod != 3)
5065	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
5066	2c0262af	bellard	else
5067	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
5068	2c0262af	bellard	gen_op_update_bt_cc();
5069	2c0262af	bellard	}
5070	2c0262af	bellard	break;
5071	2c0262af	bellard	case 0x1bc: /* bsf */
5072	2c0262af	bellard	case 0x1bd: /* bsr */
5073	14ce26e7	bellard	ot = dflag + OT_WORD;
5074	61382a50	bellard	modrm = ldub_code(s->pc++);
5075	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5076	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5077	686f3f26	bellard	/* NOTE: in order to handle the 0 case, we must load the
5078	686f3f26	bellard	result. It could be optimized with a generated jump */
5079	686f3f26	bellard	gen_op_mov_TN_reg[ot][1][reg]();
5080	2c0262af	bellard	gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
5081	686f3f26	bellard	gen_op_mov_reg_T1[ot][reg]();
5082	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
5083	2c0262af	bellard	break;
5084	2c0262af	bellard	/************************/
5085	2c0262af	bellard	/* bcd */
5086	2c0262af	bellard	case 0x27: /* daa */
5087	14ce26e7	bellard	if (CODE64(s))
5088	14ce26e7	bellard	goto illegal_op;
5089	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5090	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5091	2c0262af	bellard	gen_op_daa();
5092	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5093	2c0262af	bellard	break;
5094	2c0262af	bellard	case 0x2f: /* das */
5095	14ce26e7	bellard	if (CODE64(s))
5096	14ce26e7	bellard	goto illegal_op;
5097	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5098	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5099	2c0262af	bellard	gen_op_das();
5100	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5101	2c0262af	bellard	break;
5102	2c0262af	bellard	case 0x37: /* aaa */
5103	14ce26e7	bellard	if (CODE64(s))
5104	14ce26e7	bellard	goto illegal_op;
5105	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5106	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5107	2c0262af	bellard	gen_op_aaa();
5108	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5109	2c0262af	bellard	break;
5110	2c0262af	bellard	case 0x3f: /* aas */
5111	14ce26e7	bellard	if (CODE64(s))
5112	14ce26e7	bellard	goto illegal_op;
5113	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5114	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5115	2c0262af	bellard	gen_op_aas();
5116	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5117	2c0262af	bellard	break;
5118	2c0262af	bellard	case 0xd4: /* aam */
5119	14ce26e7	bellard	if (CODE64(s))
5120	14ce26e7	bellard	goto illegal_op;
5121	61382a50	bellard	val = ldub_code(s->pc++);
5122	2c0262af	bellard	gen_op_aam(val);
5123	2c0262af	bellard	s->cc_op = CC_OP_LOGICB;
5124	2c0262af	bellard	break;
5125	2c0262af	bellard	case 0xd5: /* aad */
5126	14ce26e7	bellard	if (CODE64(s))
5127	14ce26e7	bellard	goto illegal_op;
5128	61382a50	bellard	val = ldub_code(s->pc++);
5129	2c0262af	bellard	gen_op_aad(val);
5130	2c0262af	bellard	s->cc_op = CC_OP_LOGICB;
5131	2c0262af	bellard	break;
5132	2c0262af	bellard	/************************/
5133	2c0262af	bellard	/* misc */
5134	2c0262af	bellard	case 0x90: /* nop */
5135	14ce26e7	bellard	/* XXX: xchg + rex handling */
5136	ab1f142b	bellard	/* XXX: correct lock test for all insn */
5137	ab1f142b	bellard	if (prefixes & PREFIX_LOCK)
5138	ab1f142b	bellard	goto illegal_op;
5139	2c0262af	bellard	break;
5140	2c0262af	bellard	case 0x9b: /* fwait */
5141	7eee2a50	bellard	if ((s->flags & (HF_MP_MASK \| HF_TS_MASK)) ==
5142	7eee2a50	bellard	(HF_MP_MASK \| HF_TS_MASK)) {
5143	7eee2a50	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5144	2ee73ac3	bellard	} else {
5145	2ee73ac3	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5146	2ee73ac3	bellard	gen_op_set_cc_op(s->cc_op);
5147	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5148	2ee73ac3	bellard	gen_op_fwait();
5149	7eee2a50	bellard	}
5150	2c0262af	bellard	break;
5151	2c0262af	bellard	case 0xcc: /* int3 */
5152	2c0262af	bellard	gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
5153	2c0262af	bellard	break;
5154	2c0262af	bellard	case 0xcd: /* int N */
5155	61382a50	bellard	val = ldub_code(s->pc++);
5156	f115e911	bellard	if (s->vm86 && s->iopl != 3) {
5157	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5158	f115e911	bellard	} else {
5159	f115e911	bellard	gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
5160	f115e911	bellard	}
5161	2c0262af	bellard	break;
5162	2c0262af	bellard	case 0xce: /* into */
5163	14ce26e7	bellard	if (CODE64(s))
5164	14ce26e7	bellard	goto illegal_op;
5165	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5166	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5167	a8ede8ba	bellard	gen_jmp_im(pc_start - s->cs_base);
5168	a8ede8ba	bellard	gen_op_into(s->pc - pc_start);
5169	2c0262af	bellard	break;
5170	2c0262af	bellard	case 0xf1: /* icebp (undocumented, exits to external debugger) */
5171	2c0262af	bellard	gen_debug(s, pc_start - s->cs_base);
5172	2c0262af	bellard	break;
5173	2c0262af	bellard	case 0xfa: /* cli */
5174	2c0262af	bellard	if (!s->vm86) {
5175	2c0262af	bellard	if (s->cpl <= s->iopl) {
5176	2c0262af	bellard	gen_op_cli();
5177	2c0262af	bellard	} else {
5178	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5179	2c0262af	bellard	}
5180	2c0262af	bellard	} else {
5181	2c0262af	bellard	if (s->iopl == 3) {
5182	2c0262af	bellard	gen_op_cli();
5183	2c0262af	bellard	} else {
5184	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5185	2c0262af	bellard	}
5186	2c0262af	bellard	}
5187	2c0262af	bellard	break;
5188	2c0262af	bellard	case 0xfb: /* sti */
5189	2c0262af	bellard	if (!s->vm86) {
5190	2c0262af	bellard	if (s->cpl <= s->iopl) {
5191	2c0262af	bellard	gen_sti:
5192	2c0262af	bellard	gen_op_sti();
5193	2c0262af	bellard	/* interruptions are enabled only the first insn after sti */
5194	a2cc3b24	bellard	/* If several instructions disable interrupts, only the
5195	a2cc3b24	bellard	_first_ does it */
5196	a2cc3b24	bellard	if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5197	a2cc3b24	bellard	gen_op_set_inhibit_irq();
5198	2c0262af	bellard	/* give a chance to handle pending irqs */
5199	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5200	2c0262af	bellard	gen_eob(s);
5201	2c0262af	bellard	} else {
5202	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5203	2c0262af	bellard	}
5204	2c0262af	bellard	} else {
5205	2c0262af	bellard	if (s->iopl == 3) {
5206	2c0262af	bellard	goto gen_sti;
5207	2c0262af	bellard	} else {
5208	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5209	2c0262af	bellard	}
5210	2c0262af	bellard	}
5211	2c0262af	bellard	break;
5212	2c0262af	bellard	case 0x62: /* bound */
5213	14ce26e7	bellard	if (CODE64(s))
5214	14ce26e7	bellard	goto illegal_op;
5215	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
5216	61382a50	bellard	modrm = ldub_code(s->pc++);
5217	2c0262af	bellard	reg = (modrm >> 3) & 7;
5218	2c0262af	bellard	mod = (modrm >> 6) & 3;
5219	2c0262af	bellard	if (mod == 3)
5220	2c0262af	bellard	goto illegal_op;
5221	cabf23c3	bellard	gen_op_mov_TN_reg[ot][0][reg]();
5222	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5223	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5224	2c0262af	bellard	if (ot == OT_WORD)
5225	14ce26e7	bellard	gen_op_boundw();
5226	2c0262af	bellard	else
5227	14ce26e7	bellard	gen_op_boundl();
5228	2c0262af	bellard	break;
5229	2c0262af	bellard	case 0x1c8 ... 0x1cf: /* bswap reg */
5230	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
5231	14ce26e7	bellard	#ifdef TARGET_X86_64
5232	14ce26e7	bellard	if (dflag == 2) {
5233	14ce26e7	bellard	gen_op_mov_TN_reg[OT_QUAD][0][reg]();
5234	14ce26e7	bellard	gen_op_bswapq_T0();
5235	14ce26e7	bellard	gen_op_mov_reg_T0[OT_QUAD][reg]();
5236	14ce26e7	bellard	} else
5237	14ce26e7	bellard	#endif
5238	14ce26e7	bellard	{
5239	14ce26e7	bellard	gen_op_mov_TN_reg[OT_LONG][0][reg]();
5240	14ce26e7	bellard	gen_op_bswapl_T0();
5241	14ce26e7	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
5242	14ce26e7	bellard	}
5243	2c0262af	bellard	break;
5244	2c0262af	bellard	case 0xd6: /* salc */
5245	14ce26e7	bellard	if (CODE64(s))
5246	14ce26e7	bellard	goto illegal_op;
5247	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5248	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5249	2c0262af	bellard	gen_op_salc();
5250	2c0262af	bellard	break;
5251	2c0262af	bellard	case 0xe0: /* loopnz */
5252	2c0262af	bellard	case 0xe1: /* loopz */
5253	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5254	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5255	2c0262af	bellard	/* FALL THRU */
5256	2c0262af	bellard	case 0xe2: /* loop */
5257	2c0262af	bellard	case 0xe3: /* jecxz */
5258	14ce26e7	bellard	{
5259	14ce26e7	bellard	int l1, l2;
5260	14ce26e7	bellard
5261	14ce26e7	bellard	tval = (int8_t)insn_get(s, OT_BYTE);
5262	14ce26e7	bellard	next_eip = s->pc - s->cs_base;
5263	14ce26e7	bellard	tval += next_eip;
5264	14ce26e7	bellard	if (s->dflag == 0)
5265	14ce26e7	bellard	tval &= 0xffff;
5266	14ce26e7	bellard
5267	14ce26e7	bellard	l1 = gen_new_label();
5268	14ce26e7	bellard	l2 = gen_new_label();
5269	14ce26e7	bellard	b &= 3;
5270	14ce26e7	bellard	if (b == 3) {
5271	14ce26e7	bellard	gen_op_jz_ecx[s->aflag](l1);
5272	14ce26e7	bellard	} else {
5273	14ce26e7	bellard	gen_op_dec_ECX[s->aflag]();
5274	14ce26e7	bellard	gen_op_loop[s->aflag][b](l1);
5275	14ce26e7	bellard	}
5276	14ce26e7	bellard
5277	14ce26e7	bellard	gen_jmp_im(next_eip);
5278	14ce26e7	bellard	gen_op_jmp_label(l2);
5279	14ce26e7	bellard	gen_set_label(l1);
5280	14ce26e7	bellard	gen_jmp_im(tval);
5281	14ce26e7	bellard	gen_set_label(l2);
5282	14ce26e7	bellard	gen_eob(s);
5283	14ce26e7	bellard	}
5284	2c0262af	bellard	break;
5285	2c0262af	bellard	case 0x130: /* wrmsr */
5286	2c0262af	bellard	case 0x132: /* rdmsr */
5287	2c0262af	bellard	if (s->cpl != 0) {
5288	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5289	2c0262af	bellard	} else {
5290	2c0262af	bellard	if (b & 2)
5291	2c0262af	bellard	gen_op_rdmsr();
5292	2c0262af	bellard	else
5293	2c0262af	bellard	gen_op_wrmsr();
5294	2c0262af	bellard	}
5295	2c0262af	bellard	break;
5296	2c0262af	bellard	case 0x131: /* rdtsc */
5297	2c0262af	bellard	gen_op_rdtsc();
5298	2c0262af	bellard	break;
5299	023fe10d	bellard	case 0x134: /* sysenter */
5300	14ce26e7	bellard	if (CODE64(s))
5301	14ce26e7	bellard	goto illegal_op;
5302	023fe10d	bellard	if (!s->pe) {
5303	023fe10d	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5304	023fe10d	bellard	} else {
5305	023fe10d	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5306	023fe10d	bellard	gen_op_set_cc_op(s->cc_op);
5307	023fe10d	bellard	s->cc_op = CC_OP_DYNAMIC;
5308	023fe10d	bellard	}
5309	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5310	023fe10d	bellard	gen_op_sysenter();
5311	023fe10d	bellard	gen_eob(s);
5312	023fe10d	bellard	}
5313	023fe10d	bellard	break;
5314	023fe10d	bellard	case 0x135: /* sysexit */
5315	14ce26e7	bellard	if (CODE64(s))
5316	14ce26e7	bellard	goto illegal_op;
5317	023fe10d	bellard	if (!s->pe) {
5318	023fe10d	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5319	023fe10d	bellard	} else {
5320	023fe10d	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5321	023fe10d	bellard	gen_op_set_cc_op(s->cc_op);
5322	023fe10d	bellard	s->cc_op = CC_OP_DYNAMIC;
5323	023fe10d	bellard	}
5324	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5325	023fe10d	bellard	gen_op_sysexit();
5326	023fe10d	bellard	gen_eob(s);
5327	023fe10d	bellard	}
5328	023fe10d	bellard	break;
5329	14ce26e7	bellard	#ifdef TARGET_X86_64
5330	14ce26e7	bellard	case 0x105: /* syscall */
5331	14ce26e7	bellard	/* XXX: is it usable in real mode ? */
5332	14ce26e7	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5333	14ce26e7	bellard	gen_op_set_cc_op(s->cc_op);
5334	14ce26e7	bellard	s->cc_op = CC_OP_DYNAMIC;
5335	14ce26e7	bellard	}
5336	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5337	06c2f506	bellard	gen_op_syscall(s->pc - pc_start);
5338	14ce26e7	bellard	gen_eob(s);
5339	14ce26e7	bellard	break;
5340	14ce26e7	bellard	case 0x107: /* sysret */
5341	14ce26e7	bellard	if (!s->pe) {
5342	14ce26e7	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5343	14ce26e7	bellard	} else {
5344	14ce26e7	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5345	14ce26e7	bellard	gen_op_set_cc_op(s->cc_op);
5346	14ce26e7	bellard	s->cc_op = CC_OP_DYNAMIC;
5347	14ce26e7	bellard	}
5348	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5349	14ce26e7	bellard	gen_op_sysret(s->dflag);
5350	14ce26e7	bellard	gen_eob(s);
5351	14ce26e7	bellard	}
5352	14ce26e7	bellard	break;
5353	14ce26e7	bellard	#endif
5354	2c0262af	bellard	case 0x1a2: /* cpuid */
5355	2c0262af	bellard	gen_op_cpuid();
5356	2c0262af	bellard	break;
5357	2c0262af	bellard	case 0xf4: /* hlt */
5358	2c0262af	bellard	if (s->cpl != 0) {
5359	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5360	2c0262af	bellard	} else {
5361	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5362	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5363	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5364	2c0262af	bellard	gen_op_hlt();
5365	2c0262af	bellard	s->is_jmp = 3;
5366	2c0262af	bellard	}
5367	2c0262af	bellard	break;
5368	2c0262af	bellard	case 0x100:
5369	61382a50	bellard	modrm = ldub_code(s->pc++);
5370	2c0262af	bellard	mod = (modrm >> 6) & 3;
5371	2c0262af	bellard	op = (modrm >> 3) & 7;
5372	2c0262af	bellard	switch(op) {
5373	2c0262af	bellard	case 0: /* sldt */
5374	f115e911	bellard	if (!s->pe \|\| s->vm86)
5375	f115e911	bellard	goto illegal_op;
5376	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
5377	2c0262af	bellard	ot = OT_WORD;
5378	2c0262af	bellard	if (mod == 3)
5379	2c0262af	bellard	ot += s->dflag;
5380	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5381	2c0262af	bellard	break;
5382	2c0262af	bellard	case 2: /* lldt */
5383	f115e911	bellard	if (!s->pe \|\| s->vm86)
5384	f115e911	bellard	goto illegal_op;
5385	2c0262af	bellard	if (s->cpl != 0) {
5386	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5387	2c0262af	bellard	} else {
5388	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5389	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5390	2c0262af	bellard	gen_op_lldt_T0();
5391	2c0262af	bellard	}
5392	2c0262af	bellard	break;
5393	2c0262af	bellard	case 1: /* str */
5394	f115e911	bellard	if (!s->pe \|\| s->vm86)
5395	f115e911	bellard	goto illegal_op;
5396	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
5397	2c0262af	bellard	ot = OT_WORD;
5398	2c0262af	bellard	if (mod == 3)
5399	2c0262af	bellard	ot += s->dflag;
5400	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5401	2c0262af	bellard	break;
5402	2c0262af	bellard	case 3: /* ltr */
5403	f115e911	bellard	if (!s->pe \|\| s->vm86)
5404	f115e911	bellard	goto illegal_op;
5405	2c0262af	bellard	if (s->cpl != 0) {
5406	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5407	2c0262af	bellard	} else {
5408	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5409	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5410	2c0262af	bellard	gen_op_ltr_T0();
5411	2c0262af	bellard	}
5412	2c0262af	bellard	break;
5413	2c0262af	bellard	case 4: /* verr */
5414	2c0262af	bellard	case 5: /* verw */
5415	f115e911	bellard	if (!s->pe \|\| s->vm86)
5416	f115e911	bellard	goto illegal_op;
5417	f115e911	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5418	f115e911	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5419	f115e911	bellard	gen_op_set_cc_op(s->cc_op);
5420	f115e911	bellard	if (op == 4)
5421	f115e911	bellard	gen_op_verr();
5422	f115e911	bellard	else
5423	f115e911	bellard	gen_op_verw();
5424	f115e911	bellard	s->cc_op = CC_OP_EFLAGS;
5425	f115e911	bellard	break;
5426	2c0262af	bellard	default:
5427	2c0262af	bellard	goto illegal_op;
5428	2c0262af	bellard	}
5429	2c0262af	bellard	break;
5430	2c0262af	bellard	case 0x101:
5431	61382a50	bellard	modrm = ldub_code(s->pc++);
5432	2c0262af	bellard	mod = (modrm >> 6) & 3;
5433	2c0262af	bellard	op = (modrm >> 3) & 7;
5434	2c0262af	bellard	switch(op) {
5435	2c0262af	bellard	case 0: /* sgdt */
5436	2c0262af	bellard	case 1: /* sidt */
5437	2c0262af	bellard	if (mod == 3)
5438	2c0262af	bellard	goto illegal_op;
5439	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5440	2c0262af	bellard	if (op == 0)
5441	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
5442	2c0262af	bellard	else
5443	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
5444	2c0262af	bellard	gen_op_st_T0_A0[OT_WORD + s->mem_index]();
5445	14ce26e7	bellard	#ifdef TARGET_X86_64
5446	14ce26e7	bellard	if (CODE64(s))
5447	14ce26e7	bellard	gen_op_addq_A0_im(2);
5448	14ce26e7	bellard	else
5449	14ce26e7	bellard	#endif
5450	14ce26e7	bellard	gen_op_addl_A0_im(2);
5451	2c0262af	bellard	if (op == 0)
5452	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,gdt.base));
5453	2c0262af	bellard	else
5454	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,idt.base));
5455	2c0262af	bellard	if (!s->dflag)
5456	2c0262af	bellard	gen_op_andl_T0_im(0xffffff);
5457	14ce26e7	bellard	gen_op_st_T0_A0[CODE64(s) + OT_LONG + s->mem_index]();
5458	2c0262af	bellard	break;
5459	2c0262af	bellard	case 2: /* lgdt */
5460	2c0262af	bellard	case 3: /* lidt */
5461	2c0262af	bellard	if (mod == 3)
5462	2c0262af	bellard	goto illegal_op;
5463	2c0262af	bellard	if (s->cpl != 0) {
5464	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5465	2c0262af	bellard	} else {
5466	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5467	2c0262af	bellard	gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
5468	14ce26e7	bellard	#ifdef TARGET_X86_64
5469	14ce26e7	bellard	if (CODE64(s))
5470	14ce26e7	bellard	gen_op_addq_A0_im(2);
5471	14ce26e7	bellard	else
5472	14ce26e7	bellard	#endif
5473	14ce26e7	bellard	gen_op_addl_A0_im(2);
5474	14ce26e7	bellard	gen_op_ld_T0_A0[CODE64(s) + OT_LONG + s->mem_index]();
5475	2c0262af	bellard	if (!s->dflag)
5476	2c0262af	bellard	gen_op_andl_T0_im(0xffffff);
5477	2c0262af	bellard	if (op == 2) {
5478	14ce26e7	bellard	gen_op_movtl_env_T0(offsetof(CPUX86State,gdt.base));
5479	2c0262af	bellard	gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
5480	2c0262af	bellard	} else {
5481	14ce26e7	bellard	gen_op_movtl_env_T0(offsetof(CPUX86State,idt.base));
5482	2c0262af	bellard	gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
5483	2c0262af	bellard	}
5484	2c0262af	bellard	}
5485	2c0262af	bellard	break;
5486	2c0262af	bellard	case 4: /* smsw */
5487	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
5488	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
5489	2c0262af	bellard	break;
5490	2c0262af	bellard	case 6: /* lmsw */
5491	2c0262af	bellard	if (s->cpl != 0) {
5492	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5493	2c0262af	bellard	} else {
5494	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5495	2c0262af	bellard	gen_op_lmsw_T0();
5496	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5497	d71b9a8b	bellard	gen_eob(s);
5498	2c0262af	bellard	}
5499	2c0262af	bellard	break;
5500	2c0262af	bellard	case 7: /* invlpg */
5501	2c0262af	bellard	if (s->cpl != 0) {
5502	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5503	2c0262af	bellard	} else {
5504	14ce26e7	bellard	if (mod == 3) {
5505	14ce26e7	bellard	#ifdef TARGET_X86_64
5506	14ce26e7	bellard	if (CODE64(s) && (modrm & 7) == 0) {
5507	14ce26e7	bellard	/* swapgs */
5508	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,segs[R_GS].base));
5509	14ce26e7	bellard	gen_op_movtl_T1_env(offsetof(CPUX86State,kernelgsbase));
5510	14ce26e7	bellard	gen_op_movtl_env_T1(offsetof(CPUX86State,segs[R_GS].base));
5511	14ce26e7	bellard	gen_op_movtl_env_T0(offsetof(CPUX86State,kernelgsbase));
5512	14ce26e7	bellard	} else
5513	14ce26e7	bellard	#endif
5514	14ce26e7	bellard	{
5515	14ce26e7	bellard	goto illegal_op;
5516	14ce26e7	bellard	}
5517	14ce26e7	bellard	} else {
5518	14ce26e7	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5519	14ce26e7	bellard	gen_op_invlpg_A0();
5520	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5521	14ce26e7	bellard	gen_eob(s);
5522	14ce26e7	bellard	}
5523	2c0262af	bellard	}
5524	2c0262af	bellard	break;
5525	2c0262af	bellard	default:
5526	2c0262af	bellard	goto illegal_op;
5527	2c0262af	bellard	}
5528	2c0262af	bellard	break;
5529	3415a4dd	bellard	case 0x108: /* invd */
5530	3415a4dd	bellard	case 0x109: /* wbinvd */
5531	3415a4dd	bellard	if (s->cpl != 0) {
5532	3415a4dd	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5533	3415a4dd	bellard	} else {
5534	3415a4dd	bellard	/* nothing to do */
5535	3415a4dd	bellard	}
5536	3415a4dd	bellard	break;
5537	14ce26e7	bellard	case 0x63: /* arpl or movslS (x86_64) */
5538	14ce26e7	bellard	#ifdef TARGET_X86_64
5539	14ce26e7	bellard	if (CODE64(s)) {
5540	14ce26e7	bellard	int d_ot;
5541	14ce26e7	bellard	/* d_ot is the size of destination */
5542	14ce26e7	bellard	d_ot = dflag + OT_WORD;
5543	14ce26e7	bellard
5544	14ce26e7	bellard	modrm = ldub_code(s->pc++);
5545	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5546	14ce26e7	bellard	mod = (modrm >> 6) & 3;
5547	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5548	14ce26e7	bellard
5549	14ce26e7	bellard	if (mod == 3) {
5550	14ce26e7	bellard	gen_op_mov_TN_reg[OT_LONG][0][rm]();
5551	14ce26e7	bellard	/* sign extend */
5552	14ce26e7	bellard	if (d_ot == OT_QUAD)
5553	14ce26e7	bellard	gen_op_movslq_T0_T0();
5554	14ce26e7	bellard	gen_op_mov_reg_T0[d_ot][reg]();
5555	14ce26e7	bellard	} else {
5556	14ce26e7	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5557	14ce26e7	bellard	if (d_ot == OT_QUAD) {
5558	14ce26e7	bellard	gen_op_lds_T0_A0[OT_LONG + s->mem_index]();
5559	14ce26e7	bellard	} else {
5560	14ce26e7	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
5561	14ce26e7	bellard	}
5562	14ce26e7	bellard	gen_op_mov_reg_T0[d_ot][reg]();
5563	14ce26e7	bellard	}
5564	14ce26e7	bellard	} else
5565	14ce26e7	bellard	#endif
5566	14ce26e7	bellard	{
5567	14ce26e7	bellard	if (!s->pe \|\| s->vm86)
5568	14ce26e7	bellard	goto illegal_op;
5569	14ce26e7	bellard	ot = dflag ? OT_LONG : OT_WORD;
5570	14ce26e7	bellard	modrm = ldub_code(s->pc++);
5571	14ce26e7	bellard	reg = (modrm >> 3) & 7;
5572	14ce26e7	bellard	mod = (modrm >> 6) & 3;
5573	14ce26e7	bellard	rm = modrm & 7;
5574	14ce26e7	bellard	if (mod != 3) {
5575	14ce26e7	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5576	14ce26e7	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
5577	14ce26e7	bellard	} else {
5578	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5579	14ce26e7	bellard	}
5580	14ce26e7	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5581	14ce26e7	bellard	gen_op_set_cc_op(s->cc_op);
5582	14ce26e7	bellard	gen_op_arpl();
5583	14ce26e7	bellard	s->cc_op = CC_OP_EFLAGS;
5584	14ce26e7	bellard	if (mod != 3) {
5585	14ce26e7	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
5586	14ce26e7	bellard	} else {
5587	14ce26e7	bellard	gen_op_mov_reg_T0[ot][rm]();
5588	14ce26e7	bellard	}
5589	14ce26e7	bellard	gen_op_arpl_update();
5590	f115e911	bellard	}
5591	f115e911	bellard	break;
5592	2c0262af	bellard	case 0x102: /* lar */
5593	2c0262af	bellard	case 0x103: /* lsl */
5594	2c0262af	bellard	if (!s->pe \|\| s->vm86)
5595	2c0262af	bellard	goto illegal_op;
5596	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
5597	61382a50	bellard	modrm = ldub_code(s->pc++);
5598	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5599	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5600	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
5601	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5602	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5603	2c0262af	bellard	if (b == 0x102)
5604	2c0262af	bellard	gen_op_lar();
5605	2c0262af	bellard	else
5606	2c0262af	bellard	gen_op_lsl();
5607	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5608	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
5609	2c0262af	bellard	break;
5610	2c0262af	bellard	case 0x118:
5611	61382a50	bellard	modrm = ldub_code(s->pc++);
5612	2c0262af	bellard	mod = (modrm >> 6) & 3;
5613	2c0262af	bellard	op = (modrm >> 3) & 7;
5614	2c0262af	bellard	switch(op) {
5615	2c0262af	bellard	case 0: /* prefetchnta */
5616	2c0262af	bellard	case 1: /* prefetchnt0 */
5617	2c0262af	bellard	case 2: /* prefetchnt0 */
5618	2c0262af	bellard	case 3: /* prefetchnt0 */
5619	2c0262af	bellard	if (mod == 3)
5620	2c0262af	bellard	goto illegal_op;
5621	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5622	2c0262af	bellard	/* nothing more to do */
5623	2c0262af	bellard	break;
5624	2c0262af	bellard	default:
5625	2c0262af	bellard	goto illegal_op;
5626	2c0262af	bellard	}
5627	2c0262af	bellard	break;
5628	2c0262af	bellard	case 0x120: /* mov reg, crN */
5629	2c0262af	bellard	case 0x122: /* mov crN, reg */
5630	2c0262af	bellard	if (s->cpl != 0) {
5631	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5632	2c0262af	bellard	} else {
5633	61382a50	bellard	modrm = ldub_code(s->pc++);
5634	2c0262af	bellard	if ((modrm & 0xc0) != 0xc0)
5635	2c0262af	bellard	goto illegal_op;
5636	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5637	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5638	14ce26e7	bellard	if (CODE64(s))
5639	14ce26e7	bellard	ot = OT_QUAD;
5640	14ce26e7	bellard	else
5641	14ce26e7	bellard	ot = OT_LONG;
5642	2c0262af	bellard	switch(reg) {
5643	2c0262af	bellard	case 0:
5644	2c0262af	bellard	case 2:
5645	2c0262af	bellard	case 3:
5646	2c0262af	bellard	case 4:
5647	9230e66e	bellard	case 8:
5648	2c0262af	bellard	if (b & 2) {
5649	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5650	2c0262af	bellard	gen_op_movl_crN_T0(reg);
5651	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5652	2c0262af	bellard	gen_eob(s);
5653	2c0262af	bellard	} else {
5654	82e41634	bellard	#if !defined(CONFIG_USER_ONLY)
5655	9230e66e	bellard	if (reg == 8)
5656	9230e66e	bellard	gen_op_movtl_T0_cr8();
5657	9230e66e	bellard	else
5658	82e41634	bellard	#endif
5659	9230e66e	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg]));
5660	14ce26e7	bellard	gen_op_mov_reg_T0[ot][rm]();
5661	2c0262af	bellard	}
5662	2c0262af	bellard	break;
5663	2c0262af	bellard	default:
5664	2c0262af	bellard	goto illegal_op;
5665	2c0262af	bellard	}
5666	2c0262af	bellard	}
5667	2c0262af	bellard	break;
5668	2c0262af	bellard	case 0x121: /* mov reg, drN */
5669	2c0262af	bellard	case 0x123: /* mov drN, reg */
5670	2c0262af	bellard	if (s->cpl != 0) {
5671	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5672	2c0262af	bellard	} else {
5673	61382a50	bellard	modrm = ldub_code(s->pc++);
5674	2c0262af	bellard	if ((modrm & 0xc0) != 0xc0)
5675	2c0262af	bellard	goto illegal_op;
5676	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5677	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5678	14ce26e7	bellard	if (CODE64(s))
5679	14ce26e7	bellard	ot = OT_QUAD;
5680	14ce26e7	bellard	else
5681	14ce26e7	bellard	ot = OT_LONG;
5682	2c0262af	bellard	/* XXX: do it dynamically with CR4.DE bit */
5683	14ce26e7	bellard	if (reg == 4 \|\| reg == 5 \|\| reg >= 8)
5684	2c0262af	bellard	goto illegal_op;
5685	2c0262af	bellard	if (b & 2) {
5686	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5687	2c0262af	bellard	gen_op_movl_drN_T0(reg);
5688	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5689	2c0262af	bellard	gen_eob(s);
5690	2c0262af	bellard	} else {
5691	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,dr[reg]));
5692	14ce26e7	bellard	gen_op_mov_reg_T0[ot][rm]();
5693	2c0262af	bellard	}
5694	2c0262af	bellard	}
5695	2c0262af	bellard	break;
5696	2c0262af	bellard	case 0x106: /* clts */
5697	2c0262af	bellard	if (s->cpl != 0) {
5698	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5699	2c0262af	bellard	} else {
5700	2c0262af	bellard	gen_op_clts();
5701	7eee2a50	bellard	/* abort block because static cpu state changed */
5702	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5703	7eee2a50	bellard	gen_eob(s);
5704	2c0262af	bellard	}
5705	2c0262af	bellard	break;
5706	664e0f19	bellard	/* MMX/SSE/SSE2/PNI support */
5707	664e0f19	bellard	case 0x1c3: /* MOVNTI reg, mem */
5708	664e0f19	bellard	if (!(s->cpuid_features & CPUID_SSE2))
5709	14ce26e7	bellard	goto illegal_op;
5710	664e0f19	bellard	ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
5711	664e0f19	bellard	modrm = ldub_code(s->pc++);
5712	664e0f19	bellard	mod = (modrm >> 6) & 3;
5713	664e0f19	bellard	if (mod == 3)
5714	664e0f19	bellard	goto illegal_op;
5715	664e0f19	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5716	664e0f19	bellard	/* generate a generic store */
5717	664e0f19	bellard	gen_ldst_modrm(s, modrm, ot, reg, 1);
5718	14ce26e7	bellard	break;
5719	664e0f19	bellard	case 0x1ae:
5720	664e0f19	bellard	modrm = ldub_code(s->pc++);
5721	664e0f19	bellard	mod = (modrm >> 6) & 3;
5722	664e0f19	bellard	op = (modrm >> 3) & 7;
5723	664e0f19	bellard	switch(op) {
5724	664e0f19	bellard	case 0: /* fxsave */
5725	664e0f19	bellard	if (mod == 3 \|\| !(s->cpuid_features & CPUID_FXSR))
5726	14ce26e7	bellard	goto illegal_op;
5727	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5728	664e0f19	bellard	gen_op_fxsave_A0((s->dflag == 2));
5729	664e0f19	bellard	break;
5730	664e0f19	bellard	case 1: /* fxrstor */
5731	664e0f19	bellard	if (mod == 3 \|\| !(s->cpuid_features & CPUID_FXSR))
5732	14ce26e7	bellard	goto illegal_op;
5733	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5734	664e0f19	bellard	gen_op_fxrstor_A0((s->dflag == 2));
5735	664e0f19	bellard	break;
5736	664e0f19	bellard	case 2: /* ldmxcsr */
5737	664e0f19	bellard	case 3: /* stmxcsr */
5738	664e0f19	bellard	if (s->flags & HF_TS_MASK) {
5739	664e0f19	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5740	664e0f19	bellard	break;
5741	14ce26e7	bellard	}
5742	664e0f19	bellard	if ((s->flags & HF_EM_MASK) \|\| !(s->flags & HF_OSFXSR_MASK) \|\|
5743	664e0f19	bellard	mod == 3)
5744	14ce26e7	bellard	goto illegal_op;
5745	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5746	664e0f19	bellard	if (op == 2) {
5747	664e0f19	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
5748	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State, mxcsr));
5749	14ce26e7	bellard	} else {
5750	664e0f19	bellard	gen_op_movl_T0_env(offsetof(CPUX86State, mxcsr));
5751	664e0f19	bellard	gen_op_st_T0_A0[OT_LONG + s->mem_index]();
5752	14ce26e7	bellard	}
5753	664e0f19	bellard	break;
5754	664e0f19	bellard	case 5: /* lfence */
5755	664e0f19	bellard	case 6: /* mfence */
5756	664e0f19	bellard	case 7: /* sfence */
5757	664e0f19	bellard	if ((modrm & 0xc7) != 0xc0 \|\| !(s->cpuid_features & CPUID_SSE))
5758	664e0f19	bellard	goto illegal_op;
5759	664e0f19	bellard	break;
5760	664e0f19	bellard	default:
5761	14ce26e7	bellard	goto illegal_op;
5762	14ce26e7	bellard	}
5763	14ce26e7	bellard	break;
5764	664e0f19	bellard	case 0x110 ... 0x117:
5765	664e0f19	bellard	case 0x128 ... 0x12f:
5766	664e0f19	bellard	case 0x150 ... 0x177:
5767	664e0f19	bellard	case 0x17c ... 0x17f:
5768	664e0f19	bellard	case 0x1c2:
5769	664e0f19	bellard	case 0x1c4 ... 0x1c6:
5770	664e0f19	bellard	case 0x1d0 ... 0x1fe:
5771	664e0f19	bellard	gen_sse(s, b, pc_start, rex_r);
5772	664e0f19	bellard	break;
5773	2c0262af	bellard	default:
5774	2c0262af	bellard	goto illegal_op;
5775	2c0262af	bellard	}
5776	2c0262af	bellard	/* lock generation */
5777	2c0262af	bellard	if (s->prefix & PREFIX_LOCK)
5778	2c0262af	bellard	gen_op_unlock();
5779	2c0262af	bellard	return s->pc;
5780	2c0262af	bellard	illegal_op:
5781	ab1f142b	bellard	if (s->prefix & PREFIX_LOCK)
5782	ab1f142b	bellard	gen_op_unlock();
5783	2c0262af	bellard	/* XXX: ensure that no lock was generated */
5784	2c0262af	bellard	gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
5785	2c0262af	bellard	return s->pc;
5786	2c0262af	bellard	}
5787	2c0262af	bellard
5788	2c0262af	bellard	#define CC_OSZAPC (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C)
5789	2c0262af	bellard	#define CC_OSZAP (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P)
5790	2c0262af	bellard
5791	2c0262af	bellard	/* flags read by an operation */
5792	2c0262af	bellard	static uint16_t opc_read_flags[NB_OPS] = {
5793	2c0262af	bellard	[INDEX_op_aas] = CC_A,
5794	2c0262af	bellard	[INDEX_op_aaa] = CC_A,
5795	2c0262af	bellard	[INDEX_op_das] = CC_A \| CC_C,
5796	2c0262af	bellard	[INDEX_op_daa] = CC_A \| CC_C,
5797	2c0262af	bellard
5798	2c0262af	bellard	/* subtle: due to the incl/decl implementation, C is used */
5799	2c0262af	bellard	[INDEX_op_update_inc_cc] = CC_C,
5800	2c0262af	bellard
5801	2c0262af	bellard	[INDEX_op_into] = CC_O,
5802	2c0262af	bellard
5803	2c0262af	bellard	[INDEX_op_jb_subb] = CC_C,
5804	2c0262af	bellard	[INDEX_op_jb_subw] = CC_C,
5805	2c0262af	bellard	[INDEX_op_jb_subl] = CC_C,
5806	2c0262af	bellard
5807	2c0262af	bellard	[INDEX_op_jz_subb] = CC_Z,
5808	2c0262af	bellard	[INDEX_op_jz_subw] = CC_Z,
5809	2c0262af	bellard	[INDEX_op_jz_subl] = CC_Z,
5810	2c0262af	bellard
5811	2c0262af	bellard	[INDEX_op_jbe_subb] = CC_Z \| CC_C,
5812	2c0262af	bellard	[INDEX_op_jbe_subw] = CC_Z \| CC_C,
5813	2c0262af	bellard	[INDEX_op_jbe_subl] = CC_Z \| CC_C,
5814	2c0262af	bellard
5815	2c0262af	bellard	[INDEX_op_js_subb] = CC_S,
5816	2c0262af	bellard	[INDEX_op_js_subw] = CC_S,
5817	2c0262af	bellard	[INDEX_op_js_subl] = CC_S,
5818	2c0262af	bellard
5819	2c0262af	bellard	[INDEX_op_jl_subb] = CC_O \| CC_S,
5820	2c0262af	bellard	[INDEX_op_jl_subw] = CC_O \| CC_S,
5821	2c0262af	bellard	[INDEX_op_jl_subl] = CC_O \| CC_S,
5822	2c0262af	bellard
5823	2c0262af	bellard	[INDEX_op_jle_subb] = CC_O \| CC_S \| CC_Z,
5824	2c0262af	bellard	[INDEX_op_jle_subw] = CC_O \| CC_S \| CC_Z,
5825	2c0262af	bellard	[INDEX_op_jle_subl] = CC_O \| CC_S \| CC_Z,
5826	2c0262af	bellard
5827	2c0262af	bellard	[INDEX_op_loopnzw] = CC_Z,
5828	2c0262af	bellard	[INDEX_op_loopnzl] = CC_Z,
5829	2c0262af	bellard	[INDEX_op_loopzw] = CC_Z,
5830	2c0262af	bellard	[INDEX_op_loopzl] = CC_Z,
5831	2c0262af	bellard
5832	2c0262af	bellard	[INDEX_op_seto_T0_cc] = CC_O,
5833	2c0262af	bellard	[INDEX_op_setb_T0_cc] = CC_C,
5834	2c0262af	bellard	[INDEX_op_setz_T0_cc] = CC_Z,
5835	2c0262af	bellard	[INDEX_op_setbe_T0_cc] = CC_Z \| CC_C,
5836	2c0262af	bellard	[INDEX_op_sets_T0_cc] = CC_S,
5837	2c0262af	bellard	[INDEX_op_setp_T0_cc] = CC_P,
5838	2c0262af	bellard	[INDEX_op_setl_T0_cc] = CC_O \| CC_S,
5839	2c0262af	bellard	[INDEX_op_setle_T0_cc] = CC_O \| CC_S \| CC_Z,
5840	2c0262af	bellard
5841	2c0262af	bellard	[INDEX_op_setb_T0_subb] = CC_C,
5842	2c0262af	bellard	[INDEX_op_setb_T0_subw] = CC_C,
5843	2c0262af	bellard	[INDEX_op_setb_T0_subl] = CC_C,
5844	2c0262af	bellard
5845	2c0262af	bellard	[INDEX_op_setz_T0_subb] = CC_Z,
5846	2c0262af	bellard	[INDEX_op_setz_T0_subw] = CC_Z,
5847	2c0262af	bellard	[INDEX_op_setz_T0_subl] = CC_Z,
5848	2c0262af	bellard
5849	2c0262af	bellard	[INDEX_op_setbe_T0_subb] = CC_Z \| CC_C,
5850	2c0262af	bellard	[INDEX_op_setbe_T0_subw] = CC_Z \| CC_C,
5851	2c0262af	bellard	[INDEX_op_setbe_T0_subl] = CC_Z \| CC_C,
5852	2c0262af	bellard
5853	2c0262af	bellard	[INDEX_op_sets_T0_subb] = CC_S,
5854	2c0262af	bellard	[INDEX_op_sets_T0_subw] = CC_S,
5855	2c0262af	bellard	[INDEX_op_sets_T0_subl] = CC_S,
5856	2c0262af	bellard
5857	2c0262af	bellard	[INDEX_op_setl_T0_subb] = CC_O \| CC_S,
5858	2c0262af	bellard	[INDEX_op_setl_T0_subw] = CC_O \| CC_S,
5859	2c0262af	bellard	[INDEX_op_setl_T0_subl] = CC_O \| CC_S,
5860	2c0262af	bellard
5861	2c0262af	bellard	[INDEX_op_setle_T0_subb] = CC_O \| CC_S \| CC_Z,
5862	2c0262af	bellard	[INDEX_op_setle_T0_subw] = CC_O \| CC_S \| CC_Z,
5863	2c0262af	bellard	[INDEX_op_setle_T0_subl] = CC_O \| CC_S \| CC_Z,
5864	2c0262af	bellard
5865	2c0262af	bellard	[INDEX_op_movl_T0_eflags] = CC_OSZAPC,
5866	2c0262af	bellard	[INDEX_op_cmc] = CC_C,
5867	2c0262af	bellard	[INDEX_op_salc] = CC_C,
5868	2c0262af	bellard
5869	7399c5a9	bellard	/* needed for correct flag optimisation before string ops */
5870	14ce26e7	bellard	[INDEX_op_jnz_ecxw] = CC_OSZAPC,
5871	14ce26e7	bellard	[INDEX_op_jnz_ecxl] = CC_OSZAPC,
5872	7399c5a9	bellard	[INDEX_op_jz_ecxw] = CC_OSZAPC,
5873	7399c5a9	bellard	[INDEX_op_jz_ecxl] = CC_OSZAPC,
5874	14ce26e7	bellard
5875	14ce26e7	bellard	#ifdef TARGET_X86_64
5876	14ce26e7	bellard	[INDEX_op_jb_subq] = CC_C,
5877	14ce26e7	bellard	[INDEX_op_jz_subq] = CC_Z,
5878	14ce26e7	bellard	[INDEX_op_jbe_subq] = CC_Z \| CC_C,
5879	14ce26e7	bellard	[INDEX_op_js_subq] = CC_S,
5880	14ce26e7	bellard	[INDEX_op_jl_subq] = CC_O \| CC_S,
5881	14ce26e7	bellard	[INDEX_op_jle_subq] = CC_O \| CC_S \| CC_Z,
5882	14ce26e7	bellard
5883	14ce26e7	bellard	[INDEX_op_loopnzq] = CC_Z,
5884	14ce26e7	bellard	[INDEX_op_loopzq] = CC_Z,
5885	14ce26e7	bellard
5886	14ce26e7	bellard	[INDEX_op_setb_T0_subq] = CC_C,
5887	14ce26e7	bellard	[INDEX_op_setz_T0_subq] = CC_Z,
5888	14ce26e7	bellard	[INDEX_op_setbe_T0_subq] = CC_Z \| CC_C,
5889	14ce26e7	bellard	[INDEX_op_sets_T0_subq] = CC_S,
5890	14ce26e7	bellard	[INDEX_op_setl_T0_subq] = CC_O \| CC_S,
5891	14ce26e7	bellard	[INDEX_op_setle_T0_subq] = CC_O \| CC_S \| CC_Z,
5892	14ce26e7	bellard
5893	14ce26e7	bellard	[INDEX_op_jnz_ecxq] = CC_OSZAPC,
5894	14ce26e7	bellard	[INDEX_op_jz_ecxq] = CC_OSZAPC,
5895	14ce26e7	bellard	#endif
5896	7399c5a9	bellard
5897	4f31916f	bellard	#define DEF_READF(SUFFIX)\
5898	4f31916f	bellard	[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_C,\
5899	4f31916f	bellard	[INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_C,\
5900	4f31916f	bellard	[INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_C,\
5901	14ce26e7	bellard	X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
5902	4f31916f	bellard	[INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_C,\
5903	4f31916f	bellard	[INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_C,\
5904	4f31916f	bellard	[INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_C,\
5905	14ce26e7	bellard	X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
5906	4f31916f	bellard	\
5907	4f31916f	bellard	[INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_C,\
5908	4f31916f	bellard	[INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_C,\
5909	4f31916f	bellard	[INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_C,\
5910	14ce26e7	bellard	X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
5911	4f31916f	bellard	[INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_C,\
5912	4f31916f	bellard	[INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_C,\
5913	14ce26e7	bellard	[INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_C,\
5914	14ce26e7	bellard	X86_64_DEF([INDEX_op_rcrq ## SUFFIX ## _T0_T1_cc] = CC_C,)
5915	4f31916f	bellard
5916	4bb2fcc7	bellard	DEF_READF( )
5917	4f31916f	bellard	DEF_READF(_raw)
5918	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
5919	4f31916f	bellard	DEF_READF(_kernel)
5920	4f31916f	bellard	DEF_READF(_user)
5921	4f31916f	bellard	#endif
5922	2c0262af	bellard	};
5923	2c0262af	bellard
5924	2c0262af	bellard	/* flags written by an operation */
5925	2c0262af	bellard	static uint16_t opc_write_flags[NB_OPS] = {
5926	2c0262af	bellard	[INDEX_op_update2_cc] = CC_OSZAPC,
5927	2c0262af	bellard	[INDEX_op_update1_cc] = CC_OSZAPC,
5928	2c0262af	bellard	[INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
5929	2c0262af	bellard	[INDEX_op_update_neg_cc] = CC_OSZAPC,
5930	2c0262af	bellard	/* subtle: due to the incl/decl implementation, C is used */
5931	2c0262af	bellard	[INDEX_op_update_inc_cc] = CC_OSZAPC,
5932	2c0262af	bellard	[INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
5933	2c0262af	bellard
5934	2c0262af	bellard	[INDEX_op_mulb_AL_T0] = CC_OSZAPC,
5935	2c0262af	bellard	[INDEX_op_mulw_AX_T0] = CC_OSZAPC,
5936	2c0262af	bellard	[INDEX_op_mull_EAX_T0] = CC_OSZAPC,
5937	14ce26e7	bellard	X86_64_DEF([INDEX_op_mulq_EAX_T0] = CC_OSZAPC,)
5938	14ce26e7	bellard	[INDEX_op_imulb_AL_T0] = CC_OSZAPC,
5939	14ce26e7	bellard	[INDEX_op_imulw_AX_T0] = CC_OSZAPC,
5940	2c0262af	bellard	[INDEX_op_imull_EAX_T0] = CC_OSZAPC,
5941	14ce26e7	bellard	X86_64_DEF([INDEX_op_imulq_EAX_T0] = CC_OSZAPC,)
5942	2c0262af	bellard	[INDEX_op_imulw_T0_T1] = CC_OSZAPC,
5943	2c0262af	bellard	[INDEX_op_imull_T0_T1] = CC_OSZAPC,
5944	14ce26e7	bellard	X86_64_DEF([INDEX_op_imulq_T0_T1] = CC_OSZAPC,)
5945	14ce26e7	bellard
5946	664e0f19	bellard	/* sse */
5947	664e0f19	bellard	[INDEX_op_ucomiss] = CC_OSZAPC,
5948	664e0f19	bellard	[INDEX_op_ucomisd] = CC_OSZAPC,
5949	664e0f19	bellard	[INDEX_op_comiss] = CC_OSZAPC,
5950	664e0f19	bellard	[INDEX_op_comisd] = CC_OSZAPC,
5951	664e0f19	bellard
5952	2c0262af	bellard	/* bcd */
5953	2c0262af	bellard	[INDEX_op_aam] = CC_OSZAPC,
5954	2c0262af	bellard	[INDEX_op_aad] = CC_OSZAPC,
5955	2c0262af	bellard	[INDEX_op_aas] = CC_OSZAPC,
5956	2c0262af	bellard	[INDEX_op_aaa] = CC_OSZAPC,
5957	2c0262af	bellard	[INDEX_op_das] = CC_OSZAPC,
5958	2c0262af	bellard	[INDEX_op_daa] = CC_OSZAPC,
5959	2c0262af	bellard
5960	2c0262af	bellard	[INDEX_op_movb_eflags_T0] = CC_S \| CC_Z \| CC_A \| CC_P \| CC_C,
5961	2c0262af	bellard	[INDEX_op_movw_eflags_T0] = CC_OSZAPC,
5962	2c0262af	bellard	[INDEX_op_movl_eflags_T0] = CC_OSZAPC,
5963	4136f33c	bellard	[INDEX_op_movw_eflags_T0_io] = CC_OSZAPC,
5964	4136f33c	bellard	[INDEX_op_movl_eflags_T0_io] = CC_OSZAPC,
5965	4136f33c	bellard	[INDEX_op_movw_eflags_T0_cpl0] = CC_OSZAPC,
5966	4136f33c	bellard	[INDEX_op_movl_eflags_T0_cpl0] = CC_OSZAPC,
5967	2c0262af	bellard	[INDEX_op_clc] = CC_C,
5968	2c0262af	bellard	[INDEX_op_stc] = CC_C,
5969	2c0262af	bellard	[INDEX_op_cmc] = CC_C,
5970	2c0262af	bellard
5971	2c0262af	bellard	[INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
5972	2c0262af	bellard	[INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
5973	14ce26e7	bellard	X86_64_DEF([INDEX_op_btq_T0_T1_cc] = CC_OSZAPC,)
5974	2c0262af	bellard	[INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
5975	2c0262af	bellard	[INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
5976	14ce26e7	bellard	X86_64_DEF([INDEX_op_btsq_T0_T1_cc] = CC_OSZAPC,)
5977	2c0262af	bellard	[INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
5978	2c0262af	bellard	[INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
5979	14ce26e7	bellard	X86_64_DEF([INDEX_op_btrq_T0_T1_cc] = CC_OSZAPC,)
5980	2c0262af	bellard	[INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
5981	2c0262af	bellard	[INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
5982	14ce26e7	bellard	X86_64_DEF([INDEX_op_btcq_T0_T1_cc] = CC_OSZAPC,)
5983	2c0262af	bellard
5984	2c0262af	bellard	[INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
5985	2c0262af	bellard	[INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
5986	14ce26e7	bellard	X86_64_DEF([INDEX_op_bsfq_T0_cc] = CC_OSZAPC,)
5987	2c0262af	bellard	[INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
5988	2c0262af	bellard	[INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
5989	14ce26e7	bellard	X86_64_DEF([INDEX_op_bsrq_T0_cc] = CC_OSZAPC,)
5990	2c0262af	bellard
5991	2c0262af	bellard	[INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
5992	2c0262af	bellard	[INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
5993	2c0262af	bellard	[INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
5994	14ce26e7	bellard	X86_64_DEF([INDEX_op_cmpxchgq_T0_T1_EAX_cc] = CC_OSZAPC,)
5995	2c0262af	bellard
5996	2c0262af	bellard	[INDEX_op_cmpxchg8b] = CC_Z,
5997	2c0262af	bellard	[INDEX_op_lar] = CC_Z,
5998	2c0262af	bellard	[INDEX_op_lsl] = CC_Z,
5999	2c0262af	bellard	[INDEX_op_fcomi_ST0_FT0] = CC_Z \| CC_P \| CC_C,
6000	2c0262af	bellard	[INDEX_op_fucomi_ST0_FT0] = CC_Z \| CC_P \| CC_C,
6001	4f31916f	bellard
6002	4f31916f	bellard	#define DEF_WRITEF(SUFFIX)\
6003	4f31916f	bellard	[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6004	4f31916f	bellard	[INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6005	4f31916f	bellard	[INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6006	14ce26e7	bellard	X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6007	4f31916f	bellard	[INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6008	4f31916f	bellard	[INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6009	4f31916f	bellard	[INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6010	14ce26e7	bellard	X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6011	4f31916f	bellard	\
6012	4f31916f	bellard	[INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6013	4f31916f	bellard	[INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6014	4f31916f	bellard	[INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6015	14ce26e7	bellard	X86_64_DEF([INDEX_op_rolq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6016	4f31916f	bellard	[INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6017	4f31916f	bellard	[INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6018	4f31916f	bellard	[INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6019	14ce26e7	bellard	X86_64_DEF([INDEX_op_rorq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6020	4f31916f	bellard	\
6021	4f31916f	bellard	[INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6022	4f31916f	bellard	[INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6023	4f31916f	bellard	[INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6024	14ce26e7	bellard	X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6025	4f31916f	bellard	[INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6026	4f31916f	bellard	[INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6027	4f31916f	bellard	[INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6028	14ce26e7	bellard	X86_64_DEF([INDEX_op_rcrq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6029	4f31916f	bellard	\
6030	4f31916f	bellard	[INDEX_op_shlb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6031	4f31916f	bellard	[INDEX_op_shlw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6032	4f31916f	bellard	[INDEX_op_shll ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6033	14ce26e7	bellard	X86_64_DEF([INDEX_op_shlq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6034	4f31916f	bellard	\
6035	4f31916f	bellard	[INDEX_op_shrb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6036	4f31916f	bellard	[INDEX_op_shrw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6037	4f31916f	bellard	[INDEX_op_shrl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6038	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6039	4f31916f	bellard	\
6040	4f31916f	bellard	[INDEX_op_sarb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6041	4f31916f	bellard	[INDEX_op_sarw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6042	4f31916f	bellard	[INDEX_op_sarl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6043	14ce26e7	bellard	X86_64_DEF([INDEX_op_sarq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6044	4f31916f	bellard	\
6045	4f31916f	bellard	[INDEX_op_shldw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6046	4f31916f	bellard	[INDEX_op_shldl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6047	14ce26e7	bellard	X86_64_DEF([INDEX_op_shldq ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,)\
6048	4f31916f	bellard	[INDEX_op_shldw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6049	4f31916f	bellard	[INDEX_op_shldl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6050	14ce26e7	bellard	X86_64_DEF([INDEX_op_shldq ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,)\
6051	4f31916f	bellard	\
6052	4f31916f	bellard	[INDEX_op_shrdw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6053	4f31916f	bellard	[INDEX_op_shrdl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6054	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrdq ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,)\
6055	4f31916f	bellard	[INDEX_op_shrdw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6056	4f31916f	bellard	[INDEX_op_shrdl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6057	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrdq ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,)\
6058	4f31916f	bellard	\
6059	4f31916f	bellard	[INDEX_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6060	4f31916f	bellard	[INDEX_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6061	14ce26e7	bellard	[INDEX_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6062	14ce26e7	bellard	X86_64_DEF([INDEX_op_cmpxchgq ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,)
6063	4f31916f	bellard
6064	4f31916f	bellard
6065	4bb2fcc7	bellard	DEF_WRITEF( )
6066	4f31916f	bellard	DEF_WRITEF(_raw)
6067	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
6068	4f31916f	bellard	DEF_WRITEF(_kernel)
6069	4f31916f	bellard	DEF_WRITEF(_user)
6070	4f31916f	bellard	#endif
6071	2c0262af	bellard	};
6072	2c0262af	bellard
6073	2c0262af	bellard	/* simpler form of an operation if no flags need to be generated */
6074	2c0262af	bellard	static uint16_t opc_simpler[NB_OPS] = {
6075	2c0262af	bellard	[INDEX_op_update2_cc] = INDEX_op_nop,
6076	2c0262af	bellard	[INDEX_op_update1_cc] = INDEX_op_nop,
6077	2c0262af	bellard	[INDEX_op_update_neg_cc] = INDEX_op_nop,
6078	2c0262af	bellard	#if 0
6079	2c0262af	bellard	/* broken: CC_OP logic must be rewritten */
6080	2c0262af	bellard	[INDEX_op_update_inc_cc] = INDEX_op_nop,
6081	2c0262af	bellard	#endif
6082	2c0262af	bellard
6083	2c0262af	bellard	[INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
6084	2c0262af	bellard	[INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
6085	2c0262af	bellard	[INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
6086	14ce26e7	bellard	X86_64_DEF([INDEX_op_shlq_T0_T1_cc] = INDEX_op_shlq_T0_T1,)
6087	2c0262af	bellard
6088	2c0262af	bellard	[INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
6089	2c0262af	bellard	[INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
6090	2c0262af	bellard	[INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
6091	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrq_T0_T1_cc] = INDEX_op_shrq_T0_T1,)
6092	2c0262af	bellard
6093	2c0262af	bellard	[INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
6094	2c0262af	bellard	[INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
6095	2c0262af	bellard	[INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
6096	14ce26e7	bellard	X86_64_DEF([INDEX_op_sarq_T0_T1_cc] = INDEX_op_sarq_T0_T1,)
6097	4f31916f	bellard
6098	4f31916f	bellard	#define DEF_SIMPLER(SUFFIX)\
6099	4f31916f	bellard	[INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolb ## SUFFIX ## _T0_T1,\
6100	4f31916f	bellard	[INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolw ## SUFFIX ## _T0_T1,\
6101	4f31916f	bellard	[INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = INDEX_op_roll ## SUFFIX ## _T0_T1,\
6102	14ce26e7	bellard	X86_64_DEF([INDEX_op_rolq ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolq ## SUFFIX ## _T0_T1,)\
6103	4f31916f	bellard	\
6104	4f31916f	bellard	[INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorb ## SUFFIX ## _T0_T1,\
6105	4f31916f	bellard	[INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorw ## SUFFIX ## _T0_T1,\
6106	14ce26e7	bellard	[INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorl ## SUFFIX ## _T0_T1,\
6107	14ce26e7	bellard	X86_64_DEF([INDEX_op_rorq ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorq ## SUFFIX ## _T0_T1,)
6108	4f31916f	bellard
6109	4bb2fcc7	bellard	DEF_SIMPLER( )
6110	4f31916f	bellard	DEF_SIMPLER(_raw)
6111	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
6112	4f31916f	bellard	DEF_SIMPLER(_kernel)
6113	4f31916f	bellard	DEF_SIMPLER(_user)
6114	4f31916f	bellard	#endif
6115	2c0262af	bellard	};
6116	2c0262af	bellard
6117	2c0262af	bellard	void optimize_flags_init(void)
6118	2c0262af	bellard	{
6119	2c0262af	bellard	int i;
6120	2c0262af	bellard	/* put default values in arrays */
6121	2c0262af	bellard	for(i = 0; i < NB_OPS; i++) {
6122	2c0262af	bellard	if (opc_simpler[i] == 0)
6123	2c0262af	bellard	opc_simpler[i] = i;
6124	2c0262af	bellard	}
6125	2c0262af	bellard	}
6126	2c0262af	bellard
6127	2c0262af	bellard	/* CPU flags computation optimization: we move backward thru the
6128	2c0262af	bellard	generated code to see which flags are needed. The operation is
6129	2c0262af	bellard	modified if suitable */
6130	2c0262af	bellard	static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
6131	2c0262af	bellard	{
6132	2c0262af	bellard	uint16_t *opc_ptr;
6133	2c0262af	bellard	int live_flags, write_flags, op;
6134	2c0262af	bellard
6135	2c0262af	bellard	opc_ptr = opc_buf + opc_buf_len;
6136	2c0262af	bellard	/* live_flags contains the flags needed by the next instructions
6137	2c0262af	bellard	in the code. At the end of the bloc, we consider that all the
6138	2c0262af	bellard	flags are live. */
6139	2c0262af	bellard	live_flags = CC_OSZAPC;
6140	2c0262af	bellard	while (opc_ptr > opc_buf) {
6141	2c0262af	bellard	op = *--opc_ptr;
6142	2c0262af	bellard	/* if none of the flags written by the instruction is used,
6143	2c0262af	bellard	then we can try to find a simpler instruction */
6144	2c0262af	bellard	write_flags = opc_write_flags[op];
6145	2c0262af	bellard	if ((live_flags & write_flags) == 0) {
6146	2c0262af	bellard	*opc_ptr = opc_simpler[op];
6147	2c0262af	bellard	}
6148	2c0262af	bellard	/* compute the live flags before the instruction */
6149	2c0262af	bellard	live_flags &= ~write_flags;
6150	2c0262af	bellard	live_flags \|= opc_read_flags[op];
6151	2c0262af	bellard	}
6152	2c0262af	bellard	}
6153	2c0262af	bellard
6154	2c0262af	bellard	/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
6155	2c0262af	bellard	basic block 'tb'. If search_pc is TRUE, also generate PC
6156	2c0262af	bellard	information for each intermediate instruction. */
6157	2c0262af	bellard	static inline int gen_intermediate_code_internal(CPUState *env,
6158	2c0262af	bellard	TranslationBlock *tb,
6159	2c0262af	bellard	int search_pc)
6160	2c0262af	bellard	{
6161	2c0262af	bellard	DisasContext dc1, *dc = &dc1;
6162	14ce26e7	bellard	target_ulong pc_ptr;
6163	2c0262af	bellard	uint16_t *gen_opc_end;
6164	d720b93d	bellard	int flags, j, lj, cflags;
6165	14ce26e7	bellard	target_ulong pc_start;
6166	14ce26e7	bellard	target_ulong cs_base;
6167	2c0262af	bellard
6168	2c0262af	bellard	/* generate intermediate code */
6169	14ce26e7	bellard	pc_start = tb->pc;
6170	14ce26e7	bellard	cs_base = tb->cs_base;
6171	2c0262af	bellard	flags = tb->flags;
6172	d720b93d	bellard	cflags = tb->cflags;
6173	3a1d9b8b	bellard
6174	4f31916f	bellard	dc->pe = (flags >> HF_PE_SHIFT) & 1;
6175	2c0262af	bellard	dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
6176	2c0262af	bellard	dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
6177	2c0262af	bellard	dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
6178	2c0262af	bellard	dc->f_st = 0;
6179	2c0262af	bellard	dc->vm86 = (flags >> VM_SHIFT) & 1;
6180	2c0262af	bellard	dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
6181	2c0262af	bellard	dc->iopl = (flags >> IOPL_SHIFT) & 3;
6182	2c0262af	bellard	dc->tf = (flags >> TF_SHIFT) & 1;
6183	34865134	bellard	dc->singlestep_enabled = env->singlestep_enabled;
6184	2c0262af	bellard	dc->cc_op = CC_OP_DYNAMIC;
6185	2c0262af	bellard	dc->cs_base = cs_base;
6186	2c0262af	bellard	dc->tb = tb;
6187	2c0262af	bellard	dc->popl_esp_hack = 0;
6188	2c0262af	bellard	/* select memory access functions */
6189	2c0262af	bellard	dc->mem_index = 0;
6190	2c0262af	bellard	if (flags & HF_SOFTMMU_MASK) {
6191	2c0262af	bellard	if (dc->cpl == 3)
6192	14ce26e7	bellard	dc->mem_index = 2 * 4;
6193	2c0262af	bellard	else
6194	14ce26e7	bellard	dc->mem_index = 1 * 4;
6195	2c0262af	bellard	}
6196	14ce26e7	bellard	dc->cpuid_features = env->cpuid_features;
6197	14ce26e7	bellard	#ifdef TARGET_X86_64
6198	14ce26e7	bellard	dc->lma = (flags >> HF_LMA_SHIFT) & 1;
6199	14ce26e7	bellard	dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
6200	14ce26e7	bellard	#endif
6201	7eee2a50	bellard	dc->flags = flags;
6202	a2cc3b24	bellard	dc->jmp_opt = !(dc->tf \|\| env->singlestep_enabled \|\|
6203	a2cc3b24	bellard	(flags & HF_INHIBIT_IRQ_MASK)
6204	415fa2ea	bellard	#ifndef CONFIG_SOFTMMU
6205	2c0262af	bellard	\|\| (flags & HF_SOFTMMU_MASK)
6206	2c0262af	bellard	#endif
6207	2c0262af	bellard	);
6208	4f31916f	bellard	#if 0
6209	4f31916f	bellard	/* check addseg logic */
6210	dc196a57	bellard	if (!dc->addseg && (dc->vm86 \|\| !dc->pe \|\| !dc->code32))
6211	4f31916f	bellard	printf("ERROR addseg\n");
6212	4f31916f	bellard	#endif
6213	4f31916f	bellard
6214	2c0262af	bellard	gen_opc_ptr = gen_opc_buf;
6215	2c0262af	bellard	gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6216	2c0262af	bellard	gen_opparam_ptr = gen_opparam_buf;
6217	14ce26e7	bellard	nb_gen_labels = 0;
6218	2c0262af	bellard
6219	2c0262af	bellard	dc->is_jmp = DISAS_NEXT;
6220	2c0262af	bellard	pc_ptr = pc_start;
6221	2c0262af	bellard	lj = -1;
6222	2c0262af	bellard
6223	2c0262af	bellard	for(;;) {
6224	2c0262af	bellard	if (env->nb_breakpoints > 0) {
6225	2c0262af	bellard	for(j = 0; j < env->nb_breakpoints; j++) {
6226	14ce26e7	bellard	if (env->breakpoints[j] == pc_ptr) {
6227	2c0262af	bellard	gen_debug(dc, pc_ptr - dc->cs_base);
6228	2c0262af	bellard	break;
6229	2c0262af	bellard	}
6230	2c0262af	bellard	}
6231	2c0262af	bellard	}
6232	2c0262af	bellard	if (search_pc) {
6233	2c0262af	bellard	j = gen_opc_ptr - gen_opc_buf;
6234	2c0262af	bellard	if (lj < j) {
6235	2c0262af	bellard	lj++;
6236	2c0262af	bellard	while (lj < j)
6237	2c0262af	bellard	gen_opc_instr_start[lj++] = 0;
6238	2c0262af	bellard	}
6239	14ce26e7	bellard	gen_opc_pc[lj] = pc_ptr;
6240	2c0262af	bellard	gen_opc_cc_op[lj] = dc->cc_op;
6241	2c0262af	bellard	gen_opc_instr_start[lj] = 1;
6242	2c0262af	bellard	}
6243	2c0262af	bellard	pc_ptr = disas_insn(dc, pc_ptr);
6244	2c0262af	bellard	/* stop translation if indicated */
6245	2c0262af	bellard	if (dc->is_jmp)
6246	2c0262af	bellard	break;
6247	2c0262af	bellard	/* if single step mode, we generate only one instruction and
6248	2c0262af	bellard	generate an exception */
6249	a2cc3b24	bellard	/* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
6250	a2cc3b24	bellard	the flag and abort the translation to give the irqs a
6251	a2cc3b24	bellard	change to be happen */
6252	a2cc3b24	bellard	if (dc->tf \|\| dc->singlestep_enabled \|\|
6253	d720b93d	bellard	(flags & HF_INHIBIT_IRQ_MASK) \|\|
6254	d720b93d	bellard	(cflags & CF_SINGLE_INSN)) {
6255	14ce26e7	bellard	gen_jmp_im(pc_ptr - dc->cs_base);
6256	2c0262af	bellard	gen_eob(dc);
6257	2c0262af	bellard	break;
6258	2c0262af	bellard	}
6259	2c0262af	bellard	/* if too long translation, stop generation too */
6260	2c0262af	bellard	if (gen_opc_ptr >= gen_opc_end \|\|
6261	2c0262af	bellard	(pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
6262	14ce26e7	bellard	gen_jmp_im(pc_ptr - dc->cs_base);
6263	2c0262af	bellard	gen_eob(dc);
6264	2c0262af	bellard	break;
6265	2c0262af	bellard	}
6266	2c0262af	bellard	}
6267	2c0262af	bellard	*gen_opc_ptr = INDEX_op_end;
6268	2c0262af	bellard	/* we don't forget to fill the last values */
6269	2c0262af	bellard	if (search_pc) {
6270	2c0262af	bellard	j = gen_opc_ptr - gen_opc_buf;
6271	2c0262af	bellard	lj++;
6272	2c0262af	bellard	while (lj <= j)
6273	2c0262af	bellard	gen_opc_instr_start[lj++] = 0;
6274	2c0262af	bellard	}
6275	2c0262af	bellard
6276	2c0262af	bellard	#ifdef DEBUG_DISAS
6277	658c8bda	bellard	if (loglevel & CPU_LOG_TB_CPU) {
6278	7fe48483	bellard	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
6279	658c8bda	bellard	}
6280	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_IN_ASM) {
6281	14ce26e7	bellard	int disas_flags;
6282	2c0262af	bellard	fprintf(logfile, "----------------\n");
6283	2c0262af	bellard	fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6284	14ce26e7	bellard	#ifdef TARGET_X86_64
6285	14ce26e7	bellard	if (dc->code64)
6286	14ce26e7	bellard	disas_flags = 2;
6287	14ce26e7	bellard	else
6288	14ce26e7	bellard	#endif
6289	14ce26e7	bellard	disas_flags = !dc->code32;
6290	14ce26e7	bellard	target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags);
6291	2c0262af	bellard	fprintf(logfile, "\n");
6292	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_OP) {
6293	e19e89a5	bellard	fprintf(logfile, "OP:\n");
6294	e19e89a5	bellard	dump_ops(gen_opc_buf, gen_opparam_buf);
6295	e19e89a5	bellard	fprintf(logfile, "\n");
6296	e19e89a5	bellard	}
6297	2c0262af	bellard	}
6298	2c0262af	bellard	#endif
6299	2c0262af	bellard
6300	2c0262af	bellard	/* optimize flag computations */
6301	2c0262af	bellard	optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
6302	2c0262af	bellard
6303	2c0262af	bellard	#ifdef DEBUG_DISAS
6304	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_OP_OPT) {
6305	2c0262af	bellard	fprintf(logfile, "AFTER FLAGS OPT:\n");
6306	2c0262af	bellard	dump_ops(gen_opc_buf, gen_opparam_buf);
6307	2c0262af	bellard	fprintf(logfile, "\n");
6308	2c0262af	bellard	}
6309	2c0262af	bellard	#endif
6310	2c0262af	bellard	if (!search_pc)
6311	2c0262af	bellard	tb->size = pc_ptr - pc_start;
6312	2c0262af	bellard	return 0;
6313	2c0262af	bellard	}
6314	2c0262af	bellard
6315	2c0262af	bellard	int gen_intermediate_code(CPUState env, TranslationBlock tb)
6316	2c0262af	bellard	{
6317	2c0262af	bellard	return gen_intermediate_code_internal(env, tb, 0);
6318	2c0262af	bellard	}
6319	2c0262af	bellard
6320	2c0262af	bellard	int gen_intermediate_code_pc(CPUState env, TranslationBlock tb)
6321	2c0262af	bellard	{
6322	2c0262af	bellard	return gen_intermediate_code_internal(env, tb, 1);
6323	2c0262af	bellard	}

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