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| 1 | 79aceca5 | bellard | /*
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| 2 | 79aceca5 | bellard | * PPC emulation micro-operations for qemu.
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| 3 | 79aceca5 | bellard | *
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| 4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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| 5 | 79aceca5 | bellard | *
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| 6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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| 7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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| 8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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| 9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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| 10 | 79aceca5 | bellard | *
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| 11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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| 12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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| 15 | 79aceca5 | bellard | *
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| 16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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| 17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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| 18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 19 | 79aceca5 | bellard | */
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| 20 | 79aceca5 | bellard | |
| 21 | a541f297 | bellard | //#define DEBUG_OP
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| 22 | a541f297 | bellard | |
| 23 | 79aceca5 | bellard | #include "config.h" |
| 24 | 79aceca5 | bellard | #include "exec.h" |
| 25 | 79aceca5 | bellard | |
| 26 | 79aceca5 | bellard | #define regs (env)
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| 27 | 79aceca5 | bellard | #define Ts0 (int32_t)T0
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| 28 | 79aceca5 | bellard | #define Ts1 (int32_t)T1
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| 29 | 79aceca5 | bellard | #define Ts2 (int32_t)T2
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| 30 | 79aceca5 | bellard | |
| 31 | 28b6751f | bellard | #define FT0 (env->ft0)
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| 32 | fb0eaffc | bellard | #define FT1 (env->ft1)
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| 33 | fb0eaffc | bellard | #define FT2 (env->ft2)
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| 34 | fb0eaffc | bellard | |
| 35 | fb0eaffc | bellard | #define FTS0 ((float)env->ft0) |
| 36 | fb0eaffc | bellard | #define FTS1 ((float)env->ft1) |
| 37 | fb0eaffc | bellard | #define FTS2 ((float)env->ft2) |
| 38 | 79aceca5 | bellard | |
| 39 | 9a64fbe4 | bellard | #define PPC_OP(name) void glue(op_, name)(void) |
| 40 | 79aceca5 | bellard | |
| 41 | 28b6751f | bellard | #define REG 0 |
| 42 | 28b6751f | bellard | #include "op_template.h" |
| 43 | 28b6751f | bellard | |
| 44 | 28b6751f | bellard | #define REG 1 |
| 45 | 28b6751f | bellard | #include "op_template.h" |
| 46 | 28b6751f | bellard | |
| 47 | 28b6751f | bellard | #define REG 2 |
| 48 | 28b6751f | bellard | #include "op_template.h" |
| 49 | 28b6751f | bellard | |
| 50 | 28b6751f | bellard | #define REG 3 |
| 51 | 28b6751f | bellard | #include "op_template.h" |
| 52 | 28b6751f | bellard | |
| 53 | 28b6751f | bellard | #define REG 4 |
| 54 | 28b6751f | bellard | #include "op_template.h" |
| 55 | 28b6751f | bellard | |
| 56 | 28b6751f | bellard | #define REG 5 |
| 57 | 28b6751f | bellard | #include "op_template.h" |
| 58 | 28b6751f | bellard | |
| 59 | 28b6751f | bellard | #define REG 6 |
| 60 | 28b6751f | bellard | #include "op_template.h" |
| 61 | 28b6751f | bellard | |
| 62 | 28b6751f | bellard | #define REG 7 |
| 63 | 28b6751f | bellard | #include "op_template.h" |
| 64 | 28b6751f | bellard | |
| 65 | 28b6751f | bellard | #define REG 8 |
| 66 | 28b6751f | bellard | #include "op_template.h" |
| 67 | 28b6751f | bellard | |
| 68 | 28b6751f | bellard | #define REG 9 |
| 69 | 28b6751f | bellard | #include "op_template.h" |
| 70 | 28b6751f | bellard | |
| 71 | 28b6751f | bellard | #define REG 10 |
| 72 | 28b6751f | bellard | #include "op_template.h" |
| 73 | 28b6751f | bellard | |
| 74 | 28b6751f | bellard | #define REG 11 |
| 75 | 28b6751f | bellard | #include "op_template.h" |
| 76 | 28b6751f | bellard | |
| 77 | 28b6751f | bellard | #define REG 12 |
| 78 | 28b6751f | bellard | #include "op_template.h" |
| 79 | 28b6751f | bellard | |
| 80 | 28b6751f | bellard | #define REG 13 |
| 81 | 28b6751f | bellard | #include "op_template.h" |
| 82 | 28b6751f | bellard | |
| 83 | 28b6751f | bellard | #define REG 14 |
| 84 | 28b6751f | bellard | #include "op_template.h" |
| 85 | 28b6751f | bellard | |
| 86 | 28b6751f | bellard | #define REG 15 |
| 87 | 28b6751f | bellard | #include "op_template.h" |
| 88 | 28b6751f | bellard | |
| 89 | 28b6751f | bellard | #define REG 16 |
| 90 | 28b6751f | bellard | #include "op_template.h" |
| 91 | 28b6751f | bellard | |
| 92 | 28b6751f | bellard | #define REG 17 |
| 93 | 28b6751f | bellard | #include "op_template.h" |
| 94 | 28b6751f | bellard | |
| 95 | 28b6751f | bellard | #define REG 18 |
| 96 | 28b6751f | bellard | #include "op_template.h" |
| 97 | 28b6751f | bellard | |
| 98 | 28b6751f | bellard | #define REG 19 |
| 99 | 28b6751f | bellard | #include "op_template.h" |
| 100 | 28b6751f | bellard | |
| 101 | 28b6751f | bellard | #define REG 20 |
| 102 | 28b6751f | bellard | #include "op_template.h" |
| 103 | 28b6751f | bellard | |
| 104 | 28b6751f | bellard | #define REG 21 |
| 105 | 28b6751f | bellard | #include "op_template.h" |
| 106 | 28b6751f | bellard | |
| 107 | 28b6751f | bellard | #define REG 22 |
| 108 | 28b6751f | bellard | #include "op_template.h" |
| 109 | 28b6751f | bellard | |
| 110 | 28b6751f | bellard | #define REG 23 |
| 111 | 28b6751f | bellard | #include "op_template.h" |
| 112 | 28b6751f | bellard | |
| 113 | 28b6751f | bellard | #define REG 24 |
| 114 | 28b6751f | bellard | #include "op_template.h" |
| 115 | 28b6751f | bellard | |
| 116 | 28b6751f | bellard | #define REG 25 |
| 117 | 28b6751f | bellard | #include "op_template.h" |
| 118 | 28b6751f | bellard | |
| 119 | 28b6751f | bellard | #define REG 26 |
| 120 | 28b6751f | bellard | #include "op_template.h" |
| 121 | 28b6751f | bellard | |
| 122 | 28b6751f | bellard | #define REG 27 |
| 123 | 28b6751f | bellard | #include "op_template.h" |
| 124 | 28b6751f | bellard | |
| 125 | 28b6751f | bellard | #define REG 28 |
| 126 | 28b6751f | bellard | #include "op_template.h" |
| 127 | 28b6751f | bellard | |
| 128 | 28b6751f | bellard | #define REG 29 |
| 129 | 28b6751f | bellard | #include "op_template.h" |
| 130 | 28b6751f | bellard | |
| 131 | 28b6751f | bellard | #define REG 30 |
| 132 | 28b6751f | bellard | #include "op_template.h" |
| 133 | 28b6751f | bellard | |
| 134 | 28b6751f | bellard | #define REG 31 |
| 135 | 28b6751f | bellard | #include "op_template.h" |
| 136 | 28b6751f | bellard | |
| 137 | 79aceca5 | bellard | /* PPC state maintenance operations */
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| 138 | 79aceca5 | bellard | /* set_Rc0 */
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| 139 | 79aceca5 | bellard | PPC_OP(set_Rc0) |
| 140 | 79aceca5 | bellard | {
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| 141 | 79aceca5 | bellard | uint32_t tmp; |
| 142 | 79aceca5 | bellard | |
| 143 | 79aceca5 | bellard | if (Ts0 < 0) { |
| 144 | 79aceca5 | bellard | tmp = 0x08;
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| 145 | 79aceca5 | bellard | } else if (Ts0 > 0) { |
| 146 | 79aceca5 | bellard | tmp = 0x04;
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| 147 | 79aceca5 | bellard | } else {
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| 148 | 79aceca5 | bellard | tmp = 0x02;
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| 149 | 79aceca5 | bellard | } |
| 150 | 79aceca5 | bellard | tmp |= xer_ov; |
| 151 | 9a64fbe4 | bellard | env->crf[0] = tmp;
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| 152 | 79aceca5 | bellard | RETURN(); |
| 153 | 79aceca5 | bellard | } |
| 154 | 79aceca5 | bellard | |
| 155 | 79aceca5 | bellard | /* reset_Rc0 */
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| 156 | 79aceca5 | bellard | PPC_OP(reset_Rc0) |
| 157 | 79aceca5 | bellard | {
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| 158 | 9a64fbe4 | bellard | env->crf[0] = 0x02 | xer_ov; |
| 159 | 79aceca5 | bellard | RETURN(); |
| 160 | 79aceca5 | bellard | } |
| 161 | 79aceca5 | bellard | |
| 162 | 79aceca5 | bellard | /* set_Rc0_1 */
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| 163 | 79aceca5 | bellard | PPC_OP(set_Rc0_1) |
| 164 | 79aceca5 | bellard | {
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| 165 | 9a64fbe4 | bellard | env->crf[0] = 0x04 | xer_ov; |
| 166 | 79aceca5 | bellard | RETURN(); |
| 167 | 79aceca5 | bellard | } |
| 168 | 79aceca5 | bellard | |
| 169 | fb0eaffc | bellard | /* Set Rc1 (for floating point arithmetic) */
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| 170 | fb0eaffc | bellard | PPC_OP(set_Rc1) |
| 171 | fb0eaffc | bellard | {
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| 172 | fb0eaffc | bellard | env->crf[1] = regs->fpscr[7]; |
| 173 | fb0eaffc | bellard | RETURN(); |
| 174 | fb0eaffc | bellard | } |
| 175 | fb0eaffc | bellard | |
| 176 | 9a64fbe4 | bellard | /* Constants load */
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| 177 | 79aceca5 | bellard | PPC_OP(set_T0) |
| 178 | 79aceca5 | bellard | {
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| 179 | 79aceca5 | bellard | T0 = PARAM(1);
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| 180 | 79aceca5 | bellard | RETURN(); |
| 181 | 79aceca5 | bellard | } |
| 182 | 79aceca5 | bellard | |
| 183 | 79aceca5 | bellard | PPC_OP(set_T1) |
| 184 | 79aceca5 | bellard | {
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| 185 | 79aceca5 | bellard | T1 = PARAM(1);
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| 186 | 79aceca5 | bellard | RETURN(); |
| 187 | 79aceca5 | bellard | } |
| 188 | 79aceca5 | bellard | |
| 189 | 79aceca5 | bellard | PPC_OP(set_T2) |
| 190 | 79aceca5 | bellard | {
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| 191 | 79aceca5 | bellard | T2 = PARAM(1);
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| 192 | 79aceca5 | bellard | RETURN(); |
| 193 | 79aceca5 | bellard | } |
| 194 | 79aceca5 | bellard | |
| 195 | 9a64fbe4 | bellard | /* Generate exceptions */
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| 196 | 9fddaa0c | bellard | PPC_OP(raise_exception_err) |
| 197 | 79aceca5 | bellard | {
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| 198 | 9fddaa0c | bellard | do_raise_exception_err(PARAM(1), PARAM(2)); |
| 199 | 9a64fbe4 | bellard | } |
| 200 | 9a64fbe4 | bellard | |
| 201 | 9fddaa0c | bellard | PPC_OP(raise_exception) |
| 202 | 9a64fbe4 | bellard | {
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| 203 | 9fddaa0c | bellard | do_raise_exception(PARAM(1));
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| 204 | 9a64fbe4 | bellard | } |
| 205 | 9a64fbe4 | bellard | |
| 206 | 9fddaa0c | bellard | PPC_OP(update_nip) |
| 207 | 9a64fbe4 | bellard | {
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| 208 | 004bc62c | bellard | env->nip = PARAM(1);
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| 209 | 9a64fbe4 | bellard | } |
| 210 | 9a64fbe4 | bellard | |
| 211 | a541f297 | bellard | PPC_OP(debug) |
| 212 | a541f297 | bellard | {
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| 213 | a541f297 | bellard | env->nip = PARAM(1);
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| 214 | a541f297 | bellard | #if defined (DEBUG_OP)
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| 215 | a541f297 | bellard | dump_state(); |
| 216 | a541f297 | bellard | #endif
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| 217 | 9fddaa0c | bellard | do_raise_exception(EXCP_DEBUG); |
| 218 | a541f297 | bellard | RETURN(); |
| 219 | a541f297 | bellard | } |
| 220 | a541f297 | bellard | |
| 221 | 9a64fbe4 | bellard | /* Segment registers load and store with immediate index */
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| 222 | 9a64fbe4 | bellard | PPC_OP(load_srin) |
| 223 | 9a64fbe4 | bellard | {
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| 224 | 9a64fbe4 | bellard | T0 = regs->sr[T1 >> 28];
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| 225 | 9a64fbe4 | bellard | RETURN(); |
| 226 | 9a64fbe4 | bellard | } |
| 227 | 9a64fbe4 | bellard | |
| 228 | 9a64fbe4 | bellard | PPC_OP(store_srin) |
| 229 | 9a64fbe4 | bellard | {
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| 230 | 4b3686fa | bellard | do_store_sr(T1 >> 28);
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| 231 | 9a64fbe4 | bellard | RETURN(); |
| 232 | 9a64fbe4 | bellard | } |
| 233 | 9a64fbe4 | bellard | |
| 234 | 9a64fbe4 | bellard | PPC_OP(load_sdr1) |
| 235 | 9a64fbe4 | bellard | {
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| 236 | 9a64fbe4 | bellard | T0 = regs->sdr1; |
| 237 | 79aceca5 | bellard | RETURN(); |
| 238 | 79aceca5 | bellard | } |
| 239 | 79aceca5 | bellard | |
| 240 | 9a64fbe4 | bellard | PPC_OP(store_sdr1) |
| 241 | 79aceca5 | bellard | {
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| 242 | 9a64fbe4 | bellard | regs->sdr1 = T0; |
| 243 | 79aceca5 | bellard | RETURN(); |
| 244 | 79aceca5 | bellard | } |
| 245 | 79aceca5 | bellard | |
| 246 | 79aceca5 | bellard | PPC_OP(exit_tb) |
| 247 | 79aceca5 | bellard | {
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| 248 | 79aceca5 | bellard | EXIT_TB(); |
| 249 | 79aceca5 | bellard | } |
| 250 | 79aceca5 | bellard | |
| 251 | 9a64fbe4 | bellard | /* Load/store special registers */
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| 252 | 79aceca5 | bellard | PPC_OP(load_cr) |
| 253 | 79aceca5 | bellard | {
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| 254 | 9a64fbe4 | bellard | do_load_cr(); |
| 255 | 79aceca5 | bellard | RETURN(); |
| 256 | 79aceca5 | bellard | } |
| 257 | 79aceca5 | bellard | |
| 258 | 79aceca5 | bellard | PPC_OP(store_cr) |
| 259 | 79aceca5 | bellard | {
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| 260 | 9a64fbe4 | bellard | do_store_cr(PARAM(1));
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| 261 | 79aceca5 | bellard | RETURN(); |
| 262 | 79aceca5 | bellard | } |
| 263 | 79aceca5 | bellard | |
| 264 | 79aceca5 | bellard | PPC_OP(load_xer_cr) |
| 265 | 79aceca5 | bellard | {
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| 266 | 79aceca5 | bellard | T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1); |
| 267 | 79aceca5 | bellard | RETURN(); |
| 268 | 79aceca5 | bellard | } |
| 269 | 79aceca5 | bellard | |
| 270 | 79aceca5 | bellard | PPC_OP(clear_xer_cr) |
| 271 | 79aceca5 | bellard | {
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| 272 | 79aceca5 | bellard | xer_so = 0;
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| 273 | 79aceca5 | bellard | xer_ov = 0;
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| 274 | 79aceca5 | bellard | xer_ca = 0;
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| 275 | 79aceca5 | bellard | RETURN(); |
| 276 | 79aceca5 | bellard | } |
| 277 | 79aceca5 | bellard | |
| 278 | 79aceca5 | bellard | PPC_OP(load_xer_bc) |
| 279 | 79aceca5 | bellard | {
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| 280 | 9a64fbe4 | bellard | T1 = xer_bc; |
| 281 | 79aceca5 | bellard | RETURN(); |
| 282 | 79aceca5 | bellard | } |
| 283 | 79aceca5 | bellard | |
| 284 | 79aceca5 | bellard | PPC_OP(load_xer) |
| 285 | 79aceca5 | bellard | {
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| 286 | 9a64fbe4 | bellard | do_load_xer(); |
| 287 | 79aceca5 | bellard | RETURN(); |
| 288 | 79aceca5 | bellard | } |
| 289 | 79aceca5 | bellard | |
| 290 | 79aceca5 | bellard | PPC_OP(store_xer) |
| 291 | 79aceca5 | bellard | {
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| 292 | 9a64fbe4 | bellard | do_store_xer(); |
| 293 | 79aceca5 | bellard | RETURN(); |
| 294 | 79aceca5 | bellard | } |
| 295 | 79aceca5 | bellard | |
| 296 | 79aceca5 | bellard | PPC_OP(load_msr) |
| 297 | 79aceca5 | bellard | {
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| 298 | 9a64fbe4 | bellard | do_load_msr(); |
| 299 | 79aceca5 | bellard | RETURN(); |
| 300 | 79aceca5 | bellard | } |
| 301 | 79aceca5 | bellard | |
| 302 | 79aceca5 | bellard | PPC_OP(store_msr) |
| 303 | 79aceca5 | bellard | {
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| 304 | 9a64fbe4 | bellard | do_store_msr(); |
| 305 | 9a64fbe4 | bellard | RETURN(); |
| 306 | 9a64fbe4 | bellard | } |
| 307 | 9a64fbe4 | bellard | |
| 308 | 9a64fbe4 | bellard | /* SPR */
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| 309 | 9a64fbe4 | bellard | PPC_OP(load_spr) |
| 310 | 9a64fbe4 | bellard | {
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| 311 | 9a64fbe4 | bellard | T0 = regs->spr[PARAM(1)];
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| 312 | 9a64fbe4 | bellard | RETURN(); |
| 313 | 9a64fbe4 | bellard | } |
| 314 | 9a64fbe4 | bellard | |
| 315 | 9a64fbe4 | bellard | PPC_OP(store_spr) |
| 316 | 9a64fbe4 | bellard | {
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| 317 | 9a64fbe4 | bellard | regs->spr[PARAM(1)] = T0;
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| 318 | 79aceca5 | bellard | RETURN(); |
| 319 | 79aceca5 | bellard | } |
| 320 | 79aceca5 | bellard | |
| 321 | 79aceca5 | bellard | PPC_OP(load_lr) |
| 322 | 79aceca5 | bellard | {
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| 323 | 9a64fbe4 | bellard | T0 = regs->lr; |
| 324 | 9a64fbe4 | bellard | RETURN(); |
| 325 | 9a64fbe4 | bellard | } |
| 326 | 9a64fbe4 | bellard | |
| 327 | 9a64fbe4 | bellard | PPC_OP(store_lr) |
| 328 | 9a64fbe4 | bellard | {
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| 329 | 9a64fbe4 | bellard | regs->lr = T0; |
| 330 | 9a64fbe4 | bellard | RETURN(); |
| 331 | 9a64fbe4 | bellard | } |
| 332 | 9a64fbe4 | bellard | |
| 333 | 9a64fbe4 | bellard | PPC_OP(load_ctr) |
| 334 | 9a64fbe4 | bellard | {
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| 335 | 9a64fbe4 | bellard | T0 = regs->ctr; |
| 336 | 9a64fbe4 | bellard | RETURN(); |
| 337 | 9a64fbe4 | bellard | } |
| 338 | 9a64fbe4 | bellard | |
| 339 | 9a64fbe4 | bellard | PPC_OP(store_ctr) |
| 340 | 9a64fbe4 | bellard | {
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| 341 | 9a64fbe4 | bellard | regs->ctr = T0; |
| 342 | 9a64fbe4 | bellard | RETURN(); |
| 343 | 9a64fbe4 | bellard | } |
| 344 | 9a64fbe4 | bellard | |
| 345 | 9fddaa0c | bellard | PPC_OP(load_tbl) |
| 346 | 9a64fbe4 | bellard | {
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| 347 | 9fddaa0c | bellard | T0 = cpu_ppc_load_tbl(regs); |
| 348 | 9a64fbe4 | bellard | RETURN(); |
| 349 | 9a64fbe4 | bellard | } |
| 350 | 9a64fbe4 | bellard | |
| 351 | 9fddaa0c | bellard | PPC_OP(load_tbu) |
| 352 | 9a64fbe4 | bellard | {
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| 353 | 9fddaa0c | bellard | T0 = cpu_ppc_load_tbu(regs); |
| 354 | 9a64fbe4 | bellard | RETURN(); |
| 355 | 9a64fbe4 | bellard | } |
| 356 | 9a64fbe4 | bellard | |
| 357 | 9fddaa0c | bellard | PPC_OP(store_tbl) |
| 358 | 9a64fbe4 | bellard | {
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| 359 | 9fddaa0c | bellard | cpu_ppc_store_tbl(regs, T0); |
| 360 | 79aceca5 | bellard | RETURN(); |
| 361 | 79aceca5 | bellard | } |
| 362 | 79aceca5 | bellard | |
| 363 | 9fddaa0c | bellard | PPC_OP(store_tbu) |
| 364 | 9a64fbe4 | bellard | {
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| 365 | 9fddaa0c | bellard | cpu_ppc_store_tbu(regs, T0); |
| 366 | 9a64fbe4 | bellard | RETURN(); |
| 367 | 9a64fbe4 | bellard | } |
| 368 | 9a64fbe4 | bellard | |
| 369 | 9fddaa0c | bellard | PPC_OP(load_decr) |
| 370 | 9a64fbe4 | bellard | {
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| 371 | 9fddaa0c | bellard | T0 = cpu_ppc_load_decr(regs); |
| 372 | 9a64fbe4 | bellard | } |
| 373 | 9fddaa0c | bellard | |
| 374 | 9fddaa0c | bellard | PPC_OP(store_decr) |
| 375 | 9fddaa0c | bellard | {
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| 376 | 9fddaa0c | bellard | cpu_ppc_store_decr(regs, T0); |
| 377 | 9a64fbe4 | bellard | RETURN(); |
| 378 | 9a64fbe4 | bellard | } |
| 379 | 9a64fbe4 | bellard | |
| 380 | 9a64fbe4 | bellard | PPC_OP(load_ibat) |
| 381 | 9a64fbe4 | bellard | {
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| 382 | 9a64fbe4 | bellard | T0 = regs->IBAT[PARAM(1)][PARAM(2)]; |
| 383 | 9a64fbe4 | bellard | } |
| 384 | 9a64fbe4 | bellard | |
| 385 | 9a64fbe4 | bellard | PPC_OP(store_ibat) |
| 386 | 9a64fbe4 | bellard | {
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| 387 | 4b3686fa | bellard | do_store_ibat(PARAM(1), PARAM(2)); |
| 388 | 9a64fbe4 | bellard | } |
| 389 | 9a64fbe4 | bellard | |
| 390 | 9a64fbe4 | bellard | PPC_OP(load_dbat) |
| 391 | 9a64fbe4 | bellard | {
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| 392 | 9a64fbe4 | bellard | T0 = regs->DBAT[PARAM(1)][PARAM(2)]; |
| 393 | 9a64fbe4 | bellard | } |
| 394 | 9a64fbe4 | bellard | |
| 395 | 9a64fbe4 | bellard | PPC_OP(store_dbat) |
| 396 | 9a64fbe4 | bellard | {
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| 397 | 4b3686fa | bellard | do_store_dbat(PARAM(1), PARAM(2)); |
| 398 | 9a64fbe4 | bellard | } |
| 399 | 9a64fbe4 | bellard | |
| 400 | fb0eaffc | bellard | /* FPSCR */
|
| 401 | fb0eaffc | bellard | PPC_OP(load_fpscr) |
| 402 | fb0eaffc | bellard | {
|
| 403 | fb0eaffc | bellard | do_load_fpscr(); |
| 404 | fb0eaffc | bellard | RETURN(); |
| 405 | fb0eaffc | bellard | } |
| 406 | fb0eaffc | bellard | |
| 407 | fb0eaffc | bellard | PPC_OP(store_fpscr) |
| 408 | fb0eaffc | bellard | {
|
| 409 | fb0eaffc | bellard | do_store_fpscr(PARAM(1));
|
| 410 | fb0eaffc | bellard | RETURN(); |
| 411 | fb0eaffc | bellard | } |
| 412 | fb0eaffc | bellard | |
| 413 | fb0eaffc | bellard | PPC_OP(reset_scrfx) |
| 414 | fb0eaffc | bellard | {
|
| 415 | fb0eaffc | bellard | regs->fpscr[7] &= ~0x8; |
| 416 | fb0eaffc | bellard | RETURN(); |
| 417 | fb0eaffc | bellard | } |
| 418 | fb0eaffc | bellard | |
| 419 | 79aceca5 | bellard | /* crf operations */
|
| 420 | 79aceca5 | bellard | PPC_OP(getbit_T0) |
| 421 | 79aceca5 | bellard | {
|
| 422 | 79aceca5 | bellard | T0 = (T0 >> PARAM(1)) & 1; |
| 423 | 79aceca5 | bellard | RETURN(); |
| 424 | 79aceca5 | bellard | } |
| 425 | 79aceca5 | bellard | |
| 426 | 79aceca5 | bellard | PPC_OP(getbit_T1) |
| 427 | 79aceca5 | bellard | {
|
| 428 | 79aceca5 | bellard | T1 = (T1 >> PARAM(1)) & 1; |
| 429 | 79aceca5 | bellard | RETURN(); |
| 430 | 79aceca5 | bellard | } |
| 431 | 79aceca5 | bellard | |
| 432 | 79aceca5 | bellard | PPC_OP(setcrfbit) |
| 433 | 79aceca5 | bellard | {
|
| 434 | 79aceca5 | bellard | T1 = (T1 & PARAM(1)) | (T0 << PARAM(2)); |
| 435 | 79aceca5 | bellard | RETURN(); |
| 436 | 79aceca5 | bellard | } |
| 437 | 79aceca5 | bellard | |
| 438 | 79aceca5 | bellard | /* Branch */
|
| 439 | 9a64fbe4 | bellard | #define EIP regs->nip
|
| 440 | 9a64fbe4 | bellard | |
| 441 | e98a6e40 | bellard | PPC_OP(setlr) |
| 442 | e98a6e40 | bellard | {
|
| 443 | e98a6e40 | bellard | regs->lr = PARAM1; |
| 444 | e98a6e40 | bellard | } |
| 445 | e98a6e40 | bellard | |
| 446 | e98a6e40 | bellard | PPC_OP(b) |
| 447 | e98a6e40 | bellard | {
|
| 448 | e98a6e40 | bellard | JUMP_TB(b1, PARAM1, 0, PARAM2);
|
| 449 | e98a6e40 | bellard | } |
| 450 | e98a6e40 | bellard | |
| 451 | e98a6e40 | bellard | PPC_OP(b_T1) |
| 452 | e98a6e40 | bellard | {
|
| 453 | e98a6e40 | bellard | regs->nip = T1; |
| 454 | e98a6e40 | bellard | } |
| 455 | e98a6e40 | bellard | |
| 456 | e98a6e40 | bellard | PPC_OP(btest) |
| 457 | e98a6e40 | bellard | {
|
| 458 | e98a6e40 | bellard | if (T0) {
|
| 459 | e98a6e40 | bellard | JUMP_TB(btest, PARAM1, 0, PARAM2);
|
| 460 | e98a6e40 | bellard | } else {
|
| 461 | e98a6e40 | bellard | JUMP_TB(btest, PARAM1, 1, PARAM3);
|
| 462 | e98a6e40 | bellard | } |
| 463 | e98a6e40 | bellard | RETURN(); |
| 464 | e98a6e40 | bellard | } |
| 465 | e98a6e40 | bellard | |
| 466 | e98a6e40 | bellard | PPC_OP(btest_T1) |
| 467 | e98a6e40 | bellard | {
|
| 468 | e98a6e40 | bellard | if (T0) {
|
| 469 | e98a6e40 | bellard | regs->nip = T1 & ~3;
|
| 470 | e98a6e40 | bellard | } else {
|
| 471 | e98a6e40 | bellard | regs->nip = PARAM1; |
| 472 | e98a6e40 | bellard | } |
| 473 | e98a6e40 | bellard | RETURN(); |
| 474 | e98a6e40 | bellard | } |
| 475 | e98a6e40 | bellard | |
| 476 | e98a6e40 | bellard | PPC_OP(movl_T1_ctr) |
| 477 | e98a6e40 | bellard | {
|
| 478 | e98a6e40 | bellard | T1 = regs->ctr; |
| 479 | e98a6e40 | bellard | } |
| 480 | e98a6e40 | bellard | |
| 481 | e98a6e40 | bellard | PPC_OP(movl_T1_lr) |
| 482 | e98a6e40 | bellard | {
|
| 483 | e98a6e40 | bellard | T1 = regs->lr; |
| 484 | e98a6e40 | bellard | } |
| 485 | e98a6e40 | bellard | |
| 486 | e98a6e40 | bellard | /* tests with result in T0 */
|
| 487 | e98a6e40 | bellard | |
| 488 | e98a6e40 | bellard | PPC_OP(test_ctr) |
| 489 | e98a6e40 | bellard | {
|
| 490 | b88e4a9a | bellard | T0 = regs->ctr; |
| 491 | e98a6e40 | bellard | } |
| 492 | e98a6e40 | bellard | |
| 493 | e98a6e40 | bellard | PPC_OP(test_ctr_true) |
| 494 | e98a6e40 | bellard | {
|
| 495 | e98a6e40 | bellard | T0 = (regs->ctr != 0 && (T0 & PARAM(1)) != 0); |
| 496 | e98a6e40 | bellard | } |
| 497 | e98a6e40 | bellard | |
| 498 | e98a6e40 | bellard | PPC_OP(test_ctr_false) |
| 499 | e98a6e40 | bellard | {
|
| 500 | e98a6e40 | bellard | T0 = (regs->ctr != 0 && (T0 & PARAM(1)) == 0); |
| 501 | e98a6e40 | bellard | } |
| 502 | e98a6e40 | bellard | |
| 503 | e98a6e40 | bellard | PPC_OP(test_ctrz) |
| 504 | e98a6e40 | bellard | {
|
| 505 | e98a6e40 | bellard | T0 = (regs->ctr == 0);
|
| 506 | e98a6e40 | bellard | } |
| 507 | e98a6e40 | bellard | |
| 508 | e98a6e40 | bellard | PPC_OP(test_ctrz_true) |
| 509 | e98a6e40 | bellard | {
|
| 510 | e98a6e40 | bellard | T0 = (regs->ctr == 0 && (T0 & PARAM(1)) != 0); |
| 511 | e98a6e40 | bellard | } |
| 512 | e98a6e40 | bellard | |
| 513 | e98a6e40 | bellard | PPC_OP(test_ctrz_false) |
| 514 | e98a6e40 | bellard | {
|
| 515 | e98a6e40 | bellard | T0 = (regs->ctr == 0 && (T0 & PARAM(1)) == 0); |
| 516 | e98a6e40 | bellard | } |
| 517 | e98a6e40 | bellard | |
| 518 | e98a6e40 | bellard | PPC_OP(test_true) |
| 519 | e98a6e40 | bellard | {
|
| 520 | b88e4a9a | bellard | T0 = (T0 & PARAM(1));
|
| 521 | e98a6e40 | bellard | } |
| 522 | e98a6e40 | bellard | |
| 523 | e98a6e40 | bellard | PPC_OP(test_false) |
| 524 | e98a6e40 | bellard | {
|
| 525 | e98a6e40 | bellard | T0 = ((T0 & PARAM(1)) == 0); |
| 526 | e98a6e40 | bellard | } |
| 527 | 79aceca5 | bellard | |
| 528 | 79aceca5 | bellard | /* CTR maintenance */
|
| 529 | 79aceca5 | bellard | PPC_OP(dec_ctr) |
| 530 | 79aceca5 | bellard | {
|
| 531 | 9a64fbe4 | bellard | regs->ctr--; |
| 532 | 79aceca5 | bellard | RETURN(); |
| 533 | 79aceca5 | bellard | } |
| 534 | 79aceca5 | bellard | |
| 535 | 79aceca5 | bellard | /*** Integer arithmetic ***/
|
| 536 | 79aceca5 | bellard | /* add */
|
| 537 | 79aceca5 | bellard | PPC_OP(add) |
| 538 | 79aceca5 | bellard | {
|
| 539 | 79aceca5 | bellard | T0 += T1; |
| 540 | 79aceca5 | bellard | RETURN(); |
| 541 | 79aceca5 | bellard | } |
| 542 | 79aceca5 | bellard | |
| 543 | 79aceca5 | bellard | PPC_OP(addo) |
| 544 | 79aceca5 | bellard | {
|
| 545 | 79aceca5 | bellard | T2 = T0; |
| 546 | 79aceca5 | bellard | T0 += T1; |
| 547 | 79aceca5 | bellard | if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) { |
| 548 | 79aceca5 | bellard | xer_so = 1;
|
| 549 | 79aceca5 | bellard | xer_ov = 1;
|
| 550 | 79aceca5 | bellard | } else {
|
| 551 | 79aceca5 | bellard | xer_ov = 0;
|
| 552 | 79aceca5 | bellard | } |
| 553 | 79aceca5 | bellard | RETURN(); |
| 554 | 79aceca5 | bellard | } |
| 555 | 79aceca5 | bellard | |
| 556 | 79aceca5 | bellard | /* add carrying */
|
| 557 | 79aceca5 | bellard | PPC_OP(addc) |
| 558 | 79aceca5 | bellard | {
|
| 559 | 79aceca5 | bellard | T2 = T0; |
| 560 | 79aceca5 | bellard | T0 += T1; |
| 561 | 79aceca5 | bellard | if (T0 < T2) {
|
| 562 | 79aceca5 | bellard | xer_ca = 1;
|
| 563 | 79aceca5 | bellard | } else {
|
| 564 | 79aceca5 | bellard | xer_ca = 0;
|
| 565 | 79aceca5 | bellard | } |
| 566 | 79aceca5 | bellard | RETURN(); |
| 567 | 79aceca5 | bellard | } |
| 568 | 79aceca5 | bellard | |
| 569 | 79aceca5 | bellard | PPC_OP(addco) |
| 570 | 79aceca5 | bellard | {
|
| 571 | 79aceca5 | bellard | T2 = T0; |
| 572 | 79aceca5 | bellard | T0 += T1; |
| 573 | 79aceca5 | bellard | if (T0 < T2) {
|
| 574 | 79aceca5 | bellard | xer_ca = 1;
|
| 575 | 79aceca5 | bellard | } else {
|
| 576 | 79aceca5 | bellard | xer_ca = 0;
|
| 577 | 79aceca5 | bellard | } |
| 578 | 79aceca5 | bellard | if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) { |
| 579 | 79aceca5 | bellard | xer_so = 1;
|
| 580 | 79aceca5 | bellard | xer_ov = 1;
|
| 581 | 79aceca5 | bellard | } else {
|
| 582 | 79aceca5 | bellard | xer_ov = 0;
|
| 583 | 79aceca5 | bellard | } |
| 584 | 79aceca5 | bellard | RETURN(); |
| 585 | 79aceca5 | bellard | } |
| 586 | 79aceca5 | bellard | |
| 587 | 79aceca5 | bellard | /* add extended */
|
| 588 | 79aceca5 | bellard | /* candidate for helper (too long) */
|
| 589 | 79aceca5 | bellard | PPC_OP(adde) |
| 590 | 79aceca5 | bellard | {
|
| 591 | 79aceca5 | bellard | T2 = T0; |
| 592 | 79aceca5 | bellard | T0 += T1 + xer_ca; |
| 593 | 79aceca5 | bellard | if (T0 < T2 || (xer_ca == 1 && T0 == T2)) { |
| 594 | 79aceca5 | bellard | xer_ca = 1;
|
| 595 | 79aceca5 | bellard | } else {
|
| 596 | 79aceca5 | bellard | xer_ca = 0;
|
| 597 | 79aceca5 | bellard | } |
| 598 | 79aceca5 | bellard | RETURN(); |
| 599 | 79aceca5 | bellard | } |
| 600 | 79aceca5 | bellard | |
| 601 | 79aceca5 | bellard | PPC_OP(addeo) |
| 602 | 79aceca5 | bellard | {
|
| 603 | 79aceca5 | bellard | T2 = T0; |
| 604 | 79aceca5 | bellard | T0 += T1 + xer_ca; |
| 605 | 79aceca5 | bellard | if (T0 < T2 || (xer_ca == 1 && T0 == T2)) { |
| 606 | 79aceca5 | bellard | xer_ca = 1;
|
| 607 | 79aceca5 | bellard | } else {
|
| 608 | 79aceca5 | bellard | xer_ca = 0;
|
| 609 | 79aceca5 | bellard | } |
| 610 | 79aceca5 | bellard | if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) { |
| 611 | 79aceca5 | bellard | xer_so = 1;
|
| 612 | 79aceca5 | bellard | xer_ov = 1;
|
| 613 | 79aceca5 | bellard | } else {
|
| 614 | 79aceca5 | bellard | xer_ov = 0;
|
| 615 | 79aceca5 | bellard | } |
| 616 | 79aceca5 | bellard | RETURN(); |
| 617 | 79aceca5 | bellard | } |
| 618 | 79aceca5 | bellard | |
| 619 | 79aceca5 | bellard | /* add immediate */
|
| 620 | 79aceca5 | bellard | PPC_OP(addi) |
| 621 | 79aceca5 | bellard | {
|
| 622 | 79aceca5 | bellard | T0 += PARAM(1);
|
| 623 | 79aceca5 | bellard | RETURN(); |
| 624 | 79aceca5 | bellard | } |
| 625 | 79aceca5 | bellard | |
| 626 | 79aceca5 | bellard | /* add immediate carrying */
|
| 627 | 79aceca5 | bellard | PPC_OP(addic) |
| 628 | 79aceca5 | bellard | {
|
| 629 | 79aceca5 | bellard | T1 = T0; |
| 630 | 79aceca5 | bellard | T0 += PARAM(1);
|
| 631 | 79aceca5 | bellard | if (T0 < T1) {
|
| 632 | 79aceca5 | bellard | xer_ca = 1;
|
| 633 | 79aceca5 | bellard | } else {
|
| 634 | 79aceca5 | bellard | xer_ca = 0;
|
| 635 | 79aceca5 | bellard | } |
| 636 | 79aceca5 | bellard | RETURN(); |
| 637 | 79aceca5 | bellard | } |
| 638 | 79aceca5 | bellard | |
| 639 | 79aceca5 | bellard | /* add to minus one extended */
|
| 640 | 79aceca5 | bellard | PPC_OP(addme) |
| 641 | 79aceca5 | bellard | {
|
| 642 | 79aceca5 | bellard | T1 = T0; |
| 643 | 79aceca5 | bellard | T0 += xer_ca + (-1);
|
| 644 | 79aceca5 | bellard | if (T1 != 0) |
| 645 | 79aceca5 | bellard | xer_ca = 1;
|
| 646 | 79aceca5 | bellard | RETURN(); |
| 647 | 79aceca5 | bellard | } |
| 648 | 79aceca5 | bellard | |
| 649 | 79aceca5 | bellard | PPC_OP(addmeo) |
| 650 | 79aceca5 | bellard | {
|
| 651 | 79aceca5 | bellard | T1 = T0; |
| 652 | 79aceca5 | bellard | T0 += xer_ca + (-1);
|
| 653 | 79aceca5 | bellard | if (T1 & (T1 ^ T0) & (1 << 31)) { |
| 654 | 79aceca5 | bellard | xer_so = 1;
|
| 655 | 79aceca5 | bellard | xer_ov = 1;
|
| 656 | 79aceca5 | bellard | } else {
|
| 657 | 79aceca5 | bellard | xer_ov = 0;
|
| 658 | 79aceca5 | bellard | } |
| 659 | 79aceca5 | bellard | if (T1 != 0) |
| 660 | 79aceca5 | bellard | xer_ca = 1;
|
| 661 | 79aceca5 | bellard | RETURN(); |
| 662 | 79aceca5 | bellard | } |
| 663 | 79aceca5 | bellard | |
| 664 | 79aceca5 | bellard | /* add to zero extended */
|
| 665 | 79aceca5 | bellard | PPC_OP(addze) |
| 666 | 79aceca5 | bellard | {
|
| 667 | 79aceca5 | bellard | T1 = T0; |
| 668 | 79aceca5 | bellard | T0 += xer_ca; |
| 669 | 79aceca5 | bellard | if (T0 < T1) {
|
| 670 | 79aceca5 | bellard | xer_ca = 1;
|
| 671 | 79aceca5 | bellard | } else {
|
| 672 | 79aceca5 | bellard | xer_ca = 0;
|
| 673 | 79aceca5 | bellard | } |
| 674 | 79aceca5 | bellard | RETURN(); |
| 675 | 79aceca5 | bellard | } |
| 676 | 79aceca5 | bellard | |
| 677 | 79aceca5 | bellard | PPC_OP(addzeo) |
| 678 | 79aceca5 | bellard | {
|
| 679 | 79aceca5 | bellard | T1 = T0; |
| 680 | 79aceca5 | bellard | T0 += xer_ca; |
| 681 | 79aceca5 | bellard | if ((T1 ^ (-1)) & (T1 ^ T0) & (1 << 31)) { |
| 682 | 79aceca5 | bellard | xer_so = 1;
|
| 683 | 79aceca5 | bellard | xer_ov = 1;
|
| 684 | 79aceca5 | bellard | } else {
|
| 685 | 79aceca5 | bellard | xer_ov = 0;
|
| 686 | 79aceca5 | bellard | } |
| 687 | 79aceca5 | bellard | if (T0 < T1) {
|
| 688 | 79aceca5 | bellard | xer_ca = 1;
|
| 689 | 79aceca5 | bellard | } else {
|
| 690 | 79aceca5 | bellard | xer_ca = 0;
|
| 691 | 79aceca5 | bellard | } |
| 692 | 79aceca5 | bellard | RETURN(); |
| 693 | 79aceca5 | bellard | } |
| 694 | 79aceca5 | bellard | |
| 695 | 79aceca5 | bellard | /* divide word */
|
| 696 | 79aceca5 | bellard | /* candidate for helper (too long) */
|
| 697 | 79aceca5 | bellard | PPC_OP(divw) |
| 698 | 79aceca5 | bellard | {
|
| 699 | 79aceca5 | bellard | if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) { |
| 700 | 3cc62370 | bellard | T0 = (int32_t)((-1) * (T0 >> 31)); |
| 701 | 79aceca5 | bellard | } else {
|
| 702 | 3cc62370 | bellard | T0 = (Ts0 / Ts1); |
| 703 | 79aceca5 | bellard | } |
| 704 | 79aceca5 | bellard | RETURN(); |
| 705 | 79aceca5 | bellard | } |
| 706 | 79aceca5 | bellard | |
| 707 | 79aceca5 | bellard | PPC_OP(divwo) |
| 708 | 79aceca5 | bellard | {
|
| 709 | 79aceca5 | bellard | if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) { |
| 710 | 79aceca5 | bellard | xer_so = 1;
|
| 711 | 79aceca5 | bellard | xer_ov = 1;
|
| 712 | 79aceca5 | bellard | T0 = (-1) * (T0 >> 31); |
| 713 | 79aceca5 | bellard | } else {
|
| 714 | 79aceca5 | bellard | xer_ov = 0;
|
| 715 | 3cc62370 | bellard | T0 = (Ts0 / Ts1); |
| 716 | 79aceca5 | bellard | } |
| 717 | 79aceca5 | bellard | RETURN(); |
| 718 | 79aceca5 | bellard | } |
| 719 | 79aceca5 | bellard | |
| 720 | 79aceca5 | bellard | /* divide word unsigned */
|
| 721 | 79aceca5 | bellard | PPC_OP(divwu) |
| 722 | 79aceca5 | bellard | {
|
| 723 | 79aceca5 | bellard | if (T1 == 0) { |
| 724 | 79aceca5 | bellard | T0 = 0;
|
| 725 | 79aceca5 | bellard | } else {
|
| 726 | 79aceca5 | bellard | T0 /= T1; |
| 727 | 79aceca5 | bellard | } |
| 728 | 79aceca5 | bellard | RETURN(); |
| 729 | 79aceca5 | bellard | } |
| 730 | 79aceca5 | bellard | |
| 731 | 79aceca5 | bellard | PPC_OP(divwuo) |
| 732 | 79aceca5 | bellard | {
|
| 733 | 79aceca5 | bellard | if (T1 == 0) { |
| 734 | 79aceca5 | bellard | xer_so = 1;
|
| 735 | 79aceca5 | bellard | xer_ov = 1;
|
| 736 | 79aceca5 | bellard | T0 = 0;
|
| 737 | 79aceca5 | bellard | } else {
|
| 738 | 79aceca5 | bellard | xer_ov = 0;
|
| 739 | 79aceca5 | bellard | T0 /= T1; |
| 740 | 79aceca5 | bellard | } |
| 741 | 79aceca5 | bellard | RETURN(); |
| 742 | 79aceca5 | bellard | } |
| 743 | 79aceca5 | bellard | |
| 744 | 79aceca5 | bellard | /* multiply high word */
|
| 745 | 79aceca5 | bellard | PPC_OP(mulhw) |
| 746 | 79aceca5 | bellard | {
|
| 747 | 3cc62370 | bellard | T0 = ((int64_t)Ts0 * (int64_t)Ts1) >> 32;
|
| 748 | 79aceca5 | bellard | RETURN(); |
| 749 | 79aceca5 | bellard | } |
| 750 | 79aceca5 | bellard | |
| 751 | 79aceca5 | bellard | /* multiply high word unsigned */
|
| 752 | 79aceca5 | bellard | PPC_OP(mulhwu) |
| 753 | 79aceca5 | bellard | {
|
| 754 | 79aceca5 | bellard | T0 = ((uint64_t)T0 * (uint64_t)T1) >> 32;
|
| 755 | 79aceca5 | bellard | RETURN(); |
| 756 | 79aceca5 | bellard | } |
| 757 | 79aceca5 | bellard | |
| 758 | 79aceca5 | bellard | /* multiply low immediate */
|
| 759 | 79aceca5 | bellard | PPC_OP(mulli) |
| 760 | 79aceca5 | bellard | {
|
| 761 | 3cc62370 | bellard | T0 = (Ts0 * SPARAM(1));
|
| 762 | 79aceca5 | bellard | RETURN(); |
| 763 | 79aceca5 | bellard | } |
| 764 | 79aceca5 | bellard | |
| 765 | 79aceca5 | bellard | /* multiply low word */
|
| 766 | 79aceca5 | bellard | PPC_OP(mullw) |
| 767 | 79aceca5 | bellard | {
|
| 768 | 79aceca5 | bellard | T0 *= T1; |
| 769 | 79aceca5 | bellard | RETURN(); |
| 770 | 79aceca5 | bellard | } |
| 771 | 79aceca5 | bellard | |
| 772 | 79aceca5 | bellard | PPC_OP(mullwo) |
| 773 | 79aceca5 | bellard | {
|
| 774 | 79aceca5 | bellard | int64_t res = (int64_t)Ts0 * (int64_t)Ts1; |
| 775 | 79aceca5 | bellard | |
| 776 | 79aceca5 | bellard | if ((int32_t)res != res) {
|
| 777 | 79aceca5 | bellard | xer_ov = 1;
|
| 778 | 79aceca5 | bellard | xer_so = 1;
|
| 779 | 79aceca5 | bellard | } else {
|
| 780 | 79aceca5 | bellard | xer_ov = 0;
|
| 781 | 79aceca5 | bellard | } |
| 782 | 3cc62370 | bellard | T0 = (int32_t)res; |
| 783 | 79aceca5 | bellard | RETURN(); |
| 784 | 79aceca5 | bellard | } |
| 785 | 79aceca5 | bellard | |
| 786 | 79aceca5 | bellard | /* negate */
|
| 787 | 79aceca5 | bellard | PPC_OP(neg) |
| 788 | 79aceca5 | bellard | {
|
| 789 | 79aceca5 | bellard | if (T0 != 0x80000000) { |
| 790 | 3cc62370 | bellard | T0 = -Ts0; |
| 791 | 79aceca5 | bellard | } |
| 792 | 79aceca5 | bellard | RETURN(); |
| 793 | 79aceca5 | bellard | } |
| 794 | 79aceca5 | bellard | |
| 795 | 79aceca5 | bellard | PPC_OP(nego) |
| 796 | 79aceca5 | bellard | {
|
| 797 | 79aceca5 | bellard | if (T0 == 0x80000000) { |
| 798 | 79aceca5 | bellard | xer_ov = 1;
|
| 799 | 79aceca5 | bellard | xer_so = 1;
|
| 800 | 79aceca5 | bellard | } else {
|
| 801 | 79aceca5 | bellard | xer_ov = 0;
|
| 802 | 3cc62370 | bellard | T0 = -Ts0; |
| 803 | 79aceca5 | bellard | } |
| 804 | 79aceca5 | bellard | RETURN(); |
| 805 | 79aceca5 | bellard | } |
| 806 | 79aceca5 | bellard | |
| 807 | 79aceca5 | bellard | /* substract from */
|
| 808 | 79aceca5 | bellard | PPC_OP(subf) |
| 809 | 79aceca5 | bellard | {
|
| 810 | 79aceca5 | bellard | T0 = T1 - T0; |
| 811 | 79aceca5 | bellard | RETURN(); |
| 812 | 79aceca5 | bellard | } |
| 813 | 79aceca5 | bellard | |
| 814 | 79aceca5 | bellard | PPC_OP(subfo) |
| 815 | 79aceca5 | bellard | {
|
| 816 | 79aceca5 | bellard | T2 = T0; |
| 817 | 79aceca5 | bellard | T0 = T1 - T0; |
| 818 | 79aceca5 | bellard | if (((~T2) ^ T1 ^ (-1)) & ((~T2) ^ T0) & (1 << 31)) { |
| 819 | 79aceca5 | bellard | xer_so = 1;
|
| 820 | 79aceca5 | bellard | xer_ov = 1;
|
| 821 | 79aceca5 | bellard | } else {
|
| 822 | 79aceca5 | bellard | xer_ov = 0;
|
| 823 | 79aceca5 | bellard | } |
| 824 | 79aceca5 | bellard | RETURN(); |
| 825 | 79aceca5 | bellard | } |
| 826 | 79aceca5 | bellard | |
| 827 | 79aceca5 | bellard | /* substract from carrying */
|
| 828 | 79aceca5 | bellard | PPC_OP(subfc) |
| 829 | 79aceca5 | bellard | {
|
| 830 | 79aceca5 | bellard | T0 = T1 - T0; |
| 831 | 79aceca5 | bellard | if (T0 <= T1) {
|
| 832 | 79aceca5 | bellard | xer_ca = 1;
|
| 833 | 79aceca5 | bellard | } else {
|
| 834 | 79aceca5 | bellard | xer_ca = 0;
|
| 835 | 79aceca5 | bellard | } |
| 836 | 79aceca5 | bellard | RETURN(); |
| 837 | 79aceca5 | bellard | } |
| 838 | 79aceca5 | bellard | |
| 839 | 79aceca5 | bellard | PPC_OP(subfco) |
| 840 | 79aceca5 | bellard | {
|
| 841 | 79aceca5 | bellard | T2 = T0; |
| 842 | 79aceca5 | bellard | T0 = T1 - T0; |
| 843 | 79aceca5 | bellard | if (T0 <= T1) {
|
| 844 | 79aceca5 | bellard | xer_ca = 1;
|
| 845 | 79aceca5 | bellard | } else {
|
| 846 | 79aceca5 | bellard | xer_ca = 0;
|
| 847 | 79aceca5 | bellard | } |
| 848 | 79aceca5 | bellard | if (((~T2) ^ T1 ^ (-1)) & ((~T2) ^ T0) & (1 << 31)) { |
| 849 | 79aceca5 | bellard | xer_so = 1;
|
| 850 | 79aceca5 | bellard | xer_ov = 1;
|
| 851 | 79aceca5 | bellard | } else {
|
| 852 | 79aceca5 | bellard | xer_ov = 0;
|
| 853 | 79aceca5 | bellard | } |
| 854 | 79aceca5 | bellard | RETURN(); |
| 855 | 79aceca5 | bellard | } |
| 856 | 79aceca5 | bellard | |
| 857 | 79aceca5 | bellard | /* substract from extended */
|
| 858 | 79aceca5 | bellard | /* candidate for helper (too long) */
|
| 859 | 79aceca5 | bellard | PPC_OP(subfe) |
| 860 | 79aceca5 | bellard | {
|
| 861 | 79aceca5 | bellard | T0 = T1 + ~T0 + xer_ca; |
| 862 | 79aceca5 | bellard | if (T0 < T1 || (xer_ca == 1 && T0 == T1)) { |
| 863 | 79aceca5 | bellard | xer_ca = 1;
|
| 864 | 79aceca5 | bellard | } else {
|
| 865 | 79aceca5 | bellard | xer_ca = 0;
|
| 866 | 79aceca5 | bellard | } |
| 867 | 79aceca5 | bellard | RETURN(); |
| 868 | 79aceca5 | bellard | } |
| 869 | 79aceca5 | bellard | |
| 870 | 79aceca5 | bellard | PPC_OP(subfeo) |
| 871 | 79aceca5 | bellard | {
|
| 872 | 79aceca5 | bellard | T2 = T0; |
| 873 | 79aceca5 | bellard | T0 = T1 + ~T0 + xer_ca; |
| 874 | 79aceca5 | bellard | if ((~T2 ^ T1 ^ (-1)) & (~T2 ^ T0) & (1 << 31)) { |
| 875 | 79aceca5 | bellard | xer_so = 1;
|
| 876 | 79aceca5 | bellard | xer_ov = 1;
|
| 877 | 79aceca5 | bellard | } else {
|
| 878 | 79aceca5 | bellard | xer_ov = 0;
|
| 879 | 79aceca5 | bellard | } |
| 880 | 79aceca5 | bellard | if (T0 < T1 || (xer_ca == 1 && T0 == T1)) { |
| 881 | 79aceca5 | bellard | xer_ca = 1;
|
| 882 | 79aceca5 | bellard | } else {
|
| 883 | 79aceca5 | bellard | xer_ca = 0;
|
| 884 | 79aceca5 | bellard | } |
| 885 | 79aceca5 | bellard | RETURN(); |
| 886 | 79aceca5 | bellard | } |
| 887 | 79aceca5 | bellard | |
| 888 | 79aceca5 | bellard | /* substract from immediate carrying */
|
| 889 | 79aceca5 | bellard | PPC_OP(subfic) |
| 890 | 79aceca5 | bellard | {
|
| 891 | 79aceca5 | bellard | T0 = PARAM(1) + ~T0 + 1; |
| 892 | 79aceca5 | bellard | if (T0 <= PARAM(1)) { |
| 893 | 79aceca5 | bellard | xer_ca = 1;
|
| 894 | 79aceca5 | bellard | } else {
|
| 895 | 79aceca5 | bellard | xer_ca = 0;
|
| 896 | 79aceca5 | bellard | } |
| 897 | 79aceca5 | bellard | RETURN(); |
| 898 | 79aceca5 | bellard | } |
| 899 | 79aceca5 | bellard | |
| 900 | 79aceca5 | bellard | /* substract from minus one extended */
|
| 901 | 79aceca5 | bellard | PPC_OP(subfme) |
| 902 | 79aceca5 | bellard | {
|
| 903 | 79aceca5 | bellard | T0 = ~T0 + xer_ca - 1;
|
| 904 | 79aceca5 | bellard | |
| 905 | 79aceca5 | bellard | if (T0 != -1) |
| 906 | 79aceca5 | bellard | xer_ca = 1;
|
| 907 | 79aceca5 | bellard | RETURN(); |
| 908 | 79aceca5 | bellard | } |
| 909 | 79aceca5 | bellard | |
| 910 | 79aceca5 | bellard | PPC_OP(subfmeo) |
| 911 | 79aceca5 | bellard | {
|
| 912 | 79aceca5 | bellard | T1 = T0; |
| 913 | 79aceca5 | bellard | T0 = ~T0 + xer_ca - 1;
|
| 914 | 79aceca5 | bellard | if (~T1 & (~T1 ^ T0) & (1 << 31)) { |
| 915 | 79aceca5 | bellard | xer_so = 1;
|
| 916 | 79aceca5 | bellard | xer_ov = 1;
|
| 917 | 79aceca5 | bellard | } else {
|
| 918 | 79aceca5 | bellard | xer_ov = 0;
|
| 919 | 79aceca5 | bellard | } |
| 920 | 79aceca5 | bellard | if (T1 != -1) |
| 921 | 79aceca5 | bellard | xer_ca = 1;
|
| 922 | 79aceca5 | bellard | RETURN(); |
| 923 | 79aceca5 | bellard | } |
| 924 | 79aceca5 | bellard | |
| 925 | 79aceca5 | bellard | /* substract from zero extended */
|
| 926 | 79aceca5 | bellard | PPC_OP(subfze) |
| 927 | 79aceca5 | bellard | {
|
| 928 | 79aceca5 | bellard | T1 = ~T0; |
| 929 | 79aceca5 | bellard | T0 = T1 + xer_ca; |
| 930 | 79aceca5 | bellard | if (T0 < T1) {
|
| 931 | 79aceca5 | bellard | xer_ca = 1;
|
| 932 | 79aceca5 | bellard | } else {
|
| 933 | 79aceca5 | bellard | xer_ca = 0;
|
| 934 | 79aceca5 | bellard | } |
| 935 | 79aceca5 | bellard | RETURN(); |
| 936 | 79aceca5 | bellard | } |
| 937 | 79aceca5 | bellard | |
| 938 | 79aceca5 | bellard | PPC_OP(subfzeo) |
| 939 | 79aceca5 | bellard | {
|
| 940 | 79aceca5 | bellard | T1 = T0; |
| 941 | 79aceca5 | bellard | T0 = ~T0 + xer_ca; |
| 942 | 79aceca5 | bellard | if ((~T1 ^ (-1)) & ((~T1) ^ T0) & (1 << 31)) { |
| 943 | 79aceca5 | bellard | xer_ov = 1;
|
| 944 | 79aceca5 | bellard | xer_so = 1;
|
| 945 | 79aceca5 | bellard | } else {
|
| 946 | 79aceca5 | bellard | xer_ov = 0;
|
| 947 | 79aceca5 | bellard | } |
| 948 | 79aceca5 | bellard | if (T0 < ~T1) {
|
| 949 | 79aceca5 | bellard | xer_ca = 1;
|
| 950 | 79aceca5 | bellard | } else {
|
| 951 | 79aceca5 | bellard | xer_ca = 0;
|
| 952 | 79aceca5 | bellard | } |
| 953 | 79aceca5 | bellard | RETURN(); |
| 954 | 79aceca5 | bellard | } |
| 955 | 79aceca5 | bellard | |
| 956 | 79aceca5 | bellard | /*** Integer comparison ***/
|
| 957 | 79aceca5 | bellard | /* compare */
|
| 958 | 79aceca5 | bellard | PPC_OP(cmp) |
| 959 | 79aceca5 | bellard | {
|
| 960 | 79aceca5 | bellard | if (Ts0 < Ts1) {
|
| 961 | 79aceca5 | bellard | T0 = 0x08;
|
| 962 | 79aceca5 | bellard | } else if (Ts0 > Ts1) { |
| 963 | 79aceca5 | bellard | T0 = 0x04;
|
| 964 | 79aceca5 | bellard | } else {
|
| 965 | 79aceca5 | bellard | T0 = 0x02;
|
| 966 | 79aceca5 | bellard | } |
| 967 | 79aceca5 | bellard | RETURN(); |
| 968 | 79aceca5 | bellard | } |
| 969 | 79aceca5 | bellard | |
| 970 | 79aceca5 | bellard | /* compare immediate */
|
| 971 | 79aceca5 | bellard | PPC_OP(cmpi) |
| 972 | 79aceca5 | bellard | {
|
| 973 | 79aceca5 | bellard | if (Ts0 < SPARAM(1)) { |
| 974 | 79aceca5 | bellard | T0 = 0x08;
|
| 975 | 79aceca5 | bellard | } else if (Ts0 > SPARAM(1)) { |
| 976 | 79aceca5 | bellard | T0 = 0x04;
|
| 977 | 79aceca5 | bellard | } else {
|
| 978 | 79aceca5 | bellard | T0 = 0x02;
|
| 979 | 79aceca5 | bellard | } |
| 980 | 79aceca5 | bellard | RETURN(); |
| 981 | 79aceca5 | bellard | } |
| 982 | 79aceca5 | bellard | |
| 983 | 79aceca5 | bellard | /* compare logical */
|
| 984 | 79aceca5 | bellard | PPC_OP(cmpl) |
| 985 | 79aceca5 | bellard | {
|
| 986 | 79aceca5 | bellard | if (T0 < T1) {
|
| 987 | 79aceca5 | bellard | T0 = 0x08;
|
| 988 | 79aceca5 | bellard | } else if (T0 > T1) { |
| 989 | 79aceca5 | bellard | T0 = 0x04;
|
| 990 | 79aceca5 | bellard | } else {
|
| 991 | 79aceca5 | bellard | T0 = 0x02;
|
| 992 | 79aceca5 | bellard | } |
| 993 | 79aceca5 | bellard | RETURN(); |
| 994 | 79aceca5 | bellard | } |
| 995 | 79aceca5 | bellard | |
| 996 | 79aceca5 | bellard | /* compare logical immediate */
|
| 997 | 79aceca5 | bellard | PPC_OP(cmpli) |
| 998 | 79aceca5 | bellard | {
|
| 999 | 79aceca5 | bellard | if (T0 < PARAM(1)) { |
| 1000 | 79aceca5 | bellard | T0 = 0x08;
|
| 1001 | 79aceca5 | bellard | } else if (T0 > PARAM(1)) { |
| 1002 | 79aceca5 | bellard | T0 = 0x04;
|
| 1003 | 79aceca5 | bellard | } else {
|
| 1004 | 79aceca5 | bellard | T0 = 0x02;
|
| 1005 | 79aceca5 | bellard | } |
| 1006 | 79aceca5 | bellard | RETURN(); |
| 1007 | 79aceca5 | bellard | } |
| 1008 | 79aceca5 | bellard | |
| 1009 | 79aceca5 | bellard | /*** Integer logical ***/
|
| 1010 | 79aceca5 | bellard | /* and */
|
| 1011 | 79aceca5 | bellard | PPC_OP(and) |
| 1012 | 79aceca5 | bellard | {
|
| 1013 | 79aceca5 | bellard | T0 &= T1; |
| 1014 | 79aceca5 | bellard | RETURN(); |
| 1015 | 79aceca5 | bellard | } |
| 1016 | 79aceca5 | bellard | |
| 1017 | 79aceca5 | bellard | /* andc */
|
| 1018 | 79aceca5 | bellard | PPC_OP(andc) |
| 1019 | 79aceca5 | bellard | {
|
| 1020 | 79aceca5 | bellard | T0 &= ~T1; |
| 1021 | 79aceca5 | bellard | RETURN(); |
| 1022 | 79aceca5 | bellard | } |
| 1023 | 79aceca5 | bellard | |
| 1024 | 79aceca5 | bellard | /* andi. */
|
| 1025 | 79aceca5 | bellard | PPC_OP(andi_) |
| 1026 | 79aceca5 | bellard | {
|
| 1027 | 79aceca5 | bellard | T0 &= PARAM(1);
|
| 1028 | 79aceca5 | bellard | RETURN(); |
| 1029 | 79aceca5 | bellard | } |
| 1030 | 79aceca5 | bellard | |
| 1031 | 79aceca5 | bellard | /* count leading zero */
|
| 1032 | 79aceca5 | bellard | PPC_OP(cntlzw) |
| 1033 | 79aceca5 | bellard | {
|
| 1034 | 79aceca5 | bellard | T1 = T0; |
| 1035 | 79aceca5 | bellard | for (T0 = 32; T1 > 0; T0--) |
| 1036 | 79aceca5 | bellard | T1 = T1 >> 1;
|
| 1037 | 79aceca5 | bellard | RETURN(); |
| 1038 | 79aceca5 | bellard | } |
| 1039 | 79aceca5 | bellard | |
| 1040 | 79aceca5 | bellard | /* eqv */
|
| 1041 | 79aceca5 | bellard | PPC_OP(eqv) |
| 1042 | 79aceca5 | bellard | {
|
| 1043 | 79aceca5 | bellard | T0 = ~(T0 ^ T1); |
| 1044 | 79aceca5 | bellard | RETURN(); |
| 1045 | 79aceca5 | bellard | } |
| 1046 | 79aceca5 | bellard | |
| 1047 | 79aceca5 | bellard | /* extend sign byte */
|
| 1048 | 79aceca5 | bellard | PPC_OP(extsb) |
| 1049 | 79aceca5 | bellard | {
|
| 1050 | 3cc62370 | bellard | T0 = (int32_t)((int8_t)(Ts0)); |
| 1051 | 79aceca5 | bellard | RETURN(); |
| 1052 | 79aceca5 | bellard | } |
| 1053 | 79aceca5 | bellard | |
| 1054 | 79aceca5 | bellard | /* extend sign half word */
|
| 1055 | 79aceca5 | bellard | PPC_OP(extsh) |
| 1056 | 79aceca5 | bellard | {
|
| 1057 | 3cc62370 | bellard | T0 = (int32_t)((int16_t)(Ts0)); |
| 1058 | 79aceca5 | bellard | RETURN(); |
| 1059 | 79aceca5 | bellard | } |
| 1060 | 79aceca5 | bellard | |
| 1061 | 79aceca5 | bellard | /* nand */
|
| 1062 | 79aceca5 | bellard | PPC_OP(nand) |
| 1063 | 79aceca5 | bellard | {
|
| 1064 | 79aceca5 | bellard | T0 = ~(T0 & T1); |
| 1065 | 79aceca5 | bellard | RETURN(); |
| 1066 | 79aceca5 | bellard | } |
| 1067 | 79aceca5 | bellard | |
| 1068 | 79aceca5 | bellard | /* nor */
|
| 1069 | 79aceca5 | bellard | PPC_OP(nor) |
| 1070 | 79aceca5 | bellard | {
|
| 1071 | 79aceca5 | bellard | T0 = ~(T0 | T1); |
| 1072 | 79aceca5 | bellard | RETURN(); |
| 1073 | 79aceca5 | bellard | } |
| 1074 | 79aceca5 | bellard | |
| 1075 | 79aceca5 | bellard | /* or */
|
| 1076 | 79aceca5 | bellard | PPC_OP(or) |
| 1077 | 79aceca5 | bellard | {
|
| 1078 | 79aceca5 | bellard | T0 |= T1; |
| 1079 | 79aceca5 | bellard | RETURN(); |
| 1080 | 79aceca5 | bellard | } |
| 1081 | 79aceca5 | bellard | |
| 1082 | 79aceca5 | bellard | /* orc */
|
| 1083 | 79aceca5 | bellard | PPC_OP(orc) |
| 1084 | 79aceca5 | bellard | {
|
| 1085 | 79aceca5 | bellard | T0 |= ~T1; |
| 1086 | 79aceca5 | bellard | RETURN(); |
| 1087 | 79aceca5 | bellard | } |
| 1088 | 79aceca5 | bellard | |
| 1089 | 79aceca5 | bellard | /* ori */
|
| 1090 | 79aceca5 | bellard | PPC_OP(ori) |
| 1091 | 79aceca5 | bellard | {
|
| 1092 | 79aceca5 | bellard | T0 |= PARAM(1);
|
| 1093 | 79aceca5 | bellard | RETURN(); |
| 1094 | 79aceca5 | bellard | } |
| 1095 | 79aceca5 | bellard | |
| 1096 | 79aceca5 | bellard | /* xor */
|
| 1097 | 79aceca5 | bellard | PPC_OP(xor) |
| 1098 | 79aceca5 | bellard | {
|
| 1099 | 79aceca5 | bellard | T0 ^= T1; |
| 1100 | 79aceca5 | bellard | RETURN(); |
| 1101 | 79aceca5 | bellard | } |
| 1102 | 79aceca5 | bellard | |
| 1103 | 79aceca5 | bellard | /* xori */
|
| 1104 | 79aceca5 | bellard | PPC_OP(xori) |
| 1105 | 79aceca5 | bellard | {
|
| 1106 | 79aceca5 | bellard | T0 ^= PARAM(1);
|
| 1107 | 79aceca5 | bellard | RETURN(); |
| 1108 | 79aceca5 | bellard | } |
| 1109 | 79aceca5 | bellard | |
| 1110 | 79aceca5 | bellard | /*** Integer rotate ***/
|
| 1111 | 79aceca5 | bellard | /* rotate left word immediate then mask insert */
|
| 1112 | 79aceca5 | bellard | PPC_OP(rlwimi) |
| 1113 | 79aceca5 | bellard | {
|
| 1114 | fb0eaffc | bellard | T0 = (rotl(T0, PARAM(1)) & PARAM(2)) | (T1 & PARAM(3)); |
| 1115 | 79aceca5 | bellard | RETURN(); |
| 1116 | 79aceca5 | bellard | } |
| 1117 | 79aceca5 | bellard | |
| 1118 | 79aceca5 | bellard | /* rotate left immediate then and with mask insert */
|
| 1119 | 79aceca5 | bellard | PPC_OP(rotlwi) |
| 1120 | 79aceca5 | bellard | {
|
| 1121 | 79aceca5 | bellard | T0 = rotl(T0, PARAM(1));
|
| 1122 | 79aceca5 | bellard | RETURN(); |
| 1123 | 79aceca5 | bellard | } |
| 1124 | 79aceca5 | bellard | |
| 1125 | 79aceca5 | bellard | PPC_OP(slwi) |
| 1126 | 79aceca5 | bellard | {
|
| 1127 | 79aceca5 | bellard | T0 = T0 << PARAM(1);
|
| 1128 | 79aceca5 | bellard | RETURN(); |
| 1129 | 79aceca5 | bellard | } |
| 1130 | 79aceca5 | bellard | |
| 1131 | 79aceca5 | bellard | PPC_OP(srwi) |
| 1132 | 79aceca5 | bellard | {
|
| 1133 | 79aceca5 | bellard | T0 = T0 >> PARAM(1);
|
| 1134 | 79aceca5 | bellard | RETURN(); |
| 1135 | 79aceca5 | bellard | } |
| 1136 | 79aceca5 | bellard | |
| 1137 | 79aceca5 | bellard | /* rotate left word then and with mask insert */
|
| 1138 | 79aceca5 | bellard | PPC_OP(rlwinm) |
| 1139 | 79aceca5 | bellard | {
|
| 1140 | 79aceca5 | bellard | T0 = rotl(T0, PARAM(1)) & PARAM(2); |
| 1141 | 79aceca5 | bellard | RETURN(); |
| 1142 | 79aceca5 | bellard | } |
| 1143 | 79aceca5 | bellard | |
| 1144 | 79aceca5 | bellard | PPC_OP(rotl) |
| 1145 | 79aceca5 | bellard | {
|
| 1146 | 79aceca5 | bellard | T0 = rotl(T0, T1); |
| 1147 | 79aceca5 | bellard | RETURN(); |
| 1148 | 79aceca5 | bellard | } |
| 1149 | 79aceca5 | bellard | |
| 1150 | 79aceca5 | bellard | PPC_OP(rlwnm) |
| 1151 | 79aceca5 | bellard | {
|
| 1152 | 79aceca5 | bellard | T0 = rotl(T0, T1) & PARAM(1);
|
| 1153 | 79aceca5 | bellard | RETURN(); |
| 1154 | 79aceca5 | bellard | } |
| 1155 | 79aceca5 | bellard | |
| 1156 | 79aceca5 | bellard | /*** Integer shift ***/
|
| 1157 | 79aceca5 | bellard | /* shift left word */
|
| 1158 | 79aceca5 | bellard | PPC_OP(slw) |
| 1159 | 79aceca5 | bellard | {
|
| 1160 | 79aceca5 | bellard | if (T1 & 0x20) { |
| 1161 | 79aceca5 | bellard | T0 = 0;
|
| 1162 | 79aceca5 | bellard | } else {
|
| 1163 | 79aceca5 | bellard | T0 = T0 << T1; |
| 1164 | 79aceca5 | bellard | } |
| 1165 | 79aceca5 | bellard | RETURN(); |
| 1166 | 79aceca5 | bellard | } |
| 1167 | 79aceca5 | bellard | |
| 1168 | 79aceca5 | bellard | /* shift right algebraic word */
|
| 1169 | 79aceca5 | bellard | PPC_OP(sraw) |
| 1170 | 79aceca5 | bellard | {
|
| 1171 | 9a64fbe4 | bellard | do_sraw(); |
| 1172 | 79aceca5 | bellard | RETURN(); |
| 1173 | 79aceca5 | bellard | } |
| 1174 | 79aceca5 | bellard | |
| 1175 | 79aceca5 | bellard | /* shift right algebraic word immediate */
|
| 1176 | 79aceca5 | bellard | PPC_OP(srawi) |
| 1177 | 79aceca5 | bellard | {
|
| 1178 | 3cc62370 | bellard | T1 = T0; |
| 1179 | 3cc62370 | bellard | T0 = (Ts0 >> PARAM(1));
|
| 1180 | 79aceca5 | bellard | if (Ts1 < 0 && (Ts1 & PARAM(2)) != 0) { |
| 1181 | 79aceca5 | bellard | xer_ca = 1;
|
| 1182 | 79aceca5 | bellard | } else {
|
| 1183 | 79aceca5 | bellard | xer_ca = 0;
|
| 1184 | 79aceca5 | bellard | } |
| 1185 | 79aceca5 | bellard | RETURN(); |
| 1186 | 79aceca5 | bellard | } |
| 1187 | 79aceca5 | bellard | |
| 1188 | 79aceca5 | bellard | /* shift right word */
|
| 1189 | 79aceca5 | bellard | PPC_OP(srw) |
| 1190 | 79aceca5 | bellard | {
|
| 1191 | 79aceca5 | bellard | if (T1 & 0x20) { |
| 1192 | 79aceca5 | bellard | T0 = 0;
|
| 1193 | 79aceca5 | bellard | } else {
|
| 1194 | 79aceca5 | bellard | T0 = T0 >> T1; |
| 1195 | 79aceca5 | bellard | } |
| 1196 | 79aceca5 | bellard | RETURN(); |
| 1197 | 79aceca5 | bellard | } |
| 1198 | 79aceca5 | bellard | |
| 1199 | 79aceca5 | bellard | /*** Floating-Point arithmetic ***/
|
| 1200 | 9a64fbe4 | bellard | /* fadd - fadd. */
|
| 1201 | 9a64fbe4 | bellard | PPC_OP(fadd) |
| 1202 | 79aceca5 | bellard | {
|
| 1203 | 9a64fbe4 | bellard | FT0 += FT1; |
| 1204 | 79aceca5 | bellard | RETURN(); |
| 1205 | 79aceca5 | bellard | } |
| 1206 | 79aceca5 | bellard | |
| 1207 | 9a64fbe4 | bellard | /* fadds - fadds. */
|
| 1208 | 9a64fbe4 | bellard | PPC_OP(fadds) |
| 1209 | 79aceca5 | bellard | {
|
| 1210 | 3cc62370 | bellard | FT0 = FTS0 + FTS1; |
| 1211 | 79aceca5 | bellard | RETURN(); |
| 1212 | 79aceca5 | bellard | } |
| 1213 | 79aceca5 | bellard | |
| 1214 | 9a64fbe4 | bellard | /* fsub - fsub. */
|
| 1215 | 9a64fbe4 | bellard | PPC_OP(fsub) |
| 1216 | 79aceca5 | bellard | {
|
| 1217 | 9a64fbe4 | bellard | FT0 -= FT1; |
| 1218 | 79aceca5 | bellard | RETURN(); |
| 1219 | 79aceca5 | bellard | } |
| 1220 | 79aceca5 | bellard | |
| 1221 | 9a64fbe4 | bellard | /* fsubs - fsubs. */
|
| 1222 | 9a64fbe4 | bellard | PPC_OP(fsubs) |
| 1223 | 79aceca5 | bellard | {
|
| 1224 | 3cc62370 | bellard | FT0 = FTS0 - FTS1; |
| 1225 | 79aceca5 | bellard | RETURN(); |
| 1226 | 79aceca5 | bellard | } |
| 1227 | 79aceca5 | bellard | |
| 1228 | 9a64fbe4 | bellard | /* fmul - fmul. */
|
| 1229 | 9a64fbe4 | bellard | PPC_OP(fmul) |
| 1230 | 79aceca5 | bellard | {
|
| 1231 | 9a64fbe4 | bellard | FT0 *= FT1; |
| 1232 | 79aceca5 | bellard | RETURN(); |
| 1233 | 79aceca5 | bellard | } |
| 1234 | 79aceca5 | bellard | |
| 1235 | 9a64fbe4 | bellard | /* fmuls - fmuls. */
|
| 1236 | 9a64fbe4 | bellard | PPC_OP(fmuls) |
| 1237 | 79aceca5 | bellard | {
|
| 1238 | 3cc62370 | bellard | FT0 = FTS0 * FTS1; |
| 1239 | 79aceca5 | bellard | RETURN(); |
| 1240 | 79aceca5 | bellard | } |
| 1241 | 79aceca5 | bellard | |
| 1242 | 9a64fbe4 | bellard | /* fdiv - fdiv. */
|
| 1243 | 9a64fbe4 | bellard | PPC_OP(fdiv) |
| 1244 | 79aceca5 | bellard | {
|
| 1245 | 9a64fbe4 | bellard | FT0 /= FT1; |
| 1246 | 79aceca5 | bellard | RETURN(); |
| 1247 | 79aceca5 | bellard | } |
| 1248 | 79aceca5 | bellard | |
| 1249 | 9a64fbe4 | bellard | /* fdivs - fdivs. */
|
| 1250 | 9a64fbe4 | bellard | PPC_OP(fdivs) |
| 1251 | 79aceca5 | bellard | {
|
| 1252 | 3cc62370 | bellard | FT0 = FTS0 / FTS1; |
| 1253 | 79aceca5 | bellard | RETURN(); |
| 1254 | 79aceca5 | bellard | } |
| 1255 | 28b6751f | bellard | |
| 1256 | 9a64fbe4 | bellard | /* fsqrt - fsqrt. */
|
| 1257 | 9a64fbe4 | bellard | PPC_OP(fsqrt) |
| 1258 | 28b6751f | bellard | {
|
| 1259 | 9a64fbe4 | bellard | do_fsqrt(); |
| 1260 | 9a64fbe4 | bellard | RETURN(); |
| 1261 | 28b6751f | bellard | } |
| 1262 | 28b6751f | bellard | |
| 1263 | 9a64fbe4 | bellard | /* fsqrts - fsqrts. */
|
| 1264 | 9a64fbe4 | bellard | PPC_OP(fsqrts) |
| 1265 | 28b6751f | bellard | {
|
| 1266 | 9a64fbe4 | bellard | do_fsqrts(); |
| 1267 | 9a64fbe4 | bellard | RETURN(); |
| 1268 | 28b6751f | bellard | } |
| 1269 | 28b6751f | bellard | |
| 1270 | 9a64fbe4 | bellard | /* fres - fres. */
|
| 1271 | 9a64fbe4 | bellard | PPC_OP(fres) |
| 1272 | 28b6751f | bellard | {
|
| 1273 | 9a64fbe4 | bellard | do_fres(); |
| 1274 | 9a64fbe4 | bellard | RETURN(); |
| 1275 | 28b6751f | bellard | } |
| 1276 | 28b6751f | bellard | |
| 1277 | 9a64fbe4 | bellard | /* frsqrte - frsqrte. */
|
| 1278 | 9a64fbe4 | bellard | PPC_OP(frsqrte) |
| 1279 | 28b6751f | bellard | {
|
| 1280 | 9a64fbe4 | bellard | do_fsqrte(); |
| 1281 | 9a64fbe4 | bellard | RETURN(); |
| 1282 | 28b6751f | bellard | } |
| 1283 | 28b6751f | bellard | |
| 1284 | 9a64fbe4 | bellard | /* fsel - fsel. */
|
| 1285 | 9a64fbe4 | bellard | PPC_OP(fsel) |
| 1286 | 28b6751f | bellard | {
|
| 1287 | 9a64fbe4 | bellard | do_fsel(); |
| 1288 | 9a64fbe4 | bellard | RETURN(); |
| 1289 | 28b6751f | bellard | } |
| 1290 | 28b6751f | bellard | |
| 1291 | 9a64fbe4 | bellard | /*** Floating-Point multiply-and-add ***/
|
| 1292 | 9a64fbe4 | bellard | /* fmadd - fmadd. */
|
| 1293 | 9a64fbe4 | bellard | PPC_OP(fmadd) |
| 1294 | 28b6751f | bellard | {
|
| 1295 | 9a64fbe4 | bellard | FT0 = (FT0 * FT1) + FT2; |
| 1296 | 9a64fbe4 | bellard | RETURN(); |
| 1297 | 28b6751f | bellard | } |
| 1298 | 28b6751f | bellard | |
| 1299 | 9a64fbe4 | bellard | /* fmadds - fmadds. */
|
| 1300 | 9a64fbe4 | bellard | PPC_OP(fmadds) |
| 1301 | 28b6751f | bellard | {
|
| 1302 | 3cc62370 | bellard | FT0 = (FTS0 * FTS1) + FTS2; |
| 1303 | 9a64fbe4 | bellard | RETURN(); |
| 1304 | 28b6751f | bellard | } |
| 1305 | 28b6751f | bellard | |
| 1306 | 9a64fbe4 | bellard | /* fmsub - fmsub. */
|
| 1307 | 9a64fbe4 | bellard | PPC_OP(fmsub) |
| 1308 | 28b6751f | bellard | {
|
| 1309 | 9a64fbe4 | bellard | FT0 = (FT0 * FT1) - FT2; |
| 1310 | 9a64fbe4 | bellard | RETURN(); |
| 1311 | 28b6751f | bellard | } |
| 1312 | 28b6751f | bellard | |
| 1313 | 9a64fbe4 | bellard | /* fmsubs - fmsubs. */
|
| 1314 | 9a64fbe4 | bellard | PPC_OP(fmsubs) |
| 1315 | 28b6751f | bellard | {
|
| 1316 | 3cc62370 | bellard | FT0 = (FTS0 * FTS1) - FTS2; |
| 1317 | 9a64fbe4 | bellard | RETURN(); |
| 1318 | 28b6751f | bellard | } |
| 1319 | 28b6751f | bellard | |
| 1320 | 9a64fbe4 | bellard | /* fnmadd - fnmadd. - fnmadds - fnmadds. */
|
| 1321 | 9a64fbe4 | bellard | PPC_OP(fnmadd) |
| 1322 | 28b6751f | bellard | {
|
| 1323 | 4b3686fa | bellard | do_fnmadd(); |
| 1324 | 9a64fbe4 | bellard | RETURN(); |
| 1325 | 28b6751f | bellard | } |
| 1326 | 28b6751f | bellard | |
| 1327 | 9a64fbe4 | bellard | /* fnmadds - fnmadds. */
|
| 1328 | 9a64fbe4 | bellard | PPC_OP(fnmadds) |
| 1329 | 28b6751f | bellard | {
|
| 1330 | 1ef59d0a | bellard | do_fnmadds(); |
| 1331 | 9a64fbe4 | bellard | RETURN(); |
| 1332 | 28b6751f | bellard | } |
| 1333 | 28b6751f | bellard | |
| 1334 | 9a64fbe4 | bellard | /* fnmsub - fnmsub. */
|
| 1335 | 9a64fbe4 | bellard | PPC_OP(fnmsub) |
| 1336 | 28b6751f | bellard | {
|
| 1337 | 4b3686fa | bellard | do_fnmsub(); |
| 1338 | 9a64fbe4 | bellard | RETURN(); |
| 1339 | 28b6751f | bellard | } |
| 1340 | 28b6751f | bellard | |
| 1341 | 9a64fbe4 | bellard | /* fnmsubs - fnmsubs. */
|
| 1342 | 9a64fbe4 | bellard | PPC_OP(fnmsubs) |
| 1343 | 28b6751f | bellard | {
|
| 1344 | 1ef59d0a | bellard | do_fnmsubs(); |
| 1345 | 9a64fbe4 | bellard | RETURN(); |
| 1346 | 28b6751f | bellard | } |
| 1347 | 28b6751f | bellard | |
| 1348 | 9a64fbe4 | bellard | /*** Floating-Point round & convert ***/
|
| 1349 | 9a64fbe4 | bellard | /* frsp - frsp. */
|
| 1350 | 9a64fbe4 | bellard | PPC_OP(frsp) |
| 1351 | 28b6751f | bellard | {
|
| 1352 | 3cc62370 | bellard | FT0 = (float)FT0;
|
| 1353 | 9a64fbe4 | bellard | RETURN(); |
| 1354 | 28b6751f | bellard | } |
| 1355 | 28b6751f | bellard | |
| 1356 | 9a64fbe4 | bellard | /* fctiw - fctiw. */
|
| 1357 | 9a64fbe4 | bellard | PPC_OP(fctiw) |
| 1358 | 28b6751f | bellard | {
|
| 1359 | 9a64fbe4 | bellard | do_fctiw(); |
| 1360 | 9a64fbe4 | bellard | RETURN(); |
| 1361 | 28b6751f | bellard | } |
| 1362 | 28b6751f | bellard | |
| 1363 | 9a64fbe4 | bellard | /* fctiwz - fctiwz. */
|
| 1364 | 9a64fbe4 | bellard | PPC_OP(fctiwz) |
| 1365 | 28b6751f | bellard | {
|
| 1366 | 9a64fbe4 | bellard | do_fctiwz(); |
| 1367 | 9a64fbe4 | bellard | RETURN(); |
| 1368 | 28b6751f | bellard | } |
| 1369 | 28b6751f | bellard | |
| 1370 | 9a64fbe4 | bellard | |
| 1371 | 9a64fbe4 | bellard | /*** Floating-Point compare ***/
|
| 1372 | 9a64fbe4 | bellard | /* fcmpu */
|
| 1373 | 9a64fbe4 | bellard | PPC_OP(fcmpu) |
| 1374 | 28b6751f | bellard | {
|
| 1375 | 9a64fbe4 | bellard | do_fcmpu(); |
| 1376 | 9a64fbe4 | bellard | RETURN(); |
| 1377 | 28b6751f | bellard | } |
| 1378 | 28b6751f | bellard | |
| 1379 | 9a64fbe4 | bellard | /* fcmpo */
|
| 1380 | 9a64fbe4 | bellard | PPC_OP(fcmpo) |
| 1381 | 28b6751f | bellard | {
|
| 1382 | 9a64fbe4 | bellard | do_fcmpo(); |
| 1383 | 9a64fbe4 | bellard | RETURN(); |
| 1384 | fb0eaffc | bellard | } |
| 1385 | fb0eaffc | bellard | |
| 1386 | 9a64fbe4 | bellard | /*** Floating-point move ***/
|
| 1387 | 9a64fbe4 | bellard | /* fabs */
|
| 1388 | 9a64fbe4 | bellard | PPC_OP(fabs) |
| 1389 | fb0eaffc | bellard | {
|
| 1390 | 9a64fbe4 | bellard | do_fabs(); |
| 1391 | fb0eaffc | bellard | RETURN(); |
| 1392 | fb0eaffc | bellard | } |
| 1393 | fb0eaffc | bellard | |
| 1394 | 9a64fbe4 | bellard | /* fnabs */
|
| 1395 | 9a64fbe4 | bellard | PPC_OP(fnabs) |
| 1396 | fb0eaffc | bellard | {
|
| 1397 | 9a64fbe4 | bellard | do_fnabs(); |
| 1398 | fb0eaffc | bellard | RETURN(); |
| 1399 | fb0eaffc | bellard | } |
| 1400 | fb0eaffc | bellard | |
| 1401 | 9a64fbe4 | bellard | /* fneg */
|
| 1402 | 9a64fbe4 | bellard | PPC_OP(fneg) |
| 1403 | fb0eaffc | bellard | {
|
| 1404 | 9a64fbe4 | bellard | FT0 = -FT0; |
| 1405 | fb0eaffc | bellard | RETURN(); |
| 1406 | fb0eaffc | bellard | } |
| 1407 | fb0eaffc | bellard | |
| 1408 | 9a64fbe4 | bellard | /* Load and store */
|
| 1409 | 9a64fbe4 | bellard | #define MEMSUFFIX _raw
|
| 1410 | 9a64fbe4 | bellard | #include "op_mem.h" |
| 1411 | a541f297 | bellard | #if !defined(CONFIG_USER_ONLY)
|
| 1412 | 9a64fbe4 | bellard | #define MEMSUFFIX _user
|
| 1413 | 9a64fbe4 | bellard | #include "op_mem.h" |
| 1414 | 9a64fbe4 | bellard | |
| 1415 | 9a64fbe4 | bellard | #define MEMSUFFIX _kernel
|
| 1416 | 9a64fbe4 | bellard | #include "op_mem.h" |
| 1417 | 9a64fbe4 | bellard | #endif
|
| 1418 | 9a64fbe4 | bellard | |
| 1419 | 4b3686fa | bellard | /* Special op to check and maybe clear reservation */
|
| 1420 | 4b3686fa | bellard | PPC_OP(check_reservation) |
| 1421 | 4b3686fa | bellard | {
|
| 1422 | 4b3686fa | bellard | do_check_reservation(); |
| 1423 | 4b3686fa | bellard | RETURN(); |
| 1424 | 4b3686fa | bellard | } |
| 1425 | 4b3686fa | bellard | |
| 1426 | 9a64fbe4 | bellard | /* Return from interrupt */
|
| 1427 | 9a64fbe4 | bellard | PPC_OP(rfi) |
| 1428 | fb0eaffc | bellard | {
|
| 1429 | 9fddaa0c | bellard | regs->nip = regs->spr[SRR0] & ~0x00000003;
|
| 1430 | 4b3686fa | bellard | #if 1 // TRY |
| 1431 | 4b3686fa | bellard | T0 = regs->spr[SRR1] & ~0xFFF00000;
|
| 1432 | 4b3686fa | bellard | #else
|
| 1433 | 9a64fbe4 | bellard | T0 = regs->spr[SRR1] & ~0xFFFF0000;
|
| 1434 | 4b3686fa | bellard | #endif
|
| 1435 | 9a64fbe4 | bellard | do_store_msr(); |
| 1436 | a541f297 | bellard | #if defined (DEBUG_OP)
|
| 1437 | 9a64fbe4 | bellard | dump_rfi(); |
| 1438 | a541f297 | bellard | #endif
|
| 1439 | 9fddaa0c | bellard | // do_tlbia();
|
| 1440 | 9fddaa0c | bellard | do_raise_exception(EXCP_RFI); |
| 1441 | fb0eaffc | bellard | RETURN(); |
| 1442 | fb0eaffc | bellard | } |
| 1443 | fb0eaffc | bellard | |
| 1444 | 9a64fbe4 | bellard | /* Trap word */
|
| 1445 | 9a64fbe4 | bellard | PPC_OP(tw) |
| 1446 | fb0eaffc | bellard | {
|
| 1447 | 9a64fbe4 | bellard | if ((Ts0 < Ts1 && (PARAM(1) & 0x10)) || |
| 1448 | 9a64fbe4 | bellard | (Ts0 > Ts1 && (PARAM(1) & 0x08)) || |
| 1449 | 9a64fbe4 | bellard | (Ts0 == Ts1 && (PARAM(1) & 0x04)) || |
| 1450 | 9a64fbe4 | bellard | (T0 < T1 && (PARAM(1) & 0x02)) || |
| 1451 | 9a64fbe4 | bellard | (T0 > T1 && (PARAM(1) & 0x01))) |
| 1452 | 9fddaa0c | bellard | do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP); |
| 1453 | fb0eaffc | bellard | RETURN(); |
| 1454 | fb0eaffc | bellard | } |
| 1455 | fb0eaffc | bellard | |
| 1456 | 9a64fbe4 | bellard | PPC_OP(twi) |
| 1457 | fb0eaffc | bellard | {
|
| 1458 | 9a64fbe4 | bellard | if ((Ts0 < SPARAM(1) && (PARAM(2) & 0x10)) || |
| 1459 | 9a64fbe4 | bellard | (Ts0 > SPARAM(1) && (PARAM(2) & 0x08)) || |
| 1460 | 9a64fbe4 | bellard | (Ts0 == SPARAM(1) && (PARAM(2) & 0x04)) || |
| 1461 | 9a64fbe4 | bellard | (T0 < (uint32_t)SPARAM(1) && (PARAM(2) & 0x02)) || |
| 1462 | 9a64fbe4 | bellard | (T0 > (uint32_t)SPARAM(1) && (PARAM(2) & 0x01))) |
| 1463 | 9fddaa0c | bellard | do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP); |
| 1464 | fb0eaffc | bellard | RETURN(); |
| 1465 | fb0eaffc | bellard | } |
| 1466 | fb0eaffc | bellard | |
| 1467 | fb0eaffc | bellard | /* Instruction cache block invalidate */
|
| 1468 | 9a64fbe4 | bellard | PPC_OP(icbi) |
| 1469 | fb0eaffc | bellard | {
|
| 1470 | fb0eaffc | bellard | do_icbi(); |
| 1471 | fb0eaffc | bellard | RETURN(); |
| 1472 | fb0eaffc | bellard | } |
| 1473 | fb0eaffc | bellard | |
| 1474 | 9a64fbe4 | bellard | /* tlbia */
|
| 1475 | 9a64fbe4 | bellard | PPC_OP(tlbia) |
| 1476 | fb0eaffc | bellard | {
|
| 1477 | 9a64fbe4 | bellard | do_tlbia(); |
| 1478 | 9a64fbe4 | bellard | RETURN(); |
| 1479 | 9a64fbe4 | bellard | } |
| 1480 | 9a64fbe4 | bellard | |
| 1481 | 9a64fbe4 | bellard | /* tlbie */
|
| 1482 | 9a64fbe4 | bellard | PPC_OP(tlbie) |
| 1483 | 9a64fbe4 | bellard | {
|
| 1484 | 9a64fbe4 | bellard | do_tlbie(); |
| 1485 | fb0eaffc | bellard | RETURN(); |
| 1486 | 28b6751f | bellard | } |