root / hw / m48t59.c @ 1d849502
History | View | Annotate | Download (20 kB)
| 1 |
/*
|
|---|---|
| 2 |
* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
|
| 3 |
*
|
| 4 |
* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
|
| 5 |
*
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal
|
| 8 |
* in the Software without restriction, including without limitation the rights
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is
|
| 11 |
* furnished to do so, subject to the following conditions:
|
| 12 |
*
|
| 13 |
* The above copyright notice and this permission notice shall be included in
|
| 14 |
* all copies or substantial portions of the Software.
|
| 15 |
*
|
| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
| 22 |
* THE SOFTWARE.
|
| 23 |
*/
|
| 24 |
#include "hw.h" |
| 25 |
#include "nvram.h" |
| 26 |
#include "qemu-timer.h" |
| 27 |
#include "sysemu.h" |
| 28 |
#include "sysbus.h" |
| 29 |
#include "isa.h" |
| 30 |
|
| 31 |
//#define DEBUG_NVRAM
|
| 32 |
|
| 33 |
#if defined(DEBUG_NVRAM)
|
| 34 |
#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
| 35 |
#else
|
| 36 |
#define NVRAM_PRINTF(fmt, ...) do { } while (0) |
| 37 |
#endif
|
| 38 |
|
| 39 |
/*
|
| 40 |
* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
|
| 41 |
* alarm and a watchdog timer and related control registers. In the
|
| 42 |
* PPC platform there is also a nvram lock function.
|
| 43 |
*/
|
| 44 |
|
| 45 |
/*
|
| 46 |
* Chipset docs:
|
| 47 |
* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
|
| 48 |
* http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
|
| 49 |
* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
|
| 50 |
*/
|
| 51 |
|
| 52 |
struct M48t59State {
|
| 53 |
/* Hardware parameters */
|
| 54 |
qemu_irq IRQ; |
| 55 |
MemoryRegion iomem; |
| 56 |
uint32_t io_base; |
| 57 |
uint32_t size; |
| 58 |
/* RTC management */
|
| 59 |
time_t time_offset; |
| 60 |
time_t stop_time; |
| 61 |
/* Alarm & watchdog */
|
| 62 |
struct tm alarm;
|
| 63 |
struct QEMUTimer *alrm_timer;
|
| 64 |
struct QEMUTimer *wd_timer;
|
| 65 |
/* NVRAM storage */
|
| 66 |
uint8_t *buffer; |
| 67 |
/* Model parameters */
|
| 68 |
uint32_t type; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
|
| 69 |
/* NVRAM storage */
|
| 70 |
uint16_t addr; |
| 71 |
uint8_t lock; |
| 72 |
}; |
| 73 |
|
| 74 |
typedef struct M48t59ISAState { |
| 75 |
ISADevice busdev; |
| 76 |
M48t59State state; |
| 77 |
MemoryRegion io; |
| 78 |
} M48t59ISAState; |
| 79 |
|
| 80 |
typedef struct M48t59SysBusState { |
| 81 |
SysBusDevice busdev; |
| 82 |
M48t59State state; |
| 83 |
} M48t59SysBusState; |
| 84 |
|
| 85 |
/* Fake timer functions */
|
| 86 |
|
| 87 |
/* Alarm management */
|
| 88 |
static void alarm_cb (void *opaque) |
| 89 |
{
|
| 90 |
struct tm tm;
|
| 91 |
uint64_t next_time; |
| 92 |
M48t59State *NVRAM = opaque; |
| 93 |
|
| 94 |
qemu_set_irq(NVRAM->IRQ, 1);
|
| 95 |
if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
| 96 |
(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
| 97 |
(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
| 98 |
(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
| 99 |
/* Repeat once a month */
|
| 100 |
qemu_get_timedate(&tm, NVRAM->time_offset); |
| 101 |
tm.tm_mon++; |
| 102 |
if (tm.tm_mon == 13) { |
| 103 |
tm.tm_mon = 1;
|
| 104 |
tm.tm_year++; |
| 105 |
} |
| 106 |
next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; |
| 107 |
} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
| 108 |
(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
| 109 |
(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
| 110 |
(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
| 111 |
/* Repeat once a day */
|
| 112 |
next_time = 24 * 60 * 60; |
| 113 |
} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
| 114 |
(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
| 115 |
(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
| 116 |
(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
| 117 |
/* Repeat once an hour */
|
| 118 |
next_time = 60 * 60; |
| 119 |
} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
| 120 |
(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
| 121 |
(NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
| 122 |
(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
| 123 |
/* Repeat once a minute */
|
| 124 |
next_time = 60;
|
| 125 |
} else {
|
| 126 |
/* Repeat once a second */
|
| 127 |
next_time = 1;
|
| 128 |
} |
| 129 |
qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) + |
| 130 |
next_time * 1000);
|
| 131 |
qemu_set_irq(NVRAM->IRQ, 0);
|
| 132 |
} |
| 133 |
|
| 134 |
static void set_alarm(M48t59State *NVRAM) |
| 135 |
{
|
| 136 |
int diff;
|
| 137 |
if (NVRAM->alrm_timer != NULL) { |
| 138 |
qemu_del_timer(NVRAM->alrm_timer); |
| 139 |
diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
| 140 |
if (diff > 0) |
| 141 |
qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
|
| 142 |
} |
| 143 |
} |
| 144 |
|
| 145 |
/* RTC management helpers */
|
| 146 |
static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
| 147 |
{
|
| 148 |
qemu_get_timedate(tm, NVRAM->time_offset); |
| 149 |
} |
| 150 |
|
| 151 |
static void set_time(M48t59State *NVRAM, struct tm *tm) |
| 152 |
{
|
| 153 |
NVRAM->time_offset = qemu_timedate_diff(tm); |
| 154 |
set_alarm(NVRAM); |
| 155 |
} |
| 156 |
|
| 157 |
/* Watchdog management */
|
| 158 |
static void watchdog_cb (void *opaque) |
| 159 |
{
|
| 160 |
M48t59State *NVRAM = opaque; |
| 161 |
|
| 162 |
NVRAM->buffer[0x1FF0] |= 0x80; |
| 163 |
if (NVRAM->buffer[0x1FF7] & 0x80) { |
| 164 |
NVRAM->buffer[0x1FF7] = 0x00; |
| 165 |
NVRAM->buffer[0x1FFC] &= ~0x40; |
| 166 |
/* May it be a hw CPU Reset instead ? */
|
| 167 |
qemu_system_reset_request(); |
| 168 |
} else {
|
| 169 |
qemu_set_irq(NVRAM->IRQ, 1);
|
| 170 |
qemu_set_irq(NVRAM->IRQ, 0);
|
| 171 |
} |
| 172 |
} |
| 173 |
|
| 174 |
static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
| 175 |
{
|
| 176 |
uint64_t interval; /* in 1/16 seconds */
|
| 177 |
|
| 178 |
NVRAM->buffer[0x1FF0] &= ~0x80; |
| 179 |
if (NVRAM->wd_timer != NULL) { |
| 180 |
qemu_del_timer(NVRAM->wd_timer); |
| 181 |
if (value != 0) { |
| 182 |
interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
| 183 |
qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
| 184 |
((interval * 1000) >> 4)); |
| 185 |
} |
| 186 |
} |
| 187 |
} |
| 188 |
|
| 189 |
/* Direct access to NVRAM */
|
| 190 |
void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
| 191 |
{
|
| 192 |
M48t59State *NVRAM = opaque; |
| 193 |
struct tm tm;
|
| 194 |
int tmp;
|
| 195 |
|
| 196 |
if (addr > 0x1FF8 && addr < 0x2000) |
| 197 |
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
| 198 |
|
| 199 |
/* check for NVRAM access */
|
| 200 |
if ((NVRAM->type == 2 && addr < 0x7f8) || |
| 201 |
(NVRAM->type == 8 && addr < 0x1ff8) || |
| 202 |
(NVRAM->type == 59 && addr < 0x1ff0)) |
| 203 |
goto do_write;
|
| 204 |
|
| 205 |
/* TOD access */
|
| 206 |
switch (addr) {
|
| 207 |
case 0x1FF0: |
| 208 |
/* flags register : read-only */
|
| 209 |
break;
|
| 210 |
case 0x1FF1: |
| 211 |
/* unused */
|
| 212 |
break;
|
| 213 |
case 0x1FF2: |
| 214 |
/* alarm seconds */
|
| 215 |
tmp = from_bcd(val & 0x7F);
|
| 216 |
if (tmp >= 0 && tmp <= 59) { |
| 217 |
NVRAM->alarm.tm_sec = tmp; |
| 218 |
NVRAM->buffer[0x1FF2] = val;
|
| 219 |
set_alarm(NVRAM); |
| 220 |
} |
| 221 |
break;
|
| 222 |
case 0x1FF3: |
| 223 |
/* alarm minutes */
|
| 224 |
tmp = from_bcd(val & 0x7F);
|
| 225 |
if (tmp >= 0 && tmp <= 59) { |
| 226 |
NVRAM->alarm.tm_min = tmp; |
| 227 |
NVRAM->buffer[0x1FF3] = val;
|
| 228 |
set_alarm(NVRAM); |
| 229 |
} |
| 230 |
break;
|
| 231 |
case 0x1FF4: |
| 232 |
/* alarm hours */
|
| 233 |
tmp = from_bcd(val & 0x3F);
|
| 234 |
if (tmp >= 0 && tmp <= 23) { |
| 235 |
NVRAM->alarm.tm_hour = tmp; |
| 236 |
NVRAM->buffer[0x1FF4] = val;
|
| 237 |
set_alarm(NVRAM); |
| 238 |
} |
| 239 |
break;
|
| 240 |
case 0x1FF5: |
| 241 |
/* alarm date */
|
| 242 |
tmp = from_bcd(val & 0x1F);
|
| 243 |
if (tmp != 0) { |
| 244 |
NVRAM->alarm.tm_mday = tmp; |
| 245 |
NVRAM->buffer[0x1FF5] = val;
|
| 246 |
set_alarm(NVRAM); |
| 247 |
} |
| 248 |
break;
|
| 249 |
case 0x1FF6: |
| 250 |
/* interrupts */
|
| 251 |
NVRAM->buffer[0x1FF6] = val;
|
| 252 |
break;
|
| 253 |
case 0x1FF7: |
| 254 |
/* watchdog */
|
| 255 |
NVRAM->buffer[0x1FF7] = val;
|
| 256 |
set_up_watchdog(NVRAM, val); |
| 257 |
break;
|
| 258 |
case 0x1FF8: |
| 259 |
case 0x07F8: |
| 260 |
/* control */
|
| 261 |
NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
| 262 |
break;
|
| 263 |
case 0x1FF9: |
| 264 |
case 0x07F9: |
| 265 |
/* seconds (BCD) */
|
| 266 |
tmp = from_bcd(val & 0x7F);
|
| 267 |
if (tmp >= 0 && tmp <= 59) { |
| 268 |
get_time(NVRAM, &tm); |
| 269 |
tm.tm_sec = tmp; |
| 270 |
set_time(NVRAM, &tm); |
| 271 |
} |
| 272 |
if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
| 273 |
if (val & 0x80) { |
| 274 |
NVRAM->stop_time = time(NULL);
|
| 275 |
} else {
|
| 276 |
NVRAM->time_offset += NVRAM->stop_time - time(NULL);
|
| 277 |
NVRAM->stop_time = 0;
|
| 278 |
} |
| 279 |
} |
| 280 |
NVRAM->buffer[addr] = val & 0x80;
|
| 281 |
break;
|
| 282 |
case 0x1FFA: |
| 283 |
case 0x07FA: |
| 284 |
/* minutes (BCD) */
|
| 285 |
tmp = from_bcd(val & 0x7F);
|
| 286 |
if (tmp >= 0 && tmp <= 59) { |
| 287 |
get_time(NVRAM, &tm); |
| 288 |
tm.tm_min = tmp; |
| 289 |
set_time(NVRAM, &tm); |
| 290 |
} |
| 291 |
break;
|
| 292 |
case 0x1FFB: |
| 293 |
case 0x07FB: |
| 294 |
/* hours (BCD) */
|
| 295 |
tmp = from_bcd(val & 0x3F);
|
| 296 |
if (tmp >= 0 && tmp <= 23) { |
| 297 |
get_time(NVRAM, &tm); |
| 298 |
tm.tm_hour = tmp; |
| 299 |
set_time(NVRAM, &tm); |
| 300 |
} |
| 301 |
break;
|
| 302 |
case 0x1FFC: |
| 303 |
case 0x07FC: |
| 304 |
/* day of the week / century */
|
| 305 |
tmp = from_bcd(val & 0x07);
|
| 306 |
get_time(NVRAM, &tm); |
| 307 |
tm.tm_wday = tmp; |
| 308 |
set_time(NVRAM, &tm); |
| 309 |
NVRAM->buffer[addr] = val & 0x40;
|
| 310 |
break;
|
| 311 |
case 0x1FFD: |
| 312 |
case 0x07FD: |
| 313 |
/* date */
|
| 314 |
tmp = from_bcd(val & 0x1F);
|
| 315 |
if (tmp != 0) { |
| 316 |
get_time(NVRAM, &tm); |
| 317 |
tm.tm_mday = tmp; |
| 318 |
set_time(NVRAM, &tm); |
| 319 |
} |
| 320 |
break;
|
| 321 |
case 0x1FFE: |
| 322 |
case 0x07FE: |
| 323 |
/* month */
|
| 324 |
tmp = from_bcd(val & 0x1F);
|
| 325 |
if (tmp >= 1 && tmp <= 12) { |
| 326 |
get_time(NVRAM, &tm); |
| 327 |
tm.tm_mon = tmp - 1;
|
| 328 |
set_time(NVRAM, &tm); |
| 329 |
} |
| 330 |
break;
|
| 331 |
case 0x1FFF: |
| 332 |
case 0x07FF: |
| 333 |
/* year */
|
| 334 |
tmp = from_bcd(val); |
| 335 |
if (tmp >= 0 && tmp <= 99) { |
| 336 |
get_time(NVRAM, &tm); |
| 337 |
if (NVRAM->type == 8) |
| 338 |
tm.tm_year = from_bcd(val) + 68; // Base year is 1968 |
| 339 |
else
|
| 340 |
tm.tm_year = from_bcd(val); |
| 341 |
set_time(NVRAM, &tm); |
| 342 |
} |
| 343 |
break;
|
| 344 |
default:
|
| 345 |
/* Check lock registers state */
|
| 346 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
| 347 |
break;
|
| 348 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
| 349 |
break;
|
| 350 |
do_write:
|
| 351 |
if (addr < NVRAM->size) {
|
| 352 |
NVRAM->buffer[addr] = val & 0xFF;
|
| 353 |
} |
| 354 |
break;
|
| 355 |
} |
| 356 |
} |
| 357 |
|
| 358 |
uint32_t m48t59_read (void *opaque, uint32_t addr)
|
| 359 |
{
|
| 360 |
M48t59State *NVRAM = opaque; |
| 361 |
struct tm tm;
|
| 362 |
uint32_t retval = 0xFF;
|
| 363 |
|
| 364 |
/* check for NVRAM access */
|
| 365 |
if ((NVRAM->type == 2 && addr < 0x078f) || |
| 366 |
(NVRAM->type == 8 && addr < 0x1ff8) || |
| 367 |
(NVRAM->type == 59 && addr < 0x1ff0)) |
| 368 |
goto do_read;
|
| 369 |
|
| 370 |
/* TOD access */
|
| 371 |
switch (addr) {
|
| 372 |
case 0x1FF0: |
| 373 |
/* flags register */
|
| 374 |
goto do_read;
|
| 375 |
case 0x1FF1: |
| 376 |
/* unused */
|
| 377 |
retval = 0;
|
| 378 |
break;
|
| 379 |
case 0x1FF2: |
| 380 |
/* alarm seconds */
|
| 381 |
goto do_read;
|
| 382 |
case 0x1FF3: |
| 383 |
/* alarm minutes */
|
| 384 |
goto do_read;
|
| 385 |
case 0x1FF4: |
| 386 |
/* alarm hours */
|
| 387 |
goto do_read;
|
| 388 |
case 0x1FF5: |
| 389 |
/* alarm date */
|
| 390 |
goto do_read;
|
| 391 |
case 0x1FF6: |
| 392 |
/* interrupts */
|
| 393 |
goto do_read;
|
| 394 |
case 0x1FF7: |
| 395 |
/* A read resets the watchdog */
|
| 396 |
set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
| 397 |
goto do_read;
|
| 398 |
case 0x1FF8: |
| 399 |
case 0x07F8: |
| 400 |
/* control */
|
| 401 |
goto do_read;
|
| 402 |
case 0x1FF9: |
| 403 |
case 0x07F9: |
| 404 |
/* seconds (BCD) */
|
| 405 |
get_time(NVRAM, &tm); |
| 406 |
retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
|
| 407 |
break;
|
| 408 |
case 0x1FFA: |
| 409 |
case 0x07FA: |
| 410 |
/* minutes (BCD) */
|
| 411 |
get_time(NVRAM, &tm); |
| 412 |
retval = to_bcd(tm.tm_min); |
| 413 |
break;
|
| 414 |
case 0x1FFB: |
| 415 |
case 0x07FB: |
| 416 |
/* hours (BCD) */
|
| 417 |
get_time(NVRAM, &tm); |
| 418 |
retval = to_bcd(tm.tm_hour); |
| 419 |
break;
|
| 420 |
case 0x1FFC: |
| 421 |
case 0x07FC: |
| 422 |
/* day of the week / century */
|
| 423 |
get_time(NVRAM, &tm); |
| 424 |
retval = NVRAM->buffer[addr] | tm.tm_wday; |
| 425 |
break;
|
| 426 |
case 0x1FFD: |
| 427 |
case 0x07FD: |
| 428 |
/* date */
|
| 429 |
get_time(NVRAM, &tm); |
| 430 |
retval = to_bcd(tm.tm_mday); |
| 431 |
break;
|
| 432 |
case 0x1FFE: |
| 433 |
case 0x07FE: |
| 434 |
/* month */
|
| 435 |
get_time(NVRAM, &tm); |
| 436 |
retval = to_bcd(tm.tm_mon + 1);
|
| 437 |
break;
|
| 438 |
case 0x1FFF: |
| 439 |
case 0x07FF: |
| 440 |
/* year */
|
| 441 |
get_time(NVRAM, &tm); |
| 442 |
if (NVRAM->type == 8) |
| 443 |
retval = to_bcd(tm.tm_year - 68); // Base year is 1968 |
| 444 |
else
|
| 445 |
retval = to_bcd(tm.tm_year); |
| 446 |
break;
|
| 447 |
default:
|
| 448 |
/* Check lock registers state */
|
| 449 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
| 450 |
break;
|
| 451 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
| 452 |
break;
|
| 453 |
do_read:
|
| 454 |
if (addr < NVRAM->size) {
|
| 455 |
retval = NVRAM->buffer[addr]; |
| 456 |
} |
| 457 |
break;
|
| 458 |
} |
| 459 |
if (addr > 0x1FF9 && addr < 0x2000) |
| 460 |
NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
| 461 |
|
| 462 |
return retval;
|
| 463 |
} |
| 464 |
|
| 465 |
void m48t59_set_addr (void *opaque, uint32_t addr) |
| 466 |
{
|
| 467 |
M48t59State *NVRAM = opaque; |
| 468 |
|
| 469 |
NVRAM->addr = addr; |
| 470 |
} |
| 471 |
|
| 472 |
void m48t59_toggle_lock (void *opaque, int lock) |
| 473 |
{
|
| 474 |
M48t59State *NVRAM = opaque; |
| 475 |
|
| 476 |
NVRAM->lock ^= 1 << lock;
|
| 477 |
} |
| 478 |
|
| 479 |
/* IO access to NVRAM */
|
| 480 |
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
| 481 |
{
|
| 482 |
M48t59State *NVRAM = opaque; |
| 483 |
|
| 484 |
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
| 485 |
switch (addr) {
|
| 486 |
case 0: |
| 487 |
NVRAM->addr &= ~0x00FF;
|
| 488 |
NVRAM->addr |= val; |
| 489 |
break;
|
| 490 |
case 1: |
| 491 |
NVRAM->addr &= ~0xFF00;
|
| 492 |
NVRAM->addr |= val << 8;
|
| 493 |
break;
|
| 494 |
case 3: |
| 495 |
m48t59_write(NVRAM, NVRAM->addr, val); |
| 496 |
NVRAM->addr = 0x0000;
|
| 497 |
break;
|
| 498 |
default:
|
| 499 |
break;
|
| 500 |
} |
| 501 |
} |
| 502 |
|
| 503 |
static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
| 504 |
{
|
| 505 |
M48t59State *NVRAM = opaque; |
| 506 |
uint32_t retval; |
| 507 |
|
| 508 |
switch (addr) {
|
| 509 |
case 3: |
| 510 |
retval = m48t59_read(NVRAM, NVRAM->addr); |
| 511 |
break;
|
| 512 |
default:
|
| 513 |
retval = -1;
|
| 514 |
break;
|
| 515 |
} |
| 516 |
NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
| 517 |
|
| 518 |
return retval;
|
| 519 |
} |
| 520 |
|
| 521 |
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 522 |
{
|
| 523 |
M48t59State *NVRAM = opaque; |
| 524 |
|
| 525 |
m48t59_write(NVRAM, addr, value & 0xff);
|
| 526 |
} |
| 527 |
|
| 528 |
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 529 |
{
|
| 530 |
M48t59State *NVRAM = opaque; |
| 531 |
|
| 532 |
m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
| 533 |
m48t59_write(NVRAM, addr + 1, value & 0xff); |
| 534 |
} |
| 535 |
|
| 536 |
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 537 |
{
|
| 538 |
M48t59State *NVRAM = opaque; |
| 539 |
|
| 540 |
m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
| 541 |
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
| 542 |
m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
| 543 |
m48t59_write(NVRAM, addr + 3, value & 0xff); |
| 544 |
} |
| 545 |
|
| 546 |
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
| 547 |
{
|
| 548 |
M48t59State *NVRAM = opaque; |
| 549 |
uint32_t retval; |
| 550 |
|
| 551 |
retval = m48t59_read(NVRAM, addr); |
| 552 |
return retval;
|
| 553 |
} |
| 554 |
|
| 555 |
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
| 556 |
{
|
| 557 |
M48t59State *NVRAM = opaque; |
| 558 |
uint32_t retval; |
| 559 |
|
| 560 |
retval = m48t59_read(NVRAM, addr) << 8;
|
| 561 |
retval |= m48t59_read(NVRAM, addr + 1);
|
| 562 |
return retval;
|
| 563 |
} |
| 564 |
|
| 565 |
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
| 566 |
{
|
| 567 |
M48t59State *NVRAM = opaque; |
| 568 |
uint32_t retval; |
| 569 |
|
| 570 |
retval = m48t59_read(NVRAM, addr) << 24;
|
| 571 |
retval |= m48t59_read(NVRAM, addr + 1) << 16; |
| 572 |
retval |= m48t59_read(NVRAM, addr + 2) << 8; |
| 573 |
retval |= m48t59_read(NVRAM, addr + 3);
|
| 574 |
return retval;
|
| 575 |
} |
| 576 |
|
| 577 |
static const MemoryRegionOps nvram_ops = { |
| 578 |
.old_mmio = {
|
| 579 |
.read = { nvram_readb, nvram_readw, nvram_readl, },
|
| 580 |
.write = { nvram_writeb, nvram_writew, nvram_writel, },
|
| 581 |
}, |
| 582 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 583 |
}; |
| 584 |
|
| 585 |
static const VMStateDescription vmstate_m48t59 = { |
| 586 |
.name = "m48t59",
|
| 587 |
.version_id = 1,
|
| 588 |
.minimum_version_id = 1,
|
| 589 |
.minimum_version_id_old = 1,
|
| 590 |
.fields = (VMStateField[]) {
|
| 591 |
VMSTATE_UINT8(lock, M48t59State), |
| 592 |
VMSTATE_UINT16(addr, M48t59State), |
| 593 |
VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), |
| 594 |
VMSTATE_END_OF_LIST() |
| 595 |
} |
| 596 |
}; |
| 597 |
|
| 598 |
static void m48t59_reset_common(M48t59State *NVRAM) |
| 599 |
{
|
| 600 |
NVRAM->addr = 0;
|
| 601 |
NVRAM->lock = 0;
|
| 602 |
if (NVRAM->alrm_timer != NULL) |
| 603 |
qemu_del_timer(NVRAM->alrm_timer); |
| 604 |
|
| 605 |
if (NVRAM->wd_timer != NULL) |
| 606 |
qemu_del_timer(NVRAM->wd_timer); |
| 607 |
} |
| 608 |
|
| 609 |
static void m48t59_reset_isa(DeviceState *d) |
| 610 |
{
|
| 611 |
M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev); |
| 612 |
M48t59State *NVRAM = &isa->state; |
| 613 |
|
| 614 |
m48t59_reset_common(NVRAM); |
| 615 |
} |
| 616 |
|
| 617 |
static void m48t59_reset_sysbus(DeviceState *d) |
| 618 |
{
|
| 619 |
M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); |
| 620 |
M48t59State *NVRAM = &sys->state; |
| 621 |
|
| 622 |
m48t59_reset_common(NVRAM); |
| 623 |
} |
| 624 |
|
| 625 |
static const MemoryRegionPortio m48t59_portio[] = { |
| 626 |
{0, 4, 1, .read = NVRAM_readb, .write = NVRAM_writeb },
|
| 627 |
PORTIO_END_OF_LIST(), |
| 628 |
}; |
| 629 |
|
| 630 |
static const MemoryRegionOps m48t59_io_ops = { |
| 631 |
.old_portio = m48t59_portio, |
| 632 |
}; |
| 633 |
|
| 634 |
/* Initialisation routine */
|
| 635 |
M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base, |
| 636 |
uint32_t io_base, uint16_t size, int type)
|
| 637 |
{
|
| 638 |
DeviceState *dev; |
| 639 |
SysBusDevice *s; |
| 640 |
M48t59SysBusState *d; |
| 641 |
M48t59State *state; |
| 642 |
|
| 643 |
dev = qdev_create(NULL, "m48t59"); |
| 644 |
qdev_prop_set_uint32(dev, "type", type);
|
| 645 |
qdev_prop_set_uint32(dev, "size", size);
|
| 646 |
qdev_prop_set_uint32(dev, "io_base", io_base);
|
| 647 |
qdev_init_nofail(dev); |
| 648 |
s = sysbus_from_qdev(dev); |
| 649 |
d = FROM_SYSBUS(M48t59SysBusState, s); |
| 650 |
state = &d->state; |
| 651 |
sysbus_connect_irq(s, 0, IRQ);
|
| 652 |
if (io_base != 0) { |
| 653 |
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, state); |
| 654 |
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, state); |
| 655 |
} |
| 656 |
if (mem_base != 0) { |
| 657 |
sysbus_mmio_map(s, 0, mem_base);
|
| 658 |
} |
| 659 |
|
| 660 |
return state;
|
| 661 |
} |
| 662 |
|
| 663 |
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, |
| 664 |
int type)
|
| 665 |
{
|
| 666 |
M48t59ISAState *d; |
| 667 |
ISADevice *dev; |
| 668 |
M48t59State *s; |
| 669 |
|
| 670 |
dev = isa_create(bus, "m48t59_isa");
|
| 671 |
qdev_prop_set_uint32(&dev->qdev, "type", type);
|
| 672 |
qdev_prop_set_uint32(&dev->qdev, "size", size);
|
| 673 |
qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
|
| 674 |
qdev_init_nofail(&dev->qdev); |
| 675 |
d = DO_UPCAST(M48t59ISAState, busdev, dev); |
| 676 |
s = &d->state; |
| 677 |
|
| 678 |
memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); |
| 679 |
if (io_base != 0) { |
| 680 |
isa_register_ioport(dev, &d->io, io_base); |
| 681 |
} |
| 682 |
|
| 683 |
return s;
|
| 684 |
} |
| 685 |
|
| 686 |
static void m48t59_init_common(M48t59State *s) |
| 687 |
{
|
| 688 |
s->buffer = g_malloc0(s->size); |
| 689 |
if (s->type == 59) { |
| 690 |
s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s); |
| 691 |
s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); |
| 692 |
} |
| 693 |
qemu_get_timedate(&s->alarm, 0);
|
| 694 |
|
| 695 |
vmstate_register(NULL, -1, &vmstate_m48t59, s); |
| 696 |
} |
| 697 |
|
| 698 |
static int m48t59_init_isa1(ISADevice *dev) |
| 699 |
{
|
| 700 |
M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); |
| 701 |
M48t59State *s = &d->state; |
| 702 |
|
| 703 |
isa_init_irq(dev, &s->IRQ, 8);
|
| 704 |
m48t59_init_common(s); |
| 705 |
|
| 706 |
return 0; |
| 707 |
} |
| 708 |
|
| 709 |
static int m48t59_init1(SysBusDevice *dev) |
| 710 |
{
|
| 711 |
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); |
| 712 |
M48t59State *s = &d->state; |
| 713 |
|
| 714 |
sysbus_init_irq(dev, &s->IRQ); |
| 715 |
|
| 716 |
memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size);
|
| 717 |
sysbus_init_mmio(dev, &s->iomem); |
| 718 |
m48t59_init_common(s); |
| 719 |
|
| 720 |
return 0; |
| 721 |
} |
| 722 |
|
| 723 |
static void m48t59_init_class_isa1(ObjectClass *klass, void *data) |
| 724 |
{
|
| 725 |
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
| 726 |
ic->init = m48t59_init_isa1; |
| 727 |
} |
| 728 |
|
| 729 |
static DeviceInfo m48t59_isa_info = {
|
| 730 |
.class_init = m48t59_init_class_isa1, |
| 731 |
.name = "m48t59_isa",
|
| 732 |
.size = sizeof(M48t59ISAState),
|
| 733 |
.reset = m48t59_reset_isa, |
| 734 |
.no_user = 1,
|
| 735 |
.props = (Property[]) {
|
| 736 |
DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), |
| 737 |
DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1), |
| 738 |
DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), |
| 739 |
DEFINE_PROP_END_OF_LIST(), |
| 740 |
} |
| 741 |
}; |
| 742 |
|
| 743 |
static Property m48t59_properties[] = {
|
| 744 |
DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), |
| 745 |
DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1), |
| 746 |
DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), |
| 747 |
DEFINE_PROP_END_OF_LIST(), |
| 748 |
}; |
| 749 |
|
| 750 |
static void m48t59_class_init(ObjectClass *klass, void *data) |
| 751 |
{
|
| 752 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 753 |
|
| 754 |
k->init = m48t59_init1; |
| 755 |
} |
| 756 |
|
| 757 |
static DeviceInfo m48t59_info = {
|
| 758 |
.name = "m48t59",
|
| 759 |
.size = sizeof(M48t59SysBusState),
|
| 760 |
.reset = m48t59_reset_sysbus, |
| 761 |
.props = m48t59_properties, |
| 762 |
.class_init = m48t59_class_init, |
| 763 |
}; |
| 764 |
|
| 765 |
static void m48t59_register_devices(void) |
| 766 |
{
|
| 767 |
sysbus_register_withprop(&m48t59_info); |
| 768 |
isa_qdev_register(&m48t59_isa_info); |
| 769 |
} |
| 770 |
|
| 771 |
device_init(m48t59_register_devices) |