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1 | 27503323 | bellard | /*
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2 | 27503323 | bellard | * QEMU DMA emulation
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3 | 85571bc7 | bellard | *
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4 | 85571bc7 | bellard | * Copyright (c) 2003-2004 Vassili Karpov (malc)
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5 | 85571bc7 | bellard | *
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6 | 27503323 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 27503323 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 27503323 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 27503323 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 27503323 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 27503323 | bellard | * furnished to do so, subject to the following conditions:
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12 | 27503323 | bellard | *
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13 | 27503323 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 27503323 | bellard | * all copies or substantial portions of the Software.
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15 | 27503323 | bellard | *
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16 | 27503323 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 27503323 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 27503323 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 27503323 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 27503323 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 27503323 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 27503323 | bellard | * THE SOFTWARE.
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23 | 27503323 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "isa.h" |
26 | 1de7afc9 | Paolo Bonzini | #include "qemu/main-loop.h" |
27 | 27503323 | bellard | |
28 | 85571bc7 | bellard | /* #define DEBUG_DMA */
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29 | 7ebb5e41 | bellard | |
30 | 85571bc7 | bellard | #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) |
31 | 27503323 | bellard | #ifdef DEBUG_DMA
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32 | 27503323 | bellard | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
33 | 27503323 | bellard | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) |
34 | 27503323 | bellard | #else
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35 | 27503323 | bellard | #define linfo(...)
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36 | 27503323 | bellard | #define ldebug(...)
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37 | 27503323 | bellard | #endif
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38 | 27503323 | bellard | |
39 | 27503323 | bellard | struct dma_regs {
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40 | 27503323 | bellard | int now[2]; |
41 | 27503323 | bellard | uint16_t base[2];
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42 | 27503323 | bellard | uint8_t mode; |
43 | 27503323 | bellard | uint8_t page; |
44 | b0bda528 | bellard | uint8_t pageh; |
45 | 27503323 | bellard | uint8_t dack; |
46 | 27503323 | bellard | uint8_t eop; |
47 | 16f62432 | bellard | DMA_transfer_handler transfer_handler; |
48 | 16f62432 | bellard | void *opaque;
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49 | 27503323 | bellard | }; |
50 | 27503323 | bellard | |
51 | 27503323 | bellard | #define ADDR 0 |
52 | 27503323 | bellard | #define COUNT 1 |
53 | 27503323 | bellard | |
54 | 27503323 | bellard | static struct dma_cont { |
55 | 27503323 | bellard | uint8_t status; |
56 | 27503323 | bellard | uint8_t command; |
57 | 27503323 | bellard | uint8_t mask; |
58 | 27503323 | bellard | uint8_t flip_flop; |
59 | 9eb153f1 | bellard | int dshift;
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60 | 27503323 | bellard | struct dma_regs regs[4]; |
61 | 4556bd8b | Blue Swirl | qemu_irq *cpu_request_exit; |
62 | 58229933 | Julien Grall | MemoryRegion channel_io; |
63 | 58229933 | Julien Grall | MemoryRegion cont_io; |
64 | 27503323 | bellard | } dma_controllers[2];
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65 | 27503323 | bellard | |
66 | 27503323 | bellard | enum {
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67 | e875c40a | bellard | CMD_MEMORY_TO_MEMORY = 0x01,
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68 | e875c40a | bellard | CMD_FIXED_ADDRESS = 0x02,
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69 | e875c40a | bellard | CMD_BLOCK_CONTROLLER = 0x04,
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70 | e875c40a | bellard | CMD_COMPRESSED_TIME = 0x08,
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71 | e875c40a | bellard | CMD_CYCLIC_PRIORITY = 0x10,
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72 | e875c40a | bellard | CMD_EXTENDED_WRITE = 0x20,
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73 | e875c40a | bellard | CMD_LOW_DREQ = 0x40,
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74 | e875c40a | bellard | CMD_LOW_DACK = 0x80,
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75 | e875c40a | bellard | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS |
76 | e875c40a | bellard | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE |
77 | e875c40a | bellard | | CMD_LOW_DREQ | CMD_LOW_DACK |
78 | 27503323 | bellard | |
79 | 27503323 | bellard | }; |
80 | 27503323 | bellard | |
81 | 492c30af | aliguori | static void DMA_run (void); |
82 | 492c30af | aliguori | |
83 | 9eb153f1 | bellard | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
84 | 9eb153f1 | bellard | |
85 | 7d977de7 | bellard | static void write_page (void *opaque, uint32_t nport, uint32_t data) |
86 | 27503323 | bellard | { |
87 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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88 | 27503323 | bellard | int ichan;
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89 | 27503323 | bellard | |
90 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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91 | 27503323 | bellard | if (-1 == ichan) { |
92 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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93 | 27503323 | bellard | return;
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94 | 27503323 | bellard | } |
95 | 9eb153f1 | bellard | d->regs[ichan].page = data; |
96 | 9eb153f1 | bellard | } |
97 | 9eb153f1 | bellard | |
98 | b0bda528 | bellard | static void write_pageh (void *opaque, uint32_t nport, uint32_t data) |
99 | 9eb153f1 | bellard | { |
100 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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101 | 9eb153f1 | bellard | int ichan;
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102 | 27503323 | bellard | |
103 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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104 | b0bda528 | bellard | if (-1 == ichan) { |
105 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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106 | b0bda528 | bellard | return;
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107 | b0bda528 | bellard | } |
108 | b0bda528 | bellard | d->regs[ichan].pageh = data; |
109 | b0bda528 | bellard | } |
110 | 9eb153f1 | bellard | |
111 | b0bda528 | bellard | static uint32_t read_page (void *opaque, uint32_t nport) |
112 | b0bda528 | bellard | { |
113 | b0bda528 | bellard | struct dma_cont *d = opaque;
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114 | b0bda528 | bellard | int ichan;
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115 | b0bda528 | bellard | |
116 | b0bda528 | bellard | ichan = channels[nport & 7];
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117 | 9eb153f1 | bellard | if (-1 == ichan) { |
118 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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119 | 9eb153f1 | bellard | return 0; |
120 | 9eb153f1 | bellard | } |
121 | 9eb153f1 | bellard | return d->regs[ichan].page;
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122 | 27503323 | bellard | } |
123 | 27503323 | bellard | |
124 | b0bda528 | bellard | static uint32_t read_pageh (void *opaque, uint32_t nport) |
125 | b0bda528 | bellard | { |
126 | b0bda528 | bellard | struct dma_cont *d = opaque;
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127 | b0bda528 | bellard | int ichan;
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128 | b0bda528 | bellard | |
129 | b0bda528 | bellard | ichan = channels[nport & 7];
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130 | b0bda528 | bellard | if (-1 == ichan) { |
131 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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132 | b0bda528 | bellard | return 0; |
133 | b0bda528 | bellard | } |
134 | b0bda528 | bellard | return d->regs[ichan].pageh;
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135 | b0bda528 | bellard | } |
136 | b0bda528 | bellard | |
137 | 9eb153f1 | bellard | static inline void init_chan (struct dma_cont *d, int ichan) |
138 | 27503323 | bellard | { |
139 | 27503323 | bellard | struct dma_regs *r;
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140 | 27503323 | bellard | |
141 | 9eb153f1 | bellard | r = d->regs + ichan; |
142 | 85571bc7 | bellard | r->now[ADDR] = r->base[ADDR] << d->dshift; |
143 | 27503323 | bellard | r->now[COUNT] = 0;
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144 | 27503323 | bellard | } |
145 | 27503323 | bellard | |
146 | 9eb153f1 | bellard | static inline int getff (struct dma_cont *d) |
147 | 27503323 | bellard | { |
148 | 27503323 | bellard | int ff;
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149 | 27503323 | bellard | |
150 | 9eb153f1 | bellard | ff = d->flip_flop; |
151 | 9eb153f1 | bellard | d->flip_flop = !ff; |
152 | 27503323 | bellard | return ff;
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153 | 27503323 | bellard | } |
154 | 27503323 | bellard | |
155 | 58229933 | Julien Grall | static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) |
156 | 27503323 | bellard | { |
157 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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158 | 85571bc7 | bellard | int ichan, nreg, iport, ff, val, dir;
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159 | 27503323 | bellard | struct dma_regs *r;
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160 | 27503323 | bellard | |
161 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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162 | 9eb153f1 | bellard | ichan = iport >> 1;
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163 | 9eb153f1 | bellard | nreg = iport & 1;
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164 | 9eb153f1 | bellard | r = d->regs + ichan; |
165 | 27503323 | bellard | |
166 | 85571bc7 | bellard | dir = ((r->mode >> 5) & 1) ? -1 : 1; |
167 | 9eb153f1 | bellard | ff = getff (d); |
168 | 27503323 | bellard | if (nreg)
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169 | 9eb153f1 | bellard | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
170 | 27503323 | bellard | else
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171 | 85571bc7 | bellard | val = r->now[ADDR] + r->now[COUNT] * dir; |
172 | 27503323 | bellard | |
173 | 85571bc7 | bellard | ldebug ("read_chan %#x -> %d\n", iport, val);
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174 | 9eb153f1 | bellard | return (val >> (d->dshift + (ff << 3))) & 0xff; |
175 | 27503323 | bellard | } |
176 | 27503323 | bellard | |
177 | 58229933 | Julien Grall | static void write_chan(void *opaque, hwaddr nport, uint64_t data, |
178 | 58229933 | Julien Grall | unsigned size)
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179 | 27503323 | bellard | { |
180 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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181 | 9eb153f1 | bellard | int iport, ichan, nreg;
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182 | 27503323 | bellard | struct dma_regs *r;
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183 | 27503323 | bellard | |
184 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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185 | 9eb153f1 | bellard | ichan = iport >> 1;
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186 | 9eb153f1 | bellard | nreg = iport & 1;
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187 | 9eb153f1 | bellard | r = d->regs + ichan; |
188 | 9eb153f1 | bellard | if (getff (d)) {
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189 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
190 | 9eb153f1 | bellard | init_chan (d, ichan); |
191 | 3504fe17 | bellard | } else {
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192 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
193 | 27503323 | bellard | } |
194 | 27503323 | bellard | } |
195 | 27503323 | bellard | |
196 | 58229933 | Julien Grall | static void write_cont(void *opaque, hwaddr nport, uint64_t data, |
197 | 58229933 | Julien Grall | unsigned size)
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198 | 27503323 | bellard | { |
199 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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200 | 85571bc7 | bellard | int iport, ichan = 0; |
201 | 27503323 | bellard | |
202 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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203 | 27503323 | bellard | switch (iport) {
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204 | 58229933 | Julien Grall | case 0x01: /* command */ |
205 | df475d18 | bellard | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
206 | 58229933 | Julien Grall | dolog("command %"PRIx64" not supported\n", data); |
207 | df475d18 | bellard | return;
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208 | 27503323 | bellard | } |
209 | 27503323 | bellard | d->command = data; |
210 | 27503323 | bellard | break;
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211 | 27503323 | bellard | |
212 | 58229933 | Julien Grall | case 0x02: |
213 | 27503323 | bellard | ichan = data & 3;
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214 | 27503323 | bellard | if (data & 4) { |
215 | 27503323 | bellard | d->status |= 1 << (ichan + 4); |
216 | 27503323 | bellard | } |
217 | 27503323 | bellard | else {
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218 | 27503323 | bellard | d->status &= ~(1 << (ichan + 4)); |
219 | 27503323 | bellard | } |
220 | 27503323 | bellard | d->status &= ~(1 << ichan);
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221 | 492c30af | aliguori | DMA_run(); |
222 | 27503323 | bellard | break;
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223 | 27503323 | bellard | |
224 | 58229933 | Julien Grall | case 0x03: /* single mask */ |
225 | 27503323 | bellard | if (data & 4) |
226 | 27503323 | bellard | d->mask |= 1 << (data & 3); |
227 | 27503323 | bellard | else
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228 | 27503323 | bellard | d->mask &= ~(1 << (data & 3)); |
229 | 492c30af | aliguori | DMA_run(); |
230 | 27503323 | bellard | break;
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231 | 27503323 | bellard | |
232 | 58229933 | Julien Grall | case 0x04: /* mode */ |
233 | 27503323 | bellard | { |
234 | 16d17fdb | bellard | ichan = data & 3;
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235 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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236 | 85571bc7 | bellard | { |
237 | 85571bc7 | bellard | int op, ai, dir, opmode;
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238 | e875c40a | bellard | op = (data >> 2) & 3; |
239 | e875c40a | bellard | ai = (data >> 4) & 1; |
240 | e875c40a | bellard | dir = (data >> 5) & 1; |
241 | e875c40a | bellard | opmode = (data >> 6) & 3; |
242 | 27503323 | bellard | |
243 | e875c40a | bellard | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
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244 | e875c40a | bellard | ichan, op, ai, dir, opmode); |
245 | 85571bc7 | bellard | } |
246 | 27503323 | bellard | #endif
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247 | 27503323 | bellard | d->regs[ichan].mode = data; |
248 | 27503323 | bellard | break;
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249 | 27503323 | bellard | } |
250 | 27503323 | bellard | |
251 | 58229933 | Julien Grall | case 0x05: /* clear flip flop */ |
252 | 27503323 | bellard | d->flip_flop = 0;
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253 | 27503323 | bellard | break;
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254 | 27503323 | bellard | |
255 | 58229933 | Julien Grall | case 0x06: /* reset */ |
256 | 27503323 | bellard | d->flip_flop = 0;
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257 | 27503323 | bellard | d->mask = ~0;
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258 | 27503323 | bellard | d->status = 0;
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259 | 27503323 | bellard | d->command = 0;
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260 | 27503323 | bellard | break;
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261 | 27503323 | bellard | |
262 | 58229933 | Julien Grall | case 0x07: /* clear mask for all channels */ |
263 | 27503323 | bellard | d->mask = 0;
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264 | 492c30af | aliguori | DMA_run(); |
265 | 27503323 | bellard | break;
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266 | 27503323 | bellard | |
267 | 58229933 | Julien Grall | case 0x08: /* write mask for all channels */ |
268 | 27503323 | bellard | d->mask = data; |
269 | 492c30af | aliguori | DMA_run(); |
270 | 27503323 | bellard | break;
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271 | 27503323 | bellard | |
272 | 27503323 | bellard | default:
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273 | 85571bc7 | bellard | dolog ("unknown iport %#x\n", iport);
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274 | df475d18 | bellard | break;
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275 | 27503323 | bellard | } |
276 | 27503323 | bellard | |
277 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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278 | 27503323 | bellard | if (0xc != iport) { |
279 | 85571bc7 | bellard | linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
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280 | 9eb153f1 | bellard | nport, ichan, data); |
281 | 27503323 | bellard | } |
282 | 27503323 | bellard | #endif
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283 | 27503323 | bellard | } |
284 | 27503323 | bellard | |
285 | 58229933 | Julien Grall | static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size) |
286 | 9eb153f1 | bellard | { |
287 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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288 | 9eb153f1 | bellard | int iport, val;
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289 | 85571bc7 | bellard | |
290 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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291 | 9eb153f1 | bellard | switch (iport) {
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292 | 85571bc7 | bellard | case 0x08: /* status */ |
293 | 9eb153f1 | bellard | val = d->status; |
294 | 9eb153f1 | bellard | d->status &= 0xf0;
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295 | 9eb153f1 | bellard | break;
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296 | 85571bc7 | bellard | case 0x0f: /* mask */ |
297 | 9eb153f1 | bellard | val = d->mask; |
298 | 9eb153f1 | bellard | break;
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299 | 9eb153f1 | bellard | default:
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300 | 9eb153f1 | bellard | val = 0;
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301 | 9eb153f1 | bellard | break;
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302 | 9eb153f1 | bellard | } |
303 | 85571bc7 | bellard | |
304 | 85571bc7 | bellard | ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
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305 | 9eb153f1 | bellard | return val;
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306 | 9eb153f1 | bellard | } |
307 | 9eb153f1 | bellard | |
308 | 27503323 | bellard | int DMA_get_channel_mode (int nchan) |
309 | 27503323 | bellard | { |
310 | 27503323 | bellard | return dma_controllers[nchan > 3].regs[nchan & 3].mode; |
311 | 27503323 | bellard | } |
312 | 27503323 | bellard | |
313 | 27503323 | bellard | void DMA_hold_DREQ (int nchan) |
314 | 27503323 | bellard | { |
315 | 27503323 | bellard | int ncont, ichan;
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316 | 27503323 | bellard | |
317 | 27503323 | bellard | ncont = nchan > 3;
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318 | 27503323 | bellard | ichan = nchan & 3;
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319 | 27503323 | bellard | linfo ("held cont=%d chan=%d\n", ncont, ichan);
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320 | 27503323 | bellard | dma_controllers[ncont].status |= 1 << (ichan + 4); |
321 | 492c30af | aliguori | DMA_run(); |
322 | 27503323 | bellard | } |
323 | 27503323 | bellard | |
324 | 27503323 | bellard | void DMA_release_DREQ (int nchan) |
325 | 27503323 | bellard | { |
326 | 27503323 | bellard | int ncont, ichan;
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327 | 27503323 | bellard | |
328 | 27503323 | bellard | ncont = nchan > 3;
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329 | 27503323 | bellard | ichan = nchan & 3;
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330 | 27503323 | bellard | linfo ("released cont=%d chan=%d\n", ncont, ichan);
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331 | 27503323 | bellard | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); |
332 | 492c30af | aliguori | DMA_run(); |
333 | 27503323 | bellard | } |
334 | 27503323 | bellard | |
335 | 27503323 | bellard | static void channel_run (int ncont, int ichan) |
336 | 27503323 | bellard | { |
337 | 27503323 | bellard | int n;
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338 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
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339 | 85571bc7 | bellard | #ifdef DEBUG_DMA
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340 | 85571bc7 | bellard | int dir, opmode;
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341 | 27503323 | bellard | |
342 | 85571bc7 | bellard | dir = (r->mode >> 5) & 1; |
343 | 85571bc7 | bellard | opmode = (r->mode >> 6) & 3; |
344 | 27503323 | bellard | |
345 | 85571bc7 | bellard | if (dir) {
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346 | 85571bc7 | bellard | dolog ("DMA in address decrement mode\n");
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347 | 85571bc7 | bellard | } |
348 | 85571bc7 | bellard | if (opmode != 1) { |
349 | 85571bc7 | bellard | dolog ("DMA not in single mode select %#x\n", opmode);
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350 | 85571bc7 | bellard | } |
351 | 85571bc7 | bellard | #endif
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352 | 27503323 | bellard | |
353 | 85571bc7 | bellard | n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
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354 | 85571bc7 | bellard | r->now[COUNT], (r->base[COUNT] + 1) << ncont);
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355 | 85571bc7 | bellard | r->now[COUNT] = n; |
356 | 85571bc7 | bellard | ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); |
357 | 27503323 | bellard | } |
358 | 27503323 | bellard | |
359 | 492c30af | aliguori | static QEMUBH *dma_bh;
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360 | 492c30af | aliguori | |
361 | 492c30af | aliguori | static void DMA_run (void) |
362 | 27503323 | bellard | { |
363 | 27503323 | bellard | struct dma_cont *d;
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364 | 27503323 | bellard | int icont, ichan;
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365 | 492c30af | aliguori | int rearm = 0; |
366 | acae6f1c | Kevin Wolf | static int running = 0; |
367 | acae6f1c | Kevin Wolf | |
368 | acae6f1c | Kevin Wolf | if (running) {
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369 | acae6f1c | Kevin Wolf | rearm = 1;
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370 | acae6f1c | Kevin Wolf | goto out;
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371 | acae6f1c | Kevin Wolf | } else {
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372 | acae6f1c | Kevin Wolf | running = 1;
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373 | acae6f1c | Kevin Wolf | } |
374 | 27503323 | bellard | |
375 | 27503323 | bellard | d = dma_controllers; |
376 | 27503323 | bellard | |
377 | 27503323 | bellard | for (icont = 0; icont < 2; icont++, d++) { |
378 | 27503323 | bellard | for (ichan = 0; ichan < 4; ichan++) { |
379 | 27503323 | bellard | int mask;
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380 | 27503323 | bellard | |
381 | 27503323 | bellard | mask = 1 << ichan;
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382 | 27503323 | bellard | |
383 | 492c30af | aliguori | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) { |
384 | 27503323 | bellard | channel_run (icont, ichan); |
385 | 492c30af | aliguori | rearm = 1;
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386 | 492c30af | aliguori | } |
387 | 27503323 | bellard | } |
388 | 27503323 | bellard | } |
389 | 492c30af | aliguori | |
390 | acae6f1c | Kevin Wolf | running = 0;
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391 | acae6f1c | Kevin Wolf | out:
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392 | 492c30af | aliguori | if (rearm)
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393 | 492c30af | aliguori | qemu_bh_schedule_idle(dma_bh); |
394 | 492c30af | aliguori | } |
395 | 492c30af | aliguori | |
396 | 492c30af | aliguori | static void DMA_run_bh(void *unused) |
397 | 492c30af | aliguori | { |
398 | 492c30af | aliguori | DMA_run(); |
399 | 27503323 | bellard | } |
400 | 27503323 | bellard | |
401 | 27503323 | bellard | void DMA_register_channel (int nchan, |
402 | 85571bc7 | bellard | DMA_transfer_handler transfer_handler, |
403 | 16f62432 | bellard | void *opaque)
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404 | 27503323 | bellard | { |
405 | 27503323 | bellard | struct dma_regs *r;
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406 | 27503323 | bellard | int ichan, ncont;
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407 | 27503323 | bellard | |
408 | 27503323 | bellard | ncont = nchan > 3;
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409 | 27503323 | bellard | ichan = nchan & 3;
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410 | 27503323 | bellard | |
411 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
412 | 16f62432 | bellard | r->transfer_handler = transfer_handler; |
413 | 16f62432 | bellard | r->opaque = opaque; |
414 | 16f62432 | bellard | } |
415 | 16f62432 | bellard | |
416 | 85571bc7 | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int len) |
417 | 85571bc7 | bellard | { |
418 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
419 | a8170e5e | Avi Kivity | hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
420 | 85571bc7 | bellard | |
421 | 85571bc7 | bellard | if (r->mode & 0x20) { |
422 | 85571bc7 | bellard | int i;
|
423 | 85571bc7 | bellard | uint8_t *p = buf; |
424 | 85571bc7 | bellard | |
425 | 85571bc7 | bellard | cpu_physical_memory_read (addr - pos - len, buf, len); |
426 | 85571bc7 | bellard | /* What about 16bit transfers? */
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427 | 85571bc7 | bellard | for (i = 0; i < len >> 1; i++) { |
428 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
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429 | 85571bc7 | bellard | p[i] = b; |
430 | 85571bc7 | bellard | } |
431 | 85571bc7 | bellard | } |
432 | 85571bc7 | bellard | else
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433 | 85571bc7 | bellard | cpu_physical_memory_read (addr + pos, buf, len); |
434 | 85571bc7 | bellard | |
435 | 85571bc7 | bellard | return len;
|
436 | 85571bc7 | bellard | } |
437 | 85571bc7 | bellard | |
438 | 85571bc7 | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int len) |
439 | 85571bc7 | bellard | { |
440 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
441 | a8170e5e | Avi Kivity | hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
442 | 85571bc7 | bellard | |
443 | 85571bc7 | bellard | if (r->mode & 0x20) { |
444 | 85571bc7 | bellard | int i;
|
445 | 85571bc7 | bellard | uint8_t *p = buf; |
446 | 85571bc7 | bellard | |
447 | 85571bc7 | bellard | cpu_physical_memory_write (addr - pos - len, buf, len); |
448 | 85571bc7 | bellard | /* What about 16bit transfers? */
|
449 | 85571bc7 | bellard | for (i = 0; i < len; i++) { |
450 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
|
451 | 85571bc7 | bellard | p[i] = b; |
452 | 85571bc7 | bellard | } |
453 | 85571bc7 | bellard | } |
454 | 85571bc7 | bellard | else
|
455 | 85571bc7 | bellard | cpu_physical_memory_write (addr + pos, buf, len); |
456 | 85571bc7 | bellard | |
457 | 85571bc7 | bellard | return len;
|
458 | 85571bc7 | bellard | } |
459 | 85571bc7 | bellard | |
460 | 16f62432 | bellard | /* request the emulator to transfer a new DMA memory block ASAP */
|
461 | 16f62432 | bellard | void DMA_schedule(int nchan) |
462 | 16f62432 | bellard | { |
463 | 4556bd8b | Blue Swirl | struct dma_cont *d = &dma_controllers[nchan > 3]; |
464 | 4556bd8b | Blue Swirl | |
465 | 4556bd8b | Blue Swirl | qemu_irq_pulse(*d->cpu_request_exit); |
466 | 27503323 | bellard | } |
467 | 27503323 | bellard | |
468 | d7d02e3c | bellard | static void dma_reset(void *opaque) |
469 | d7d02e3c | bellard | { |
470 | d7d02e3c | bellard | struct dma_cont *d = opaque;
|
471 | 58229933 | Julien Grall | write_cont(d, (0x06 << d->dshift), 0, 1); |
472 | d7d02e3c | bellard | } |
473 | d7d02e3c | bellard | |
474 | ca9cc28c | balrog | static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len) |
475 | ca9cc28c | balrog | { |
476 | ca9cc28c | balrog | dolog ("unregistered DMA channel used nchan=%d dma_pos=%d dma_len=%d\n",
|
477 | ca9cc28c | balrog | nchan, dma_pos, dma_len); |
478 | ca9cc28c | balrog | return dma_pos;
|
479 | ca9cc28c | balrog | } |
480 | ca9cc28c | balrog | |
481 | 58229933 | Julien Grall | |
482 | 58229933 | Julien Grall | static const MemoryRegionOps channel_io_ops = { |
483 | 58229933 | Julien Grall | .read = read_chan, |
484 | 58229933 | Julien Grall | .write = write_chan, |
485 | 58229933 | Julien Grall | .endianness = DEVICE_NATIVE_ENDIAN, |
486 | 58229933 | Julien Grall | .impl = { |
487 | 58229933 | Julien Grall | .min_access_size = 1,
|
488 | 58229933 | Julien Grall | .max_access_size = 1,
|
489 | 58229933 | Julien Grall | }, |
490 | 58229933 | Julien Grall | }; |
491 | 58229933 | Julien Grall | |
492 | 58229933 | Julien Grall | /* IOport from page_base */
|
493 | 58229933 | Julien Grall | static const MemoryRegionPortio page_portio_list[] = { |
494 | 58229933 | Julien Grall | { 0x01, 3, 1, .write = write_page, .read = read_page, }, |
495 | 58229933 | Julien Grall | { 0x07, 1, 1, .write = write_page, .read = read_page, }, |
496 | 58229933 | Julien Grall | PORTIO_END_OF_LIST(), |
497 | 58229933 | Julien Grall | }; |
498 | 58229933 | Julien Grall | |
499 | 58229933 | Julien Grall | /* IOport from pageh_base */
|
500 | 58229933 | Julien Grall | static const MemoryRegionPortio pageh_portio_list[] = { |
501 | 58229933 | Julien Grall | { 0x01, 3, 1, .write = write_pageh, .read = read_pageh, }, |
502 | 58229933 | Julien Grall | { 0x07, 3, 1, .write = write_pageh, .read = read_pageh, }, |
503 | 58229933 | Julien Grall | PORTIO_END_OF_LIST(), |
504 | 58229933 | Julien Grall | }; |
505 | 58229933 | Julien Grall | |
506 | 58229933 | Julien Grall | static const MemoryRegionOps cont_io_ops = { |
507 | 58229933 | Julien Grall | .read = read_cont, |
508 | 58229933 | Julien Grall | .write = write_cont, |
509 | 58229933 | Julien Grall | .endianness = DEVICE_NATIVE_ENDIAN, |
510 | 58229933 | Julien Grall | .impl = { |
511 | 58229933 | Julien Grall | .min_access_size = 1,
|
512 | 58229933 | Julien Grall | .max_access_size = 1,
|
513 | 58229933 | Julien Grall | }, |
514 | 58229933 | Julien Grall | }; |
515 | 58229933 | Julien Grall | |
516 | 9eb153f1 | bellard | /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
|
517 | 85571bc7 | bellard | static void dma_init2(struct dma_cont *d, int base, int dshift, |
518 | 4556bd8b | Blue Swirl | int page_base, int pageh_base, |
519 | 4556bd8b | Blue Swirl | qemu_irq *cpu_request_exit) |
520 | 27503323 | bellard | { |
521 | 27503323 | bellard | int i;
|
522 | 27503323 | bellard | |
523 | 9eb153f1 | bellard | d->dshift = dshift; |
524 | 4556bd8b | Blue Swirl | d->cpu_request_exit = cpu_request_exit; |
525 | 58229933 | Julien Grall | |
526 | 58229933 | Julien Grall | memory_region_init_io(&d->channel_io, &channel_io_ops, d, |
527 | 58229933 | Julien Grall | "dma-chan", 8 << d->dshift); |
528 | 58229933 | Julien Grall | memory_region_add_subregion(isa_address_space_io(NULL),
|
529 | 58229933 | Julien Grall | base, &d->channel_io); |
530 | 58229933 | Julien Grall | |
531 | 58229933 | Julien Grall | isa_register_portio_list(NULL, page_base, page_portio_list, d,
|
532 | 58229933 | Julien Grall | "dma-page");
|
533 | 58229933 | Julien Grall | if (pageh_base >= 0) { |
534 | 58229933 | Julien Grall | isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d,
|
535 | 58229933 | Julien Grall | "dma-pageh");
|
536 | 27503323 | bellard | } |
537 | 58229933 | Julien Grall | |
538 | 58229933 | Julien Grall | memory_region_init_io(&d->cont_io, &cont_io_ops, d, "dma-cont",
|
539 | 58229933 | Julien Grall | 8 << d->dshift);
|
540 | 58229933 | Julien Grall | memory_region_add_subregion(isa_address_space_io(NULL),
|
541 | 58229933 | Julien Grall | base + (8 << d->dshift), &d->cont_io);
|
542 | 58229933 | Julien Grall | |
543 | a08d4367 | Jan Kiszka | qemu_register_reset(dma_reset, d); |
544 | d7d02e3c | bellard | dma_reset(d); |
545 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE (d->regs); ++i) { |
546 | ca9cc28c | balrog | d->regs[i].transfer_handler = dma_phony_handler; |
547 | ca9cc28c | balrog | } |
548 | 9eb153f1 | bellard | } |
549 | 27503323 | bellard | |
550 | 7b5045c5 | Juan Quintela | static const VMStateDescription vmstate_dma_regs = { |
551 | 7b5045c5 | Juan Quintela | .name = "dma_regs",
|
552 | 7b5045c5 | Juan Quintela | .version_id = 1,
|
553 | 7b5045c5 | Juan Quintela | .minimum_version_id = 1,
|
554 | 7b5045c5 | Juan Quintela | .minimum_version_id_old = 1,
|
555 | 7b5045c5 | Juan Quintela | .fields = (VMStateField []) { |
556 | 7b5045c5 | Juan Quintela | VMSTATE_INT32_ARRAY(now, struct dma_regs, 2), |
557 | 7b5045c5 | Juan Quintela | VMSTATE_UINT16_ARRAY(base, struct dma_regs, 2), |
558 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(mode, struct dma_regs),
|
559 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(page, struct dma_regs),
|
560 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(pageh, struct dma_regs),
|
561 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(dack, struct dma_regs),
|
562 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(eop, struct dma_regs),
|
563 | 7b5045c5 | Juan Quintela | VMSTATE_END_OF_LIST() |
564 | 85571bc7 | bellard | } |
565 | 7b5045c5 | Juan Quintela | }; |
566 | 85571bc7 | bellard | |
567 | e59fb374 | Juan Quintela | static int dma_post_load(void *opaque, int version_id) |
568 | 85571bc7 | bellard | { |
569 | 492c30af | aliguori | DMA_run(); |
570 | 492c30af | aliguori | |
571 | 85571bc7 | bellard | return 0; |
572 | 85571bc7 | bellard | } |
573 | 85571bc7 | bellard | |
574 | 7b5045c5 | Juan Quintela | static const VMStateDescription vmstate_dma = { |
575 | 7b5045c5 | Juan Quintela | .name = "dma",
|
576 | 7b5045c5 | Juan Quintela | .version_id = 1,
|
577 | 7b5045c5 | Juan Quintela | .minimum_version_id = 1,
|
578 | 7b5045c5 | Juan Quintela | .minimum_version_id_old = 1,
|
579 | 7b5045c5 | Juan Quintela | .post_load = dma_post_load, |
580 | 7b5045c5 | Juan Quintela | .fields = (VMStateField []) { |
581 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(command, struct dma_cont),
|
582 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(mask, struct dma_cont),
|
583 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(flip_flop, struct dma_cont),
|
584 | 7b5045c5 | Juan Quintela | VMSTATE_INT32(dshift, struct dma_cont),
|
585 | 7b5045c5 | Juan Quintela | VMSTATE_STRUCT_ARRAY(regs, struct dma_cont, 4, 1, vmstate_dma_regs, struct dma_regs), |
586 | 7b5045c5 | Juan Quintela | VMSTATE_END_OF_LIST() |
587 | 7b5045c5 | Juan Quintela | } |
588 | 7b5045c5 | Juan Quintela | }; |
589 | 7b5045c5 | Juan Quintela | |
590 | 4556bd8b | Blue Swirl | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
591 | 9eb153f1 | bellard | { |
592 | 85571bc7 | bellard | dma_init2(&dma_controllers[0], 0x00, 0, 0x80, |
593 | 4556bd8b | Blue Swirl | high_page_enable ? 0x480 : -1, cpu_request_exit); |
594 | b0bda528 | bellard | dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, |
595 | 4556bd8b | Blue Swirl | high_page_enable ? 0x488 : -1, cpu_request_exit); |
596 | 0be71e32 | Alex Williamson | vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]); |
597 | 0be71e32 | Alex Williamson | vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]); |
598 | 492c30af | aliguori | |
599 | 492c30af | aliguori | dma_bh = qemu_bh_new(DMA_run_bh, NULL);
|
600 | 27503323 | bellard | } |