root / hw / zynq_slcr.c @ 1de7afc9
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/*
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* Status and system control registers for Xilinx Zynq Platform
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*
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* Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (c) 2012 PetaLogix Pty Ltd.
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* Based on hw/arm_sysctl.c, written by Paul Brook
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "qemu/timer.h" |
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#include "sysbus.h" |
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#include "sysemu.h" |
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|
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#ifdef ZYNQ_ARM_SLCR_ERR_DEBUG
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#define DB_PRINT(...) do { \ |
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \ |
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} while (0); |
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#else
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#define DB_PRINT(...)
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#endif
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|
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#define XILINX_LOCK_KEY 0x767b |
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#define XILINX_UNLOCK_KEY 0xdf0d |
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|
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typedef enum { |
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ARM_PLL_CTRL, |
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DDR_PLL_CTRL, |
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IO_PLL_CTRL, |
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PLL_STATUS, |
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ARM_PPL_CFG, |
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DDR_PLL_CFG, |
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IO_PLL_CFG, |
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PLL_BG_CTRL, |
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PLL_MAX |
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} PLLValues; |
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|
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typedef enum { |
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ARM_CLK_CTRL, |
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DDR_CLK_CTRL, |
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DCI_CLK_CTRL, |
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APER_CLK_CTRL, |
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USB0_CLK_CTRL, |
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USB1_CLK_CTRL, |
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GEM0_RCLK_CTRL, |
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GEM1_RCLK_CTRL, |
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GEM0_CLK_CTRL, |
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GEM1_CLK_CTRL, |
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SMC_CLK_CTRL, |
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LQSPI_CLK_CTRL, |
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SDIO_CLK_CTRL, |
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UART_CLK_CTRL, |
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SPI_CLK_CTRL, |
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CAN_CLK_CTRL, |
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CAN_MIOCLK_CTRL, |
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DBG_CLK_CTRL, |
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PCAP_CLK_CTRL, |
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TOPSW_CLK_CTRL, |
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CLK_MAX |
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} ClkValues; |
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|
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typedef enum { |
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CLK_CTRL, |
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THR_CTRL, |
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THR_CNT, |
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THR_STA, |
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FPGA_MAX |
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} FPGAValues; |
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|
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typedef enum { |
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SYNC_CTRL, |
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SYNC_STATUS, |
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BANDGAP_TRIP, |
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CC_TEST, |
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PLL_PREDIVISOR, |
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CLK_621_TRUE, |
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PICTURE_DBG, |
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PICTURE_DBG_UCNT, |
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PICTURE_DBG_LCNT, |
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MISC_MAX |
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} MiscValues; |
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|
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typedef enum { |
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PSS, |
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DDDR, |
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DMAC = 3,
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USB, |
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GEM, |
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SDIO, |
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SPI, |
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CAN, |
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I2C, |
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UART, |
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GPIO, |
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LQSPI, |
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SMC, |
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OCM, |
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DEVCI, |
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FPGA, |
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A9_CPU, |
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RS_AWDT, |
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RST_REASON, |
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RST_REASON_CLR, |
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REBOOT_STATUS, |
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BOOT_MODE, |
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RESET_MAX |
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} ResetValues; |
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|
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typedef struct { |
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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|
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union {
|
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struct {
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uint16_t scl; |
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uint16_t lockval; |
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uint32_t pll[PLL_MAX]; /* 0x100 - 0x11C */
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uint32_t clk[CLK_MAX]; /* 0x120 - 0x16C */
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uint32_t fpga[4][FPGA_MAX]; /* 0x170 - 0x1AC */ |
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uint32_t misc[MISC_MAX]; /* 0x1B0 - 0x1D8 */
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uint32_t reset[RESET_MAX]; /* 0x200 - 0x25C */
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uint32_t apu_ctrl; /* 0x300 */
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uint32_t wdt_clk_sel; /* 0x304 */
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uint32_t tz_ocm[3]; /* 0x400 - 0x408 */ |
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uint32_t tz_ddr; /* 0x430 */
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uint32_t tz_dma[3]; /* 0x440 - 0x448 */ |
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uint32_t tz_misc[3]; /* 0x450 - 0x458 */ |
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uint32_t tz_fpga[2]; /* 0x484 - 0x488 */ |
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uint32_t dbg_ctrl; /* 0x500 */
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uint32_t pss_idcode; /* 0x530 */
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uint32_t ddr[8]; /* 0x600 - 0x620 - 0x604-missing */ |
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uint32_t mio[54]; /* 0x700 - 0x7D4 */ |
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uint32_t mio_func[4]; /* 0x800 - 0x810 */ |
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uint32_t sd[2]; /* 0x830 - 0x834 */ |
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uint32_t lvl_shftr_en; /* 0x900 */
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uint32_t ocm_cfg; /* 0x910 */
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uint32_t cpu_ram[8]; /* 0xA00 - 0xA1C */ |
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uint32_t iou[7]; /* 0xA30 - 0xA48 */ |
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uint32_t dmac_ram; /* 0xA50 */
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uint32_t afi[4][3]; /* 0xA60 - 0xA8C */ |
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uint32_t ocm[3]; /* 0xA90 - 0xA98 */ |
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uint32_t devci_ram; /* 0xAA0 */
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uint32_t csg_ram; /* 0xAB0 */
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uint32_t gpiob[12]; /* 0xB00 - 0xB2C */ |
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uint32_t ddriob[14]; /* 0xB40 - 0xB74 */ |
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}; |
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uint8_t data[0x1000];
|
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}; |
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} ZynqSLCRState; |
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|
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static void zynq_slcr_reset(DeviceState *d) |
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{
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int i;
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ZynqSLCRState *s = |
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FROM_SYSBUS(ZynqSLCRState, sysbus_from_qdev(d)); |
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DB_PRINT("RESET\n");
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s->lockval = 1;
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/* 0x100 - 0x11C */
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s->pll[ARM_PLL_CTRL] = 0x0001A008;
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s->pll[DDR_PLL_CTRL] = 0x0001A008;
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s->pll[IO_PLL_CTRL] = 0x0001A008;
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s->pll[PLL_STATUS] = 0x0000003F;
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s->pll[ARM_PPL_CFG] = 0x00014000;
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s->pll[DDR_PLL_CFG] = 0x00014000;
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s->pll[IO_PLL_CFG] = 0x00014000;
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/* 0x120 - 0x16C */
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s->clk[ARM_CLK_CTRL] = 0x1F000400;
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s->clk[DDR_CLK_CTRL] = 0x18400003;
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s->clk[DCI_CLK_CTRL] = 0x01E03201;
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s->clk[APER_CLK_CTRL] = 0x01FFCCCD;
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s->clk[USB0_CLK_CTRL] = s->clk[USB1_CLK_CTRL] = 0x00101941;
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s->clk[GEM0_RCLK_CTRL] = s->clk[GEM1_RCLK_CTRL] = 0x00000001;
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s->clk[GEM0_CLK_CTRL] = s->clk[GEM1_CLK_CTRL] = 0x00003C01;
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s->clk[SMC_CLK_CTRL] = 0x00003C01;
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s->clk[LQSPI_CLK_CTRL] = 0x00002821;
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s->clk[SDIO_CLK_CTRL] = 0x00001E03;
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s->clk[UART_CLK_CTRL] = 0x00003F03;
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s->clk[SPI_CLK_CTRL] = 0x00003F03;
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s->clk[CAN_CLK_CTRL] = 0x00501903;
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s->clk[DBG_CLK_CTRL] = 0x00000F03;
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s->clk[PCAP_CLK_CTRL] = 0x00000F01;
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/* 0x170 - 0x1AC */
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s->fpga[0][CLK_CTRL] = s->fpga[1][CLK_CTRL] = s->fpga[2][CLK_CTRL] = |
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s->fpga[3][CLK_CTRL] = 0x00101800; |
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s->fpga[0][THR_STA] = s->fpga[1][THR_STA] = s->fpga[2][THR_STA] = |
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s->fpga[3][THR_STA] = 0x00010000; |
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|
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/* 0x1B0 - 0x1D8 */
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s->misc[BANDGAP_TRIP] = 0x0000001F;
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s->misc[PLL_PREDIVISOR] = 0x00000001;
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s->misc[CLK_621_TRUE] = 0x00000001;
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|
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/* 0x200 - 0x25C */
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s->reset[FPGA] = 0x01F33F0F;
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s->reset[RST_REASON] = 0x00000040;
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/* 0x700 - 0x7D4 */
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for (i = 0; i < 54; i++) { |
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s->mio[i] = 0x00001601;
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} |
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for (i = 2; i <= 8; i++) { |
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s->mio[i] = 0x00000601;
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} |
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|
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/* MIO_MST_TRI0, MIO_MST_TRI1 */
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s->mio_func[2] = s->mio_func[3] = 0xFFFFFFFF; |
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|
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s->cpu_ram[0] = s->cpu_ram[1] = s->cpu_ram[3] = |
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s->cpu_ram[4] = s->cpu_ram[7] = 0x00010101; |
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s->cpu_ram[2] = s->cpu_ram[5] = 0x01010101; |
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s->cpu_ram[6] = 0x00000001; |
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|
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s->iou[0] = s->iou[1] = s->iou[2] = s->iou[3] = 0x09090909; |
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s->iou[4] = s->iou[5] = 0x00090909; |
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s->iou[6] = 0x00000909; |
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|
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s->dmac_ram = 0x00000009;
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|
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s->afi[0][0] = s->afi[0][1] = 0x09090909; |
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s->afi[1][0] = s->afi[1][1] = 0x09090909; |
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s->afi[2][0] = s->afi[2][1] = 0x09090909; |
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s->afi[3][0] = s->afi[3][1] = 0x09090909; |
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s->afi[0][2] = s->afi[1][2] = s->afi[2][2] = s->afi[3][2] = 0x00000909; |
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|
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s->ocm[0] = 0x01010101; |
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s->ocm[1] = s->ocm[2] = 0x09090909; |
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|
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s->devci_ram = 0x00000909;
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s->csg_ram = 0x00000001;
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|
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s->ddriob[0] = s->ddriob[1] = s->ddriob[2] = s->ddriob[3] = 0x00000e00; |
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s->ddriob[4] = s->ddriob[5] = s->ddriob[6] = 0x00000e00; |
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s->ddriob[12] = 0x00000021; |
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} |
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|
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static inline uint32_t zynq_slcr_read_imp(void *opaque, |
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hwaddr offset) |
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{
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ZynqSLCRState *s = (ZynqSLCRState *)opaque; |
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|
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switch (offset) {
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case 0x0: /* SCL */ |
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return s->scl;
|
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case 0x4: /* LOCK */ |
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case 0x8: /* UNLOCK */ |
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DB_PRINT("Reading SCLR_LOCK/UNLOCK is not enabled\n");
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return 0; |
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case 0x0C: /* LOCKSTA */ |
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return s->lockval;
|
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case 0x100 ... 0x11C: |
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return s->pll[(offset - 0x100) / 4]; |
| 264 |
case 0x120 ... 0x16C: |
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return s->clk[(offset - 0x120) / 4]; |
| 266 |
case 0x170 ... 0x1AC: |
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return s->fpga[0][(offset - 0x170) / 4]; |
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case 0x1B0 ... 0x1D8: |
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return s->misc[(offset - 0x1B0) / 4]; |
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case 0x200 ... 0x258: |
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return s->reset[(offset - 0x200) / 4]; |
| 272 |
case 0x25c: |
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return 1; |
| 274 |
case 0x300: |
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return s->apu_ctrl;
|
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case 0x304: |
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return s->wdt_clk_sel;
|
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case 0x400 ... 0x408: |
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return s->tz_ocm[(offset - 0x400) / 4]; |
| 280 |
case 0x430: |
| 281 |
return s->tz_ddr;
|
| 282 |
case 0x440 ... 0x448: |
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return s->tz_dma[(offset - 0x440) / 4]; |
| 284 |
case 0x450 ... 0x458: |
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return s->tz_misc[(offset - 0x450) / 4]; |
| 286 |
case 0x484 ... 0x488: |
| 287 |
return s->tz_fpga[(offset - 0x484) / 4]; |
| 288 |
case 0x500: |
| 289 |
return s->dbg_ctrl;
|
| 290 |
case 0x530: |
| 291 |
return s->pss_idcode;
|
| 292 |
case 0x600 ... 0x620: |
| 293 |
if (offset == 0x604) { |
| 294 |
goto bad_reg;
|
| 295 |
} |
| 296 |
return s->ddr[(offset - 0x600) / 4]; |
| 297 |
case 0x700 ... 0x7D4: |
| 298 |
return s->mio[(offset - 0x700) / 4]; |
| 299 |
case 0x800 ... 0x810: |
| 300 |
return s->mio_func[(offset - 0x800) / 4]; |
| 301 |
case 0x830 ... 0x834: |
| 302 |
return s->sd[(offset - 0x830) / 4]; |
| 303 |
case 0x900: |
| 304 |
return s->lvl_shftr_en;
|
| 305 |
case 0x910: |
| 306 |
return s->ocm_cfg;
|
| 307 |
case 0xA00 ... 0xA1C: |
| 308 |
return s->cpu_ram[(offset - 0xA00) / 4]; |
| 309 |
case 0xA30 ... 0xA48: |
| 310 |
return s->iou[(offset - 0xA30) / 4]; |
| 311 |
case 0xA50: |
| 312 |
return s->dmac_ram;
|
| 313 |
case 0xA60 ... 0xA8C: |
| 314 |
return s->afi[0][(offset - 0xA60) / 4]; |
| 315 |
case 0xA90 ... 0xA98: |
| 316 |
return s->ocm[(offset - 0xA90) / 4]; |
| 317 |
case 0xAA0: |
| 318 |
return s->devci_ram;
|
| 319 |
case 0xAB0: |
| 320 |
return s->csg_ram;
|
| 321 |
case 0xB00 ... 0xB2C: |
| 322 |
return s->gpiob[(offset - 0xB00) / 4]; |
| 323 |
case 0xB40 ... 0xB74: |
| 324 |
return s->ddriob[(offset - 0xB40) / 4]; |
| 325 |
default:
|
| 326 |
bad_reg:
|
| 327 |
DB_PRINT("Bad register offset 0x%x\n", (int)offset); |
| 328 |
return 0; |
| 329 |
} |
| 330 |
} |
| 331 |
|
| 332 |
static uint64_t zynq_slcr_read(void *opaque, hwaddr offset, |
| 333 |
unsigned size)
|
| 334 |
{
|
| 335 |
uint32_t ret = zynq_slcr_read_imp(opaque, offset); |
| 336 |
|
| 337 |
DB_PRINT("addr: %08x data: %08x\n", offset, ret);
|
| 338 |
return ret;
|
| 339 |
} |
| 340 |
|
| 341 |
static void zynq_slcr_write(void *opaque, hwaddr offset, |
| 342 |
uint64_t val, unsigned size)
|
| 343 |
{
|
| 344 |
ZynqSLCRState *s = (ZynqSLCRState *)opaque; |
| 345 |
|
| 346 |
DB_PRINT("offset: %08x data: %08x\n", offset, (unsigned)val); |
| 347 |
|
| 348 |
switch (offset) {
|
| 349 |
case 0x00: /* SCL */ |
| 350 |
s->scl = val & 0x1;
|
| 351 |
return;
|
| 352 |
case 0x4: /* SLCR_LOCK */ |
| 353 |
if ((val & 0xFFFF) == XILINX_LOCK_KEY) { |
| 354 |
DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, |
| 355 |
(unsigned)val & 0xFFFF); |
| 356 |
s->lockval = 1;
|
| 357 |
} else {
|
| 358 |
DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
|
| 359 |
(int)offset, (unsigned)val & 0xFFFF); |
| 360 |
} |
| 361 |
return;
|
| 362 |
case 0x8: /* SLCR_UNLOCK */ |
| 363 |
if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) { |
| 364 |
DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, |
| 365 |
(unsigned)val & 0xFFFF); |
| 366 |
s->lockval = 0;
|
| 367 |
} else {
|
| 368 |
DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
|
| 369 |
(int)offset, (unsigned)val & 0xFFFF); |
| 370 |
} |
| 371 |
return;
|
| 372 |
case 0xc: /* LOCKSTA */ |
| 373 |
DB_PRINT("Writing SCLR_LOCKSTA is not enabled\n");
|
| 374 |
return;
|
| 375 |
} |
| 376 |
|
| 377 |
if (!s->lockval) {
|
| 378 |
switch (offset) {
|
| 379 |
case 0x100 ... 0x11C: |
| 380 |
if (offset == 0x10C) { |
| 381 |
goto bad_reg;
|
| 382 |
} |
| 383 |
s->pll[(offset - 0x100) / 4] = val; |
| 384 |
break;
|
| 385 |
case 0x120 ... 0x16C: |
| 386 |
s->clk[(offset - 0x120) / 4] = val; |
| 387 |
break;
|
| 388 |
case 0x170 ... 0x1AC: |
| 389 |
s->fpga[0][(offset - 0x170) / 4] = val; |
| 390 |
break;
|
| 391 |
case 0x1B0 ... 0x1D8: |
| 392 |
s->misc[(offset - 0x1B0) / 4] = val; |
| 393 |
break;
|
| 394 |
case 0x200 ... 0x25C: |
| 395 |
if (offset == 0x250) { |
| 396 |
goto bad_reg;
|
| 397 |
} |
| 398 |
s->reset[(offset - 0x200) / 4] = val; |
| 399 |
break;
|
| 400 |
case 0x300: |
| 401 |
s->apu_ctrl = val; |
| 402 |
break;
|
| 403 |
case 0x304: |
| 404 |
s->wdt_clk_sel = val; |
| 405 |
break;
|
| 406 |
case 0x400 ... 0x408: |
| 407 |
s->tz_ocm[(offset - 0x400) / 4] = val; |
| 408 |
break;
|
| 409 |
case 0x430: |
| 410 |
s->tz_ddr = val; |
| 411 |
break;
|
| 412 |
case 0x440 ... 0x448: |
| 413 |
s->tz_dma[(offset - 0x440) / 4] = val; |
| 414 |
break;
|
| 415 |
case 0x450 ... 0x458: |
| 416 |
s->tz_misc[(offset - 0x450) / 4] = val; |
| 417 |
break;
|
| 418 |
case 0x484 ... 0x488: |
| 419 |
s->tz_fpga[(offset - 0x484) / 4] = val; |
| 420 |
break;
|
| 421 |
case 0x500: |
| 422 |
s->dbg_ctrl = val; |
| 423 |
break;
|
| 424 |
case 0x530: |
| 425 |
s->pss_idcode = val; |
| 426 |
break;
|
| 427 |
case 0x600 ... 0x620: |
| 428 |
if (offset == 0x604) { |
| 429 |
goto bad_reg;
|
| 430 |
} |
| 431 |
s->ddr[(offset - 0x600) / 4] = val; |
| 432 |
break;
|
| 433 |
case 0x700 ... 0x7D4: |
| 434 |
s->mio[(offset - 0x700) / 4] = val; |
| 435 |
break;
|
| 436 |
case 0x800 ... 0x810: |
| 437 |
s->mio_func[(offset - 0x800) / 4] = val; |
| 438 |
break;
|
| 439 |
case 0x830 ... 0x834: |
| 440 |
s->sd[(offset - 0x830) / 4] = val; |
| 441 |
break;
|
| 442 |
case 0x900: |
| 443 |
s->lvl_shftr_en = val; |
| 444 |
break;
|
| 445 |
case 0x910: |
| 446 |
break;
|
| 447 |
case 0xA00 ... 0xA1C: |
| 448 |
s->cpu_ram[(offset - 0xA00) / 4] = val; |
| 449 |
break;
|
| 450 |
case 0xA30 ... 0xA48: |
| 451 |
s->iou[(offset - 0xA30) / 4] = val; |
| 452 |
break;
|
| 453 |
case 0xA50: |
| 454 |
s->dmac_ram = val; |
| 455 |
break;
|
| 456 |
case 0xA60 ... 0xA8C: |
| 457 |
s->afi[0][(offset - 0xA60) / 4] = val; |
| 458 |
break;
|
| 459 |
case 0xA90: |
| 460 |
s->ocm[0] = val;
|
| 461 |
break;
|
| 462 |
case 0xAA0: |
| 463 |
s->devci_ram = val; |
| 464 |
break;
|
| 465 |
case 0xAB0: |
| 466 |
s->csg_ram = val; |
| 467 |
break;
|
| 468 |
case 0xB00 ... 0xB2C: |
| 469 |
if (offset == 0xB20 || offset == 0xB2C) { |
| 470 |
goto bad_reg;
|
| 471 |
} |
| 472 |
s->gpiob[(offset - 0xB00) / 4] = val; |
| 473 |
break;
|
| 474 |
case 0xB40 ... 0xB74: |
| 475 |
s->ddriob[(offset - 0xB40) / 4] = val; |
| 476 |
break;
|
| 477 |
default:
|
| 478 |
bad_reg:
|
| 479 |
DB_PRINT("Bad register write %x <= %08x\n", (int)offset, val); |
| 480 |
} |
| 481 |
} else {
|
| 482 |
DB_PRINT("SCLR registers are locked. Unlock them first\n");
|
| 483 |
} |
| 484 |
} |
| 485 |
|
| 486 |
static const MemoryRegionOps slcr_ops = { |
| 487 |
.read = zynq_slcr_read, |
| 488 |
.write = zynq_slcr_write, |
| 489 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 490 |
}; |
| 491 |
|
| 492 |
static int zynq_slcr_init(SysBusDevice *dev) |
| 493 |
{
|
| 494 |
ZynqSLCRState *s = FROM_SYSBUS(ZynqSLCRState, dev); |
| 495 |
|
| 496 |
memory_region_init_io(&s->iomem, &slcr_ops, s, "slcr", 0x1000); |
| 497 |
sysbus_init_mmio(dev, &s->iomem); |
| 498 |
|
| 499 |
return 0; |
| 500 |
} |
| 501 |
|
| 502 |
static const VMStateDescription vmstate_zynq_slcr = { |
| 503 |
.name = "zynq_slcr",
|
| 504 |
.version_id = 1,
|
| 505 |
.minimum_version_id = 1,
|
| 506 |
.minimum_version_id_old = 1,
|
| 507 |
.fields = (VMStateField[]) {
|
| 508 |
VMSTATE_UINT8_ARRAY(data, ZynqSLCRState, 0x1000),
|
| 509 |
VMSTATE_END_OF_LIST() |
| 510 |
} |
| 511 |
}; |
| 512 |
|
| 513 |
static void zynq_slcr_class_init(ObjectClass *klass, void *data) |
| 514 |
{
|
| 515 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 516 |
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
| 517 |
|
| 518 |
sdc->init = zynq_slcr_init; |
| 519 |
dc->vmsd = &vmstate_zynq_slcr; |
| 520 |
dc->reset = zynq_slcr_reset; |
| 521 |
} |
| 522 |
|
| 523 |
static TypeInfo zynq_slcr_info = {
|
| 524 |
.class_init = zynq_slcr_class_init, |
| 525 |
.name = "xilinx,zynq_slcr",
|
| 526 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 527 |
.instance_size = sizeof(ZynqSLCRState),
|
| 528 |
}; |
| 529 |
|
| 530 |
static void zynq_slcr_register_types(void) |
| 531 |
{
|
| 532 |
type_register_static(&zynq_slcr_info); |
| 533 |
} |
| 534 |
|
| 535 |
type_init(zynq_slcr_register_types) |