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1 | 02645926 | balrog | /*
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2 | 02645926 | balrog | * TI OMAP on-chip I2C controller. Only "new I2C" mode supported.
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3 | 02645926 | balrog | *
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4 | 02645926 | balrog | * Copyright (C) 2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | 02645926 | balrog | *
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6 | 02645926 | balrog | * This program is free software; you can redistribute it and/or
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7 | 02645926 | balrog | * modify it under the terms of the GNU General Public License as
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8 | 02645926 | balrog | * published by the Free Software Foundation; either version 2 of
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9 | 02645926 | balrog | * the License, or (at your option) any later version.
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10 | 02645926 | balrog | *
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11 | 02645926 | balrog | * This program is distributed in the hope that it will be useful,
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12 | 02645926 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 02645926 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | 02645926 | balrog | * GNU General Public License for more details.
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15 | 02645926 | balrog | *
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16 | 02645926 | balrog | * You should have received a copy of the GNU General Public License
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17 | 02645926 | balrog | * along with this program; if not, write to the Free Software
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18 | 02645926 | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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19 | 02645926 | balrog | * MA 02111-1307 USA
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20 | 02645926 | balrog | */
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21 | 02645926 | balrog | #include "vl.h" |
22 | 02645926 | balrog | |
23 | 02645926 | balrog | struct omap_i2c_s {
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24 | 02645926 | balrog | target_phys_addr_t base; |
25 | 02645926 | balrog | qemu_irq irq; |
26 | 02645926 | balrog | qemu_irq drq[2];
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27 | 02645926 | balrog | i2c_slave slave; |
28 | 02645926 | balrog | i2c_bus *bus; |
29 | 02645926 | balrog | |
30 | 02645926 | balrog | uint8_t mask; |
31 | 02645926 | balrog | uint16_t stat; |
32 | 02645926 | balrog | uint16_t dma; |
33 | 02645926 | balrog | uint16_t count; |
34 | 02645926 | balrog | int count_cur;
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35 | 02645926 | balrog | uint32_t fifo; |
36 | 02645926 | balrog | int rxlen;
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37 | 02645926 | balrog | int txlen;
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38 | 02645926 | balrog | uint16_t control; |
39 | 02645926 | balrog | uint16_t addr[2];
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40 | 02645926 | balrog | uint8_t divider; |
41 | 02645926 | balrog | uint8_t times[2];
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42 | 02645926 | balrog | uint16_t test; |
43 | 02645926 | balrog | }; |
44 | 02645926 | balrog | |
45 | 02645926 | balrog | static void omap_i2c_interrupts_update(struct omap_i2c_s *s) |
46 | 02645926 | balrog | { |
47 | 02645926 | balrog | qemu_set_irq(s->irq, s->stat & s->mask); |
48 | 02645926 | balrog | if ((s->dma >> 15) & 1) /* RDMA_EN */ |
49 | 02645926 | balrog | qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */ |
50 | 02645926 | balrog | if ((s->dma >> 7) & 1) /* XDMA_EN */ |
51 | 02645926 | balrog | qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */ |
52 | 02645926 | balrog | } |
53 | 02645926 | balrog | |
54 | 02645926 | balrog | /* These are only stubs now. */
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55 | 02645926 | balrog | static void omap_i2c_event(i2c_slave *i2c, enum i2c_event event) |
56 | 02645926 | balrog | { |
57 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) i2c; |
58 | 02645926 | balrog | |
59 | 02645926 | balrog | if ((~s->control >> 15) & 1) /* I2C_EN */ |
60 | 02645926 | balrog | return;
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61 | 02645926 | balrog | |
62 | 02645926 | balrog | switch (event) {
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63 | 02645926 | balrog | case I2C_START_SEND:
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64 | 02645926 | balrog | case I2C_START_RECV:
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65 | 02645926 | balrog | s->stat |= 1 << 9; /* AAS */ |
66 | 02645926 | balrog | break;
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67 | 02645926 | balrog | case I2C_FINISH:
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68 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
69 | 02645926 | balrog | break;
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70 | 02645926 | balrog | case I2C_NACK:
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71 | 02645926 | balrog | s->stat |= 1 << 1; /* NACK */ |
72 | 02645926 | balrog | break;
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73 | 02645926 | balrog | } |
74 | 02645926 | balrog | |
75 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
76 | 02645926 | balrog | } |
77 | 02645926 | balrog | |
78 | 02645926 | balrog | static int omap_i2c_rx(i2c_slave *i2c) |
79 | 02645926 | balrog | { |
80 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) i2c; |
81 | 02645926 | balrog | uint8_t ret = 0;
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82 | 02645926 | balrog | |
83 | 02645926 | balrog | if ((~s->control >> 15) & 1) /* I2C_EN */ |
84 | 02645926 | balrog | return -1; |
85 | 02645926 | balrog | |
86 | 02645926 | balrog | if (s->txlen)
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87 | 02645926 | balrog | ret = s->fifo >> ((-- s->txlen) << 3) & 0xff; |
88 | 02645926 | balrog | else
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89 | 02645926 | balrog | s->stat |= 1 << 10; /* XUDF */ |
90 | 02645926 | balrog | s->stat |= 1 << 4; /* XRDY */ |
91 | 02645926 | balrog | |
92 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
93 | 02645926 | balrog | return ret;
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94 | 02645926 | balrog | } |
95 | 02645926 | balrog | |
96 | 02645926 | balrog | static int omap_i2c_tx(i2c_slave *i2c, uint8_t data) |
97 | 02645926 | balrog | { |
98 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) i2c; |
99 | 02645926 | balrog | |
100 | 02645926 | balrog | if ((~s->control >> 15) & 1) /* I2C_EN */ |
101 | 02645926 | balrog | return 1; |
102 | 02645926 | balrog | |
103 | 02645926 | balrog | if (s->rxlen < 4) |
104 | 02645926 | balrog | s->fifo |= data << ((s->rxlen ++) << 3);
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105 | 02645926 | balrog | else
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106 | 02645926 | balrog | s->stat |= 1 << 11; /* ROVR */ |
107 | 02645926 | balrog | s->stat |= 1 << 3; /* RRDY */ |
108 | 02645926 | balrog | |
109 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
110 | 02645926 | balrog | return 1; |
111 | 02645926 | balrog | } |
112 | 02645926 | balrog | |
113 | 02645926 | balrog | static void omap_i2c_fifo_run(struct omap_i2c_s *s) |
114 | 02645926 | balrog | { |
115 | 02645926 | balrog | int ack = 1; |
116 | 02645926 | balrog | |
117 | 02645926 | balrog | if (!i2c_bus_busy(s->bus))
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118 | 02645926 | balrog | return;
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119 | 02645926 | balrog | |
120 | 02645926 | balrog | if ((s->control >> 2) & 1) { /* RM */ |
121 | 02645926 | balrog | if ((s->control >> 1) & 1) { /* STP */ |
122 | 02645926 | balrog | i2c_end_transfer(s->bus); |
123 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
124 | 02645926 | balrog | s->count_cur = s->count; |
125 | 02645926 | balrog | } else if ((s->control >> 9) & 1) { /* TRX */ |
126 | 02645926 | balrog | while (ack && s->txlen)
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127 | 02645926 | balrog | ack = (i2c_send(s->bus, |
128 | 02645926 | balrog | (s->fifo >> ((-- s->txlen) << 3)) &
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129 | 02645926 | balrog | 0xff) >= 0); |
130 | 02645926 | balrog | s->stat |= 1 << 4; /* XRDY */ |
131 | 02645926 | balrog | } else {
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132 | 02645926 | balrog | while (s->rxlen < 4) |
133 | 02645926 | balrog | s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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134 | 02645926 | balrog | s->stat |= 1 << 3; /* RRDY */ |
135 | 02645926 | balrog | } |
136 | 02645926 | balrog | } else {
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137 | 02645926 | balrog | if ((s->control >> 9) & 1) { /* TRX */ |
138 | 02645926 | balrog | while (ack && s->count_cur && s->txlen) {
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139 | 02645926 | balrog | ack = (i2c_send(s->bus, |
140 | 02645926 | balrog | (s->fifo >> ((-- s->txlen) << 3)) &
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141 | 02645926 | balrog | 0xff) >= 0); |
142 | 02645926 | balrog | s->count_cur --; |
143 | 02645926 | balrog | } |
144 | 02645926 | balrog | if (ack && s->count_cur)
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145 | 02645926 | balrog | s->stat |= 1 << 4; /* XRDY */ |
146 | 02645926 | balrog | if (!s->count_cur) {
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147 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
148 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
149 | 02645926 | balrog | } |
150 | 02645926 | balrog | } else {
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151 | 02645926 | balrog | while (s->count_cur && s->rxlen < 4) { |
152 | 02645926 | balrog | s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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153 | 02645926 | balrog | s->count_cur --; |
154 | 02645926 | balrog | } |
155 | 02645926 | balrog | if (s->rxlen)
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156 | 02645926 | balrog | s->stat |= 1 << 3; /* RRDY */ |
157 | 02645926 | balrog | } |
158 | 02645926 | balrog | if (!s->count_cur) {
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159 | 02645926 | balrog | if ((s->control >> 1) & 1) { /* STP */ |
160 | 02645926 | balrog | i2c_end_transfer(s->bus); |
161 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
162 | 02645926 | balrog | s->count_cur = s->count; |
163 | 02645926 | balrog | } else {
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164 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
165 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
166 | 02645926 | balrog | } |
167 | 02645926 | balrog | } |
168 | 02645926 | balrog | } |
169 | 02645926 | balrog | |
170 | 02645926 | balrog | s->stat |= (!ack) << 1; /* NACK */ |
171 | 02645926 | balrog | if (!ack)
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172 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
173 | 02645926 | balrog | } |
174 | 02645926 | balrog | |
175 | 02645926 | balrog | void omap_i2c_reset(struct omap_i2c_s *s) |
176 | 02645926 | balrog | { |
177 | 02645926 | balrog | s->mask = 0;
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178 | 02645926 | balrog | s->stat = 0;
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179 | 02645926 | balrog | s->dma = 0;
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180 | 02645926 | balrog | s->count = 0;
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181 | 02645926 | balrog | s->count_cur = 0;
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182 | 02645926 | balrog | s->fifo = 0;
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183 | 02645926 | balrog | s->rxlen = 0;
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184 | 02645926 | balrog | s->txlen = 0;
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185 | 02645926 | balrog | s->control = 0;
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186 | 02645926 | balrog | s->addr[0] = 0; |
187 | 02645926 | balrog | s->addr[1] = 0; |
188 | 02645926 | balrog | s->divider = 0;
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189 | 02645926 | balrog | s->times[0] = 0; |
190 | 02645926 | balrog | s->times[1] = 0; |
191 | 02645926 | balrog | s->test = 0;
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192 | 02645926 | balrog | } |
193 | 02645926 | balrog | |
194 | 02645926 | balrog | static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr) |
195 | 02645926 | balrog | { |
196 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
197 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
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198 | 02645926 | balrog | uint16_t ret; |
199 | 02645926 | balrog | |
200 | 02645926 | balrog | switch (offset) {
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201 | 02645926 | balrog | case 0x00: /* I2C_REV */ |
202 | 02645926 | balrog | /* TODO: set a value greater or equal to real hardware */
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203 | 02645926 | balrog | return 0x11; /* REV */ |
204 | 02645926 | balrog | |
205 | 02645926 | balrog | case 0x04: /* I2C_IE */ |
206 | 02645926 | balrog | return s->mask;
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207 | 02645926 | balrog | |
208 | 02645926 | balrog | case 0x08: /* I2C_STAT */ |
209 | 02645926 | balrog | return s->stat | (i2c_bus_busy(s->bus) << 12); |
210 | 02645926 | balrog | |
211 | 02645926 | balrog | case 0x0c: /* I2C_IV */ |
212 | 02645926 | balrog | ret = ffs(s->stat & s->mask); |
213 | 02645926 | balrog | if (ret)
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214 | 02645926 | balrog | s->stat ^= 1 << (ret - 1); |
215 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
216 | 02645926 | balrog | return ret;
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217 | 02645926 | balrog | |
218 | 02645926 | balrog | case 0x14: /* I2C_BUF */ |
219 | 02645926 | balrog | return s->dma;
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220 | 02645926 | balrog | |
221 | 02645926 | balrog | case 0x18: /* I2C_CNT */ |
222 | 02645926 | balrog | return s->count_cur; /* DCOUNT */ |
223 | 02645926 | balrog | |
224 | 02645926 | balrog | case 0x1c: /* I2C_DATA */ |
225 | 02645926 | balrog | ret = 0;
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226 | 02645926 | balrog | if (s->control & (1 << 14)) { /* BE */ |
227 | 02645926 | balrog | ret |= ((s->fifo >> 0) & 0xff) << 8; |
228 | 02645926 | balrog | ret |= ((s->fifo >> 8) & 0xff) << 0; |
229 | 02645926 | balrog | } else {
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230 | 02645926 | balrog | ret |= ((s->fifo >> 8) & 0xff) << 8; |
231 | 02645926 | balrog | ret |= ((s->fifo >> 0) & 0xff) << 0; |
232 | 02645926 | balrog | } |
233 | 02645926 | balrog | if (s->rxlen == 1) { |
234 | 02645926 | balrog | s->stat |= 1 << 15; /* SBD */ |
235 | 02645926 | balrog | s->rxlen = 0;
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236 | 02645926 | balrog | } else if (s->rxlen > 1) { |
237 | 02645926 | balrog | if (s->rxlen > 2) |
238 | 02645926 | balrog | s->fifo >>= 16;
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239 | 02645926 | balrog | s->rxlen -= 2;
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240 | 02645926 | balrog | } else
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241 | 02645926 | balrog | /* XXX: remote access (qualifier) error - what's that? */;
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242 | 02645926 | balrog | if (!s->rxlen) {
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243 | 02645926 | balrog | s->stat |= ~(1 << 3); /* RRDY */ |
244 | 02645926 | balrog | if (((s->control >> 10) & 1) && /* MST */ |
245 | 02645926 | balrog | ((~s->control >> 9) & 1)) { /* TRX */ |
246 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
247 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
248 | 02645926 | balrog | } |
249 | 02645926 | balrog | } |
250 | 02645926 | balrog | s->stat &= ~(1 << 11); /* ROVR */ |
251 | 02645926 | balrog | omap_i2c_fifo_run(s); |
252 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
253 | 02645926 | balrog | return ret;
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254 | 02645926 | balrog | |
255 | 02645926 | balrog | case 0x24: /* I2C_CON */ |
256 | 02645926 | balrog | return s->control;
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257 | 02645926 | balrog | |
258 | 02645926 | balrog | case 0x28: /* I2C_OA */ |
259 | 02645926 | balrog | return s->addr[0]; |
260 | 02645926 | balrog | |
261 | 02645926 | balrog | case 0x2c: /* I2C_SA */ |
262 | 02645926 | balrog | return s->addr[1]; |
263 | 02645926 | balrog | |
264 | 02645926 | balrog | case 0x30: /* I2C_PSC */ |
265 | 02645926 | balrog | return s->divider;
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266 | 02645926 | balrog | |
267 | 02645926 | balrog | case 0x34: /* I2C_SCLL */ |
268 | 02645926 | balrog | return s->times[0]; |
269 | 02645926 | balrog | |
270 | 02645926 | balrog | case 0x38: /* I2C_SCLH */ |
271 | 02645926 | balrog | return s->times[1]; |
272 | 02645926 | balrog | |
273 | 02645926 | balrog | case 0x3c: /* I2C_SYSTEST */ |
274 | 02645926 | balrog | if (s->test & (1 << 15)) { /* ST_EN */ |
275 | 02645926 | balrog | s->test ^= 0xa;
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276 | 02645926 | balrog | return s->test;
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277 | 02645926 | balrog | } else
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278 | 02645926 | balrog | return s->test & ~0x300f; |
279 | 02645926 | balrog | } |
280 | 02645926 | balrog | |
281 | 02645926 | balrog | OMAP_BAD_REG(addr); |
282 | 02645926 | balrog | return 0; |
283 | 02645926 | balrog | } |
284 | 02645926 | balrog | |
285 | 02645926 | balrog | static void omap_i2c_write(void *opaque, target_phys_addr_t addr, |
286 | 02645926 | balrog | uint32_t value) |
287 | 02645926 | balrog | { |
288 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
289 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
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290 | 02645926 | balrog | int nack;
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291 | 02645926 | balrog | |
292 | 02645926 | balrog | switch (offset) {
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293 | 02645926 | balrog | case 0x00: /* I2C_REV */ |
294 | 02645926 | balrog | case 0x08: /* I2C_STAT */ |
295 | 02645926 | balrog | case 0x0c: /* I2C_IV */ |
296 | 02645926 | balrog | OMAP_BAD_REG(addr); |
297 | 02645926 | balrog | return;
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298 | 02645926 | balrog | |
299 | 02645926 | balrog | case 0x04: /* I2C_IE */ |
300 | 02645926 | balrog | s->mask = value & 0x1f;
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301 | 02645926 | balrog | break;
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302 | 02645926 | balrog | |
303 | 02645926 | balrog | case 0x14: /* I2C_BUF */ |
304 | 02645926 | balrog | s->dma = value & 0x8080;
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305 | 02645926 | balrog | if (value & (1 << 15)) /* RDMA_EN */ |
306 | 02645926 | balrog | s->mask &= ~(1 << 3); /* RRDY_IE */ |
307 | 02645926 | balrog | if (value & (1 << 7)) /* XDMA_EN */ |
308 | 02645926 | balrog | s->mask &= ~(1 << 4); /* XRDY_IE */ |
309 | 02645926 | balrog | break;
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310 | 02645926 | balrog | |
311 | 02645926 | balrog | case 0x18: /* I2C_CNT */ |
312 | 02645926 | balrog | s->count = value; /* DCOUNT */
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313 | 02645926 | balrog | break;
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314 | 02645926 | balrog | |
315 | 02645926 | balrog | case 0x1c: /* I2C_DATA */ |
316 | 02645926 | balrog | if (s->txlen > 2) { |
317 | 02645926 | balrog | /* XXX: remote access (qualifier) error - what's that? */
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318 | 02645926 | balrog | break;
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319 | 02645926 | balrog | } |
320 | 02645926 | balrog | s->fifo <<= 16;
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321 | 02645926 | balrog | s->txlen += 2;
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322 | 02645926 | balrog | if (s->control & (1 << 14)) { /* BE */ |
323 | 02645926 | balrog | s->fifo |= ((value >> 8) & 0xff) << 8; |
324 | 02645926 | balrog | s->fifo |= ((value >> 0) & 0xff) << 0; |
325 | 02645926 | balrog | } else {
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326 | 02645926 | balrog | s->fifo |= ((value >> 0) & 0xff) << 8; |
327 | 02645926 | balrog | s->fifo |= ((value >> 8) & 0xff) << 0; |
328 | 02645926 | balrog | } |
329 | 02645926 | balrog | s->stat &= ~(1 << 10); /* XUDF */ |
330 | 02645926 | balrog | if (s->txlen > 2) |
331 | 02645926 | balrog | s->stat &= ~(1 << 4); /* XRDY */ |
332 | 02645926 | balrog | omap_i2c_fifo_run(s); |
333 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
334 | 02645926 | balrog | break;
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335 | 02645926 | balrog | |
336 | 02645926 | balrog | case 0x24: /* I2C_CON */ |
337 | 02645926 | balrog | s->control = value & 0xcf07;
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338 | 02645926 | balrog | if (~value & (1 << 15)) { /* I2C_EN */ |
339 | 02645926 | balrog | omap_i2c_reset(s); |
340 | 02645926 | balrog | break;
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341 | 02645926 | balrog | } |
342 | 02645926 | balrog | if (~value & (1 << 10)) { /* MST */ |
343 | 02645926 | balrog | printf("%s: I^2C slave mode not supported\n", __FUNCTION__);
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344 | 02645926 | balrog | break;
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345 | 02645926 | balrog | } |
346 | 02645926 | balrog | if (value & (1 << 9)) { /* XA */ |
347 | 02645926 | balrog | printf("%s: 10-bit addressing mode not supported\n", __FUNCTION__);
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348 | 02645926 | balrog | break;
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349 | 02645926 | balrog | } |
350 | 02645926 | balrog | if (value & (1 << 0)) { /* STT */ |
351 | 02645926 | balrog | nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */ |
352 | 02645926 | balrog | (~value >> 9) & 1); /* TRX */ |
353 | 02645926 | balrog | s->stat |= nack << 1; /* NACK */ |
354 | 02645926 | balrog | s->control &= ~(1 << 0); /* STT */ |
355 | 02645926 | balrog | if (nack)
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356 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
357 | 02645926 | balrog | else
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358 | 02645926 | balrog | omap_i2c_fifo_run(s); |
359 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
360 | 02645926 | balrog | } |
361 | 02645926 | balrog | break;
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362 | 02645926 | balrog | |
363 | 02645926 | balrog | case 0x28: /* I2C_OA */ |
364 | 02645926 | balrog | s->addr[0] = value & 0x3ff; |
365 | 02645926 | balrog | i2c_set_slave_address(&s->slave, value & 0x7f);
|
366 | 02645926 | balrog | break;
|
367 | 02645926 | balrog | |
368 | 02645926 | balrog | case 0x2c: /* I2C_SA */ |
369 | 02645926 | balrog | s->addr[1] = value & 0x3ff; |
370 | 02645926 | balrog | break;
|
371 | 02645926 | balrog | |
372 | 02645926 | balrog | case 0x30: /* I2C_PSC */ |
373 | 02645926 | balrog | s->divider = value; |
374 | 02645926 | balrog | break;
|
375 | 02645926 | balrog | |
376 | 02645926 | balrog | case 0x34: /* I2C_SCLL */ |
377 | 02645926 | balrog | s->times[0] = value;
|
378 | 02645926 | balrog | break;
|
379 | 02645926 | balrog | |
380 | 02645926 | balrog | case 0x38: /* I2C_SCLH */ |
381 | 02645926 | balrog | s->times[1] = value;
|
382 | 02645926 | balrog | break;
|
383 | 02645926 | balrog | |
384 | 02645926 | balrog | case 0x3c: /* I2C_SYSTEST */ |
385 | 02645926 | balrog | s->test = value & 0xf00f;
|
386 | 02645926 | balrog | if (value & (1 << 15)) /* ST_EN */ |
387 | 02645926 | balrog | printf("%s: System Test not supported\n", __FUNCTION__);
|
388 | 02645926 | balrog | break;
|
389 | 02645926 | balrog | |
390 | 02645926 | balrog | default:
|
391 | 02645926 | balrog | OMAP_BAD_REG(addr); |
392 | 02645926 | balrog | return;
|
393 | 02645926 | balrog | } |
394 | 02645926 | balrog | } |
395 | 02645926 | balrog | |
396 | 02645926 | balrog | static CPUReadMemoryFunc *omap_i2c_readfn[] = {
|
397 | 02645926 | balrog | omap_badwidth_read16, |
398 | 02645926 | balrog | omap_i2c_read, |
399 | 02645926 | balrog | omap_badwidth_read16, |
400 | 02645926 | balrog | }; |
401 | 02645926 | balrog | |
402 | 02645926 | balrog | static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
|
403 | 02645926 | balrog | omap_badwidth_write16, |
404 | 02645926 | balrog | omap_i2c_write, |
405 | 02645926 | balrog | omap_i2c_write, /* TODO: Only the last fifo write can be 8 bit. */
|
406 | 02645926 | balrog | }; |
407 | 02645926 | balrog | |
408 | 02645926 | balrog | struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
|
409 | 02645926 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk clk) |
410 | 02645926 | balrog | { |
411 | 02645926 | balrog | int iomemtype;
|
412 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) |
413 | 02645926 | balrog | qemu_mallocz(sizeof(struct omap_i2c_s)); |
414 | 02645926 | balrog | |
415 | 02645926 | balrog | s->base = base; |
416 | 02645926 | balrog | s->irq = irq; |
417 | 02645926 | balrog | s->drq[0] = dma[0]; |
418 | 02645926 | balrog | s->drq[1] = dma[1]; |
419 | 02645926 | balrog | s->slave.event = omap_i2c_event; |
420 | 02645926 | balrog | s->slave.recv = omap_i2c_rx; |
421 | 02645926 | balrog | s->slave.send = omap_i2c_tx; |
422 | 02645926 | balrog | s->bus = i2c_init_bus(); |
423 | 02645926 | balrog | omap_i2c_reset(s); |
424 | 02645926 | balrog | |
425 | 02645926 | balrog | iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
|
426 | 02645926 | balrog | omap_i2c_writefn, s); |
427 | 02645926 | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
428 | 02645926 | balrog | |
429 | 02645926 | balrog | return s;
|
430 | 02645926 | balrog | } |
431 | 02645926 | balrog | |
432 | 02645926 | balrog | i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
|
433 | 02645926 | balrog | { |
434 | 02645926 | balrog | return s->bus;
|
435 | 02645926 | balrog | } |