root / hw / slavio_misc.c @ 1e414679
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1 | 3475187d | bellard | /*
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2 | 3475187d | bellard | * QEMU Sparc SLAVIO aux io port emulation
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 3475187d | bellard | #include "vl.h" |
25 | 3475187d | bellard | /* debug misc */
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26 | 3475187d | bellard | //#define DEBUG_MISC
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27 | 3475187d | bellard | |
28 | 3475187d | bellard | /*
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29 | 3475187d | bellard | * This is the auxio port, chip control and system control part of
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30 | 3475187d | bellard | * chip STP2001 (Slave I/O), also produced as NCR89C105. See
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31 | 3475187d | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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32 | 3475187d | bellard | *
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33 | 3475187d | bellard | * This also includes the PMC CPU idle controller.
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34 | 3475187d | bellard | */
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35 | 3475187d | bellard | |
36 | 3475187d | bellard | #ifdef DEBUG_MISC
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37 | 3475187d | bellard | #define MISC_DPRINTF(fmt, args...) \
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38 | 3475187d | bellard | do { printf("MISC: " fmt , ##args); } while (0) |
39 | 3475187d | bellard | #else
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40 | 3475187d | bellard | #define MISC_DPRINTF(fmt, args...)
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41 | 3475187d | bellard | #endif
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42 | 3475187d | bellard | |
43 | 3475187d | bellard | typedef struct MiscState { |
44 | d537cf6c | pbrook | qemu_irq irq; |
45 | 3475187d | bellard | uint8_t config; |
46 | 3475187d | bellard | uint8_t aux1, aux2; |
47 | bfa30a38 | blueswir1 | uint8_t diag, mctrl; |
48 | bfa30a38 | blueswir1 | uint32_t sysctrl; |
49 | 6a3b9cc9 | blueswir1 | uint16_t leds; |
50 | 3475187d | bellard | } MiscState; |
51 | 3475187d | bellard | |
52 | 5aca8c3b | blueswir1 | #define MISC_SIZE 1 |
53 | bfa30a38 | blueswir1 | #define SYSCTRL_MAXADDR 3 |
54 | bfa30a38 | blueswir1 | #define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1) |
55 | 6a3b9cc9 | blueswir1 | #define LED_MAXADDR 2 |
56 | 6a3b9cc9 | blueswir1 | #define LED_SIZE (LED_MAXADDR + 1) |
57 | 3475187d | bellard | |
58 | 3475187d | bellard | static void slavio_misc_update_irq(void *opaque) |
59 | 3475187d | bellard | { |
60 | 3475187d | bellard | MiscState *s = opaque; |
61 | 3475187d | bellard | |
62 | 3475187d | bellard | if ((s->aux2 & 0x4) && (s->config & 0x8)) { |
63 | d537cf6c | pbrook | MISC_DPRINTF("Raise IRQ\n");
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64 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
65 | 3475187d | bellard | } else {
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66 | d537cf6c | pbrook | MISC_DPRINTF("Lower IRQ\n");
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67 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
68 | 3475187d | bellard | } |
69 | 3475187d | bellard | } |
70 | 3475187d | bellard | |
71 | 3475187d | bellard | static void slavio_misc_reset(void *opaque) |
72 | 3475187d | bellard | { |
73 | 3475187d | bellard | MiscState *s = opaque; |
74 | 3475187d | bellard | |
75 | 4e3b1ea1 | bellard | // Diagnostic and system control registers not cleared in reset
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76 | 3475187d | bellard | s->config = s->aux1 = s->aux2 = s->mctrl = 0;
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77 | 3475187d | bellard | } |
78 | 3475187d | bellard | |
79 | 3475187d | bellard | void slavio_set_power_fail(void *opaque, int power_failing) |
80 | 3475187d | bellard | { |
81 | 3475187d | bellard | MiscState *s = opaque; |
82 | 3475187d | bellard | |
83 | 3475187d | bellard | MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
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84 | 3475187d | bellard | if (power_failing && (s->config & 0x8)) { |
85 | f930d07e | blueswir1 | s->aux2 |= 0x4;
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86 | 3475187d | bellard | } else {
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87 | f930d07e | blueswir1 | s->aux2 &= ~0x4;
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88 | 3475187d | bellard | } |
89 | 3475187d | bellard | slavio_misc_update_irq(s); |
90 | 3475187d | bellard | } |
91 | 3475187d | bellard | |
92 | bfa30a38 | blueswir1 | static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, |
93 | bfa30a38 | blueswir1 | uint32_t val) |
94 | 3475187d | bellard | { |
95 | 3475187d | bellard | MiscState *s = opaque; |
96 | 3475187d | bellard | |
97 | 3475187d | bellard | switch (addr & 0xfff0000) { |
98 | 3475187d | bellard | case 0x1800000: |
99 | f930d07e | blueswir1 | MISC_DPRINTF("Write config %2.2x\n", val & 0xff); |
100 | f930d07e | blueswir1 | s->config = val & 0xff;
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101 | f930d07e | blueswir1 | slavio_misc_update_irq(s); |
102 | f930d07e | blueswir1 | break;
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103 | 3475187d | bellard | case 0x1900000: |
104 | f930d07e | blueswir1 | MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); |
105 | f930d07e | blueswir1 | s->aux1 = val & 0xff;
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106 | f930d07e | blueswir1 | break;
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107 | 3475187d | bellard | case 0x1910000: |
108 | f930d07e | blueswir1 | val &= 0x3;
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109 | f930d07e | blueswir1 | MISC_DPRINTF("Write aux2 %2.2x\n", val);
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110 | f930d07e | blueswir1 | val |= s->aux2 & 0x4;
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111 | f930d07e | blueswir1 | if (val & 0x2) // Clear Power Fail int |
112 | f930d07e | blueswir1 | val &= 0x1;
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113 | f930d07e | blueswir1 | s->aux2 = val; |
114 | f930d07e | blueswir1 | if (val & 1) |
115 | f930d07e | blueswir1 | qemu_system_shutdown_request(); |
116 | f930d07e | blueswir1 | slavio_misc_update_irq(s); |
117 | f930d07e | blueswir1 | break;
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118 | 3475187d | bellard | case 0x1a00000: |
119 | f930d07e | blueswir1 | MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); |
120 | f930d07e | blueswir1 | s->diag = val & 0xff;
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121 | f930d07e | blueswir1 | break;
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122 | 3475187d | bellard | case 0x1b00000: |
123 | f930d07e | blueswir1 | MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); |
124 | f930d07e | blueswir1 | s->mctrl = val & 0xff;
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125 | f930d07e | blueswir1 | break;
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126 | 3475187d | bellard | case 0xa000000: |
127 | f930d07e | blueswir1 | MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); |
128 | ba3c64fb | bellard | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
129 | f930d07e | blueswir1 | break;
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130 | 3475187d | bellard | } |
131 | 3475187d | bellard | } |
132 | 3475187d | bellard | |
133 | 3475187d | bellard | static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr) |
134 | 3475187d | bellard | { |
135 | 3475187d | bellard | MiscState *s = opaque; |
136 | 3475187d | bellard | uint32_t ret = 0;
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137 | 3475187d | bellard | |
138 | 3475187d | bellard | switch (addr & 0xfff0000) { |
139 | 3475187d | bellard | case 0x1800000: |
140 | f930d07e | blueswir1 | ret = s->config; |
141 | f930d07e | blueswir1 | MISC_DPRINTF("Read config %2.2x\n", ret);
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142 | f930d07e | blueswir1 | break;
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143 | 3475187d | bellard | case 0x1900000: |
144 | f930d07e | blueswir1 | ret = s->aux1; |
145 | f930d07e | blueswir1 | MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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146 | f930d07e | blueswir1 | break;
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147 | 3475187d | bellard | case 0x1910000: |
148 | f930d07e | blueswir1 | ret = s->aux2; |
149 | f930d07e | blueswir1 | MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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150 | f930d07e | blueswir1 | break;
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151 | 3475187d | bellard | case 0x1a00000: |
152 | f930d07e | blueswir1 | ret = s->diag; |
153 | f930d07e | blueswir1 | MISC_DPRINTF("Read diag %2.2x\n", ret);
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154 | f930d07e | blueswir1 | break;
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155 | 3475187d | bellard | case 0x1b00000: |
156 | f930d07e | blueswir1 | ret = s->mctrl; |
157 | f930d07e | blueswir1 | MISC_DPRINTF("Read modem control %2.2x\n", ret);
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158 | f930d07e | blueswir1 | break;
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159 | 3475187d | bellard | case 0xa000000: |
160 | f930d07e | blueswir1 | MISC_DPRINTF("Read power management %2.2x\n", ret);
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161 | f930d07e | blueswir1 | break;
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162 | 3475187d | bellard | } |
163 | 3475187d | bellard | return ret;
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164 | 3475187d | bellard | } |
165 | 3475187d | bellard | |
166 | 3475187d | bellard | static CPUReadMemoryFunc *slavio_misc_mem_read[3] = { |
167 | 3475187d | bellard | slavio_misc_mem_readb, |
168 | 3475187d | bellard | slavio_misc_mem_readb, |
169 | 3475187d | bellard | slavio_misc_mem_readb, |
170 | 3475187d | bellard | }; |
171 | 3475187d | bellard | |
172 | 3475187d | bellard | static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = { |
173 | 3475187d | bellard | slavio_misc_mem_writeb, |
174 | 3475187d | bellard | slavio_misc_mem_writeb, |
175 | 3475187d | bellard | slavio_misc_mem_writeb, |
176 | 3475187d | bellard | }; |
177 | 3475187d | bellard | |
178 | bfa30a38 | blueswir1 | static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) |
179 | bfa30a38 | blueswir1 | { |
180 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
181 | bfa30a38 | blueswir1 | uint32_t ret = 0, saddr;
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182 | bfa30a38 | blueswir1 | |
183 | bfa30a38 | blueswir1 | saddr = addr & SYSCTRL_MAXADDR; |
184 | bfa30a38 | blueswir1 | switch (saddr) {
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185 | bfa30a38 | blueswir1 | case 0: |
186 | bfa30a38 | blueswir1 | ret = s->sysctrl; |
187 | bfa30a38 | blueswir1 | break;
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188 | bfa30a38 | blueswir1 | default:
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189 | bfa30a38 | blueswir1 | break;
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190 | bfa30a38 | blueswir1 | } |
191 | bfa30a38 | blueswir1 | MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr, |
192 | bfa30a38 | blueswir1 | ret); |
193 | bfa30a38 | blueswir1 | return ret;
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194 | bfa30a38 | blueswir1 | } |
195 | bfa30a38 | blueswir1 | |
196 | bfa30a38 | blueswir1 | static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr, |
197 | bfa30a38 | blueswir1 | uint32_t val) |
198 | bfa30a38 | blueswir1 | { |
199 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
200 | bfa30a38 | blueswir1 | uint32_t saddr; |
201 | bfa30a38 | blueswir1 | |
202 | bfa30a38 | blueswir1 | saddr = addr & SYSCTRL_MAXADDR; |
203 | bfa30a38 | blueswir1 | MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " = %x\n", addr, |
204 | bfa30a38 | blueswir1 | val); |
205 | bfa30a38 | blueswir1 | switch (saddr) {
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206 | bfa30a38 | blueswir1 | case 0: |
207 | bfa30a38 | blueswir1 | if (val & 1) { |
208 | bfa30a38 | blueswir1 | s->sysctrl = 0x2;
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209 | bfa30a38 | blueswir1 | qemu_system_reset_request(); |
210 | bfa30a38 | blueswir1 | } |
211 | bfa30a38 | blueswir1 | break;
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212 | bfa30a38 | blueswir1 | default:
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213 | bfa30a38 | blueswir1 | break;
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214 | bfa30a38 | blueswir1 | } |
215 | bfa30a38 | blueswir1 | } |
216 | bfa30a38 | blueswir1 | |
217 | bfa30a38 | blueswir1 | static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = { |
218 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_readl, |
219 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_readl, |
220 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_readl, |
221 | bfa30a38 | blueswir1 | }; |
222 | bfa30a38 | blueswir1 | |
223 | bfa30a38 | blueswir1 | static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = { |
224 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_writel, |
225 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_writel, |
226 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_writel, |
227 | bfa30a38 | blueswir1 | }; |
228 | bfa30a38 | blueswir1 | |
229 | 6a3b9cc9 | blueswir1 | static uint32_t slavio_led_mem_reads(void *opaque, target_phys_addr_t addr) |
230 | 6a3b9cc9 | blueswir1 | { |
231 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
232 | 6a3b9cc9 | blueswir1 | uint32_t ret = 0, saddr;
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233 | 6a3b9cc9 | blueswir1 | |
234 | 6a3b9cc9 | blueswir1 | saddr = addr & LED_MAXADDR; |
235 | 6a3b9cc9 | blueswir1 | switch (saddr) {
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236 | 6a3b9cc9 | blueswir1 | case 0: |
237 | 6a3b9cc9 | blueswir1 | ret = s->leds; |
238 | 6a3b9cc9 | blueswir1 | break;
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239 | 6a3b9cc9 | blueswir1 | default:
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240 | 6a3b9cc9 | blueswir1 | break;
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241 | 6a3b9cc9 | blueswir1 | } |
242 | 6a3b9cc9 | blueswir1 | MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr, |
243 | 6a3b9cc9 | blueswir1 | ret); |
244 | 6a3b9cc9 | blueswir1 | return ret;
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245 | 6a3b9cc9 | blueswir1 | } |
246 | 6a3b9cc9 | blueswir1 | |
247 | 6a3b9cc9 | blueswir1 | static void slavio_led_mem_writes(void *opaque, target_phys_addr_t addr, |
248 | 6a3b9cc9 | blueswir1 | uint32_t val) |
249 | 6a3b9cc9 | blueswir1 | { |
250 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
251 | 6a3b9cc9 | blueswir1 | uint32_t saddr; |
252 | 6a3b9cc9 | blueswir1 | |
253 | 6a3b9cc9 | blueswir1 | saddr = addr & LED_MAXADDR; |
254 | 6a3b9cc9 | blueswir1 | MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr, |
255 | 6a3b9cc9 | blueswir1 | val); |
256 | 6a3b9cc9 | blueswir1 | switch (saddr) {
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257 | 6a3b9cc9 | blueswir1 | case 0: |
258 | 6a3b9cc9 | blueswir1 | s->sysctrl = val; |
259 | 6a3b9cc9 | blueswir1 | break;
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260 | 6a3b9cc9 | blueswir1 | default:
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261 | 6a3b9cc9 | blueswir1 | break;
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262 | 6a3b9cc9 | blueswir1 | } |
263 | 6a3b9cc9 | blueswir1 | } |
264 | 6a3b9cc9 | blueswir1 | |
265 | 6a3b9cc9 | blueswir1 | static CPUReadMemoryFunc *slavio_led_mem_read[3] = { |
266 | 6a3b9cc9 | blueswir1 | slavio_led_mem_reads, |
267 | 6a3b9cc9 | blueswir1 | slavio_led_mem_reads, |
268 | 6a3b9cc9 | blueswir1 | slavio_led_mem_reads, |
269 | 6a3b9cc9 | blueswir1 | }; |
270 | 6a3b9cc9 | blueswir1 | |
271 | 6a3b9cc9 | blueswir1 | static CPUWriteMemoryFunc *slavio_led_mem_write[3] = { |
272 | 6a3b9cc9 | blueswir1 | slavio_led_mem_writes, |
273 | 6a3b9cc9 | blueswir1 | slavio_led_mem_writes, |
274 | 6a3b9cc9 | blueswir1 | slavio_led_mem_writes, |
275 | 6a3b9cc9 | blueswir1 | }; |
276 | 6a3b9cc9 | blueswir1 | |
277 | 3475187d | bellard | static void slavio_misc_save(QEMUFile *f, void *opaque) |
278 | 3475187d | bellard | { |
279 | 3475187d | bellard | MiscState *s = opaque; |
280 | d537cf6c | pbrook | int tmp;
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281 | bfa30a38 | blueswir1 | uint8_t tmp8; |
282 | 3475187d | bellard | |
283 | d537cf6c | pbrook | tmp = 0;
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284 | d537cf6c | pbrook | qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
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285 | 3475187d | bellard | qemu_put_8s(f, &s->config); |
286 | 3475187d | bellard | qemu_put_8s(f, &s->aux1); |
287 | 3475187d | bellard | qemu_put_8s(f, &s->aux2); |
288 | 3475187d | bellard | qemu_put_8s(f, &s->diag); |
289 | 3475187d | bellard | qemu_put_8s(f, &s->mctrl); |
290 | bfa30a38 | blueswir1 | tmp8 = s->sysctrl & 0xff;
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291 | bfa30a38 | blueswir1 | qemu_put_8s(f, &tmp8); |
292 | 3475187d | bellard | } |
293 | 3475187d | bellard | |
294 | 3475187d | bellard | static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id) |
295 | 3475187d | bellard | { |
296 | 3475187d | bellard | MiscState *s = opaque; |
297 | d537cf6c | pbrook | int tmp;
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298 | bfa30a38 | blueswir1 | uint8_t tmp8; |
299 | 3475187d | bellard | |
300 | 3475187d | bellard | if (version_id != 1) |
301 | 3475187d | bellard | return -EINVAL;
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302 | 3475187d | bellard | |
303 | d537cf6c | pbrook | qemu_get_be32s(f, &tmp); |
304 | 3475187d | bellard | qemu_get_8s(f, &s->config); |
305 | 3475187d | bellard | qemu_get_8s(f, &s->aux1); |
306 | 3475187d | bellard | qemu_get_8s(f, &s->aux2); |
307 | 3475187d | bellard | qemu_get_8s(f, &s->diag); |
308 | 3475187d | bellard | qemu_get_8s(f, &s->mctrl); |
309 | bfa30a38 | blueswir1 | qemu_get_8s(f, &tmp8); |
310 | bfa30a38 | blueswir1 | s->sysctrl = (uint32_t)tmp8; |
311 | 3475187d | bellard | return 0; |
312 | 3475187d | bellard | } |
313 | 3475187d | bellard | |
314 | 5dcb6b91 | blueswir1 | void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
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315 | 5dcb6b91 | blueswir1 | qemu_irq irq) |
316 | 3475187d | bellard | { |
317 | 3475187d | bellard | int slavio_misc_io_memory;
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318 | 3475187d | bellard | MiscState *s; |
319 | 3475187d | bellard | |
320 | 3475187d | bellard | s = qemu_mallocz(sizeof(MiscState));
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321 | 3475187d | bellard | if (!s)
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322 | 3475187d | bellard | return NULL; |
323 | 3475187d | bellard | |
324 | bfa30a38 | blueswir1 | /* 8 bit registers */
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325 | bfa30a38 | blueswir1 | slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read,
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326 | bfa30a38 | blueswir1 | slavio_misc_mem_write, s); |
327 | 3475187d | bellard | // Slavio control
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328 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1800000, MISC_SIZE,
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329 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
330 | 3475187d | bellard | // AUX 1
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331 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1900000, MISC_SIZE,
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332 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
333 | 3475187d | bellard | // AUX 2
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334 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1910000, MISC_SIZE,
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335 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
336 | 3475187d | bellard | // Diagnostics
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337 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1a00000, MISC_SIZE,
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338 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
339 | 3475187d | bellard | // Modem control
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340 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1b00000, MISC_SIZE,
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341 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
342 | 3475187d | bellard | // Power management
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343 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory); |
344 | 3475187d | bellard | |
345 | 6a3b9cc9 | blueswir1 | /* 16 bit registers */
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346 | 6a3b9cc9 | blueswir1 | slavio_misc_io_memory = cpu_register_io_memory(0, slavio_led_mem_read,
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347 | 6a3b9cc9 | blueswir1 | slavio_led_mem_write, s); |
348 | 6a3b9cc9 | blueswir1 | /* ss600mp diag LEDs */
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349 | 6a3b9cc9 | blueswir1 | cpu_register_physical_memory(base + 0x1600000, MISC_SIZE,
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350 | 6a3b9cc9 | blueswir1 | slavio_misc_io_memory); |
351 | 6a3b9cc9 | blueswir1 | |
352 | bfa30a38 | blueswir1 | /* 32 bit registers */
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353 | bfa30a38 | blueswir1 | slavio_misc_io_memory = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
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354 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_write, |
355 | bfa30a38 | blueswir1 | s); |
356 | bfa30a38 | blueswir1 | // System control
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357 | bfa30a38 | blueswir1 | cpu_register_physical_memory(base + 0x1f00000, SYSCTRL_SIZE,
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358 | bfa30a38 | blueswir1 | slavio_misc_io_memory); |
359 | bfa30a38 | blueswir1 | |
360 | 3475187d | bellard | s->irq = irq; |
361 | 3475187d | bellard | |
362 | bfa30a38 | blueswir1 | register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, |
363 | bfa30a38 | blueswir1 | s); |
364 | 3475187d | bellard | qemu_register_reset(slavio_misc_reset, s); |
365 | 3475187d | bellard | slavio_misc_reset(s); |
366 | 3475187d | bellard | return s;
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367 | 3475187d | bellard | } |