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/*
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* Luminary Micro Stellaris preipherals
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "vl.h" |
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#include "arm_pic.h" |
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typedef const struct { |
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const char *name; |
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uint32_t did0; |
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uint32_t did1; |
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uint32_t dc0; |
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uint32_t dc1; |
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uint32_t dc2; |
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uint32_t dc3; |
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uint32_t dc4; |
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enum {OLED_I2C, OLED_SSI} oled;
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} stellaris_board_info; |
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/* General purpose timer module. */
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/* Multiplication factor to convert from GPTM timer ticks to qemu timer
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ticks. */
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static int stellaris_clock_scale; |
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typedef struct gptm_state { |
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uint32_t config; |
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uint32_t mode[2];
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uint32_t control; |
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uint32_t state; |
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uint32_t mask; |
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uint32_t load[2];
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uint32_t match[2];
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uint32_t prescale[2];
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uint32_t match_prescale[2];
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uint32_t rtc; |
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int64_t tick[2];
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struct gptm_state *opaque[2]; |
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uint32_t base; |
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QEMUTimer *timer[2];
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/* The timers have an alternate output used to trigger the ADC. */
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qemu_irq trigger; |
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qemu_irq irq; |
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} gptm_state; |
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static void gptm_update_irq(gptm_state *s) |
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{ |
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int level;
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level = (s->state & s->mask) != 0;
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qemu_set_irq(s->irq, level); |
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} |
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static void gptm_stop(gptm_state *s, int n) |
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{ |
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qemu_del_timer(s->timer[n]); |
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} |
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static void gptm_reload(gptm_state *s, int n, int reset) |
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{ |
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int64_t tick; |
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if (reset)
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tick = qemu_get_clock(vm_clock); |
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else
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tick = s->tick[n]; |
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if (s->config == 0) { |
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/* 32-bit CountDown. */
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uint32_t count; |
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count = s->load[0] | (s->load[1] << 16); |
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tick += (int64_t)count * stellaris_clock_scale; |
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} else if (s->config == 1) { |
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/* 32-bit RTC. 1Hz tick. */
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tick += ticks_per_sec; |
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} else if (s->mode[n] == 0xa) { |
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/* PWM mode. Not implemented. */
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} else {
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cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
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s->mode[n]); |
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} |
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s->tick[n] = tick; |
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qemu_mod_timer(s->timer[n], tick); |
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} |
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static void gptm_tick(void *opaque) |
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{ |
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gptm_state **p = (gptm_state **)opaque; |
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gptm_state *s; |
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int n;
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s = *p; |
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n = p - s->opaque; |
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if (s->config == 0) { |
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s->state |= 1;
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if ((s->control & 0x20)) { |
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/* Output trigger. */
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qemu_irq_raise(s->trigger); |
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qemu_irq_lower(s->trigger); |
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} |
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if (s->mode[0] & 1) { |
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/* One-shot. */
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s->control &= ~1;
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} else {
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/* Periodic. */
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gptm_reload(s, 0, 0); |
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} |
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} else if (s->config == 1) { |
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/* RTC. */
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uint32_t match; |
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s->rtc++; |
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match = s->match[0] | (s->match[1] << 16); |
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if (s->rtc > match)
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s->rtc = 0;
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if (s->rtc == 0) { |
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s->state |= 8;
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} |
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gptm_reload(s, 0, 0); |
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} else if (s->mode[n] == 0xa) { |
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/* PWM mode. Not implemented. */
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} else {
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cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
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s->mode[n]); |
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} |
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gptm_update_irq(s); |
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} |
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static uint32_t gptm_read(void *opaque, target_phys_addr_t offset) |
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{ |
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gptm_state *s = (gptm_state *)opaque; |
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offset -= s->base; |
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switch (offset) {
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case 0x00: /* CFG */ |
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return s->config;
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case 0x04: /* TAMR */ |
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return s->mode[0]; |
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case 0x08: /* TBMR */ |
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return s->mode[1]; |
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case 0x0c: /* CTL */ |
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return s->control;
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case 0x18: /* IMR */ |
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return s->mask;
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case 0x1c: /* RIS */ |
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return s->state;
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case 0x20: /* MIS */ |
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return s->state & s->mask;
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case 0x24: /* CR */ |
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return 0; |
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case 0x28: /* TAILR */ |
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return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); |
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case 0x2c: /* TBILR */ |
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return s->load[1]; |
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case 0x30: /* TAMARCHR */ |
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return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); |
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case 0x34: /* TBMATCHR */ |
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return s->match[1]; |
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case 0x38: /* TAPR */ |
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return s->prescale[0]; |
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case 0x3c: /* TBPR */ |
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return s->prescale[1]; |
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case 0x40: /* TAPMR */ |
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return s->match_prescale[0]; |
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case 0x44: /* TBPMR */ |
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return s->match_prescale[1]; |
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case 0x48: /* TAR */ |
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if (s->control == 1) |
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return s->rtc;
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case 0x4c: /* TBR */ |
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cpu_abort(cpu_single_env, "TODO: Timer value read\n");
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default:
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cpu_abort(cpu_single_env, "gptm_read: Bad offset 0x%x\n", (int)offset); |
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return 0; |
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} |
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} |
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static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value) |
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{ |
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gptm_state *s = (gptm_state *)opaque; |
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uint32_t oldval; |
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offset -= s->base; |
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/* The timers should be disabled before changing the configuration.
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We take advantage of this and defer everything until the timer
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is enabled. */
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switch (offset) {
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case 0x00: /* CFG */ |
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s->config = value; |
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break;
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case 0x04: /* TAMR */ |
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s->mode[0] = value;
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break;
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case 0x08: /* TBMR */ |
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s->mode[1] = value;
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break;
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case 0x0c: /* CTL */ |
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oldval = s->control; |
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s->control = value; |
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/* TODO: Implement pause. */
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if ((oldval ^ value) & 1) { |
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if (value & 1) { |
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gptm_reload(s, 0, 1); |
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} else {
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gptm_stop(s, 0);
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} |
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} |
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if (((oldval ^ value) & 0x100) && s->config >= 4) { |
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if (value & 0x100) { |
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gptm_reload(s, 1, 1); |
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} else {
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gptm_stop(s, 1);
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} |
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} |
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break;
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case 0x18: /* IMR */ |
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s->mask = value & 0x77;
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gptm_update_irq(s); |
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break;
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case 0x24: /* CR */ |
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s->state &= ~value; |
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break;
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case 0x28: /* TAILR */ |
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s->load[0] = value & 0xffff; |
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if (s->config < 4) { |
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s->load[1] = value >> 16; |
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} |
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break;
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case 0x2c: /* TBILR */ |
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s->load[1] = value & 0xffff; |
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break;
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case 0x30: /* TAMARCHR */ |
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s->match[0] = value & 0xffff; |
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if (s->config < 4) { |
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s->match[1] = value >> 16; |
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} |
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break;
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case 0x34: /* TBMATCHR */ |
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s->match[1] = value >> 16; |
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break;
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case 0x38: /* TAPR */ |
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s->prescale[0] = value;
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break;
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case 0x3c: /* TBPR */ |
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s->prescale[1] = value;
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break;
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case 0x40: /* TAPMR */ |
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s->match_prescale[0] = value;
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break;
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case 0x44: /* TBPMR */ |
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s->match_prescale[0] = value;
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break;
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default:
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cpu_abort(cpu_single_env, "gptm_write: Bad offset 0x%x\n", (int)offset); |
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} |
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gptm_update_irq(s); |
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} |
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static CPUReadMemoryFunc *gptm_readfn[] = {
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gptm_read, |
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gptm_read, |
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gptm_read |
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}; |
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static CPUWriteMemoryFunc *gptm_writefn[] = {
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gptm_write, |
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gptm_write, |
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gptm_write |
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}; |
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static void stellaris_gptm_init(uint32_t base, qemu_irq irq, qemu_irq trigger) |
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{ |
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int iomemtype;
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gptm_state *s; |
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s = (gptm_state *)qemu_mallocz(sizeof(gptm_state));
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s->base = base; |
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s->irq = irq; |
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s->trigger = trigger; |
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s->opaque[0] = s->opaque[1] = s; |
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iomemtype = cpu_register_io_memory(0, gptm_readfn,
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gptm_writefn, s); |
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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s->timer[0] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[0]); |
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s->timer[1] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[1]); |
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/* ??? Save/restore. */
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} |
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/* System controller. */
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typedef struct { |
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uint32_t base; |
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uint32_t pborctl; |
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uint32_t ldopctl; |
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uint32_t int_status; |
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uint32_t int_mask; |
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uint32_t resc; |
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uint32_t rcc; |
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uint32_t rcgc[3];
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uint32_t scgc[3];
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uint32_t dcgc[3];
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uint32_t clkvclr; |
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uint32_t ldoarst; |
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qemu_irq irq; |
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stellaris_board_info *board; |
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} ssys_state; |
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static void ssys_update(ssys_state *s) |
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{ |
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qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
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} |
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|
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static uint32_t pllcfg_sandstorm[16] = { |
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0x31c0, /* 1 Mhz */ |
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0x1ae0, /* 1.8432 Mhz */ |
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0x18c0, /* 2 Mhz */ |
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0xd573, /* 2.4576 Mhz */ |
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0x37a6, /* 3.57954 Mhz */ |
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0x1ae2, /* 3.6864 Mhz */ |
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0x0c40, /* 4 Mhz */ |
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0x98bc, /* 4.906 Mhz */ |
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0x935b, /* 4.9152 Mhz */ |
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0x09c0, /* 5 Mhz */ |
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0x4dee, /* 5.12 Mhz */ |
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0x0c41, /* 6 Mhz */ |
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0x75db, /* 6.144 Mhz */ |
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0x1ae6, /* 7.3728 Mhz */ |
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0x0600, /* 8 Mhz */ |
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0x585b /* 8.192 Mhz */ |
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}; |
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|
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static uint32_t pllcfg_fury[16] = { |
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0x3200, /* 1 Mhz */ |
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0x1b20, /* 1.8432 Mhz */ |
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0x1900, /* 2 Mhz */ |
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0xf42b, /* 2.4576 Mhz */ |
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0x37e3, /* 3.57954 Mhz */ |
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0x1b21, /* 3.6864 Mhz */ |
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0x0c80, /* 4 Mhz */ |
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0x98ee, /* 4.906 Mhz */ |
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0xd5b4, /* 4.9152 Mhz */ |
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0x0a00, /* 5 Mhz */ |
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0x4e27, /* 5.12 Mhz */ |
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0x1902, /* 6 Mhz */ |
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0xec1c, /* 6.144 Mhz */ |
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0x1b23, /* 7.3728 Mhz */ |
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0x0640, /* 8 Mhz */ |
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0xb11c /* 8.192 Mhz */ |
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}; |
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|
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static uint32_t ssys_read(void *opaque, target_phys_addr_t offset) |
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{ |
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ssys_state *s = (ssys_state *)opaque; |
358 |
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offset -= s->base; |
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switch (offset) {
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case 0x000: /* DID0 */ |
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return s->board->did0;
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case 0x004: /* DID1 */ |
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return s->board->did1;
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case 0x008: /* DC0 */ |
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return s->board->dc0;
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case 0x010: /* DC1 */ |
368 |
return s->board->dc1;
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case 0x014: /* DC2 */ |
370 |
return s->board->dc2;
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case 0x018: /* DC3 */ |
372 |
return s->board->dc3;
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case 0x01c: /* DC4 */ |
374 |
return s->board->dc4;
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case 0x030: /* PBORCTL */ |
376 |
return s->pborctl;
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case 0x034: /* LDOPCTL */ |
378 |
return s->ldopctl;
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case 0x040: /* SRCR0 */ |
380 |
return 0; |
381 |
case 0x044: /* SRCR1 */ |
382 |
return 0; |
383 |
case 0x048: /* SRCR2 */ |
384 |
return 0; |
385 |
case 0x050: /* RIS */ |
386 |
return s->int_status;
|
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case 0x054: /* IMC */ |
388 |
return s->int_mask;
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case 0x058: /* MISC */ |
390 |
return s->int_status & s->int_mask;
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case 0x05c: /* RESC */ |
392 |
return s->resc;
|
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case 0x060: /* RCC */ |
394 |
return s->rcc;
|
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case 0x064: /* PLLCFG */ |
396 |
{ |
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int xtal;
|
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xtal = (s->rcc >> 6) & 0xf; |
399 |
if (s->board->did0 & (1 << 16)) { |
400 |
return pllcfg_fury[xtal];
|
401 |
} else {
|
402 |
return pllcfg_sandstorm[xtal];
|
403 |
} |
404 |
} |
405 |
case 0x100: /* RCGC0 */ |
406 |
return s->rcgc[0]; |
407 |
case 0x104: /* RCGC1 */ |
408 |
return s->rcgc[1]; |
409 |
case 0x108: /* RCGC2 */ |
410 |
return s->rcgc[2]; |
411 |
case 0x110: /* SCGC0 */ |
412 |
return s->scgc[0]; |
413 |
case 0x114: /* SCGC1 */ |
414 |
return s->scgc[1]; |
415 |
case 0x118: /* SCGC2 */ |
416 |
return s->scgc[2]; |
417 |
case 0x120: /* DCGC0 */ |
418 |
return s->dcgc[0]; |
419 |
case 0x124: /* DCGC1 */ |
420 |
return s->dcgc[1]; |
421 |
case 0x128: /* DCGC2 */ |
422 |
return s->dcgc[2]; |
423 |
case 0x150: /* CLKVCLR */ |
424 |
return s->clkvclr;
|
425 |
case 0x160: /* LDOARST */ |
426 |
return s->ldoarst;
|
427 |
default:
|
428 |
cpu_abort(cpu_single_env, "gptm_read: Bad offset 0x%x\n", (int)offset); |
429 |
return 0; |
430 |
} |
431 |
} |
432 |
|
433 |
static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value) |
434 |
{ |
435 |
ssys_state *s = (ssys_state *)opaque; |
436 |
|
437 |
offset -= s->base; |
438 |
switch (offset) {
|
439 |
case 0x030: /* PBORCTL */ |
440 |
s->pborctl = value & 0xffff;
|
441 |
break;
|
442 |
case 0x034: /* LDOPCTL */ |
443 |
s->ldopctl = value & 0x1f;
|
444 |
break;
|
445 |
case 0x040: /* SRCR0 */ |
446 |
case 0x044: /* SRCR1 */ |
447 |
case 0x048: /* SRCR2 */ |
448 |
fprintf(stderr, "Peripheral reset not implemented\n");
|
449 |
break;
|
450 |
case 0x054: /* IMC */ |
451 |
s->int_mask = value & 0x7f;
|
452 |
break;
|
453 |
case 0x058: /* MISC */ |
454 |
s->int_status &= ~value; |
455 |
break;
|
456 |
case 0x05c: /* RESC */ |
457 |
s->resc = value & 0x3f;
|
458 |
break;
|
459 |
case 0x060: /* RCC */ |
460 |
if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { |
461 |
/* PLL enable. */
|
462 |
s->int_status |= (1 << 6); |
463 |
} |
464 |
s->rcc = value; |
465 |
stellaris_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); |
466 |
break;
|
467 |
case 0x100: /* RCGC0 */ |
468 |
s->rcgc[0] = value;
|
469 |
break;
|
470 |
case 0x104: /* RCGC1 */ |
471 |
s->rcgc[1] = value;
|
472 |
break;
|
473 |
case 0x108: /* RCGC2 */ |
474 |
s->rcgc[2] = value;
|
475 |
break;
|
476 |
case 0x110: /* SCGC0 */ |
477 |
s->scgc[0] = value;
|
478 |
break;
|
479 |
case 0x114: /* SCGC1 */ |
480 |
s->scgc[1] = value;
|
481 |
break;
|
482 |
case 0x118: /* SCGC2 */ |
483 |
s->scgc[2] = value;
|
484 |
break;
|
485 |
case 0x120: /* DCGC0 */ |
486 |
s->dcgc[0] = value;
|
487 |
break;
|
488 |
case 0x124: /* DCGC1 */ |
489 |
s->dcgc[1] = value;
|
490 |
break;
|
491 |
case 0x128: /* DCGC2 */ |
492 |
s->dcgc[2] = value;
|
493 |
break;
|
494 |
case 0x150: /* CLKVCLR */ |
495 |
s->clkvclr = value; |
496 |
break;
|
497 |
case 0x160: /* LDOARST */ |
498 |
s->ldoarst = value; |
499 |
break;
|
500 |
default:
|
501 |
cpu_abort(cpu_single_env, "gptm_write: Bad offset 0x%x\n", (int)offset); |
502 |
} |
503 |
ssys_update(s); |
504 |
} |
505 |
|
506 |
static CPUReadMemoryFunc *ssys_readfn[] = {
|
507 |
ssys_read, |
508 |
ssys_read, |
509 |
ssys_read |
510 |
}; |
511 |
|
512 |
static CPUWriteMemoryFunc *ssys_writefn[] = {
|
513 |
ssys_write, |
514 |
ssys_write, |
515 |
ssys_write |
516 |
}; |
517 |
|
518 |
void ssys_reset(void *opaque) |
519 |
{ |
520 |
ssys_state *s = (ssys_state *)opaque; |
521 |
|
522 |
s->pborctl = 0x7ffd;
|
523 |
s->rcc = 0x078e3ac0;
|
524 |
s->rcgc[0] = 1; |
525 |
s->scgc[0] = 1; |
526 |
s->dcgc[0] = 1; |
527 |
} |
528 |
|
529 |
static void stellaris_sys_init(uint32_t base, qemu_irq irq, |
530 |
stellaris_board_info * board) |
531 |
{ |
532 |
int iomemtype;
|
533 |
ssys_state *s; |
534 |
|
535 |
s = (ssys_state *)qemu_mallocz(sizeof(ssys_state));
|
536 |
s->base = base; |
537 |
s->irq = irq; |
538 |
s->board = board; |
539 |
|
540 |
iomemtype = cpu_register_io_memory(0, ssys_readfn,
|
541 |
ssys_writefn, s); |
542 |
cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
543 |
ssys_reset(s); |
544 |
/* ??? Save/restore. */
|
545 |
} |
546 |
|
547 |
|
548 |
/* I2C controller. */
|
549 |
|
550 |
typedef struct { |
551 |
i2c_bus *bus; |
552 |
qemu_irq irq; |
553 |
uint32_t base; |
554 |
uint32_t msa; |
555 |
uint32_t mcs; |
556 |
uint32_t mdr; |
557 |
uint32_t mtpr; |
558 |
uint32_t mimr; |
559 |
uint32_t mris; |
560 |
uint32_t mcr; |
561 |
} stellaris_i2c_state; |
562 |
|
563 |
#define STELLARIS_I2C_MCS_BUSY 0x01 |
564 |
#define STELLARIS_I2C_MCS_ERROR 0x02 |
565 |
#define STELLARIS_I2C_MCS_ADRACK 0x04 |
566 |
#define STELLARIS_I2C_MCS_DATACK 0x08 |
567 |
#define STELLARIS_I2C_MCS_ARBLST 0x10 |
568 |
#define STELLARIS_I2C_MCS_IDLE 0x20 |
569 |
#define STELLARIS_I2C_MCS_BUSBSY 0x40 |
570 |
|
571 |
static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset) |
572 |
{ |
573 |
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
574 |
|
575 |
offset -= s->base; |
576 |
switch (offset) {
|
577 |
case 0x00: /* MSA */ |
578 |
return s->msa;
|
579 |
case 0x04: /* MCS */ |
580 |
/* We don't emulate timing, so the controller is never busy. */
|
581 |
return s->mcs | STELLARIS_I2C_MCS_IDLE;
|
582 |
case 0x08: /* MDR */ |
583 |
return s->mdr;
|
584 |
case 0x0c: /* MTPR */ |
585 |
return s->mtpr;
|
586 |
case 0x10: /* MIMR */ |
587 |
return s->mimr;
|
588 |
case 0x14: /* MRIS */ |
589 |
return s->mris;
|
590 |
case 0x18: /* MMIS */ |
591 |
return s->mris & s->mimr;
|
592 |
case 0x20: /* MCR */ |
593 |
return s->mcr;
|
594 |
default:
|
595 |
cpu_abort(cpu_single_env, "strllaris_i2c_read: Bad offset 0x%x\n",
|
596 |
(int)offset);
|
597 |
return 0; |
598 |
} |
599 |
} |
600 |
|
601 |
static void stellaris_i2c_update(stellaris_i2c_state *s) |
602 |
{ |
603 |
int level;
|
604 |
|
605 |
level = (s->mris & s->mimr) != 0;
|
606 |
qemu_set_irq(s->irq, level); |
607 |
} |
608 |
|
609 |
static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset, |
610 |
uint32_t value) |
611 |
{ |
612 |
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
613 |
|
614 |
offset -= s->base; |
615 |
switch (offset) {
|
616 |
case 0x00: /* MSA */ |
617 |
s->msa = value & 0xff;
|
618 |
break;
|
619 |
case 0x04: /* MCS */ |
620 |
if ((s->mcr & 0x10) == 0) { |
621 |
/* Disabled. Do nothing. */
|
622 |
break;
|
623 |
} |
624 |
/* Grab the bus if this is starting a transfer. */
|
625 |
if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { |
626 |
if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { |
627 |
s->mcs |= STELLARIS_I2C_MCS_ARBLST; |
628 |
} else {
|
629 |
s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; |
630 |
s->mcs |= STELLARIS_I2C_MCS_BUSBSY; |
631 |
} |
632 |
} |
633 |
/* If we don't have the bus then indicate an error. */
|
634 |
if (!i2c_bus_busy(s->bus)
|
635 |
|| (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
|
636 |
s->mcs |= STELLARIS_I2C_MCS_ERROR; |
637 |
break;
|
638 |
} |
639 |
s->mcs &= ~STELLARIS_I2C_MCS_ERROR; |
640 |
if (value & 1) { |
641 |
/* Transfer a byte. */
|
642 |
/* TODO: Handle errors. */
|
643 |
if (s->msa & 1) { |
644 |
/* Recv */
|
645 |
s->mdr = i2c_recv(s->bus) & 0xff;
|
646 |
} else {
|
647 |
/* Send */
|
648 |
i2c_send(s->bus, s->mdr); |
649 |
} |
650 |
/* Raise an interrupt. */
|
651 |
s->mris |= 1;
|
652 |
} |
653 |
if (value & 4) { |
654 |
/* Finish transfer. */
|
655 |
i2c_end_transfer(s->bus); |
656 |
s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; |
657 |
} |
658 |
break;
|
659 |
case 0x08: /* MDR */ |
660 |
s->mdr = value & 0xff;
|
661 |
break;
|
662 |
case 0x0c: /* MTPR */ |
663 |
s->mtpr = value & 0xff;
|
664 |
break;
|
665 |
case 0x10: /* MIMR */ |
666 |
s->mimr = 1;
|
667 |
break;
|
668 |
case 0x1c: /* MICR */ |
669 |
s->mris &= ~value; |
670 |
break;
|
671 |
case 0x20: /* MCR */ |
672 |
if (value & 1) |
673 |
cpu_abort(cpu_single_env, |
674 |
"stellaris_i2c_write: Loopback not implemented\n");
|
675 |
if (value & 0x20) |
676 |
cpu_abort(cpu_single_env, |
677 |
"stellaris_i2c_write: Slave mode not implemented\n");
|
678 |
s->mcr = value & 0x31;
|
679 |
break;
|
680 |
default:
|
681 |
cpu_abort(cpu_single_env, "stellaris_i2c_write: Bad offset 0x%x\n",
|
682 |
(int)offset);
|
683 |
} |
684 |
stellaris_i2c_update(s); |
685 |
} |
686 |
|
687 |
static void stellaris_i2c_reset(stellaris_i2c_state *s) |
688 |
{ |
689 |
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
|
690 |
i2c_end_transfer(s->bus); |
691 |
|
692 |
s->msa = 0;
|
693 |
s->mcs = 0;
|
694 |
s->mdr = 0;
|
695 |
s->mtpr = 1;
|
696 |
s->mimr = 0;
|
697 |
s->mris = 0;
|
698 |
s->mcr = 0;
|
699 |
stellaris_i2c_update(s); |
700 |
} |
701 |
|
702 |
static CPUReadMemoryFunc *stellaris_i2c_readfn[] = {
|
703 |
stellaris_i2c_read, |
704 |
stellaris_i2c_read, |
705 |
stellaris_i2c_read |
706 |
}; |
707 |
|
708 |
static CPUWriteMemoryFunc *stellaris_i2c_writefn[] = {
|
709 |
stellaris_i2c_write, |
710 |
stellaris_i2c_write, |
711 |
stellaris_i2c_write |
712 |
}; |
713 |
|
714 |
static void stellaris_i2c_init(uint32_t base, qemu_irq irq, i2c_bus *bus) |
715 |
{ |
716 |
stellaris_i2c_state *s; |
717 |
int iomemtype;
|
718 |
|
719 |
s = (stellaris_i2c_state *)qemu_mallocz(sizeof(stellaris_i2c_state));
|
720 |
s->base = base; |
721 |
s->irq = irq; |
722 |
s->bus = bus; |
723 |
|
724 |
iomemtype = cpu_register_io_memory(0, stellaris_i2c_readfn,
|
725 |
stellaris_i2c_writefn, s); |
726 |
cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
727 |
/* ??? For now we only implement the master interface. */
|
728 |
stellaris_i2c_reset(s); |
729 |
} |
730 |
|
731 |
/* Analogue to Digital Converter. This is only partially implemented,
|
732 |
enough for applications that use a combined ADC and timer tick. */
|
733 |
|
734 |
#define STELLARIS_ADC_EM_CONTROLLER 0 |
735 |
#define STELLARIS_ADC_EM_COMP 1 |
736 |
#define STELLARIS_ADC_EM_EXTERNAL 4 |
737 |
#define STELLARIS_ADC_EM_TIMER 5 |
738 |
#define STELLARIS_ADC_EM_PWM0 6 |
739 |
#define STELLARIS_ADC_EM_PWM1 7 |
740 |
#define STELLARIS_ADC_EM_PWM2 8 |
741 |
|
742 |
#define STELLARIS_ADC_FIFO_EMPTY 0x0100 |
743 |
#define STELLARIS_ADC_FIFO_FULL 0x1000 |
744 |
|
745 |
typedef struct |
746 |
{ |
747 |
uint32_t base; |
748 |
uint32_t actss; |
749 |
uint32_t ris; |
750 |
uint32_t im; |
751 |
uint32_t emux; |
752 |
uint32_t ostat; |
753 |
uint32_t ustat; |
754 |
uint32_t sspri; |
755 |
uint32_t sac; |
756 |
struct {
|
757 |
uint32_t state; |
758 |
uint32_t data[16];
|
759 |
} fifo[4];
|
760 |
uint32_t ssmux[4];
|
761 |
uint32_t ssctl[4];
|
762 |
qemu_irq irq; |
763 |
} stellaris_adc_state; |
764 |
|
765 |
static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) |
766 |
{ |
767 |
int tail;
|
768 |
|
769 |
tail = s->fifo[n].state & 0xf;
|
770 |
if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
|
771 |
s->ustat |= 1 << n;
|
772 |
} else {
|
773 |
s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); |
774 |
s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; |
775 |
if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) |
776 |
s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; |
777 |
} |
778 |
return s->fifo[n].data[tail];
|
779 |
} |
780 |
|
781 |
static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, |
782 |
uint32_t value) |
783 |
{ |
784 |
int head;
|
785 |
|
786 |
head = (s->fifo[n].state >> 4) & 0xf; |
787 |
if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
|
788 |
s->ostat |= 1 << n;
|
789 |
return;
|
790 |
} |
791 |
s->fifo[n].data[head] = value; |
792 |
head = (head + 1) & 0xf; |
793 |
s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; |
794 |
s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); |
795 |
if ((s->fifo[n].state & 0xf) == head) |
796 |
s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; |
797 |
} |
798 |
|
799 |
static void stellaris_adc_update(stellaris_adc_state *s) |
800 |
{ |
801 |
int level;
|
802 |
|
803 |
level = (s->ris & s->im) != 0;
|
804 |
qemu_set_irq(s->irq, level); |
805 |
} |
806 |
|
807 |
static void stellaris_adc_trigger(void *opaque, int irq, int level) |
808 |
{ |
809 |
stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
810 |
/* Some applications use the ADC as a random number source, so introduce
|
811 |
some variation into the signal. */
|
812 |
static uint32_t noise = 0; |
813 |
|
814 |
if ((s->actss & 1) == 0) { |
815 |
return;
|
816 |
} |
817 |
|
818 |
noise = noise * 314159 + 1; |
819 |
/* ??? actual inputs not implemented. Return an arbitrary value. */
|
820 |
stellaris_adc_fifo_write(s, 0, 0x200 + ((noise >> 16) & 7)); |
821 |
s->ris |= 1;
|
822 |
stellaris_adc_update(s); |
823 |
} |
824 |
|
825 |
static void stellaris_adc_reset(stellaris_adc_state *s) |
826 |
{ |
827 |
int n;
|
828 |
|
829 |
for (n = 0; n < 4; n++) { |
830 |
s->ssmux[n] = 0;
|
831 |
s->ssctl[n] = 0;
|
832 |
s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; |
833 |
} |
834 |
} |
835 |
|
836 |
static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset) |
837 |
{ |
838 |
stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
839 |
|
840 |
/* TODO: Implement this. */
|
841 |
offset -= s->base; |
842 |
if (offset >= 0x40 && offset < 0xc0) { |
843 |
int n;
|
844 |
n = (offset - 0x40) >> 5; |
845 |
switch (offset & 0x1f) { |
846 |
case 0x00: /* SSMUX */ |
847 |
return s->ssmux[n];
|
848 |
case 0x04: /* SSCTL */ |
849 |
return s->ssctl[n];
|
850 |
case 0x08: /* SSFIFO */ |
851 |
return stellaris_adc_fifo_read(s, n);
|
852 |
case 0x0c: /* SSFSTAT */ |
853 |
return s->fifo[n].state;
|
854 |
default:
|
855 |
break;
|
856 |
} |
857 |
} |
858 |
switch (offset) {
|
859 |
case 0x00: /* ACTSS */ |
860 |
return s->actss;
|
861 |
case 0x04: /* RIS */ |
862 |
return s->ris;
|
863 |
case 0x08: /* IM */ |
864 |
return s->im;
|
865 |
case 0x0c: /* ISC */ |
866 |
return s->ris & s->im;
|
867 |
case 0x10: /* OSTAT */ |
868 |
return s->ostat;
|
869 |
case 0x14: /* EMUX */ |
870 |
return s->emux;
|
871 |
case 0x18: /* USTAT */ |
872 |
return s->ustat;
|
873 |
case 0x20: /* SSPRI */ |
874 |
return s->sspri;
|
875 |
case 0x30: /* SAC */ |
876 |
return s->sac;
|
877 |
default:
|
878 |
cpu_abort(cpu_single_env, "strllaris_adc_read: Bad offset 0x%x\n",
|
879 |
(int)offset);
|
880 |
return 0; |
881 |
} |
882 |
} |
883 |
|
884 |
static void stellaris_adc_write(void *opaque, target_phys_addr_t offset, |
885 |
uint32_t value) |
886 |
{ |
887 |
stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
888 |
|
889 |
/* TODO: Implement this. */
|
890 |
offset -= s->base; |
891 |
if (offset >= 0x40 && offset < 0xc0) { |
892 |
int n;
|
893 |
n = (offset - 0x40) >> 5; |
894 |
switch (offset & 0x1f) { |
895 |
case 0x00: /* SSMUX */ |
896 |
s->ssmux[n] = value & 0x33333333;
|
897 |
return;
|
898 |
case 0x04: /* SSCTL */ |
899 |
if (value != 6) { |
900 |
cpu_abort(cpu_single_env, "ADC: Unimplemented sequence %x\n",
|
901 |
value); |
902 |
} |
903 |
s->ssctl[n] = value; |
904 |
return;
|
905 |
default:
|
906 |
break;
|
907 |
} |
908 |
} |
909 |
switch (offset) {
|
910 |
case 0x00: /* ACTSS */ |
911 |
s->actss = value & 0xf;
|
912 |
if (value & 0xe) { |
913 |
cpu_abort(cpu_single_env, |
914 |
"Not implemented: ADC sequencers 1-3\n");
|
915 |
} |
916 |
break;
|
917 |
case 0x08: /* IM */ |
918 |
s->im = value; |
919 |
break;
|
920 |
case 0x0c: /* ISC */ |
921 |
s->ris &= ~value; |
922 |
break;
|
923 |
case 0x10: /* OSTAT */ |
924 |
s->ostat &= ~value; |
925 |
break;
|
926 |
case 0x14: /* EMUX */ |
927 |
s->emux = value; |
928 |
break;
|
929 |
case 0x18: /* USTAT */ |
930 |
s->ustat &= ~value; |
931 |
break;
|
932 |
case 0x20: /* SSPRI */ |
933 |
s->sspri = value; |
934 |
break;
|
935 |
case 0x28: /* PSSI */ |
936 |
cpu_abort(cpu_single_env, "Not implemented: ADC sample initiate\n");
|
937 |
break;
|
938 |
case 0x30: /* SAC */ |
939 |
s->sac = value; |
940 |
break;
|
941 |
default:
|
942 |
cpu_abort(cpu_single_env, "stellaris_adc_write: Bad offset 0x%x\n",
|
943 |
(int)offset);
|
944 |
} |
945 |
stellaris_adc_update(s); |
946 |
} |
947 |
|
948 |
static CPUReadMemoryFunc *stellaris_adc_readfn[] = {
|
949 |
stellaris_adc_read, |
950 |
stellaris_adc_read, |
951 |
stellaris_adc_read |
952 |
}; |
953 |
|
954 |
static CPUWriteMemoryFunc *stellaris_adc_writefn[] = {
|
955 |
stellaris_adc_write, |
956 |
stellaris_adc_write, |
957 |
stellaris_adc_write |
958 |
}; |
959 |
|
960 |
static qemu_irq stellaris_adc_init(uint32_t base, qemu_irq irq)
|
961 |
{ |
962 |
stellaris_adc_state *s; |
963 |
int iomemtype;
|
964 |
qemu_irq *qi; |
965 |
|
966 |
s = (stellaris_adc_state *)qemu_mallocz(sizeof(stellaris_adc_state));
|
967 |
s->base = base; |
968 |
s->irq = irq; |
969 |
|
970 |
iomemtype = cpu_register_io_memory(0, stellaris_adc_readfn,
|
971 |
stellaris_adc_writefn, s); |
972 |
cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
973 |
stellaris_adc_reset(s); |
974 |
qi = qemu_allocate_irqs(stellaris_adc_trigger, s, 1);
|
975 |
return qi[0]; |
976 |
} |
977 |
|
978 |
/* Board init. */
|
979 |
static stellaris_board_info stellaris_boards[] = {
|
980 |
{ "LM3S811EVB",
|
981 |
0,
|
982 |
0x0032000e,
|
983 |
0x001f001f, /* dc0 */ |
984 |
0x001132bf,
|
985 |
0x01071013,
|
986 |
0x3f0f01ff,
|
987 |
0x0000001f,
|
988 |
OLED_I2C |
989 |
}, |
990 |
{ "LM3S6965EVB",
|
991 |
0x10010002,
|
992 |
0x1073402e,
|
993 |
0x00ff007f, /* dc0 */ |
994 |
0x001133ff,
|
995 |
0x030f5317,
|
996 |
0x0f0f87ff,
|
997 |
0x5000007f,
|
998 |
OLED_SSI |
999 |
} |
1000 |
}; |
1001 |
|
1002 |
static void stellaris_init(const char *kernel_filename, const char *cpu_model, |
1003 |
DisplayState *ds, stellaris_board_info *board) |
1004 |
{ |
1005 |
static const int uart_irq[] = {5, 6, 33, 34}; |
1006 |
static const int timer_irq[] = {19, 21, 23, 35}; |
1007 |
static const uint32_t gpio_addr[7] = |
1008 |
{ 0x40004000, 0x40005000, 0x40006000, 0x40007000, |
1009 |
0x40024000, 0x40025000, 0x40026000}; |
1010 |
static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; |
1011 |
|
1012 |
qemu_irq *pic; |
1013 |
qemu_irq *gpio_in[5];
|
1014 |
qemu_irq *gpio_out[5];
|
1015 |
qemu_irq adc; |
1016 |
int sram_size;
|
1017 |
int flash_size;
|
1018 |
i2c_bus *i2c; |
1019 |
int i;
|
1020 |
|
1021 |
flash_size = ((board->dc0 & 0xffff) + 1) << 1; |
1022 |
sram_size = (board->dc0 >> 18) + 1; |
1023 |
pic = armv7m_init(flash_size, sram_size, kernel_filename, cpu_model); |
1024 |
|
1025 |
if (board->dc1 & (1 << 16)) { |
1026 |
adc = stellaris_adc_init(0x40038000, pic[14]); |
1027 |
} else {
|
1028 |
adc = NULL;
|
1029 |
} |
1030 |
for (i = 0; i < 4; i++) { |
1031 |
if (board->dc2 & (0x10000 << i)) { |
1032 |
stellaris_gptm_init(0x40030000 + i * 0x1000, |
1033 |
pic[timer_irq[i]], adc); |
1034 |
} |
1035 |
} |
1036 |
|
1037 |
stellaris_sys_init(0x400fe000, pic[28], board); |
1038 |
|
1039 |
for (i = 0; i < 7; i++) { |
1040 |
if (board->dc4 & (1 << i)) { |
1041 |
gpio_in[i] = pl061_init(gpio_addr[i], pic[gpio_irq[i]], |
1042 |
&gpio_out[i]); |
1043 |
} |
1044 |
} |
1045 |
|
1046 |
if (board->dc2 & (1 << 12)) { |
1047 |
i2c = i2c_init_bus(); |
1048 |
stellaris_i2c_init(0x40020000, pic[8], i2c); |
1049 |
if (board->oled == OLED_I2C) {
|
1050 |
ssd0303_init(ds, i2c, 0x3d);
|
1051 |
} |
1052 |
} |
1053 |
|
1054 |
for (i = 0; i < 4; i++) { |
1055 |
if (board->dc2 & (1 << i)) { |
1056 |
pl011_init(0x4000c000 + i * 0x1000, pic[uart_irq[i]], |
1057 |
serial_hds[i], PL011_LUMINARY); |
1058 |
} |
1059 |
} |
1060 |
if (board->dc2 & (1 << 4)) { |
1061 |
if (board->oled == OLED_SSI) {
|
1062 |
void * oled;
|
1063 |
/* FIXME: Implement chip select for OLED/MMC. */
|
1064 |
oled = ssd0323_init(ds, &gpio_out[2][7]); |
1065 |
pl022_init(0x40008000, pic[7], ssd0323_xfer_ssi, oled); |
1066 |
} else {
|
1067 |
pl022_init(0x40008000, pic[7], NULL, NULL); |
1068 |
} |
1069 |
} |
1070 |
} |
1071 |
|
1072 |
/* FIXME: Figure out how to generate these from stellaris_boards. */
|
1073 |
static void lm3s811evb_init(int ram_size, int vga_ram_size, |
1074 |
const char *boot_device, DisplayState *ds, |
1075 |
const char **fd_filename, int snapshot, |
1076 |
const char *kernel_filename, const char *kernel_cmdline, |
1077 |
const char *initrd_filename, const char *cpu_model) |
1078 |
{ |
1079 |
stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[0]);
|
1080 |
} |
1081 |
|
1082 |
static void lm3s6965evb_init(int ram_size, int vga_ram_size, |
1083 |
const char *boot_device, DisplayState *ds, |
1084 |
const char **fd_filename, int snapshot, |
1085 |
const char *kernel_filename, const char *kernel_cmdline, |
1086 |
const char *initrd_filename, const char *cpu_model) |
1087 |
{ |
1088 |
stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[1]);
|
1089 |
} |
1090 |
|
1091 |
QEMUMachine lm3s811evb_machine = { |
1092 |
"lm3s811evb",
|
1093 |
"Stellaris LM3S811EVB",
|
1094 |
lm3s811evb_init, |
1095 |
}; |
1096 |
|
1097 |
QEMUMachine lm3s6965evb_machine = { |
1098 |
"lm3s6965evb",
|
1099 |
"Stellaris LM3S6965EVB",
|
1100 |
lm3s6965evb_init, |
1101 |
}; |