Archipelago » qemu

#define NB_MMU_MODES 2

typedef struct CPUX86State {

    /* standard registers */

    target_ulong regs[CPU_NB_REGS];

    target_ulong eip;

    XMMReg xmm_regs[CPU_NB_REGS];

    XMMReg xmm_t0;

    MMXReg mmx_t0;

    /* sysenter registers */

    uint32_t sysenter_cs;

#include "cpu-defs.h"

register struct CPUX86State *env asm(AREG0);

extern FILE *logfile;

extern int loglevel;

#define EAX (env->regs[R_EAX])

#define ECX (env->regs[R_ECX])

#define EDX (env->regs[R_EDX])

#define EBX (env->regs[R_EBX])

#define ESP (env->regs[R_ESP])

#define EBP (env->regs[R_EBP])

#define ESI (env->regs[R_ESI])

#define EDI (env->regs[R_EDI])

#define DF  (env->df)

#define CC_SRC (env->cc_src)

        if (count > 1)

            res |= t0 >> (DATA_BITS + 1 - count);

        t0 = res;

            (lshift(src ^ t0, 11 - (DATA_BITS - 1)) & CC_O) |

            ((src >> (DATA_BITS - count)) & CC_C);

    } else {

    }

    return t0;

}

        if (count > 1)

            res |= t0 << (DATA_BITS + 1 - count);

        t0 = res;

            (lshift(src ^ t0, 11 - (DATA_BITS - 1)) & CC_O) |

            ((src >> (count - 1)) & CC_C);

    } else {

    }

    return t0;

}

//#define MACRO_TEST   1

/* global register indexes */

/* local register indexes (only used inside old micro ops) */

static TCGv cpu_tmp0, cpu_tmp1_i64, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp4, cpu_ptr0, cpu_ptr1;

static TCGv cpu_tmp5, cpu_tmp6;

#define REG_LH_OFFSET 4

#endif

{

    switch(ot) {

    case OT_BYTE:

        if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {

        } else {

        }

        break;

    case OT_WORD:

        break;

#ifdef TARGET_X86_64

    case OT_LONG:

        /* high part of register set to zero */

        tcg_gen_movi_tl(cpu_tmp0, 0);

        tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);

        break;

    default:

    case OT_QUAD:

        break;

#else

    default:

    case OT_LONG:

        break;

#endif

    }

static inline void gen_op_mov_reg_T0(int ot, int reg)

{

}

static inline void gen_op_mov_reg_T1(int ot, int reg)

{

}

static inline void gen_op_mov_reg_A0(int size, int reg)

    }

}

{

    switch(ot) {

    case OT_BYTE:

        if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {

            goto std_case;

        } else {

        }

        break;

    default:

    std_case:

        break;

    }

}

static inline void gen_op_movl_A0_reg(int reg)

{

    tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);

    }

}

{

    int mem_index = (idx >> 2) - 1;

    switch(idx & 3) {

    case 0:

        break;

    case 1:

        break;

    case 2:

        break;

    default:

    case 3:

        break;

    }

}

static inline void gen_op_ldu_T0_A0(int idx)

{

}

static inline void gen_op_ld_T1_A0(int idx)

{

    int mem_index = (idx >> 2) - 1;

    switch(idx & 3) {

    case 0:

        break;

    case 1:

        break;

    case 2:

        break;

    default:

    case 3:

        break;

    }

}

static inline void gen_op_st_T0_A0(int idx)

{

}

static inline void gen_op_st_T1_A0(int idx)

{

}

static inline void gen_jmp_im(target_ulong pc)

    tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);

}

{

    case JCC_O:

        gen_compute_eflags(cpu_T[0]);

        tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);

        break;

    default:

    slow_jcc:

        tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, 

                           cpu_T[0], 0, l1);

        break;

{

    target_ulong mask;

    int shift_label;

    if (ot == OT_QUAD)

        mask = 0x3f;

    else

    if (s->cc_op != CC_OP_DYNAMIC)

        gen_op_set_cc_op(s->cc_op);

    shift_label = gen_new_label();

    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);

    if (is_right)

        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);

    else

    gen_set_label(shift_label);

    s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */

}

static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,

{

    target_ulong mask;

    int label1, label2, data_bits;

    if (ot == OT_QUAD)

        mask = 0x3f;

    else

        mask = 0x1f;

    /* load */

    /* Must test zero case to avoid using undefined behaviour in TCG

       shifts. */

    label1 = gen_new_label();

    if (ot <= OT_WORD)

    else

    data_bits = 8 << ot;

    /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:

       fix TCG definition) */

    if (is_right) {

        tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);

    } else {

        tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);

    }

    gen_set_label(label1);

    /* store */

    /* update eflags */

    if (s->cc_op != CC_OP_DYNAMIC)

        gen_op_set_cc_op(s->cc_op);

    label2 = gen_new_label();

    gen_compute_eflags(cpu_cc_src);

    tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));

    tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));

    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);

    tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);

    if (is_right) {

    }

    tcg_gen_discard_tl(cpu_cc_dst);

    tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);

    gen_set_label(label2);

    s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */

}

static void *helper_rotc[8] = {

    /* update eflags */

    label1 = gen_new_label();

    tcg_gen_discard_tl(cpu_cc_dst);

    tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);

{

    int label1, label2, data_bits;

    target_ulong mask;

    if (ot == OT_QUAD)

        mask = 0x3f;

        mask = 0x1f;

    /* load */

    tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);

    /* Must test zero case to avoid using undefined behaviour in TCG

       shifts. */

    label1 = gen_new_label();

    if (ot == OT_WORD) {

        /* Note: we implement the Intel behaviour for shift count > 16 */

        if (is_right) {

            /* only needed if count > 16, but a test would complicate */

        } else {

            /* XXX: not optimal */

            tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5);

            tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6);

        }

    } else {

        data_bits = 8 << ot;

        if (is_right) {

            if (ot == OT_LONG)

        } else {

            if (ot == OT_LONG)

        }

    }

    gen_set_label(label1);

    /* store */

    /* update eflags */

    if (s->cc_op != CC_OP_DYNAMIC)

        gen_op_set_cc_op(s->cc_op);

    label2 = gen_new_label();

    if (is_right) {

        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);

    } else {

    }

    gen_set_label(label2);

    s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */

}

static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)

static void gen_setcc(DisasContext *s, int b)

{

    int inv, jcc_op, l1;

    if (is_fast_jcc_case(s, b)) {

        /* nominal case: we use a jump */

        l1 = gen_new_label();

        gen_jcc1(s, s->cc_op, b ^ 1, l1);

        gen_set_label(l1);

    } else {

        /* slow case: it is more efficient not to generate a jump,

           although it is questionnable whether this optimization is

           worth to */

        inv = b & 1;

        jcc_op = (b >> 1) & 7;

        if (inv) {

            tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);

        }

    case 0x1b1: /* cmpxchg Ev, Gv */

        {

            int label1, label2;

            if ((b & 1) == 0)

                ot = OT_BYTE;

            modrm = ldub_code(s->pc++);

            reg = ((modrm >> 3) & 7) | rex_r;

            mod = (modrm >> 6) & 3;

            if (mod == 3) {

                rm = (modrm & 7) | REX_B(s);

            } else {

                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);

                rm = 0; /* avoid warning */

            }

            label1 = gen_new_label();

            if (mod == 3) {

                label2 = gen_new_label();

                tcg_gen_br(label2);

                gen_set_label(label1);

                gen_set_label(label2);

            } else {

                gen_set_label(label1);

                /* always store */

            }

            s->cc_op = CC_OP_SUBB + ot;

        }

        break;

    case 0x1c7: /* cmpxchg8b */

                        (JCC_BE << 1),

                        (JCC_P << 1),

                    };

                    l1 = gen_new_label();

                    tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32(opreg));

                    gen_set_label(l1);

                }

    case 0x140 ... 0x14f: /* cmov Gv, Ev */

        {

            int l1;

            ot = dflag + OT_WORD;

            modrm = ldub_code(s->pc++);

            reg = ((modrm >> 3) & 7) | rex_r;

            mod = (modrm >> 6) & 3;

            if (mod != 3) {

                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);

            } else {

                rm = (modrm & 7) | REX_B(s);

            }

#ifdef TARGET_X86_64

            if (ot == OT_LONG) {

                /* XXX: specific Intel behaviour ? */

                l1 = gen_new_label();

                gen_jcc1(s, s->cc_op, b ^ 1, l1);

                gen_set_label(l1);

                tcg_gen_movi_tl(cpu_tmp0, 0);

                tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);

            {

                l1 = gen_new_label();

                gen_jcc1(s, s->cc_op, b ^ 1, l1);

                gen_set_label(l1);

            }

        }

        break;

    case 0x1bd: /* bsr */

        {

            int label1;

            ot = dflag + OT_WORD;

            modrm = ldub_code(s->pc++);

            reg = ((modrm >> 3) & 7) | rex_r;

            gen_extu(ot, cpu_T[0]);

            label1 = gen_new_label();

            tcg_gen_movi_tl(cpu_cc_dst, 0);

            if (b & 1) {

            } else {

            }

            gen_op_mov_reg_T0(ot, reg);

            tcg_gen_movi_tl(cpu_cc_dst, 1);

            gen_set_label(label1);

            tcg_gen_discard_tl(cpu_cc_src);

            s->cc_op = CC_OP_LOGICB + ot;

        }

        break;

        /************************/

#endif

        {

            int label1;

            if (!s->pe || s->vm86)

                goto illegal_op;

            ot = OT_WORD;

            modrm = ldub_code(s->pc++);

            reg = (modrm >> 3) & 7;

            rm = modrm & 7;

            if (mod != 3) {

                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);

            } else {

            }

            label1 = gen_new_label();

            gen_set_label(label1);

            if (mod != 3) {

            } else {

            }

            if (s->cc_op != CC_OP_DYNAMIC)

                gen_op_set_cc_op(s->cc_op);

            gen_compute_eflags(cpu_cc_src);

            tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);

            s->cc_op = CC_OP_EFLAGS;

        }

        break;

    case 0x102: /* lar */

    case 0x103: /* lsl */

        {

            int label1;

            if (!s->pe || s->vm86)

                goto illegal_op;

            ot = dflag ? OT_LONG : OT_WORD;

            modrm = ldub_code(s->pc++);

            reg = ((modrm >> 3) & 7) | rex_r;

            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);

            if (s->cc_op != CC_OP_DYNAMIC)

                gen_op_set_cc_op(s->cc_op);

            if (b == 0x102)

            else

            tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);

            label1 = gen_new_label();

            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);

            gen_set_label(label1);

            s->cc_op = CC_OP_EFLAGS;

        }

        break;

    case 0x118:

    return s->pc;

}

void optimize_flags_init(void)

{

#if TCG_TARGET_REG_BITS == 32

#else

    assert(sizeof(CCTable) == (1 << 4));

#endif

    cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");

    cpu_cc_op = tcg_global_mem_new(TCG_TYPE_I32,

                                   TCG_AREG0, offsetof(CPUState, cc_op), "cc_op");

    cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,

                                    TCG_AREG0, offsetof(CPUState, cc_src), "cc_src");

    cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,

                                    TCG_AREG0, offsetof(CPUState, cc_dst), "cc_dst");

    /* register helpers */

        printf("ERROR addseg\n");

#endif

    cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);

    cpu_tmp1_i64 = tcg_temp_new(TCG_TYPE_I64);

    cpu_tmp2_i32 = tcg_temp_new(TCG_TYPE_I32);

    cpu_tmp3_i32 = tcg_temp_new(TCG_TYPE_I32);

    cpu_tmp4 = tcg_temp_new(TCG_TYPE_TL);