root / target-unicore32 / ucf64_helper.c @ 1e5cdaa1
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/*
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* UniCore-F64 simulation helpers for QEMU.
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*
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* Copyright (C) 2010-2012 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation, or any later version.
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* See the COPYING file in the top-level directory.
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*/
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#include "cpu.h" |
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#include "helper.h" |
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/*
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* The convention used for UniCore-F64 instructions:
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* Single precition routines have a "s" suffix
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* Double precision routines have a "d" suffix.
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*/
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/* Convert host exception flags to f64 form. */
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static inline int ucf64_exceptbits_from_host(int host_bits) |
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{
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int target_bits = 0; |
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if (host_bits & float_flag_invalid) {
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target_bits |= UCF64_FPSCR_FLAG_INVALID; |
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} |
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if (host_bits & float_flag_divbyzero) {
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target_bits |= UCF64_FPSCR_FLAG_DIVZERO; |
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} |
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if (host_bits & float_flag_overflow) {
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target_bits |= UCF64_FPSCR_FLAG_OVERFLOW; |
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} |
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if (host_bits & float_flag_underflow) {
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target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW; |
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} |
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if (host_bits & float_flag_inexact) {
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target_bits |= UCF64_FPSCR_FLAG_INEXACT; |
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} |
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return target_bits;
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} |
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uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env) |
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{
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int i;
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uint32_t fpscr; |
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fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK); |
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i = get_float_exception_flags(&env->ucf64.fp_status); |
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fpscr |= ucf64_exceptbits_from_host(i); |
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return fpscr;
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} |
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/* Convert ucf64 exception flags to target form. */
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static inline int ucf64_exceptbits_to_host(int target_bits) |
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{
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int host_bits = 0; |
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if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
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host_bits |= float_flag_invalid; |
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} |
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if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
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host_bits |= float_flag_divbyzero; |
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} |
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if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
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host_bits |= float_flag_overflow; |
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} |
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if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
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host_bits |= float_flag_underflow; |
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} |
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if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
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host_bits |= float_flag_inexact; |
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} |
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return host_bits;
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} |
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void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
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{
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int i;
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uint32_t changed; |
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changed = env->ucf64.xregs[UC32_UCF64_FPSCR]; |
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env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK); |
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changed ^= val; |
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if (changed & (UCF64_FPSCR_RND_MASK)) {
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i = UCF64_FPSCR_RND(val); |
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switch (i) {
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case 0: |
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i = float_round_nearest_even; |
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break;
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case 1: |
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i = float_round_to_zero; |
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break;
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case 2: |
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i = float_round_up; |
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break;
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case 3: |
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i = float_round_down; |
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break;
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default: /* 100 and 101 not implement */ |
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cpu_abort(env, "Unsupported UniCore-F64 round mode");
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} |
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set_float_rounding_mode(i, &env->ucf64.fp_status); |
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} |
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i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val)); |
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set_float_exception_flags(i, &env->ucf64.fp_status); |
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} |
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float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env) |
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{
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return float32_add(a, b, &env->ucf64.fp_status);
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} |
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float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env) |
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{
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return float64_add(a, b, &env->ucf64.fp_status);
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} |
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float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env) |
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{
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return float32_sub(a, b, &env->ucf64.fp_status);
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} |
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float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env) |
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{
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return float64_sub(a, b, &env->ucf64.fp_status);
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} |
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float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env) |
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{
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return float32_mul(a, b, &env->ucf64.fp_status);
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} |
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float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env) |
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{
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return float64_mul(a, b, &env->ucf64.fp_status);
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} |
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float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env) |
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{
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return float32_div(a, b, &env->ucf64.fp_status);
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} |
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float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env) |
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{
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return float64_div(a, b, &env->ucf64.fp_status);
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} |
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float32 HELPER(ucf64_negs)(float32 a) |
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{
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return float32_chs(a);
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} |
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float64 HELPER(ucf64_negd)(float64 a) |
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{
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return float64_chs(a);
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} |
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float32 HELPER(ucf64_abss)(float32 a) |
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{
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return float32_abs(a);
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} |
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float64 HELPER(ucf64_absd)(float64 a) |
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{
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return float64_abs(a);
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} |
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void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c,
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CPUUniCore32State *env) |
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{
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int flag;
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flag = float32_compare_quiet(a, b, &env->ucf64.fp_status); |
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env->CF = 0;
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switch (c & 0x7) { |
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case 0: /* F */ |
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break;
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case 1: /* UN */ |
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if (flag == 2) { |
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env->CF = 1;
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} |
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break;
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case 2: /* EQ */ |
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if (flag == 0) { |
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env->CF = 1;
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} |
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break;
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case 3: /* UEQ */ |
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if ((flag == 0) || (flag == 2)) { |
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env->CF = 1;
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} |
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break;
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case 4: /* OLT */ |
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if (flag == -1) { |
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env->CF = 1;
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} |
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break;
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case 5: /* ULT */ |
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if ((flag == -1) || (flag == 2)) { |
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env->CF = 1;
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} |
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break;
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case 6: /* OLE */ |
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if ((flag == -1) || (flag == 0)) { |
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env->CF = 1;
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} |
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break;
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case 7: /* ULE */ |
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if (flag != 1) { |
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env->CF = 1;
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} |
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break;
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} |
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env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
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| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
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} |
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void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c,
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CPUUniCore32State *env) |
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{
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int flag;
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flag = float64_compare_quiet(a, b, &env->ucf64.fp_status); |
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env->CF = 0;
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switch (c & 0x7) { |
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case 0: /* F */ |
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break;
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case 1: /* UN */ |
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if (flag == 2) { |
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env->CF = 1;
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} |
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break;
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case 2: /* EQ */ |
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if (flag == 0) { |
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env->CF = 1;
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} |
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break;
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case 3: /* UEQ */ |
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if ((flag == 0) || (flag == 2)) { |
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env->CF = 1;
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} |
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break;
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case 4: /* OLT */ |
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if (flag == -1) { |
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env->CF = 1;
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} |
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break;
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case 5: /* ULT */ |
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if ((flag == -1) || (flag == 2)) { |
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env->CF = 1;
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} |
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break;
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case 6: /* OLE */ |
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if ((flag == -1) || (flag == 0)) { |
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env->CF = 1;
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} |
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break;
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case 7: /* ULE */ |
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if (flag != 1) { |
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env->CF = 1;
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} |
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break;
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} |
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env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
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| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
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} |
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/* Helper routines to perform bitwise copies between float and int. */
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static inline float32 ucf64_itos(uint32_t i) |
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{
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union {
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uint32_t i; |
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float32 s; |
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} v; |
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v.i = i; |
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return v.s;
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} |
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static inline uint32_t ucf64_stoi(float32 s) |
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{
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union {
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uint32_t i; |
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float32 s; |
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} v; |
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v.s = s; |
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return v.i;
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} |
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static inline float64 ucf64_itod(uint64_t i) |
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{
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union {
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uint64_t i; |
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float64 d; |
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} v; |
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v.i = i; |
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return v.d;
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} |
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static inline uint64_t ucf64_dtoi(float64 d) |
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{
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union {
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uint64_t i; |
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float64 d; |
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} v; |
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v.d = d; |
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return v.i;
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} |
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/* Integer to float conversion. */
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float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env) |
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{
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return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
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} |
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float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env) |
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{
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return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
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} |
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/* Float to integer conversion. */
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float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env) |
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{
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return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
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} |
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float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env) |
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{
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return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
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} |
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/* floating point conversion */
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float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env) |
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{
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return float32_to_float64(x, &env->ucf64.fp_status);
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} |
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float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env) |
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{
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return float64_to_float32(x, &env->ucf64.fp_status);
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} |