root / target-i386 / ops_template_mem.h @ 1e8a7cfd
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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 micro operations (included several times to generate
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3 | 2c0262af | bellard | * different operand sizes)
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4 | 2c0262af | bellard | *
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5 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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6 | 2c0262af | bellard | *
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7 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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8 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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10 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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11 | 2c0262af | bellard | *
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12 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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13 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 2c0262af | bellard | * Lesser General Public License for more details.
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16 | 2c0262af | bellard | *
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17 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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19 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 2c0262af | bellard | */
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21 | 2c0262af | bellard | #ifdef MEM_WRITE
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22 | 2c0262af | bellard | |
23 | 943144d9 | bellard | #if MEM_WRITE == 0 |
24 | 943144d9 | bellard | |
25 | 943144d9 | bellard | #if DATA_BITS == 8 |
26 | 943144d9 | bellard | #define MEM_SUFFIX b_raw
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27 | 943144d9 | bellard | #elif DATA_BITS == 16 |
28 | 943144d9 | bellard | #define MEM_SUFFIX w_raw
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29 | 943144d9 | bellard | #elif DATA_BITS == 32 |
30 | 943144d9 | bellard | #define MEM_SUFFIX l_raw
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31 | 14ce26e7 | bellard | #elif DATA_BITS == 64 |
32 | 14ce26e7 | bellard | #define MEM_SUFFIX q_raw
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33 | 943144d9 | bellard | #endif
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34 | 943144d9 | bellard | |
35 | 943144d9 | bellard | #elif MEM_WRITE == 1 |
36 | 943144d9 | bellard | |
37 | 943144d9 | bellard | #if DATA_BITS == 8 |
38 | 943144d9 | bellard | #define MEM_SUFFIX b_kernel
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39 | 943144d9 | bellard | #elif DATA_BITS == 16 |
40 | 943144d9 | bellard | #define MEM_SUFFIX w_kernel
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41 | 943144d9 | bellard | #elif DATA_BITS == 32 |
42 | 943144d9 | bellard | #define MEM_SUFFIX l_kernel
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43 | 14ce26e7 | bellard | #elif DATA_BITS == 64 |
44 | 14ce26e7 | bellard | #define MEM_SUFFIX q_kernel
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45 | 943144d9 | bellard | #endif
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46 | 943144d9 | bellard | |
47 | 943144d9 | bellard | #elif MEM_WRITE == 2 |
48 | 943144d9 | bellard | |
49 | 2c0262af | bellard | #if DATA_BITS == 8 |
50 | 943144d9 | bellard | #define MEM_SUFFIX b_user
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51 | 2c0262af | bellard | #elif DATA_BITS == 16 |
52 | 943144d9 | bellard | #define MEM_SUFFIX w_user
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53 | 2c0262af | bellard | #elif DATA_BITS == 32 |
54 | 943144d9 | bellard | #define MEM_SUFFIX l_user
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55 | 14ce26e7 | bellard | #elif DATA_BITS == 64 |
56 | 14ce26e7 | bellard | #define MEM_SUFFIX q_user
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57 | 943144d9 | bellard | #endif
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58 | 943144d9 | bellard | |
59 | 943144d9 | bellard | #else
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60 | 943144d9 | bellard | |
61 | 943144d9 | bellard | #error invalid MEM_WRITE
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62 | 943144d9 | bellard | |
63 | 2c0262af | bellard | #endif
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64 | 2c0262af | bellard | |
65 | 2c0262af | bellard | #else
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66 | 2c0262af | bellard | |
67 | 2c0262af | bellard | #define MEM_SUFFIX SUFFIX
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68 | 2c0262af | bellard | |
69 | 2c0262af | bellard | #endif
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70 | 2c0262af | bellard | |
71 | 2c0262af | bellard | void OPPROTO glue(glue(op_rol, MEM_SUFFIX), _T0_T1_cc)(void) |
72 | 2c0262af | bellard | { |
73 | 14ce26e7 | bellard | int count;
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74 | 14ce26e7 | bellard | target_long src; |
75 | 14ce26e7 | bellard | |
76 | 2c0262af | bellard | count = T1 & SHIFT_MASK; |
77 | 2c0262af | bellard | if (count) {
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78 | 2c0262af | bellard | src = T0; |
79 | 2c0262af | bellard | T0 &= DATA_MASK; |
80 | 2c0262af | bellard | T0 = (T0 << count) | (T0 >> (DATA_BITS - count)); |
81 | 2c0262af | bellard | #ifdef MEM_WRITE
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82 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
83 | 2c0262af | bellard | #else
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84 | 2c0262af | bellard | /* gcc 3.2 workaround. This is really a bug in gcc. */
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85 | 2c0262af | bellard | asm volatile("" : : "r" (T0)); |
86 | 2c0262af | bellard | #endif
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87 | 2c0262af | bellard | CC_SRC = (cc_table[CC_OP].compute_all() & ~(CC_O | CC_C)) | |
88 | 2c0262af | bellard | (lshift(src ^ T0, 11 - (DATA_BITS - 1)) & CC_O) | |
89 | 2c0262af | bellard | (T0 & CC_C); |
90 | 2c0262af | bellard | CC_OP = CC_OP_EFLAGS; |
91 | 2c0262af | bellard | } |
92 | 2c0262af | bellard | FORCE_RET(); |
93 | 2c0262af | bellard | } |
94 | 2c0262af | bellard | |
95 | 2c0262af | bellard | void OPPROTO glue(glue(op_ror, MEM_SUFFIX), _T0_T1_cc)(void) |
96 | 2c0262af | bellard | { |
97 | 14ce26e7 | bellard | int count;
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98 | 14ce26e7 | bellard | target_long src; |
99 | 14ce26e7 | bellard | |
100 | 2c0262af | bellard | count = T1 & SHIFT_MASK; |
101 | 2c0262af | bellard | if (count) {
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102 | 2c0262af | bellard | src = T0; |
103 | 2c0262af | bellard | T0 &= DATA_MASK; |
104 | 2c0262af | bellard | T0 = (T0 >> count) | (T0 << (DATA_BITS - count)); |
105 | 2c0262af | bellard | #ifdef MEM_WRITE
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106 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
107 | 2c0262af | bellard | #else
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108 | 2c0262af | bellard | /* gcc 3.2 workaround. This is really a bug in gcc. */
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109 | 2c0262af | bellard | asm volatile("" : : "r" (T0)); |
110 | 2c0262af | bellard | #endif
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111 | 2c0262af | bellard | CC_SRC = (cc_table[CC_OP].compute_all() & ~(CC_O | CC_C)) | |
112 | 2c0262af | bellard | (lshift(src ^ T0, 11 - (DATA_BITS - 1)) & CC_O) | |
113 | 2c0262af | bellard | ((T0 >> (DATA_BITS - 1)) & CC_C);
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114 | 2c0262af | bellard | CC_OP = CC_OP_EFLAGS; |
115 | 2c0262af | bellard | } |
116 | 2c0262af | bellard | FORCE_RET(); |
117 | 2c0262af | bellard | } |
118 | 2c0262af | bellard | |
119 | 2c0262af | bellard | void OPPROTO glue(glue(op_rol, MEM_SUFFIX), _T0_T1)(void) |
120 | 2c0262af | bellard | { |
121 | 2c0262af | bellard | int count;
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122 | 2c0262af | bellard | count = T1 & SHIFT_MASK; |
123 | 2c0262af | bellard | if (count) {
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124 | 2c0262af | bellard | T0 &= DATA_MASK; |
125 | 2c0262af | bellard | T0 = (T0 << count) | (T0 >> (DATA_BITS - count)); |
126 | 2c0262af | bellard | #ifdef MEM_WRITE
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127 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
128 | 2c0262af | bellard | #endif
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129 | 2c0262af | bellard | } |
130 | 2c0262af | bellard | FORCE_RET(); |
131 | 2c0262af | bellard | } |
132 | 2c0262af | bellard | |
133 | 2c0262af | bellard | void OPPROTO glue(glue(op_ror, MEM_SUFFIX), _T0_T1)(void) |
134 | 2c0262af | bellard | { |
135 | 2c0262af | bellard | int count;
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136 | 2c0262af | bellard | count = T1 & SHIFT_MASK; |
137 | 2c0262af | bellard | if (count) {
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138 | 2c0262af | bellard | T0 &= DATA_MASK; |
139 | 2c0262af | bellard | T0 = (T0 >> count) | (T0 << (DATA_BITS - count)); |
140 | 2c0262af | bellard | #ifdef MEM_WRITE
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141 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
142 | 2c0262af | bellard | #endif
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143 | 2c0262af | bellard | } |
144 | 2c0262af | bellard | FORCE_RET(); |
145 | 2c0262af | bellard | } |
146 | 2c0262af | bellard | |
147 | 2c0262af | bellard | void OPPROTO glue(glue(op_rcl, MEM_SUFFIX), _T0_T1_cc)(void) |
148 | 2c0262af | bellard | { |
149 | 14ce26e7 | bellard | int count, eflags;
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150 | 14ce26e7 | bellard | target_ulong src; |
151 | 14ce26e7 | bellard | target_long res; |
152 | 2c0262af | bellard | |
153 | 14ce26e7 | bellard | count = T1 & SHIFT1_MASK; |
154 | 2c0262af | bellard | #if DATA_BITS == 16 |
155 | 2c0262af | bellard | count = rclw_table[count]; |
156 | 2c0262af | bellard | #elif DATA_BITS == 8 |
157 | 2c0262af | bellard | count = rclb_table[count]; |
158 | 2c0262af | bellard | #endif
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159 | 2c0262af | bellard | if (count) {
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160 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
161 | 2c0262af | bellard | T0 &= DATA_MASK; |
162 | 2c0262af | bellard | src = T0; |
163 | 31313213 | bellard | res = (T0 << count) | ((target_ulong)(eflags & CC_C) << (count - 1));
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164 | 2c0262af | bellard | if (count > 1) |
165 | 2c0262af | bellard | res |= T0 >> (DATA_BITS + 1 - count);
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166 | 2c0262af | bellard | T0 = res; |
167 | 2c0262af | bellard | #ifdef MEM_WRITE
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168 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
169 | 2c0262af | bellard | #endif
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170 | 2c0262af | bellard | CC_SRC = (eflags & ~(CC_C | CC_O)) | |
171 | 2c0262af | bellard | (lshift(src ^ T0, 11 - (DATA_BITS - 1)) & CC_O) | |
172 | 2c0262af | bellard | ((src >> (DATA_BITS - count)) & CC_C); |
173 | 2c0262af | bellard | CC_OP = CC_OP_EFLAGS; |
174 | 2c0262af | bellard | } |
175 | 2c0262af | bellard | FORCE_RET(); |
176 | 2c0262af | bellard | } |
177 | 2c0262af | bellard | |
178 | 2c0262af | bellard | void OPPROTO glue(glue(op_rcr, MEM_SUFFIX), _T0_T1_cc)(void) |
179 | 2c0262af | bellard | { |
180 | 14ce26e7 | bellard | int count, eflags;
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181 | 14ce26e7 | bellard | target_ulong src; |
182 | 14ce26e7 | bellard | target_long res; |
183 | 2c0262af | bellard | |
184 | 14ce26e7 | bellard | count = T1 & SHIFT1_MASK; |
185 | 2c0262af | bellard | #if DATA_BITS == 16 |
186 | 2c0262af | bellard | count = rclw_table[count]; |
187 | 2c0262af | bellard | #elif DATA_BITS == 8 |
188 | 2c0262af | bellard | count = rclb_table[count]; |
189 | 2c0262af | bellard | #endif
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190 | 2c0262af | bellard | if (count) {
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191 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
192 | 2c0262af | bellard | T0 &= DATA_MASK; |
193 | 2c0262af | bellard | src = T0; |
194 | 31313213 | bellard | res = (T0 >> count) | ((target_ulong)(eflags & CC_C) << (DATA_BITS - count)); |
195 | 2c0262af | bellard | if (count > 1) |
196 | 2c0262af | bellard | res |= T0 << (DATA_BITS + 1 - count);
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197 | 2c0262af | bellard | T0 = res; |
198 | 2c0262af | bellard | #ifdef MEM_WRITE
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199 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
200 | 2c0262af | bellard | #endif
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201 | 2c0262af | bellard | CC_SRC = (eflags & ~(CC_C | CC_O)) | |
202 | 2c0262af | bellard | (lshift(src ^ T0, 11 - (DATA_BITS - 1)) & CC_O) | |
203 | 2c0262af | bellard | ((src >> (count - 1)) & CC_C);
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204 | 2c0262af | bellard | CC_OP = CC_OP_EFLAGS; |
205 | 2c0262af | bellard | } |
206 | 2c0262af | bellard | FORCE_RET(); |
207 | 2c0262af | bellard | } |
208 | 2c0262af | bellard | |
209 | 2c0262af | bellard | void OPPROTO glue(glue(op_shl, MEM_SUFFIX), _T0_T1_cc)(void) |
210 | 2c0262af | bellard | { |
211 | 14ce26e7 | bellard | int count;
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212 | 14ce26e7 | bellard | target_long src; |
213 | 14ce26e7 | bellard | |
214 | 14ce26e7 | bellard | count = T1 & SHIFT1_MASK; |
215 | 2c0262af | bellard | if (count) {
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216 | 2c0262af | bellard | src = (DATA_TYPE)T0 << (count - 1);
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217 | 2c0262af | bellard | T0 = T0 << count; |
218 | 2c0262af | bellard | #ifdef MEM_WRITE
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219 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
220 | 2c0262af | bellard | #endif
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221 | 2c0262af | bellard | CC_SRC = src; |
222 | 2c0262af | bellard | CC_DST = T0; |
223 | 2c0262af | bellard | CC_OP = CC_OP_SHLB + SHIFT; |
224 | 2c0262af | bellard | } |
225 | 2c0262af | bellard | FORCE_RET(); |
226 | 2c0262af | bellard | } |
227 | 2c0262af | bellard | |
228 | 2c0262af | bellard | void OPPROTO glue(glue(op_shr, MEM_SUFFIX), _T0_T1_cc)(void) |
229 | 2c0262af | bellard | { |
230 | 14ce26e7 | bellard | int count;
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231 | 14ce26e7 | bellard | target_long src; |
232 | 14ce26e7 | bellard | |
233 | 14ce26e7 | bellard | count = T1 & SHIFT1_MASK; |
234 | 2c0262af | bellard | if (count) {
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235 | 2c0262af | bellard | T0 &= DATA_MASK; |
236 | 2c0262af | bellard | src = T0 >> (count - 1);
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237 | 2c0262af | bellard | T0 = T0 >> count; |
238 | 2c0262af | bellard | #ifdef MEM_WRITE
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239 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
240 | 2c0262af | bellard | #endif
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241 | 2c0262af | bellard | CC_SRC = src; |
242 | 2c0262af | bellard | CC_DST = T0; |
243 | 2c0262af | bellard | CC_OP = CC_OP_SARB + SHIFT; |
244 | 2c0262af | bellard | } |
245 | 2c0262af | bellard | FORCE_RET(); |
246 | 2c0262af | bellard | } |
247 | 2c0262af | bellard | |
248 | 2c0262af | bellard | void OPPROTO glue(glue(op_sar, MEM_SUFFIX), _T0_T1_cc)(void) |
249 | 2c0262af | bellard | { |
250 | 14ce26e7 | bellard | int count;
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251 | 14ce26e7 | bellard | target_long src; |
252 | 14ce26e7 | bellard | |
253 | 14ce26e7 | bellard | count = T1 & SHIFT1_MASK; |
254 | 2c0262af | bellard | if (count) {
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255 | 2c0262af | bellard | src = (DATA_STYPE)T0; |
256 | 2c0262af | bellard | T0 = src >> count; |
257 | 2c0262af | bellard | src = src >> (count - 1);
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258 | 2c0262af | bellard | #ifdef MEM_WRITE
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259 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
260 | 2c0262af | bellard | #endif
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261 | 2c0262af | bellard | CC_SRC = src; |
262 | 2c0262af | bellard | CC_DST = T0; |
263 | 2c0262af | bellard | CC_OP = CC_OP_SARB + SHIFT; |
264 | 2c0262af | bellard | } |
265 | 2c0262af | bellard | FORCE_RET(); |
266 | 2c0262af | bellard | } |
267 | 2c0262af | bellard | |
268 | 2c0262af | bellard | #if DATA_BITS == 16 |
269 | 2c0262af | bellard | /* XXX: overflow flag might be incorrect in some cases in shldw */
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270 | 2c0262af | bellard | void OPPROTO glue(glue(op_shld, MEM_SUFFIX), _T0_T1_im_cc)(void) |
271 | 2c0262af | bellard | { |
272 | 2c0262af | bellard | int count;
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273 | 2c0262af | bellard | unsigned int res, tmp; |
274 | 2c0262af | bellard | count = PARAM1; |
275 | 2c0262af | bellard | T1 &= 0xffff;
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276 | 2c0262af | bellard | res = T1 | (T0 << 16);
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277 | 2c0262af | bellard | tmp = res >> (32 - count);
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278 | 2c0262af | bellard | res <<= count; |
279 | 2c0262af | bellard | if (count > 16) |
280 | 2c0262af | bellard | res |= T1 << (count - 16);
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281 | 2c0262af | bellard | T0 = res >> 16;
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282 | 2c0262af | bellard | #ifdef MEM_WRITE
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283 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
284 | 2c0262af | bellard | #endif
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285 | 2c0262af | bellard | CC_SRC = tmp; |
286 | 2c0262af | bellard | CC_DST = T0; |
287 | 2c0262af | bellard | } |
288 | 2c0262af | bellard | |
289 | 2c0262af | bellard | void OPPROTO glue(glue(op_shld, MEM_SUFFIX), _T0_T1_ECX_cc)(void) |
290 | 2c0262af | bellard | { |
291 | 2c0262af | bellard | int count;
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292 | 2c0262af | bellard | unsigned int res, tmp; |
293 | 2c0262af | bellard | count = ECX & 0x1f;
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294 | 2c0262af | bellard | if (count) {
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295 | 2c0262af | bellard | T1 &= 0xffff;
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296 | 2c0262af | bellard | res = T1 | (T0 << 16);
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297 | 2c0262af | bellard | tmp = res >> (32 - count);
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298 | 2c0262af | bellard | res <<= count; |
299 | 2c0262af | bellard | if (count > 16) |
300 | 2c0262af | bellard | res |= T1 << (count - 16);
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301 | 2c0262af | bellard | T0 = res >> 16;
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302 | 2c0262af | bellard | #ifdef MEM_WRITE
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303 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
304 | 2c0262af | bellard | #endif
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305 | 2c0262af | bellard | CC_SRC = tmp; |
306 | 2c0262af | bellard | CC_DST = T0; |
307 | 2c0262af | bellard | CC_OP = CC_OP_SARB + SHIFT; |
308 | 2c0262af | bellard | } |
309 | 2c0262af | bellard | FORCE_RET(); |
310 | 2c0262af | bellard | } |
311 | 2c0262af | bellard | |
312 | 2c0262af | bellard | void OPPROTO glue(glue(op_shrd, MEM_SUFFIX), _T0_T1_im_cc)(void) |
313 | 2c0262af | bellard | { |
314 | 2c0262af | bellard | int count;
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315 | 2c0262af | bellard | unsigned int res, tmp; |
316 | 2c0262af | bellard | |
317 | 2c0262af | bellard | count = PARAM1; |
318 | 2c0262af | bellard | res = (T0 & 0xffff) | (T1 << 16); |
319 | 2c0262af | bellard | tmp = res >> (count - 1);
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320 | 2c0262af | bellard | res >>= count; |
321 | 2c0262af | bellard | if (count > 16) |
322 | 2c0262af | bellard | res |= T1 << (32 - count);
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323 | 2c0262af | bellard | T0 = res; |
324 | 2c0262af | bellard | #ifdef MEM_WRITE
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325 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
326 | 2c0262af | bellard | #endif
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327 | 2c0262af | bellard | CC_SRC = tmp; |
328 | 2c0262af | bellard | CC_DST = T0; |
329 | 2c0262af | bellard | } |
330 | 2c0262af | bellard | |
331 | 2c0262af | bellard | |
332 | 2c0262af | bellard | void OPPROTO glue(glue(op_shrd, MEM_SUFFIX), _T0_T1_ECX_cc)(void) |
333 | 2c0262af | bellard | { |
334 | 2c0262af | bellard | int count;
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335 | 2c0262af | bellard | unsigned int res, tmp; |
336 | 2c0262af | bellard | |
337 | 2c0262af | bellard | count = ECX & 0x1f;
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338 | 2c0262af | bellard | if (count) {
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339 | 2c0262af | bellard | res = (T0 & 0xffff) | (T1 << 16); |
340 | 2c0262af | bellard | tmp = res >> (count - 1);
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341 | 2c0262af | bellard | res >>= count; |
342 | 2c0262af | bellard | if (count > 16) |
343 | 2c0262af | bellard | res |= T1 << (32 - count);
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344 | 2c0262af | bellard | T0 = res; |
345 | 2c0262af | bellard | #ifdef MEM_WRITE
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346 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
347 | 2c0262af | bellard | #endif
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348 | 2c0262af | bellard | CC_SRC = tmp; |
349 | 2c0262af | bellard | CC_DST = T0; |
350 | 2c0262af | bellard | CC_OP = CC_OP_SARB + SHIFT; |
351 | 2c0262af | bellard | } |
352 | 2c0262af | bellard | FORCE_RET(); |
353 | 2c0262af | bellard | } |
354 | 2c0262af | bellard | #endif
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355 | 2c0262af | bellard | |
356 | 14ce26e7 | bellard | #if DATA_BITS >= 32 |
357 | 2c0262af | bellard | void OPPROTO glue(glue(op_shld, MEM_SUFFIX), _T0_T1_im_cc)(void) |
358 | 2c0262af | bellard | { |
359 | 14ce26e7 | bellard | int count;
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360 | 14ce26e7 | bellard | target_long tmp; |
361 | 14ce26e7 | bellard | |
362 | 2c0262af | bellard | count = PARAM1; |
363 | 2c0262af | bellard | T0 &= DATA_MASK; |
364 | 2c0262af | bellard | T1 &= DATA_MASK; |
365 | 2c0262af | bellard | tmp = T0 << (count - 1);
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366 | 2c0262af | bellard | T0 = (T0 << count) | (T1 >> (DATA_BITS - count)); |
367 | 2c0262af | bellard | #ifdef MEM_WRITE
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368 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
369 | 2c0262af | bellard | #endif
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370 | 2c0262af | bellard | CC_SRC = tmp; |
371 | 2c0262af | bellard | CC_DST = T0; |
372 | 2c0262af | bellard | } |
373 | 2c0262af | bellard | |
374 | 2c0262af | bellard | void OPPROTO glue(glue(op_shld, MEM_SUFFIX), _T0_T1_ECX_cc)(void) |
375 | 2c0262af | bellard | { |
376 | 14ce26e7 | bellard | int count;
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377 | 14ce26e7 | bellard | target_long tmp; |
378 | 14ce26e7 | bellard | |
379 | 14ce26e7 | bellard | count = ECX & SHIFT1_MASK; |
380 | 2c0262af | bellard | if (count) {
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381 | 2c0262af | bellard | T0 &= DATA_MASK; |
382 | 2c0262af | bellard | T1 &= DATA_MASK; |
383 | 2c0262af | bellard | tmp = T0 << (count - 1);
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384 | 2c0262af | bellard | T0 = (T0 << count) | (T1 >> (DATA_BITS - count)); |
385 | 2c0262af | bellard | #ifdef MEM_WRITE
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386 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
387 | 2c0262af | bellard | #endif
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388 | 2c0262af | bellard | CC_SRC = tmp; |
389 | 2c0262af | bellard | CC_DST = T0; |
390 | 2c0262af | bellard | CC_OP = CC_OP_SHLB + SHIFT; |
391 | 2c0262af | bellard | } |
392 | 2c0262af | bellard | FORCE_RET(); |
393 | 2c0262af | bellard | } |
394 | 2c0262af | bellard | |
395 | 2c0262af | bellard | void OPPROTO glue(glue(op_shrd, MEM_SUFFIX), _T0_T1_im_cc)(void) |
396 | 2c0262af | bellard | { |
397 | 14ce26e7 | bellard | int count;
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398 | 14ce26e7 | bellard | target_long tmp; |
399 | 14ce26e7 | bellard | |
400 | 2c0262af | bellard | count = PARAM1; |
401 | 2c0262af | bellard | T0 &= DATA_MASK; |
402 | 2c0262af | bellard | T1 &= DATA_MASK; |
403 | 2c0262af | bellard | tmp = T0 >> (count - 1);
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404 | 2c0262af | bellard | T0 = (T0 >> count) | (T1 << (DATA_BITS - count)); |
405 | 2c0262af | bellard | #ifdef MEM_WRITE
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406 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
407 | 2c0262af | bellard | #endif
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408 | 2c0262af | bellard | CC_SRC = tmp; |
409 | 2c0262af | bellard | CC_DST = T0; |
410 | 2c0262af | bellard | } |
411 | 2c0262af | bellard | |
412 | 2c0262af | bellard | |
413 | 2c0262af | bellard | void OPPROTO glue(glue(op_shrd, MEM_SUFFIX), _T0_T1_ECX_cc)(void) |
414 | 2c0262af | bellard | { |
415 | 14ce26e7 | bellard | int count;
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416 | 14ce26e7 | bellard | target_long tmp; |
417 | 14ce26e7 | bellard | |
418 | 14ce26e7 | bellard | count = ECX & SHIFT1_MASK; |
419 | 2c0262af | bellard | if (count) {
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420 | 2c0262af | bellard | T0 &= DATA_MASK; |
421 | 2c0262af | bellard | T1 &= DATA_MASK; |
422 | 2c0262af | bellard | tmp = T0 >> (count - 1);
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423 | 2c0262af | bellard | T0 = (T0 >> count) | (T1 << (DATA_BITS - count)); |
424 | 2c0262af | bellard | #ifdef MEM_WRITE
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425 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
426 | 2c0262af | bellard | #endif
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427 | 2c0262af | bellard | CC_SRC = tmp; |
428 | 2c0262af | bellard | CC_DST = T0; |
429 | 2c0262af | bellard | CC_OP = CC_OP_SARB + SHIFT; |
430 | 2c0262af | bellard | } |
431 | 2c0262af | bellard | FORCE_RET(); |
432 | 2c0262af | bellard | } |
433 | 2c0262af | bellard | #endif
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434 | 2c0262af | bellard | |
435 | 2c0262af | bellard | /* carry add/sub (we only need to set CC_OP differently) */
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436 | 2c0262af | bellard | |
437 | 2c0262af | bellard | void OPPROTO glue(glue(op_adc, MEM_SUFFIX), _T0_T1_cc)(void) |
438 | 2c0262af | bellard | { |
439 | 2c0262af | bellard | int cf;
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440 | 2c0262af | bellard | cf = cc_table[CC_OP].compute_c(); |
441 | 2c0262af | bellard | T0 = T0 + T1 + cf; |
442 | 2c0262af | bellard | #ifdef MEM_WRITE
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443 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
444 | 2c0262af | bellard | #endif
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445 | 2c0262af | bellard | CC_SRC = T1; |
446 | 2c0262af | bellard | CC_DST = T0; |
447 | 14ce26e7 | bellard | CC_OP = CC_OP_ADDB + SHIFT + cf * 4;
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448 | 2c0262af | bellard | } |
449 | 2c0262af | bellard | |
450 | 2c0262af | bellard | void OPPROTO glue(glue(op_sbb, MEM_SUFFIX), _T0_T1_cc)(void) |
451 | 2c0262af | bellard | { |
452 | 2c0262af | bellard | int cf;
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453 | 2c0262af | bellard | cf = cc_table[CC_OP].compute_c(); |
454 | 2c0262af | bellard | T0 = T0 - T1 - cf; |
455 | 2c0262af | bellard | #ifdef MEM_WRITE
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456 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
457 | 2c0262af | bellard | #endif
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458 | 2c0262af | bellard | CC_SRC = T1; |
459 | 2c0262af | bellard | CC_DST = T0; |
460 | 14ce26e7 | bellard | CC_OP = CC_OP_SUBB + SHIFT + cf * 4;
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461 | 2c0262af | bellard | } |
462 | 2c0262af | bellard | |
463 | 2c0262af | bellard | void OPPROTO glue(glue(op_cmpxchg, MEM_SUFFIX), _T0_T1_EAX_cc)(void) |
464 | 2c0262af | bellard | { |
465 | 14ce26e7 | bellard | target_ulong src, dst; |
466 | 2c0262af | bellard | |
467 | 2c0262af | bellard | src = T0; |
468 | 2c0262af | bellard | dst = EAX - T0; |
469 | 2c0262af | bellard | if ((DATA_TYPE)dst == 0) { |
470 | 2c0262af | bellard | T0 = T1; |
471 | 1e4fe7ce | bellard | #ifdef MEM_WRITE
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472 | 14ce26e7 | bellard | glue(st, MEM_SUFFIX)(A0, T0); |
473 | 1e4fe7ce | bellard | #endif
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474 | 2c0262af | bellard | } else {
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475 | 2c0262af | bellard | EAX = (EAX & ~DATA_MASK) | (T0 & DATA_MASK); |
476 | 2c0262af | bellard | } |
477 | 2c0262af | bellard | CC_SRC = src; |
478 | 2c0262af | bellard | CC_DST = dst; |
479 | 2c0262af | bellard | FORCE_RET(); |
480 | 2c0262af | bellard | } |
481 | 2c0262af | bellard | |
482 | 2c0262af | bellard | #undef MEM_SUFFIX
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483 | 2c0262af | bellard | #undef MEM_WRITE |