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1 | 27503323 | bellard | /*
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2 | 27503323 | bellard | * QEMU DMA emulation
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3 | 85571bc7 | bellard | *
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4 | 85571bc7 | bellard | * Copyright (c) 2003-2004 Vassili Karpov (malc)
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5 | 85571bc7 | bellard | *
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6 | 27503323 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 27503323 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 27503323 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 27503323 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 27503323 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 27503323 | bellard | * furnished to do so, subject to the following conditions:
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12 | 27503323 | bellard | *
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13 | 27503323 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 27503323 | bellard | * all copies or substantial portions of the Software.
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15 | 27503323 | bellard | *
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16 | 27503323 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 27503323 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 27503323 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 27503323 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 27503323 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 27503323 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 27503323 | bellard | * THE SOFTWARE.
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23 | 27503323 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "isa.h" |
26 | 27503323 | bellard | |
27 | 85571bc7 | bellard | /* #define DEBUG_DMA */
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28 | 7ebb5e41 | bellard | |
29 | 85571bc7 | bellard | #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) |
30 | 27503323 | bellard | #ifdef DEBUG_DMA
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31 | 27503323 | bellard | #define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__) |
32 | 27503323 | bellard | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
33 | 27503323 | bellard | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) |
34 | 27503323 | bellard | #else
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35 | 27503323 | bellard | #define lwarn(...)
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36 | 27503323 | bellard | #define linfo(...)
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37 | 27503323 | bellard | #define ldebug(...)
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38 | 27503323 | bellard | #endif
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39 | 27503323 | bellard | |
40 | 27503323 | bellard | #define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0]))) |
41 | 27503323 | bellard | |
42 | 27503323 | bellard | struct dma_regs {
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43 | 27503323 | bellard | int now[2]; |
44 | 27503323 | bellard | uint16_t base[2];
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45 | 27503323 | bellard | uint8_t mode; |
46 | 27503323 | bellard | uint8_t page; |
47 | b0bda528 | bellard | uint8_t pageh; |
48 | 27503323 | bellard | uint8_t dack; |
49 | 27503323 | bellard | uint8_t eop; |
50 | 16f62432 | bellard | DMA_transfer_handler transfer_handler; |
51 | 16f62432 | bellard | void *opaque;
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52 | 27503323 | bellard | }; |
53 | 27503323 | bellard | |
54 | 27503323 | bellard | #define ADDR 0 |
55 | 27503323 | bellard | #define COUNT 1 |
56 | 27503323 | bellard | |
57 | 27503323 | bellard | static struct dma_cont { |
58 | 27503323 | bellard | uint8_t status; |
59 | 27503323 | bellard | uint8_t command; |
60 | 27503323 | bellard | uint8_t mask; |
61 | 27503323 | bellard | uint8_t flip_flop; |
62 | 9eb153f1 | bellard | int dshift;
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63 | 27503323 | bellard | struct dma_regs regs[4]; |
64 | 27503323 | bellard | } dma_controllers[2];
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65 | 27503323 | bellard | |
66 | 27503323 | bellard | enum {
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67 | e875c40a | bellard | CMD_MEMORY_TO_MEMORY = 0x01,
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68 | e875c40a | bellard | CMD_FIXED_ADDRESS = 0x02,
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69 | e875c40a | bellard | CMD_BLOCK_CONTROLLER = 0x04,
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70 | e875c40a | bellard | CMD_COMPRESSED_TIME = 0x08,
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71 | e875c40a | bellard | CMD_CYCLIC_PRIORITY = 0x10,
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72 | e875c40a | bellard | CMD_EXTENDED_WRITE = 0x20,
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73 | e875c40a | bellard | CMD_LOW_DREQ = 0x40,
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74 | e875c40a | bellard | CMD_LOW_DACK = 0x80,
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75 | e875c40a | bellard | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS |
76 | e875c40a | bellard | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE |
77 | e875c40a | bellard | | CMD_LOW_DREQ | CMD_LOW_DACK |
78 | 27503323 | bellard | |
79 | 27503323 | bellard | }; |
80 | 27503323 | bellard | |
81 | 492c30af | aliguori | static void DMA_run (void); |
82 | 492c30af | aliguori | |
83 | 9eb153f1 | bellard | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
84 | 9eb153f1 | bellard | |
85 | 7d977de7 | bellard | static void write_page (void *opaque, uint32_t nport, uint32_t data) |
86 | 27503323 | bellard | { |
87 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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88 | 27503323 | bellard | int ichan;
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89 | 27503323 | bellard | |
90 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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91 | 27503323 | bellard | if (-1 == ichan) { |
92 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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93 | 27503323 | bellard | return;
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94 | 27503323 | bellard | } |
95 | 9eb153f1 | bellard | d->regs[ichan].page = data; |
96 | 9eb153f1 | bellard | } |
97 | 9eb153f1 | bellard | |
98 | b0bda528 | bellard | static void write_pageh (void *opaque, uint32_t nport, uint32_t data) |
99 | 9eb153f1 | bellard | { |
100 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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101 | 9eb153f1 | bellard | int ichan;
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102 | 27503323 | bellard | |
103 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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104 | b0bda528 | bellard | if (-1 == ichan) { |
105 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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106 | b0bda528 | bellard | return;
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107 | b0bda528 | bellard | } |
108 | b0bda528 | bellard | d->regs[ichan].pageh = data; |
109 | b0bda528 | bellard | } |
110 | 9eb153f1 | bellard | |
111 | b0bda528 | bellard | static uint32_t read_page (void *opaque, uint32_t nport) |
112 | b0bda528 | bellard | { |
113 | b0bda528 | bellard | struct dma_cont *d = opaque;
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114 | b0bda528 | bellard | int ichan;
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115 | b0bda528 | bellard | |
116 | b0bda528 | bellard | ichan = channels[nport & 7];
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117 | 9eb153f1 | bellard | if (-1 == ichan) { |
118 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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119 | 9eb153f1 | bellard | return 0; |
120 | 9eb153f1 | bellard | } |
121 | 9eb153f1 | bellard | return d->regs[ichan].page;
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122 | 27503323 | bellard | } |
123 | 27503323 | bellard | |
124 | b0bda528 | bellard | static uint32_t read_pageh (void *opaque, uint32_t nport) |
125 | b0bda528 | bellard | { |
126 | b0bda528 | bellard | struct dma_cont *d = opaque;
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127 | b0bda528 | bellard | int ichan;
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128 | b0bda528 | bellard | |
129 | b0bda528 | bellard | ichan = channels[nport & 7];
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130 | b0bda528 | bellard | if (-1 == ichan) { |
131 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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132 | b0bda528 | bellard | return 0; |
133 | b0bda528 | bellard | } |
134 | b0bda528 | bellard | return d->regs[ichan].pageh;
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135 | b0bda528 | bellard | } |
136 | b0bda528 | bellard | |
137 | 9eb153f1 | bellard | static inline void init_chan (struct dma_cont *d, int ichan) |
138 | 27503323 | bellard | { |
139 | 27503323 | bellard | struct dma_regs *r;
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140 | 27503323 | bellard | |
141 | 9eb153f1 | bellard | r = d->regs + ichan; |
142 | 85571bc7 | bellard | r->now[ADDR] = r->base[ADDR] << d->dshift; |
143 | 27503323 | bellard | r->now[COUNT] = 0;
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144 | 27503323 | bellard | } |
145 | 27503323 | bellard | |
146 | 9eb153f1 | bellard | static inline int getff (struct dma_cont *d) |
147 | 27503323 | bellard | { |
148 | 27503323 | bellard | int ff;
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149 | 27503323 | bellard | |
150 | 9eb153f1 | bellard | ff = d->flip_flop; |
151 | 9eb153f1 | bellard | d->flip_flop = !ff; |
152 | 27503323 | bellard | return ff;
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153 | 27503323 | bellard | } |
154 | 27503323 | bellard | |
155 | 7d977de7 | bellard | static uint32_t read_chan (void *opaque, uint32_t nport) |
156 | 27503323 | bellard | { |
157 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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158 | 85571bc7 | bellard | int ichan, nreg, iport, ff, val, dir;
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159 | 27503323 | bellard | struct dma_regs *r;
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160 | 27503323 | bellard | |
161 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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162 | 9eb153f1 | bellard | ichan = iport >> 1;
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163 | 9eb153f1 | bellard | nreg = iport & 1;
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164 | 9eb153f1 | bellard | r = d->regs + ichan; |
165 | 27503323 | bellard | |
166 | 85571bc7 | bellard | dir = ((r->mode >> 5) & 1) ? -1 : 1; |
167 | 9eb153f1 | bellard | ff = getff (d); |
168 | 27503323 | bellard | if (nreg)
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169 | 9eb153f1 | bellard | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
170 | 27503323 | bellard | else
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171 | 85571bc7 | bellard | val = r->now[ADDR] + r->now[COUNT] * dir; |
172 | 27503323 | bellard | |
173 | 85571bc7 | bellard | ldebug ("read_chan %#x -> %d\n", iport, val);
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174 | 9eb153f1 | bellard | return (val >> (d->dshift + (ff << 3))) & 0xff; |
175 | 27503323 | bellard | } |
176 | 27503323 | bellard | |
177 | 7d977de7 | bellard | static void write_chan (void *opaque, uint32_t nport, uint32_t data) |
178 | 27503323 | bellard | { |
179 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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180 | 9eb153f1 | bellard | int iport, ichan, nreg;
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181 | 27503323 | bellard | struct dma_regs *r;
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182 | 27503323 | bellard | |
183 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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184 | 9eb153f1 | bellard | ichan = iport >> 1;
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185 | 9eb153f1 | bellard | nreg = iport & 1;
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186 | 9eb153f1 | bellard | r = d->regs + ichan; |
187 | 9eb153f1 | bellard | if (getff (d)) {
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188 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
189 | 9eb153f1 | bellard | init_chan (d, ichan); |
190 | 3504fe17 | bellard | } else {
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191 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
192 | 27503323 | bellard | } |
193 | 27503323 | bellard | } |
194 | 27503323 | bellard | |
195 | 7d977de7 | bellard | static void write_cont (void *opaque, uint32_t nport, uint32_t data) |
196 | 27503323 | bellard | { |
197 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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198 | 85571bc7 | bellard | int iport, ichan = 0; |
199 | 27503323 | bellard | |
200 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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201 | 27503323 | bellard | switch (iport) {
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202 | 85571bc7 | bellard | case 0x08: /* command */ |
203 | df475d18 | bellard | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
204 | 85571bc7 | bellard | dolog ("command %#x not supported\n", data);
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205 | df475d18 | bellard | return;
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206 | 27503323 | bellard | } |
207 | 27503323 | bellard | d->command = data; |
208 | 27503323 | bellard | break;
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209 | 27503323 | bellard | |
210 | 85571bc7 | bellard | case 0x09: |
211 | 27503323 | bellard | ichan = data & 3;
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212 | 27503323 | bellard | if (data & 4) { |
213 | 27503323 | bellard | d->status |= 1 << (ichan + 4); |
214 | 27503323 | bellard | } |
215 | 27503323 | bellard | else {
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216 | 27503323 | bellard | d->status &= ~(1 << (ichan + 4)); |
217 | 27503323 | bellard | } |
218 | 27503323 | bellard | d->status &= ~(1 << ichan);
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219 | 492c30af | aliguori | DMA_run(); |
220 | 27503323 | bellard | break;
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221 | 27503323 | bellard | |
222 | 85571bc7 | bellard | case 0x0a: /* single mask */ |
223 | 27503323 | bellard | if (data & 4) |
224 | 27503323 | bellard | d->mask |= 1 << (data & 3); |
225 | 27503323 | bellard | else
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226 | 27503323 | bellard | d->mask &= ~(1 << (data & 3)); |
227 | 492c30af | aliguori | DMA_run(); |
228 | 27503323 | bellard | break;
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229 | 27503323 | bellard | |
230 | 85571bc7 | bellard | case 0x0b: /* mode */ |
231 | 27503323 | bellard | { |
232 | 16d17fdb | bellard | ichan = data & 3;
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233 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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234 | 85571bc7 | bellard | { |
235 | 85571bc7 | bellard | int op, ai, dir, opmode;
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236 | e875c40a | bellard | op = (data >> 2) & 3; |
237 | e875c40a | bellard | ai = (data >> 4) & 1; |
238 | e875c40a | bellard | dir = (data >> 5) & 1; |
239 | e875c40a | bellard | opmode = (data >> 6) & 3; |
240 | 27503323 | bellard | |
241 | e875c40a | bellard | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
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242 | e875c40a | bellard | ichan, op, ai, dir, opmode); |
243 | 85571bc7 | bellard | } |
244 | 27503323 | bellard | #endif
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245 | 27503323 | bellard | d->regs[ichan].mode = data; |
246 | 27503323 | bellard | break;
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247 | 27503323 | bellard | } |
248 | 27503323 | bellard | |
249 | 85571bc7 | bellard | case 0x0c: /* clear flip flop */ |
250 | 27503323 | bellard | d->flip_flop = 0;
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251 | 27503323 | bellard | break;
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252 | 27503323 | bellard | |
253 | 85571bc7 | bellard | case 0x0d: /* reset */ |
254 | 27503323 | bellard | d->flip_flop = 0;
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255 | 27503323 | bellard | d->mask = ~0;
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256 | 27503323 | bellard | d->status = 0;
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257 | 27503323 | bellard | d->command = 0;
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258 | 27503323 | bellard | break;
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259 | 27503323 | bellard | |
260 | 85571bc7 | bellard | case 0x0e: /* clear mask for all channels */ |
261 | 27503323 | bellard | d->mask = 0;
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262 | 492c30af | aliguori | DMA_run(); |
263 | 27503323 | bellard | break;
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264 | 27503323 | bellard | |
265 | 85571bc7 | bellard | case 0x0f: /* write mask for all channels */ |
266 | 27503323 | bellard | d->mask = data; |
267 | 492c30af | aliguori | DMA_run(); |
268 | 27503323 | bellard | break;
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269 | 27503323 | bellard | |
270 | 27503323 | bellard | default:
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271 | 85571bc7 | bellard | dolog ("unknown iport %#x\n", iport);
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272 | df475d18 | bellard | break;
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273 | 27503323 | bellard | } |
274 | 27503323 | bellard | |
275 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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276 | 27503323 | bellard | if (0xc != iport) { |
277 | 85571bc7 | bellard | linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
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278 | 9eb153f1 | bellard | nport, ichan, data); |
279 | 27503323 | bellard | } |
280 | 27503323 | bellard | #endif
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281 | 27503323 | bellard | } |
282 | 27503323 | bellard | |
283 | 9eb153f1 | bellard | static uint32_t read_cont (void *opaque, uint32_t nport) |
284 | 9eb153f1 | bellard | { |
285 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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286 | 9eb153f1 | bellard | int iport, val;
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287 | 85571bc7 | bellard | |
288 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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289 | 9eb153f1 | bellard | switch (iport) {
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290 | 85571bc7 | bellard | case 0x08: /* status */ |
291 | 9eb153f1 | bellard | val = d->status; |
292 | 9eb153f1 | bellard | d->status &= 0xf0;
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293 | 9eb153f1 | bellard | break;
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294 | 85571bc7 | bellard | case 0x0f: /* mask */ |
295 | 9eb153f1 | bellard | val = d->mask; |
296 | 9eb153f1 | bellard | break;
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297 | 9eb153f1 | bellard | default:
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298 | 9eb153f1 | bellard | val = 0;
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299 | 9eb153f1 | bellard | break;
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300 | 9eb153f1 | bellard | } |
301 | 85571bc7 | bellard | |
302 | 85571bc7 | bellard | ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
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303 | 9eb153f1 | bellard | return val;
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304 | 9eb153f1 | bellard | } |
305 | 9eb153f1 | bellard | |
306 | 27503323 | bellard | int DMA_get_channel_mode (int nchan) |
307 | 27503323 | bellard | { |
308 | 27503323 | bellard | return dma_controllers[nchan > 3].regs[nchan & 3].mode; |
309 | 27503323 | bellard | } |
310 | 27503323 | bellard | |
311 | 27503323 | bellard | void DMA_hold_DREQ (int nchan) |
312 | 27503323 | bellard | { |
313 | 27503323 | bellard | int ncont, ichan;
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314 | 27503323 | bellard | |
315 | 27503323 | bellard | ncont = nchan > 3;
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316 | 27503323 | bellard | ichan = nchan & 3;
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317 | 27503323 | bellard | linfo ("held cont=%d chan=%d\n", ncont, ichan);
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318 | 27503323 | bellard | dma_controllers[ncont].status |= 1 << (ichan + 4); |
319 | 492c30af | aliguori | DMA_run(); |
320 | 27503323 | bellard | } |
321 | 27503323 | bellard | |
322 | 27503323 | bellard | void DMA_release_DREQ (int nchan) |
323 | 27503323 | bellard | { |
324 | 27503323 | bellard | int ncont, ichan;
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325 | 27503323 | bellard | |
326 | 27503323 | bellard | ncont = nchan > 3;
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327 | 27503323 | bellard | ichan = nchan & 3;
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328 | 27503323 | bellard | linfo ("released cont=%d chan=%d\n", ncont, ichan);
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329 | 27503323 | bellard | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); |
330 | 492c30af | aliguori | DMA_run(); |
331 | 27503323 | bellard | } |
332 | 27503323 | bellard | |
333 | 27503323 | bellard | static void channel_run (int ncont, int ichan) |
334 | 27503323 | bellard | { |
335 | 27503323 | bellard | int n;
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336 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
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337 | 85571bc7 | bellard | #ifdef DEBUG_DMA
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338 | 85571bc7 | bellard | int dir, opmode;
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339 | 27503323 | bellard | |
340 | 85571bc7 | bellard | dir = (r->mode >> 5) & 1; |
341 | 85571bc7 | bellard | opmode = (r->mode >> 6) & 3; |
342 | 27503323 | bellard | |
343 | 85571bc7 | bellard | if (dir) {
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344 | 85571bc7 | bellard | dolog ("DMA in address decrement mode\n");
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345 | 85571bc7 | bellard | } |
346 | 85571bc7 | bellard | if (opmode != 1) { |
347 | 85571bc7 | bellard | dolog ("DMA not in single mode select %#x\n", opmode);
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348 | 85571bc7 | bellard | } |
349 | 85571bc7 | bellard | #endif
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350 | 27503323 | bellard | |
351 | 85571bc7 | bellard | r = dma_controllers[ncont].regs + ichan; |
352 | 85571bc7 | bellard | n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
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353 | 85571bc7 | bellard | r->now[COUNT], (r->base[COUNT] + 1) << ncont);
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354 | 85571bc7 | bellard | r->now[COUNT] = n; |
355 | 85571bc7 | bellard | ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); |
356 | 27503323 | bellard | } |
357 | 27503323 | bellard | |
358 | 492c30af | aliguori | static QEMUBH *dma_bh;
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359 | 492c30af | aliguori | |
360 | 492c30af | aliguori | static void DMA_run (void) |
361 | 27503323 | bellard | { |
362 | 27503323 | bellard | struct dma_cont *d;
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363 | 27503323 | bellard | int icont, ichan;
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364 | 492c30af | aliguori | int rearm = 0; |
365 | 27503323 | bellard | |
366 | 27503323 | bellard | d = dma_controllers; |
367 | 27503323 | bellard | |
368 | 27503323 | bellard | for (icont = 0; icont < 2; icont++, d++) { |
369 | 27503323 | bellard | for (ichan = 0; ichan < 4; ichan++) { |
370 | 27503323 | bellard | int mask;
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371 | 27503323 | bellard | |
372 | 27503323 | bellard | mask = 1 << ichan;
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373 | 27503323 | bellard | |
374 | 492c30af | aliguori | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) { |
375 | 27503323 | bellard | channel_run (icont, ichan); |
376 | 492c30af | aliguori | rearm = 1;
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377 | 492c30af | aliguori | } |
378 | 27503323 | bellard | } |
379 | 27503323 | bellard | } |
380 | 492c30af | aliguori | |
381 | 492c30af | aliguori | if (rearm)
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382 | 492c30af | aliguori | qemu_bh_schedule_idle(dma_bh); |
383 | 492c30af | aliguori | } |
384 | 492c30af | aliguori | |
385 | 492c30af | aliguori | static void DMA_run_bh(void *unused) |
386 | 492c30af | aliguori | { |
387 | 492c30af | aliguori | DMA_run(); |
388 | 27503323 | bellard | } |
389 | 27503323 | bellard | |
390 | 27503323 | bellard | void DMA_register_channel (int nchan, |
391 | 85571bc7 | bellard | DMA_transfer_handler transfer_handler, |
392 | 16f62432 | bellard | void *opaque)
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393 | 27503323 | bellard | { |
394 | 27503323 | bellard | struct dma_regs *r;
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395 | 27503323 | bellard | int ichan, ncont;
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396 | 27503323 | bellard | |
397 | 27503323 | bellard | ncont = nchan > 3;
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398 | 27503323 | bellard | ichan = nchan & 3;
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399 | 27503323 | bellard | |
400 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
401 | 16f62432 | bellard | r->transfer_handler = transfer_handler; |
402 | 16f62432 | bellard | r->opaque = opaque; |
403 | 16f62432 | bellard | } |
404 | 16f62432 | bellard | |
405 | 85571bc7 | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int len) |
406 | 85571bc7 | bellard | { |
407 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
408 | 71db710f | blueswir1 | target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
409 | 85571bc7 | bellard | |
410 | 85571bc7 | bellard | if (r->mode & 0x20) { |
411 | 85571bc7 | bellard | int i;
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412 | 85571bc7 | bellard | uint8_t *p = buf; |
413 | 85571bc7 | bellard | |
414 | 85571bc7 | bellard | cpu_physical_memory_read (addr - pos - len, buf, len); |
415 | 85571bc7 | bellard | /* What about 16bit transfers? */
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416 | 85571bc7 | bellard | for (i = 0; i < len >> 1; i++) { |
417 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
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418 | 85571bc7 | bellard | p[i] = b; |
419 | 85571bc7 | bellard | } |
420 | 85571bc7 | bellard | } |
421 | 85571bc7 | bellard | else
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422 | 85571bc7 | bellard | cpu_physical_memory_read (addr + pos, buf, len); |
423 | 85571bc7 | bellard | |
424 | 85571bc7 | bellard | return len;
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425 | 85571bc7 | bellard | } |
426 | 85571bc7 | bellard | |
427 | 85571bc7 | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int len) |
428 | 85571bc7 | bellard | { |
429 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
430 | 71db710f | blueswir1 | target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
431 | 85571bc7 | bellard | |
432 | 85571bc7 | bellard | if (r->mode & 0x20) { |
433 | 85571bc7 | bellard | int i;
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434 | 85571bc7 | bellard | uint8_t *p = buf; |
435 | 85571bc7 | bellard | |
436 | 85571bc7 | bellard | cpu_physical_memory_write (addr - pos - len, buf, len); |
437 | 85571bc7 | bellard | /* What about 16bit transfers? */
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438 | 85571bc7 | bellard | for (i = 0; i < len; i++) { |
439 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
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440 | 85571bc7 | bellard | p[i] = b; |
441 | 85571bc7 | bellard | } |
442 | 85571bc7 | bellard | } |
443 | 85571bc7 | bellard | else
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444 | 85571bc7 | bellard | cpu_physical_memory_write (addr + pos, buf, len); |
445 | 85571bc7 | bellard | |
446 | 85571bc7 | bellard | return len;
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447 | 85571bc7 | bellard | } |
448 | 85571bc7 | bellard | |
449 | 16f62432 | bellard | /* request the emulator to transfer a new DMA memory block ASAP */
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450 | 16f62432 | bellard | void DMA_schedule(int nchan) |
451 | 16f62432 | bellard | { |
452 | c68ea704 | bellard | CPUState *env = cpu_single_env; |
453 | c68ea704 | bellard | if (env)
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454 | c68ea704 | bellard | cpu_interrupt(env, CPU_INTERRUPT_EXIT); |
455 | 27503323 | bellard | } |
456 | 27503323 | bellard | |
457 | d7d02e3c | bellard | static void dma_reset(void *opaque) |
458 | d7d02e3c | bellard | { |
459 | d7d02e3c | bellard | struct dma_cont *d = opaque;
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460 | d7d02e3c | bellard | write_cont (d, (0x0d << d->dshift), 0); |
461 | d7d02e3c | bellard | } |
462 | d7d02e3c | bellard | |
463 | ca9cc28c | balrog | static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len) |
464 | ca9cc28c | balrog | { |
465 | ca9cc28c | balrog | dolog ("unregistered DMA channel used nchan=%d dma_pos=%d dma_len=%d\n",
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466 | ca9cc28c | balrog | nchan, dma_pos, dma_len); |
467 | ca9cc28c | balrog | return dma_pos;
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468 | ca9cc28c | balrog | } |
469 | ca9cc28c | balrog | |
470 | 9eb153f1 | bellard | /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
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471 | 85571bc7 | bellard | static void dma_init2(struct dma_cont *d, int base, int dshift, |
472 | b0bda528 | bellard | int page_base, int pageh_base) |
473 | 27503323 | bellard | { |
474 | d70040bc | pbrook | static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; |
475 | 27503323 | bellard | int i;
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476 | 27503323 | bellard | |
477 | 9eb153f1 | bellard | d->dshift = dshift; |
478 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
479 | 9eb153f1 | bellard | register_ioport_write (base + (i << dshift), 1, 1, write_chan, d); |
480 | 9eb153f1 | bellard | register_ioport_read (base + (i << dshift), 1, 1, read_chan, d); |
481 | 27503323 | bellard | } |
482 | 27503323 | bellard | for (i = 0; i < LENOFA (page_port_list); i++) { |
483 | 85571bc7 | bellard | register_ioport_write (page_base + page_port_list[i], 1, 1, |
484 | 9eb153f1 | bellard | write_page, d); |
485 | 85571bc7 | bellard | register_ioport_read (page_base + page_port_list[i], 1, 1, |
486 | 9eb153f1 | bellard | read_page, d); |
487 | b0bda528 | bellard | if (pageh_base >= 0) { |
488 | 85571bc7 | bellard | register_ioport_write (pageh_base + page_port_list[i], 1, 1, |
489 | b0bda528 | bellard | write_pageh, d); |
490 | 85571bc7 | bellard | register_ioport_read (pageh_base + page_port_list[i], 1, 1, |
491 | b0bda528 | bellard | read_pageh, d); |
492 | b0bda528 | bellard | } |
493 | 27503323 | bellard | } |
494 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
495 | 85571bc7 | bellard | register_ioport_write (base + ((i + 8) << dshift), 1, 1, |
496 | 9eb153f1 | bellard | write_cont, d); |
497 | 85571bc7 | bellard | register_ioport_read (base + ((i + 8) << dshift), 1, 1, |
498 | 9eb153f1 | bellard | read_cont, d); |
499 | 27503323 | bellard | } |
500 | d7d02e3c | bellard | qemu_register_reset(dma_reset, d); |
501 | d7d02e3c | bellard | dma_reset(d); |
502 | ca9cc28c | balrog | for (i = 0; i < LENOFA (d->regs); ++i) { |
503 | ca9cc28c | balrog | d->regs[i].transfer_handler = dma_phony_handler; |
504 | ca9cc28c | balrog | } |
505 | 9eb153f1 | bellard | } |
506 | 27503323 | bellard | |
507 | 85571bc7 | bellard | static void dma_save (QEMUFile *f, void *opaque) |
508 | 85571bc7 | bellard | { |
509 | 85571bc7 | bellard | struct dma_cont *d = opaque;
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510 | 85571bc7 | bellard | int i;
|
511 | 85571bc7 | bellard | |
512 | 85571bc7 | bellard | /* qemu_put_8s (f, &d->status); */
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513 | 85571bc7 | bellard | qemu_put_8s (f, &d->command); |
514 | 85571bc7 | bellard | qemu_put_8s (f, &d->mask); |
515 | 85571bc7 | bellard | qemu_put_8s (f, &d->flip_flop); |
516 | bee8d684 | ths | qemu_put_be32 (f, d->dshift); |
517 | 85571bc7 | bellard | |
518 | 85571bc7 | bellard | for (i = 0; i < 4; ++i) { |
519 | 85571bc7 | bellard | struct dma_regs *r = &d->regs[i];
|
520 | bee8d684 | ths | qemu_put_be32 (f, r->now[0]);
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521 | bee8d684 | ths | qemu_put_be32 (f, r->now[1]);
|
522 | 85571bc7 | bellard | qemu_put_be16s (f, &r->base[0]);
|
523 | 85571bc7 | bellard | qemu_put_be16s (f, &r->base[1]);
|
524 | 85571bc7 | bellard | qemu_put_8s (f, &r->mode); |
525 | 85571bc7 | bellard | qemu_put_8s (f, &r->page); |
526 | 85571bc7 | bellard | qemu_put_8s (f, &r->pageh); |
527 | 85571bc7 | bellard | qemu_put_8s (f, &r->dack); |
528 | 85571bc7 | bellard | qemu_put_8s (f, &r->eop); |
529 | 85571bc7 | bellard | } |
530 | 85571bc7 | bellard | } |
531 | 85571bc7 | bellard | |
532 | 85571bc7 | bellard | static int dma_load (QEMUFile *f, void *opaque, int version_id) |
533 | 85571bc7 | bellard | { |
534 | 85571bc7 | bellard | struct dma_cont *d = opaque;
|
535 | 85571bc7 | bellard | int i;
|
536 | 85571bc7 | bellard | |
537 | 85571bc7 | bellard | if (version_id != 1) |
538 | 85571bc7 | bellard | return -EINVAL;
|
539 | 85571bc7 | bellard | |
540 | 85571bc7 | bellard | /* qemu_get_8s (f, &d->status); */
|
541 | 85571bc7 | bellard | qemu_get_8s (f, &d->command); |
542 | 85571bc7 | bellard | qemu_get_8s (f, &d->mask); |
543 | 85571bc7 | bellard | qemu_get_8s (f, &d->flip_flop); |
544 | bee8d684 | ths | d->dshift=qemu_get_be32 (f); |
545 | 85571bc7 | bellard | |
546 | 85571bc7 | bellard | for (i = 0; i < 4; ++i) { |
547 | 85571bc7 | bellard | struct dma_regs *r = &d->regs[i];
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548 | bee8d684 | ths | r->now[0]=qemu_get_be32 (f);
|
549 | bee8d684 | ths | r->now[1]=qemu_get_be32 (f);
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550 | 85571bc7 | bellard | qemu_get_be16s (f, &r->base[0]);
|
551 | 85571bc7 | bellard | qemu_get_be16s (f, &r->base[1]);
|
552 | 85571bc7 | bellard | qemu_get_8s (f, &r->mode); |
553 | 85571bc7 | bellard | qemu_get_8s (f, &r->page); |
554 | 85571bc7 | bellard | qemu_get_8s (f, &r->pageh); |
555 | 85571bc7 | bellard | qemu_get_8s (f, &r->dack); |
556 | 85571bc7 | bellard | qemu_get_8s (f, &r->eop); |
557 | 85571bc7 | bellard | } |
558 | 492c30af | aliguori | |
559 | 492c30af | aliguori | DMA_run(); |
560 | 492c30af | aliguori | |
561 | 85571bc7 | bellard | return 0; |
562 | 85571bc7 | bellard | } |
563 | 85571bc7 | bellard | |
564 | b0bda528 | bellard | void DMA_init (int high_page_enable) |
565 | 9eb153f1 | bellard | { |
566 | 85571bc7 | bellard | dma_init2(&dma_controllers[0], 0x00, 0, 0x80, |
567 | b0bda528 | bellard | high_page_enable ? 0x480 : -1); |
568 | b0bda528 | bellard | dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, |
569 | b0bda528 | bellard | high_page_enable ? 0x488 : -1); |
570 | 85571bc7 | bellard | register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]); |
571 | 85571bc7 | bellard | register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]); |
572 | 492c30af | aliguori | |
573 | 492c30af | aliguori | dma_bh = qemu_bh_new(DMA_run_bh, NULL);
|
574 | 27503323 | bellard | } |