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1 | 2f062c72 | ths | /*
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2 | 2f062c72 | ths | * QEMU SCI/SCIF serial port emulation
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3 | 2f062c72 | ths | *
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4 | 2f062c72 | ths | * Copyright (c) 2007 Magnus Damm
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5 | 2f062c72 | ths | *
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6 | 2f062c72 | ths | * Based on serial.c - QEMU 16450 UART emulation
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7 | 2f062c72 | ths | * Copyright (c) 2003-2004 Fabrice Bellard
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8 | 2f062c72 | ths | *
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9 | 2f062c72 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | 2f062c72 | ths | * of this software and associated documentation files (the "Software"), to deal
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11 | 2f062c72 | ths | * in the Software without restriction, including without limitation the rights
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12 | 2f062c72 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | 2f062c72 | ths | * copies of the Software, and to permit persons to whom the Software is
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14 | 2f062c72 | ths | * furnished to do so, subject to the following conditions:
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15 | 2f062c72 | ths | *
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16 | 2f062c72 | ths | * The above copyright notice and this permission notice shall be included in
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17 | 2f062c72 | ths | * all copies or substantial portions of the Software.
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18 | 2f062c72 | ths | *
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19 | 2f062c72 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | 2f062c72 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | 2f062c72 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | 2f062c72 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | 2f062c72 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | 2f062c72 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | 2f062c72 | ths | * THE SOFTWARE.
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26 | 2f062c72 | ths | */
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27 | 87ecb68b | pbrook | #include "hw.h" |
28 | 87ecb68b | pbrook | #include "sh.h" |
29 | 87ecb68b | pbrook | #include "qemu-char.h" |
30 | 9a9d0b81 | Benoît Canet | #include "exec-memory.h" |
31 | 2f062c72 | ths | |
32 | 2f062c72 | ths | //#define DEBUG_SERIAL
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33 | 2f062c72 | ths | |
34 | 2f062c72 | ths | #define SH_SERIAL_FLAG_TEND (1 << 0) |
35 | 2f062c72 | ths | #define SH_SERIAL_FLAG_TDE (1 << 1) |
36 | 2f062c72 | ths | #define SH_SERIAL_FLAG_RDF (1 << 2) |
37 | 2f062c72 | ths | #define SH_SERIAL_FLAG_BRK (1 << 3) |
38 | 2f062c72 | ths | #define SH_SERIAL_FLAG_DR (1 << 4) |
39 | 2f062c72 | ths | |
40 | 63242a00 | aurel32 | #define SH_RX_FIFO_LENGTH (16) |
41 | 63242a00 | aurel32 | |
42 | 2f062c72 | ths | typedef struct { |
43 | 9a9d0b81 | Benoît Canet | MemoryRegion iomem; |
44 | 9a9d0b81 | Benoît Canet | MemoryRegion iomem_p4; |
45 | 9a9d0b81 | Benoît Canet | MemoryRegion iomem_a7; |
46 | 2f062c72 | ths | uint8_t smr; |
47 | 2f062c72 | ths | uint8_t brr; |
48 | 2f062c72 | ths | uint8_t scr; |
49 | 2f062c72 | ths | uint8_t dr; /* ftdr / tdr */
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50 | 2f062c72 | ths | uint8_t sr; /* fsr / ssr */
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51 | 2f062c72 | ths | uint16_t fcr; |
52 | 2f062c72 | ths | uint8_t sptr; |
53 | 2f062c72 | ths | |
54 | 63242a00 | aurel32 | uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
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55 | 2f062c72 | ths | uint8_t rx_cnt; |
56 | 63242a00 | aurel32 | uint8_t rx_tail; |
57 | 63242a00 | aurel32 | uint8_t rx_head; |
58 | 2f062c72 | ths | |
59 | 2f062c72 | ths | int freq;
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60 | 2f062c72 | ths | int feat;
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61 | 2f062c72 | ths | int flags;
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62 | 63242a00 | aurel32 | int rtrg;
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63 | 2f062c72 | ths | |
64 | 2f062c72 | ths | CharDriverState *chr; |
65 | bf5b7423 | aurel32 | |
66 | 4e7ed2d1 | aurel32 | qemu_irq eri; |
67 | 4e7ed2d1 | aurel32 | qemu_irq rxi; |
68 | 4e7ed2d1 | aurel32 | qemu_irq txi; |
69 | 4e7ed2d1 | aurel32 | qemu_irq tei; |
70 | 4e7ed2d1 | aurel32 | qemu_irq bri; |
71 | 2f062c72 | ths | } sh_serial_state; |
72 | 2f062c72 | ths | |
73 | 63242a00 | aurel32 | static void sh_serial_clear_fifo(sh_serial_state * s) |
74 | 63242a00 | aurel32 | { |
75 | 63242a00 | aurel32 | memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
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76 | 63242a00 | aurel32 | s->rx_cnt = 0;
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77 | 63242a00 | aurel32 | s->rx_head = 0;
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78 | 63242a00 | aurel32 | s->rx_tail = 0;
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79 | 63242a00 | aurel32 | } |
80 | 63242a00 | aurel32 | |
81 | 9a9d0b81 | Benoît Canet | static void sh_serial_write(void *opaque, target_phys_addr_t offs, |
82 | 9a9d0b81 | Benoît Canet | uint64_t val, unsigned size)
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83 | 2f062c72 | ths | { |
84 | 2f062c72 | ths | sh_serial_state *s = opaque; |
85 | 2f062c72 | ths | unsigned char ch; |
86 | 2f062c72 | ths | |
87 | 2f062c72 | ths | #ifdef DEBUG_SERIAL
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88 | 8da3ff18 | pbrook | printf("sh_serial: write offs=0x%02x val=0x%02x\n",
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89 | 8da3ff18 | pbrook | offs, val); |
90 | 2f062c72 | ths | #endif
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91 | 2f062c72 | ths | switch(offs) {
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92 | 2f062c72 | ths | case 0x00: /* SMR */ |
93 | 2f062c72 | ths | s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); |
94 | 2f062c72 | ths | return;
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95 | 2f062c72 | ths | case 0x04: /* BRR */ |
96 | 2f062c72 | ths | s->brr = val; |
97 | 2f062c72 | ths | return;
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98 | 2f062c72 | ths | case 0x08: /* SCR */ |
99 | 63242a00 | aurel32 | /* TODO : For SH7751, SCIF mask should be 0xfb. */
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100 | bf5b7423 | aurel32 | s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff); |
101 | 2f062c72 | ths | if (!(val & (1 << 5))) |
102 | 2f062c72 | ths | s->flags |= SH_SERIAL_FLAG_TEND; |
103 | bf5b7423 | aurel32 | if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
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104 | 4e7ed2d1 | aurel32 | qemu_set_irq(s->txi, val & (1 << 7)); |
105 | bf5b7423 | aurel32 | } |
106 | 4e7ed2d1 | aurel32 | if (!(val & (1 << 6))) { |
107 | 4e7ed2d1 | aurel32 | qemu_set_irq(s->rxi, 0);
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108 | 63242a00 | aurel32 | } |
109 | 2f062c72 | ths | return;
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110 | 2f062c72 | ths | case 0x0c: /* FTDR / TDR */ |
111 | 2f062c72 | ths | if (s->chr) {
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112 | 2f062c72 | ths | ch = val; |
113 | 2cc6e0a1 | Anthony Liguori | qemu_chr_fe_write(s->chr, &ch, 1);
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114 | 2f062c72 | ths | } |
115 | 2f062c72 | ths | s->dr = val; |
116 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_TDE; |
117 | 2f062c72 | ths | return;
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118 | 2f062c72 | ths | #if 0
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119 | 2f062c72 | ths | case 0x14: /* FRDR / RDR */
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120 | 2f062c72 | ths | ret = 0;
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121 | 2f062c72 | ths | break;
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122 | 2f062c72 | ths | #endif
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123 | 2f062c72 | ths | } |
124 | 2f062c72 | ths | if (s->feat & SH_SERIAL_FEAT_SCIF) {
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125 | 2f062c72 | ths | switch(offs) {
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126 | 2f062c72 | ths | case 0x10: /* FSR */ |
127 | 2f062c72 | ths | if (!(val & (1 << 6))) |
128 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_TEND; |
129 | 2f062c72 | ths | if (!(val & (1 << 5))) |
130 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_TDE; |
131 | 2f062c72 | ths | if (!(val & (1 << 4))) |
132 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_BRK; |
133 | 2f062c72 | ths | if (!(val & (1 << 1))) |
134 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_RDF; |
135 | 2f062c72 | ths | if (!(val & (1 << 0))) |
136 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_DR; |
137 | 63242a00 | aurel32 | |
138 | 63242a00 | aurel32 | if (!(val & (1 << 1)) || !(val & (1 << 0))) { |
139 | 4e7ed2d1 | aurel32 | if (s->rxi) {
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140 | 4e7ed2d1 | aurel32 | qemu_set_irq(s->rxi, 0);
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141 | 63242a00 | aurel32 | } |
142 | 63242a00 | aurel32 | } |
143 | 2f062c72 | ths | return;
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144 | 2f062c72 | ths | case 0x18: /* FCR */ |
145 | 2f062c72 | ths | s->fcr = val; |
146 | 63242a00 | aurel32 | switch ((val >> 6) & 3) { |
147 | 63242a00 | aurel32 | case 0: |
148 | 63242a00 | aurel32 | s->rtrg = 1;
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149 | 63242a00 | aurel32 | break;
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150 | 63242a00 | aurel32 | case 1: |
151 | 63242a00 | aurel32 | s->rtrg = 4;
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152 | 63242a00 | aurel32 | break;
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153 | 63242a00 | aurel32 | case 2: |
154 | 63242a00 | aurel32 | s->rtrg = 8;
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155 | 63242a00 | aurel32 | break;
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156 | 63242a00 | aurel32 | case 3: |
157 | 63242a00 | aurel32 | s->rtrg = 14;
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158 | 63242a00 | aurel32 | break;
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159 | 63242a00 | aurel32 | } |
160 | 63242a00 | aurel32 | if (val & (1 << 1)) { |
161 | 63242a00 | aurel32 | sh_serial_clear_fifo(s); |
162 | 63242a00 | aurel32 | s->sr &= ~(1 << 1); |
163 | 63242a00 | aurel32 | } |
164 | 63242a00 | aurel32 | |
165 | 2f062c72 | ths | return;
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166 | 2f062c72 | ths | case 0x20: /* SPTR */ |
167 | 63242a00 | aurel32 | s->sptr = val & 0xf3;
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168 | 2f062c72 | ths | return;
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169 | 2f062c72 | ths | case 0x24: /* LSR */ |
170 | 2f062c72 | ths | return;
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171 | 2f062c72 | ths | } |
172 | 2f062c72 | ths | } |
173 | 2f062c72 | ths | else {
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174 | 2f062c72 | ths | switch(offs) {
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175 | d1f193b0 | aurel32 | #if 0
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176 | 2f062c72 | ths | case 0x0c:
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177 | 2f062c72 | ths | ret = s->dr;
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178 | 2f062c72 | ths | break;
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179 | 2f062c72 | ths | case 0x10:
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180 | 2f062c72 | ths | ret = 0;
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181 | 2f062c72 | ths | break;
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182 | d1f193b0 | aurel32 | #endif
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183 | 2f062c72 | ths | case 0x1c: |
184 | d1f193b0 | aurel32 | s->sptr = val & 0x8f;
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185 | d1f193b0 | aurel32 | return;
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186 | 2f062c72 | ths | } |
187 | 2f062c72 | ths | } |
188 | 2f062c72 | ths | |
189 | 2f062c72 | ths | fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
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190 | 43dc2a64 | Blue Swirl | abort(); |
191 | 2f062c72 | ths | } |
192 | 2f062c72 | ths | |
193 | 9a9d0b81 | Benoît Canet | static uint64_t sh_serial_read(void *opaque, target_phys_addr_t offs, |
194 | 9a9d0b81 | Benoît Canet | unsigned size)
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195 | 2f062c72 | ths | { |
196 | 2f062c72 | ths | sh_serial_state *s = opaque; |
197 | 2f062c72 | ths | uint32_t ret = ~0;
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198 | 2f062c72 | ths | |
199 | 2f062c72 | ths | #if 0
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200 | 2f062c72 | ths | switch(offs) {
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201 | 2f062c72 | ths | case 0x00:
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202 | 2f062c72 | ths | ret = s->smr;
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203 | 2f062c72 | ths | break;
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204 | 2f062c72 | ths | case 0x04:
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205 | 2f062c72 | ths | ret = s->brr;
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206 | 2f062c72 | ths | break;
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207 | 2f062c72 | ths | case 0x08:
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208 | 2f062c72 | ths | ret = s->scr;
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209 | 2f062c72 | ths | break;
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210 | 2f062c72 | ths | case 0x14:
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211 | 2f062c72 | ths | ret = 0;
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212 | 2f062c72 | ths | break;
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213 | 2f062c72 | ths | }
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214 | 2f062c72 | ths | #endif
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215 | 2f062c72 | ths | if (s->feat & SH_SERIAL_FEAT_SCIF) {
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216 | 2f062c72 | ths | switch(offs) {
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217 | bf5b7423 | aurel32 | case 0x00: /* SMR */ |
218 | bf5b7423 | aurel32 | ret = s->smr; |
219 | bf5b7423 | aurel32 | break;
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220 | bf5b7423 | aurel32 | case 0x08: /* SCR */ |
221 | bf5b7423 | aurel32 | ret = s->scr; |
222 | bf5b7423 | aurel32 | break;
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223 | 2f062c72 | ths | case 0x10: /* FSR */ |
224 | 2f062c72 | ths | ret = 0;
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225 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_TEND)
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226 | 2f062c72 | ths | ret |= (1 << 6); |
227 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_TDE)
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228 | 2f062c72 | ths | ret |= (1 << 5); |
229 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_BRK)
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230 | 2f062c72 | ths | ret |= (1 << 4); |
231 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_RDF)
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232 | 2f062c72 | ths | ret |= (1 << 1); |
233 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_DR)
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234 | 2f062c72 | ths | ret |= (1 << 0); |
235 | 2f062c72 | ths | |
236 | 63242a00 | aurel32 | if (s->scr & (1 << 5)) |
237 | 2f062c72 | ths | s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND; |
238 | 2f062c72 | ths | |
239 | 2f062c72 | ths | break;
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240 | 63242a00 | aurel32 | case 0x14: |
241 | 63242a00 | aurel32 | if (s->rx_cnt > 0) { |
242 | 63242a00 | aurel32 | ret = s->rx_fifo[s->rx_tail++]; |
243 | 63242a00 | aurel32 | s->rx_cnt--; |
244 | 63242a00 | aurel32 | if (s->rx_tail == SH_RX_FIFO_LENGTH)
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245 | 63242a00 | aurel32 | s->rx_tail = 0;
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246 | 63242a00 | aurel32 | if (s->rx_cnt < s->rtrg)
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247 | 63242a00 | aurel32 | s->flags &= ~SH_SERIAL_FLAG_RDF; |
248 | 63242a00 | aurel32 | } |
249 | 63242a00 | aurel32 | break;
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250 | 2f062c72 | ths | #if 0
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251 | 2f062c72 | ths | case 0x18:
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252 | 2f062c72 | ths | ret = s->fcr;
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253 | 2f062c72 | ths | break;
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254 | 2f062c72 | ths | #endif
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255 | 2f062c72 | ths | case 0x1c: |
256 | 2f062c72 | ths | ret = s->rx_cnt; |
257 | 2f062c72 | ths | break;
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258 | 2f062c72 | ths | case 0x20: |
259 | 2f062c72 | ths | ret = s->sptr; |
260 | 2f062c72 | ths | break;
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261 | 2f062c72 | ths | case 0x24: |
262 | 2f062c72 | ths | ret = 0;
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263 | 2f062c72 | ths | break;
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264 | 2f062c72 | ths | } |
265 | 2f062c72 | ths | } |
266 | 2f062c72 | ths | else {
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267 | 2f062c72 | ths | switch(offs) {
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268 | d1f193b0 | aurel32 | #if 0
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269 | 2f062c72 | ths | case 0x0c:
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270 | 2f062c72 | ths | ret = s->dr;
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271 | 2f062c72 | ths | break;
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272 | 2f062c72 | ths | case 0x10:
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273 | 2f062c72 | ths | ret = 0;
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274 | 2f062c72 | ths | break;
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275 | 63242a00 | aurel32 | case 0x14:
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276 | 63242a00 | aurel32 | ret = s->rx_fifo[0];
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277 | 63242a00 | aurel32 | break;
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278 | d1f193b0 | aurel32 | #endif
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279 | 2f062c72 | ths | case 0x1c: |
280 | 2f062c72 | ths | ret = s->sptr; |
281 | 2f062c72 | ths | break;
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282 | 2f062c72 | ths | } |
283 | 2f062c72 | ths | } |
284 | 2f062c72 | ths | #ifdef DEBUG_SERIAL
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285 | 8da3ff18 | pbrook | printf("sh_serial: read offs=0x%02x val=0x%x\n",
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286 | 8da3ff18 | pbrook | offs, ret); |
287 | 2f062c72 | ths | #endif
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288 | 2f062c72 | ths | |
289 | 2f062c72 | ths | if (ret & ~((1 << 16) - 1)) { |
290 | 2f062c72 | ths | fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
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291 | 43dc2a64 | Blue Swirl | abort(); |
292 | 2f062c72 | ths | } |
293 | 2f062c72 | ths | |
294 | 2f062c72 | ths | return ret;
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295 | 2f062c72 | ths | } |
296 | 2f062c72 | ths | |
297 | 2f062c72 | ths | static int sh_serial_can_receive(sh_serial_state *s) |
298 | 2f062c72 | ths | { |
299 | 63242a00 | aurel32 | return s->scr & (1 << 4); |
300 | 2f062c72 | ths | } |
301 | 2f062c72 | ths | |
302 | 2f062c72 | ths | static void sh_serial_receive_break(sh_serial_state *s) |
303 | 2f062c72 | ths | { |
304 | 63242a00 | aurel32 | if (s->feat & SH_SERIAL_FEAT_SCIF)
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305 | 63242a00 | aurel32 | s->sr |= (1 << 4); |
306 | 2f062c72 | ths | } |
307 | 2f062c72 | ths | |
308 | 2f062c72 | ths | static int sh_serial_can_receive1(void *opaque) |
309 | 2f062c72 | ths | { |
310 | 2f062c72 | ths | sh_serial_state *s = opaque; |
311 | 2f062c72 | ths | return sh_serial_can_receive(s);
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312 | 2f062c72 | ths | } |
313 | 2f062c72 | ths | |
314 | 2f062c72 | ths | static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) |
315 | 2f062c72 | ths | { |
316 | 2f062c72 | ths | sh_serial_state *s = opaque; |
317 | b7d2b020 | Aurelien Jarno | |
318 | b7d2b020 | Aurelien Jarno | if (s->feat & SH_SERIAL_FEAT_SCIF) {
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319 | b7d2b020 | Aurelien Jarno | int i;
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320 | b7d2b020 | Aurelien Jarno | for (i = 0; i < size; i++) { |
321 | b7d2b020 | Aurelien Jarno | if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
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322 | b7d2b020 | Aurelien Jarno | s->rx_fifo[s->rx_head++] = buf[i]; |
323 | b7d2b020 | Aurelien Jarno | if (s->rx_head == SH_RX_FIFO_LENGTH) {
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324 | b7d2b020 | Aurelien Jarno | s->rx_head = 0;
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325 | b7d2b020 | Aurelien Jarno | } |
326 | b7d2b020 | Aurelien Jarno | s->rx_cnt++; |
327 | b7d2b020 | Aurelien Jarno | if (s->rx_cnt >= s->rtrg) {
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328 | b7d2b020 | Aurelien Jarno | s->flags |= SH_SERIAL_FLAG_RDF; |
329 | b7d2b020 | Aurelien Jarno | if (s->scr & (1 << 6) && s->rxi) { |
330 | b7d2b020 | Aurelien Jarno | qemu_set_irq(s->rxi, 1);
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331 | b7d2b020 | Aurelien Jarno | } |
332 | b7d2b020 | Aurelien Jarno | } |
333 | b7d2b020 | Aurelien Jarno | } |
334 | b7d2b020 | Aurelien Jarno | } |
335 | b7d2b020 | Aurelien Jarno | } else {
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336 | b7d2b020 | Aurelien Jarno | s->rx_fifo[0] = buf[0]; |
337 | b7d2b020 | Aurelien Jarno | } |
338 | 2f062c72 | ths | } |
339 | 2f062c72 | ths | |
340 | 2f062c72 | ths | static void sh_serial_event(void *opaque, int event) |
341 | 2f062c72 | ths | { |
342 | 2f062c72 | ths | sh_serial_state *s = opaque; |
343 | 2f062c72 | ths | if (event == CHR_EVENT_BREAK)
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344 | 2f062c72 | ths | sh_serial_receive_break(s); |
345 | 2f062c72 | ths | } |
346 | 2f062c72 | ths | |
347 | 9a9d0b81 | Benoît Canet | static const MemoryRegionOps sh_serial_ops = { |
348 | 9a9d0b81 | Benoît Canet | .read = sh_serial_read, |
349 | 9a9d0b81 | Benoît Canet | .write = sh_serial_write, |
350 | 9a9d0b81 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
351 | 2f062c72 | ths | }; |
352 | 2f062c72 | ths | |
353 | 9a9d0b81 | Benoît Canet | void sh_serial_init(MemoryRegion *sysmem,
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354 | 9a9d0b81 | Benoît Canet | target_phys_addr_t base, int feat,
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355 | 9a9d0b81 | Benoît Canet | uint32_t freq, CharDriverState *chr, |
356 | 9a9d0b81 | Benoît Canet | qemu_irq eri_source, |
357 | 9a9d0b81 | Benoît Canet | qemu_irq rxi_source, |
358 | 9a9d0b81 | Benoît Canet | qemu_irq txi_source, |
359 | 9a9d0b81 | Benoît Canet | qemu_irq tei_source, |
360 | 9a9d0b81 | Benoît Canet | qemu_irq bri_source) |
361 | 2f062c72 | ths | { |
362 | 2f062c72 | ths | sh_serial_state *s; |
363 | 2f062c72 | ths | |
364 | 7267c094 | Anthony Liguori | s = g_malloc0(sizeof(sh_serial_state));
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365 | 2f062c72 | ths | |
366 | 2f062c72 | ths | s->feat = feat; |
367 | 2f062c72 | ths | s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE; |
368 | 63242a00 | aurel32 | s->rtrg = 1;
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369 | 2f062c72 | ths | |
370 | 2f062c72 | ths | s->smr = 0;
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371 | 2f062c72 | ths | s->brr = 0xff;
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372 | b7d35e65 | balrog | s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */ |
373 | 2f062c72 | ths | s->sptr = 0;
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374 | 2f062c72 | ths | |
375 | 2f062c72 | ths | if (feat & SH_SERIAL_FEAT_SCIF) {
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376 | 2f062c72 | ths | s->fcr = 0;
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377 | 2f062c72 | ths | } |
378 | 2f062c72 | ths | else {
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379 | 2f062c72 | ths | s->dr = 0xff;
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380 | 2f062c72 | ths | } |
381 | 2f062c72 | ths | |
382 | 63242a00 | aurel32 | sh_serial_clear_fifo(s); |
383 | 2f062c72 | ths | |
384 | 9a9d0b81 | Benoît Canet | memory_region_init_io(&s->iomem, &sh_serial_ops, s, |
385 | 9a9d0b81 | Benoît Canet | "serial", 0x100000000ULL); |
386 | 9a9d0b81 | Benoît Canet | |
387 | 9a9d0b81 | Benoît Canet | memory_region_init_alias(&s->iomem_p4, "serial-p4", &s->iomem,
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388 | 9a9d0b81 | Benoît Canet | 0, 0x28); |
389 | 9a9d0b81 | Benoît Canet | memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); |
390 | 9a9d0b81 | Benoît Canet | |
391 | 9a9d0b81 | Benoît Canet | memory_region_init_alias(&s->iomem_a7, "serial-a7", &s->iomem,
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392 | 9a9d0b81 | Benoît Canet | 0, 0x28); |
393 | 9a9d0b81 | Benoît Canet | memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); |
394 | 2f062c72 | ths | |
395 | 2f062c72 | ths | s->chr = chr; |
396 | 2f062c72 | ths | |
397 | 2f062c72 | ths | if (chr)
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398 | 2f062c72 | ths | qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1, |
399 | 2f062c72 | ths | sh_serial_event, s); |
400 | bf5b7423 | aurel32 | |
401 | bf5b7423 | aurel32 | s->eri = eri_source; |
402 | bf5b7423 | aurel32 | s->rxi = rxi_source; |
403 | bf5b7423 | aurel32 | s->txi = txi_source; |
404 | bf5b7423 | aurel32 | s->tei = tei_source; |
405 | bf5b7423 | aurel32 | s->bri = bri_source; |
406 | 2f062c72 | ths | } |