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/*
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* QEMU PC System Emulator
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <stdarg.h> |
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#include <string.h> |
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#include <getopt.h> |
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#include <inttypes.h> |
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#include <unistd.h> |
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#include <sys/mman.h> |
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#include <fcntl.h> |
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#include <signal.h> |
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#include <time.h> |
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#include <sys/time.h> |
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#include <malloc.h> |
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#include <termios.h> |
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#include <sys/poll.h> |
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#include <errno.h> |
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#include <sys/wait.h> |
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#include <sys/ioctl.h> |
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#include <sys/socket.h> |
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#include <linux/if.h> |
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#include <linux/if_tun.h> |
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#include "cpu.h" |
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#include "disas.h" |
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#include "thunk.h" |
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#include "vl.h" |
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|
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#define DEFAULT_NETWORK_SCRIPT "/etc/qemu-ifup" |
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#define BIOS_FILENAME "bios.bin" |
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#define VGABIOS_FILENAME "vgabios.bin" |
56 |
|
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//#define DEBUG_UNUSED_IOPORT
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|
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//#define DEBUG_IRQ_LATENCY
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|
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/* output Bochs bios info messages */
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//#define DEBUG_BIOS
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|
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/* debug IDE devices */
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//#define DEBUG_IDE
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|
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/* debug PIC */
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//#define DEBUG_PIC
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|
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/* debug NE2000 card */
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//#define DEBUG_NE2000
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|
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/* debug PC keyboard */
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//#define DEBUG_KBD
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|
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/* debug PC keyboard : only mouse */
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//#define DEBUG_MOUSE
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|
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#define PHYS_RAM_BASE 0xac000000 |
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#define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024) |
81 |
|
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#define KERNEL_LOAD_ADDR 0x00100000 |
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#define INITRD_LOAD_ADDR 0x00400000 |
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#define KERNEL_PARAMS_ADDR 0x00090000 |
85 |
|
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#define GUI_REFRESH_INTERVAL 30 |
87 |
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#define MAX_DISKS 2 |
89 |
|
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/* from plex86 (BSD license) */
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struct __attribute__ ((packed)) linux_params {
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// For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
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// I just padded out the VESA parts, rather than define them.
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/* 0x000 */ uint8_t orig_x;
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/* 0x001 */ uint8_t orig_y;
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/* 0x002 */ uint16_t ext_mem_k;
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/* 0x004 */ uint16_t orig_video_page;
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/* 0x006 */ uint8_t orig_video_mode;
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/* 0x007 */ uint8_t orig_video_cols;
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/* 0x008 */ uint16_t unused1;
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/* 0x00a */ uint16_t orig_video_ega_bx;
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/* 0x00c */ uint16_t unused2;
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/* 0x00e */ uint8_t orig_video_lines;
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/* 0x00f */ uint8_t orig_video_isVGA;
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/* 0x010 */ uint16_t orig_video_points;
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/* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info. |
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/* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F) |
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/* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline |
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// is calculated as 0x90000 + cl_offset, bu
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// only if cl_magic == 0xA33F.
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/* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info. |
113 |
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/* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info |
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/* 0x054 */ uint8_t pad2[0x80 - 0x54]; |
116 |
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// Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
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// Might be truncated?
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/* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41 |
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/* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46 |
121 |
|
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// System description table truncated to 16 bytes
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// From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
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/* 0x0a0 */ uint16_t sys_description_len;
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/* 0x0a2 */ uint8_t sys_description_table[14]; |
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// [0] machine id
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// [1] machine submodel id
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// [2] BIOS revision
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// [3] bit1: MCA bus
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|
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/* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0]; |
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/* 0x1e0 */ uint32_t alt_mem_k;
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/* 0x1e4 */ uint8_t pad4[4]; |
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/* 0x1e8 */ uint8_t e820map_entries;
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/* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR |
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/* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea]; |
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/* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors |
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/* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0) |
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/* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the |
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// (b)zImage-file (in 16 byte units, rounded up)
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/* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK) |
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/* 0x1f8 */ uint16_t ramdisk_flags;
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/* 0x1fa */ uint16_t vga_mode; // (old one) |
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/* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor) |
145 |
/* 0x1fe */ uint8_t pad6[1]; |
146 |
/* 0x1ff */ uint8_t aux_device_info;
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/* 0x200 */ uint16_t jump_setup; // Jump to start of setup code, |
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// aka "reserved" field.
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/* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS" |
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/* 0x206 */ uint16_t header_format_version; // Version number of header format; |
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/* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with |
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// boot loaders, look there.
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/* 0x210 */ uint8_t loader_type;
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// 0 for old one.
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// else 0xTV:
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// T=0: LILO
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// T=1: Loadlin
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// T=2: bootsect-loader
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// T=3: SYSLINUX
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// T=4: ETHERBOOT
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// V=version
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/* 0x211 */ uint8_t loadflags;
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// bit0 = 1: kernel is loaded high (bzImage)
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// bit7 = 1: Heap and pointer (see below) set by boot
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// loader.
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/* 0x212 */ uint16_t setup_S_temp1;
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/* 0x214 */ uint32_t kernel_start;
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/* 0x218 */ uint32_t initrd_start;
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/* 0x21c */ uint32_t initrd_size;
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/* 0x220 */ uint8_t setup_S_temp2[4]; |
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/* 0x224 */ uint16_t setup_S_heap_end_pointer;
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/* 0x226 */ uint8_t pad7[0x2d0 - 0x226]; |
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/* 0x2d0 : Int 15, ax=e820 memory map. */
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// (linux/include/asm-i386/e820.h, 'struct e820entry')
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#define E820MAX 32 |
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#define E820_RAM 1 |
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#define E820_RESERVED 2 |
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#define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */ |
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#define E820_NVS 4 |
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struct {
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uint64_t addr; |
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uint64_t size; |
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uint32_t type; |
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} e820map[E820MAX]; |
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/* 0x550 */ uint8_t pad8[0x600 - 0x550]; |
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// BIOS Enhanced Disk Drive Services.
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// (From linux/include/asm-i386/edd.h, 'struct edd_info')
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// Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
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/* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600]; |
193 |
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/* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4]; |
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/* 0x800 */ uint8_t commandline[0x800]; |
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/* 0x1000 */
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uint64_t gdt_table[256];
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uint64_t idt_table[48];
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}; |
201 |
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#define KERNEL_CS 0x10 |
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#define KERNEL_DS 0x18 |
204 |
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#define MAX_IOPORTS 4096 |
206 |
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static const char *bios_dir = CONFIG_QEMU_SHAREDIR; |
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char phys_ram_file[1024]; |
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CPUX86State *global_env; |
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CPUX86State *cpu_single_env; |
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IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
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IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
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BlockDriverState *bs_table[MAX_DISKS]; |
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int vga_ram_size;
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static DisplayState display_state;
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int nographic;
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int term_inited;
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int64_t ticks_per_sec; |
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/***********************************************************/
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/* x86 io ports */
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uint32_t default_ioport_readb(CPUX86State *env, uint32_t address) |
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{ |
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#ifdef DEBUG_UNUSED_IOPORT
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fprintf(stderr, "inb: port=0x%04x\n", address);
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#endif
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return 0xff; |
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} |
230 |
|
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void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
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{ |
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#ifdef DEBUG_UNUSED_IOPORT
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fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
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#endif
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} |
237 |
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/* default is to make two byte accesses */
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uint32_t default_ioport_readw(CPUX86State *env, uint32_t address) |
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{ |
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uint32_t data; |
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data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address); |
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data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8; |
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return data;
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} |
246 |
|
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void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
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{ |
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ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff); |
250 |
ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff); |
251 |
} |
252 |
|
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uint32_t default_ioport_readl(CPUX86State *env, uint32_t address) |
254 |
{ |
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#ifdef DEBUG_UNUSED_IOPORT
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fprintf(stderr, "inl: port=0x%04x\n", address);
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#endif
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return 0xffffffff; |
259 |
} |
260 |
|
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void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
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{ |
263 |
#ifdef DEBUG_UNUSED_IOPORT
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fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
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#endif
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} |
267 |
|
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void init_ioports(void) |
269 |
{ |
270 |
int i;
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271 |
|
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for(i = 0; i < MAX_IOPORTS; i++) { |
273 |
ioport_read_table[0][i] = default_ioport_readb;
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ioport_write_table[0][i] = default_ioport_writeb;
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ioport_read_table[1][i] = default_ioport_readw;
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ioport_write_table[1][i] = default_ioport_writew;
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ioport_read_table[2][i] = default_ioport_readl;
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ioport_write_table[2][i] = default_ioport_writel;
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} |
280 |
} |
281 |
|
282 |
/* size is the word size in byte */
|
283 |
int register_ioport_read(int start, int length, IOPortReadFunc *func, int size) |
284 |
{ |
285 |
int i, bsize;
|
286 |
|
287 |
if (size == 1) |
288 |
bsize = 0;
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289 |
else if (size == 2) |
290 |
bsize = 1;
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291 |
else if (size == 4) |
292 |
bsize = 2;
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293 |
else
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294 |
return -1; |
295 |
for(i = start; i < start + length; i += size)
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296 |
ioport_read_table[bsize][i] = func; |
297 |
return 0; |
298 |
} |
299 |
|
300 |
/* size is the word size in byte */
|
301 |
int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size) |
302 |
{ |
303 |
int i, bsize;
|
304 |
|
305 |
if (size == 1) |
306 |
bsize = 0;
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307 |
else if (size == 2) |
308 |
bsize = 1;
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309 |
else if (size == 4) |
310 |
bsize = 2;
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311 |
else
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312 |
return -1; |
313 |
for(i = start; i < start + length; i += size)
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314 |
ioport_write_table[bsize][i] = func; |
315 |
return 0; |
316 |
} |
317 |
|
318 |
void pstrcpy(char *buf, int buf_size, const char *str) |
319 |
{ |
320 |
int c;
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321 |
char *q = buf;
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322 |
|
323 |
if (buf_size <= 0) |
324 |
return;
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325 |
|
326 |
for(;;) {
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327 |
c = *str++; |
328 |
if (c == 0 || q >= buf + buf_size - 1) |
329 |
break;
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330 |
*q++ = c; |
331 |
} |
332 |
*q = '\0';
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333 |
} |
334 |
|
335 |
/* strcat and truncate. */
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336 |
char *pstrcat(char *buf, int buf_size, const char *s) |
337 |
{ |
338 |
int len;
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339 |
len = strlen(buf); |
340 |
if (len < buf_size)
|
341 |
pstrcpy(buf + len, buf_size - len, s); |
342 |
return buf;
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343 |
} |
344 |
|
345 |
int load_kernel(const char *filename, uint8_t *addr) |
346 |
{ |
347 |
int fd, size, setup_sects;
|
348 |
uint8_t bootsect[512];
|
349 |
|
350 |
fd = open(filename, O_RDONLY); |
351 |
if (fd < 0) |
352 |
return -1; |
353 |
if (read(fd, bootsect, 512) != 512) |
354 |
goto fail;
|
355 |
setup_sects = bootsect[0x1F1];
|
356 |
if (!setup_sects)
|
357 |
setup_sects = 4;
|
358 |
/* skip 16 bit setup code */
|
359 |
lseek(fd, (setup_sects + 1) * 512, SEEK_SET); |
360 |
size = read(fd, addr, 16 * 1024 * 1024); |
361 |
if (size < 0) |
362 |
goto fail;
|
363 |
close(fd); |
364 |
return size;
|
365 |
fail:
|
366 |
close(fd); |
367 |
return -1; |
368 |
} |
369 |
|
370 |
/* return the size or -1 if error */
|
371 |
int load_image(const char *filename, uint8_t *addr) |
372 |
{ |
373 |
int fd, size;
|
374 |
fd = open(filename, O_RDONLY); |
375 |
if (fd < 0) |
376 |
return -1; |
377 |
size = lseek(fd, 0, SEEK_END);
|
378 |
lseek(fd, 0, SEEK_SET);
|
379 |
if (read(fd, addr, size) != size) {
|
380 |
close(fd); |
381 |
return -1; |
382 |
} |
383 |
close(fd); |
384 |
return size;
|
385 |
} |
386 |
|
387 |
void cpu_x86_outb(CPUX86State *env, int addr, int val) |
388 |
{ |
389 |
ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val); |
390 |
} |
391 |
|
392 |
void cpu_x86_outw(CPUX86State *env, int addr, int val) |
393 |
{ |
394 |
ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val); |
395 |
} |
396 |
|
397 |
void cpu_x86_outl(CPUX86State *env, int addr, int val) |
398 |
{ |
399 |
ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val); |
400 |
} |
401 |
|
402 |
int cpu_x86_inb(CPUX86State *env, int addr) |
403 |
{ |
404 |
return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr); |
405 |
} |
406 |
|
407 |
int cpu_x86_inw(CPUX86State *env, int addr) |
408 |
{ |
409 |
return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr); |
410 |
} |
411 |
|
412 |
int cpu_x86_inl(CPUX86State *env, int addr) |
413 |
{ |
414 |
return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr); |
415 |
} |
416 |
|
417 |
/***********************************************************/
|
418 |
void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
|
419 |
{ |
420 |
} |
421 |
|
422 |
void hw_error(const char *fmt, ...) |
423 |
{ |
424 |
va_list ap; |
425 |
|
426 |
va_start(ap, fmt); |
427 |
fprintf(stderr, "qemu: hardware error: ");
|
428 |
vfprintf(stderr, fmt, ap); |
429 |
fprintf(stderr, "\n");
|
430 |
#ifdef TARGET_I386
|
431 |
cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP); |
432 |
#endif
|
433 |
va_end(ap); |
434 |
abort(); |
435 |
} |
436 |
|
437 |
/***********************************************************/
|
438 |
/* cmos emulation */
|
439 |
|
440 |
#define RTC_SECONDS 0 |
441 |
#define RTC_SECONDS_ALARM 1 |
442 |
#define RTC_MINUTES 2 |
443 |
#define RTC_MINUTES_ALARM 3 |
444 |
#define RTC_HOURS 4 |
445 |
#define RTC_HOURS_ALARM 5 |
446 |
#define RTC_ALARM_DONT_CARE 0xC0 |
447 |
|
448 |
#define RTC_DAY_OF_WEEK 6 |
449 |
#define RTC_DAY_OF_MONTH 7 |
450 |
#define RTC_MONTH 8 |
451 |
#define RTC_YEAR 9 |
452 |
|
453 |
#define RTC_REG_A 10 |
454 |
#define RTC_REG_B 11 |
455 |
#define RTC_REG_C 12 |
456 |
#define RTC_REG_D 13 |
457 |
|
458 |
/* PC cmos mappings */
|
459 |
#define REG_EQUIPMENT_BYTE 0x14 |
460 |
|
461 |
uint8_t cmos_data[128];
|
462 |
uint8_t cmos_index; |
463 |
|
464 |
void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
|
465 |
{ |
466 |
if (addr == 0x70) { |
467 |
cmos_index = data & 0x7f;
|
468 |
} |
469 |
} |
470 |
|
471 |
uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr) |
472 |
{ |
473 |
int ret;
|
474 |
|
475 |
if (addr == 0x70) { |
476 |
return 0xff; |
477 |
} else {
|
478 |
/* toggle update-in-progress bit for Linux (same hack as
|
479 |
plex86) */
|
480 |
ret = cmos_data[cmos_index]; |
481 |
if (cmos_index == RTC_REG_A)
|
482 |
cmos_data[RTC_REG_A] ^= 0x80;
|
483 |
else if (cmos_index == RTC_REG_C) |
484 |
cmos_data[RTC_REG_C] = 0x00;
|
485 |
return ret;
|
486 |
} |
487 |
} |
488 |
|
489 |
|
490 |
static inline int to_bcd(int a) |
491 |
{ |
492 |
return ((a / 10) << 4) | (a % 10); |
493 |
} |
494 |
|
495 |
void cmos_init(void) |
496 |
{ |
497 |
struct tm *tm;
|
498 |
time_t ti; |
499 |
int val;
|
500 |
|
501 |
ti = time(NULL);
|
502 |
tm = gmtime(&ti); |
503 |
cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec); |
504 |
cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min); |
505 |
cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour); |
506 |
cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday); |
507 |
cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday); |
508 |
cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
|
509 |
cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
|
510 |
|
511 |
cmos_data[RTC_REG_A] = 0x26;
|
512 |
cmos_data[RTC_REG_B] = 0x02;
|
513 |
cmos_data[RTC_REG_C] = 0x00;
|
514 |
cmos_data[RTC_REG_D] = 0x80;
|
515 |
|
516 |
/* various important CMOS locations needed by PC/Bochs bios */
|
517 |
|
518 |
cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */ |
519 |
cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */ |
520 |
|
521 |
/* memory size */
|
522 |
val = (phys_ram_size / 1024) - 1024; |
523 |
if (val > 65535) |
524 |
val = 65535;
|
525 |
cmos_data[0x17] = val;
|
526 |
cmos_data[0x18] = val >> 8; |
527 |
cmos_data[0x30] = val;
|
528 |
cmos_data[0x31] = val >> 8; |
529 |
|
530 |
val = (phys_ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
531 |
if (val > 65535) |
532 |
val = 65535;
|
533 |
cmos_data[0x34] = val;
|
534 |
cmos_data[0x35] = val >> 8; |
535 |
|
536 |
cmos_data[0x3d] = 0x02; /* hard drive boot */ |
537 |
|
538 |
register_ioport_write(0x70, 2, cmos_ioport_write, 1); |
539 |
register_ioport_read(0x70, 2, cmos_ioport_read, 1); |
540 |
} |
541 |
|
542 |
/***********************************************************/
|
543 |
/* 8259 pic emulation */
|
544 |
|
545 |
typedef struct PicState { |
546 |
uint8_t last_irr; /* edge detection */
|
547 |
uint8_t irr; /* interrupt request register */
|
548 |
uint8_t imr; /* interrupt mask register */
|
549 |
uint8_t isr; /* interrupt service register */
|
550 |
uint8_t priority_add; /* used to compute irq priority */
|
551 |
uint8_t irq_base; |
552 |
uint8_t read_reg_select; |
553 |
uint8_t special_mask; |
554 |
uint8_t init_state; |
555 |
uint8_t auto_eoi; |
556 |
uint8_t rotate_on_autoeoi; |
557 |
uint8_t init4; /* true if 4 byte init */
|
558 |
} PicState; |
559 |
|
560 |
/* 0 is master pic, 1 is slave pic */
|
561 |
PicState pics[2];
|
562 |
int pic_irq_requested;
|
563 |
|
564 |
/* set irq level. If an edge is detected, then the IRR is set to 1 */
|
565 |
static inline void pic_set_irq1(PicState *s, int irq, int level) |
566 |
{ |
567 |
int mask;
|
568 |
mask = 1 << irq;
|
569 |
if (level) {
|
570 |
if ((s->last_irr & mask) == 0) |
571 |
s->irr |= mask; |
572 |
s->last_irr |= mask; |
573 |
} else {
|
574 |
s->last_irr &= ~mask; |
575 |
} |
576 |
} |
577 |
|
578 |
static inline int get_priority(PicState *s, int mask) |
579 |
{ |
580 |
int priority;
|
581 |
if (mask == 0) |
582 |
return -1; |
583 |
priority = 7;
|
584 |
while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) |
585 |
priority--; |
586 |
return priority;
|
587 |
} |
588 |
|
589 |
/* return the pic wanted interrupt. return -1 if none */
|
590 |
static int pic_get_irq(PicState *s) |
591 |
{ |
592 |
int mask, cur_priority, priority;
|
593 |
|
594 |
mask = s->irr & ~s->imr; |
595 |
priority = get_priority(s, mask); |
596 |
if (priority < 0) |
597 |
return -1; |
598 |
/* compute current priority */
|
599 |
cur_priority = get_priority(s, s->isr); |
600 |
if (priority > cur_priority) {
|
601 |
/* higher priority found: an irq should be generated */
|
602 |
return priority;
|
603 |
} else {
|
604 |
return -1; |
605 |
} |
606 |
} |
607 |
|
608 |
/* raise irq to CPU if necessary. must be called every time the active
|
609 |
irq may change */
|
610 |
static void pic_update_irq(void) |
611 |
{ |
612 |
int irq2, irq;
|
613 |
|
614 |
/* first look at slave pic */
|
615 |
irq2 = pic_get_irq(&pics[1]);
|
616 |
if (irq2 >= 0) { |
617 |
/* if irq request by slave pic, signal master PIC */
|
618 |
pic_set_irq1(&pics[0], 2, 1); |
619 |
pic_set_irq1(&pics[0], 2, 0); |
620 |
} |
621 |
/* look at requested irq */
|
622 |
irq = pic_get_irq(&pics[0]);
|
623 |
if (irq >= 0) { |
624 |
if (irq == 2) { |
625 |
/* from slave pic */
|
626 |
pic_irq_requested = 8 + irq2;
|
627 |
} else {
|
628 |
/* from master pic */
|
629 |
pic_irq_requested = irq; |
630 |
} |
631 |
cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD); |
632 |
} |
633 |
} |
634 |
|
635 |
#ifdef DEBUG_IRQ_LATENCY
|
636 |
int64_t irq_time[16];
|
637 |
int64_t cpu_get_ticks(void);
|
638 |
#endif
|
639 |
#if defined(DEBUG_PIC)
|
640 |
int irq_level[16]; |
641 |
#endif
|
642 |
|
643 |
void pic_set_irq(int irq, int level) |
644 |
{ |
645 |
#if defined(DEBUG_PIC)
|
646 |
if (level != irq_level[irq]) {
|
647 |
printf("pic_set_irq: irq=%d level=%d\n", irq, level);
|
648 |
irq_level[irq] = level; |
649 |
} |
650 |
#endif
|
651 |
#ifdef DEBUG_IRQ_LATENCY
|
652 |
if (level) {
|
653 |
irq_time[irq] = cpu_get_ticks(); |
654 |
} |
655 |
#endif
|
656 |
pic_set_irq1(&pics[irq >> 3], irq & 7, level); |
657 |
pic_update_irq(); |
658 |
} |
659 |
|
660 |
int cpu_x86_get_pic_interrupt(CPUX86State *env)
|
661 |
{ |
662 |
int irq, irq2, intno;
|
663 |
|
664 |
/* signal the pic that the irq was acked by the CPU */
|
665 |
irq = pic_irq_requested; |
666 |
#ifdef DEBUG_IRQ_LATENCY
|
667 |
printf("IRQ%d latency=%0.3fus\n",
|
668 |
irq, |
669 |
(double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec); |
670 |
#endif
|
671 |
#ifdef DEBUG_PIC
|
672 |
printf("pic_interrupt: irq=%d\n", irq);
|
673 |
#endif
|
674 |
|
675 |
if (irq >= 8) { |
676 |
irq2 = irq & 7;
|
677 |
pics[1].isr |= (1 << irq2); |
678 |
pics[1].irr &= ~(1 << irq2); |
679 |
irq = 2;
|
680 |
intno = pics[1].irq_base + irq2;
|
681 |
} else {
|
682 |
intno = pics[0].irq_base + irq;
|
683 |
} |
684 |
pics[0].isr |= (1 << irq); |
685 |
pics[0].irr &= ~(1 << irq); |
686 |
return intno;
|
687 |
} |
688 |
|
689 |
void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
690 |
{ |
691 |
PicState *s; |
692 |
int priority;
|
693 |
|
694 |
#ifdef DEBUG_PIC
|
695 |
printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
|
696 |
#endif
|
697 |
s = &pics[addr >> 7];
|
698 |
addr &= 1;
|
699 |
if (addr == 0) { |
700 |
if (val & 0x10) { |
701 |
/* init */
|
702 |
memset(s, 0, sizeof(PicState)); |
703 |
s->init_state = 1;
|
704 |
s->init4 = val & 1;
|
705 |
if (val & 0x02) |
706 |
hw_error("single mode not supported");
|
707 |
if (val & 0x08) |
708 |
hw_error("level sensitive irq not supported");
|
709 |
} else if (val & 0x08) { |
710 |
if (val & 0x02) |
711 |
s->read_reg_select = val & 1;
|
712 |
if (val & 0x40) |
713 |
s->special_mask = (val >> 5) & 1; |
714 |
} else {
|
715 |
switch(val) {
|
716 |
case 0x00: |
717 |
case 0x80: |
718 |
s->rotate_on_autoeoi = val >> 7;
|
719 |
break;
|
720 |
case 0x20: /* end of interrupt */ |
721 |
case 0xa0: |
722 |
priority = get_priority(s, s->isr); |
723 |
if (priority >= 0) { |
724 |
s->isr &= ~(1 << ((priority + s->priority_add) & 7)); |
725 |
} |
726 |
if (val == 0xa0) |
727 |
s->priority_add = (s->priority_add + 1) & 7; |
728 |
pic_update_irq(); |
729 |
break;
|
730 |
case 0x60 ... 0x67: |
731 |
priority = val & 7;
|
732 |
s->isr &= ~(1 << priority);
|
733 |
pic_update_irq(); |
734 |
break;
|
735 |
case 0xc0 ... 0xc7: |
736 |
s->priority_add = (val + 1) & 7; |
737 |
pic_update_irq(); |
738 |
break;
|
739 |
case 0xe0 ... 0xe7: |
740 |
priority = val & 7;
|
741 |
s->isr &= ~(1 << priority);
|
742 |
s->priority_add = (priority + 1) & 7; |
743 |
pic_update_irq(); |
744 |
break;
|
745 |
} |
746 |
} |
747 |
} else {
|
748 |
switch(s->init_state) {
|
749 |
case 0: |
750 |
/* normal mode */
|
751 |
s->imr = val; |
752 |
pic_update_irq(); |
753 |
break;
|
754 |
case 1: |
755 |
s->irq_base = val & 0xf8;
|
756 |
s->init_state = 2;
|
757 |
break;
|
758 |
case 2: |
759 |
if (s->init4) {
|
760 |
s->init_state = 3;
|
761 |
} else {
|
762 |
s->init_state = 0;
|
763 |
} |
764 |
break;
|
765 |
case 3: |
766 |
s->auto_eoi = (val >> 1) & 1; |
767 |
s->init_state = 0;
|
768 |
break;
|
769 |
} |
770 |
} |
771 |
} |
772 |
|
773 |
uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr1) |
774 |
{ |
775 |
PicState *s; |
776 |
unsigned int addr; |
777 |
int ret;
|
778 |
|
779 |
addr = addr1; |
780 |
s = &pics[addr >> 7];
|
781 |
addr &= 1;
|
782 |
if (addr == 0) { |
783 |
if (s->read_reg_select)
|
784 |
ret = s->isr; |
785 |
else
|
786 |
ret = s->irr; |
787 |
} else {
|
788 |
ret = s->imr; |
789 |
} |
790 |
#ifdef DEBUG_PIC
|
791 |
printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
|
792 |
#endif
|
793 |
return ret;
|
794 |
} |
795 |
|
796 |
void pic_init(void) |
797 |
{ |
798 |
register_ioport_write(0x20, 2, pic_ioport_write, 1); |
799 |
register_ioport_read(0x20, 2, pic_ioport_read, 1); |
800 |
register_ioport_write(0xa0, 2, pic_ioport_write, 1); |
801 |
register_ioport_read(0xa0, 2, pic_ioport_read, 1); |
802 |
} |
803 |
|
804 |
/***********************************************************/
|
805 |
/* 8253 PIT emulation */
|
806 |
|
807 |
#define PIT_FREQ 1193182 |
808 |
|
809 |
#define RW_STATE_LSB 0 |
810 |
#define RW_STATE_MSB 1 |
811 |
#define RW_STATE_WORD0 2 |
812 |
#define RW_STATE_WORD1 3 |
813 |
#define RW_STATE_LATCHED_WORD0 4 |
814 |
#define RW_STATE_LATCHED_WORD1 5 |
815 |
|
816 |
typedef struct PITChannelState { |
817 |
int count; /* can be 65536 */ |
818 |
uint16_t latched_count; |
819 |
uint8_t rw_state; |
820 |
uint8_t mode; |
821 |
uint8_t bcd; /* not supported */
|
822 |
uint8_t gate; /* timer start */
|
823 |
int64_t count_load_time; |
824 |
int64_t count_last_edge_check_time; |
825 |
} PITChannelState; |
826 |
|
827 |
PITChannelState pit_channels[3];
|
828 |
int speaker_data_on;
|
829 |
int dummy_refresh_clock;
|
830 |
int pit_min_timer_count = 0; |
831 |
|
832 |
|
833 |
#if defined(__powerpc__)
|
834 |
|
835 |
static inline uint32_t get_tbl(void) |
836 |
{ |
837 |
uint32_t tbl; |
838 |
asm volatile("mftb %0" : "=r" (tbl)); |
839 |
return tbl;
|
840 |
} |
841 |
|
842 |
static inline uint32_t get_tbu(void) |
843 |
{ |
844 |
uint32_t tbl; |
845 |
asm volatile("mftbu %0" : "=r" (tbl)); |
846 |
return tbl;
|
847 |
} |
848 |
|
849 |
int64_t cpu_get_real_ticks(void)
|
850 |
{ |
851 |
uint32_t l, h, h1; |
852 |
/* NOTE: we test if wrapping has occurred */
|
853 |
do {
|
854 |
h = get_tbu(); |
855 |
l = get_tbl(); |
856 |
h1 = get_tbu(); |
857 |
} while (h != h1);
|
858 |
return ((int64_t)h << 32) | l; |
859 |
} |
860 |
|
861 |
#elif defined(__i386__)
|
862 |
|
863 |
int64_t cpu_get_real_ticks(void)
|
864 |
{ |
865 |
int64_t val; |
866 |
asm("rdtsc" : "=A" (val)); |
867 |
return val;
|
868 |
} |
869 |
|
870 |
#else
|
871 |
#error unsupported CPU
|
872 |
#endif
|
873 |
|
874 |
static int64_t cpu_ticks_offset;
|
875 |
static int64_t cpu_ticks_last;
|
876 |
|
877 |
int64_t cpu_get_ticks(void)
|
878 |
{ |
879 |
return cpu_get_real_ticks() + cpu_ticks_offset;
|
880 |
} |
881 |
|
882 |
/* enable cpu_get_ticks() */
|
883 |
void cpu_enable_ticks(void) |
884 |
{ |
885 |
cpu_ticks_offset = cpu_ticks_last - cpu_get_real_ticks(); |
886 |
} |
887 |
|
888 |
/* disable cpu_get_ticks() : the clock is stopped. You must not call
|
889 |
cpu_get_ticks() after that. */
|
890 |
void cpu_disable_ticks(void) |
891 |
{ |
892 |
cpu_ticks_last = cpu_get_ticks(); |
893 |
} |
894 |
|
895 |
int64_t get_clock(void)
|
896 |
{ |
897 |
struct timeval tv;
|
898 |
gettimeofday(&tv, NULL);
|
899 |
return tv.tv_sec * 1000000LL + tv.tv_usec; |
900 |
} |
901 |
|
902 |
void cpu_calibrate_ticks(void) |
903 |
{ |
904 |
int64_t usec, ticks; |
905 |
|
906 |
usec = get_clock(); |
907 |
ticks = cpu_get_ticks(); |
908 |
usleep(50 * 1000); |
909 |
usec = get_clock() - usec; |
910 |
ticks = cpu_get_ticks() - ticks; |
911 |
ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec; |
912 |
} |
913 |
|
914 |
/* compute with 96 bit intermediate result: (a*b)/c */
|
915 |
static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
|
916 |
{ |
917 |
union {
|
918 |
uint64_t ll; |
919 |
struct {
|
920 |
#ifdef WORDS_BIGENDIAN
|
921 |
uint32_t high, low; |
922 |
#else
|
923 |
uint32_t low, high; |
924 |
#endif
|
925 |
} l; |
926 |
} u, res; |
927 |
uint64_t rl, rh; |
928 |
|
929 |
u.ll = a; |
930 |
rl = (uint64_t)u.l.low * (uint64_t)b; |
931 |
rh = (uint64_t)u.l.high * (uint64_t)b; |
932 |
rh += (rl >> 32);
|
933 |
res.l.high = rh / c; |
934 |
res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; |
935 |
return res.ll;
|
936 |
} |
937 |
|
938 |
static int pit_get_count(PITChannelState *s) |
939 |
{ |
940 |
uint64_t d; |
941 |
int counter;
|
942 |
|
943 |
d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
944 |
switch(s->mode) {
|
945 |
case 0: |
946 |
case 1: |
947 |
case 4: |
948 |
case 5: |
949 |
counter = (s->count - d) & 0xffff;
|
950 |
break;
|
951 |
default:
|
952 |
counter = s->count - (d % s->count); |
953 |
break;
|
954 |
} |
955 |
return counter;
|
956 |
} |
957 |
|
958 |
/* get pit output bit */
|
959 |
static int pit_get_out(PITChannelState *s) |
960 |
{ |
961 |
uint64_t d; |
962 |
int out;
|
963 |
|
964 |
d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
965 |
switch(s->mode) {
|
966 |
default:
|
967 |
case 0: |
968 |
out = (d >= s->count); |
969 |
break;
|
970 |
case 1: |
971 |
out = (d < s->count); |
972 |
break;
|
973 |
case 2: |
974 |
if ((d % s->count) == 0 && d != 0) |
975 |
out = 1;
|
976 |
else
|
977 |
out = 0;
|
978 |
break;
|
979 |
case 3: |
980 |
out = (d % s->count) < (s->count >> 1);
|
981 |
break;
|
982 |
case 4: |
983 |
case 5: |
984 |
out = (d == s->count); |
985 |
break;
|
986 |
} |
987 |
return out;
|
988 |
} |
989 |
|
990 |
/* get the number of 0 to 1 transitions we had since we call this
|
991 |
function */
|
992 |
/* XXX: maybe better to use ticks precision to avoid getting edges
|
993 |
twice if checks are done at very small intervals */
|
994 |
static int pit_get_out_edges(PITChannelState *s) |
995 |
{ |
996 |
uint64_t d1, d2; |
997 |
int64_t ticks; |
998 |
int ret, v;
|
999 |
|
1000 |
ticks = cpu_get_ticks(); |
1001 |
d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time, |
1002 |
PIT_FREQ, ticks_per_sec); |
1003 |
d2 = muldiv64(ticks - s->count_load_time, |
1004 |
PIT_FREQ, ticks_per_sec); |
1005 |
s->count_last_edge_check_time = ticks; |
1006 |
switch(s->mode) {
|
1007 |
default:
|
1008 |
case 0: |
1009 |
if (d1 < s->count && d2 >= s->count)
|
1010 |
ret = 1;
|
1011 |
else
|
1012 |
ret = 0;
|
1013 |
break;
|
1014 |
case 1: |
1015 |
ret = 0;
|
1016 |
break;
|
1017 |
case 2: |
1018 |
d1 /= s->count; |
1019 |
d2 /= s->count; |
1020 |
ret = d2 - d1; |
1021 |
break;
|
1022 |
case 3: |
1023 |
v = s->count - (s->count >> 1);
|
1024 |
d1 = (d1 + v) / s->count; |
1025 |
d2 = (d2 + v) / s->count; |
1026 |
ret = d2 - d1; |
1027 |
break;
|
1028 |
case 4: |
1029 |
case 5: |
1030 |
if (d1 < s->count && d2 >= s->count)
|
1031 |
ret = 1;
|
1032 |
else
|
1033 |
ret = 0;
|
1034 |
break;
|
1035 |
} |
1036 |
return ret;
|
1037 |
} |
1038 |
|
1039 |
static inline void pit_load_count(PITChannelState *s, int val) |
1040 |
{ |
1041 |
if (val == 0) |
1042 |
val = 0x10000;
|
1043 |
s->count_load_time = cpu_get_ticks(); |
1044 |
s->count_last_edge_check_time = s->count_load_time; |
1045 |
s->count = val; |
1046 |
if (s == &pit_channels[0] && val <= pit_min_timer_count) { |
1047 |
fprintf(stderr, |
1048 |
"\nWARNING: vl: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
|
1049 |
PIT_FREQ / pit_min_timer_count); |
1050 |
} |
1051 |
} |
1052 |
|
1053 |
void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1054 |
{ |
1055 |
int channel, access;
|
1056 |
PITChannelState *s; |
1057 |
|
1058 |
addr &= 3;
|
1059 |
if (addr == 3) { |
1060 |
channel = val >> 6;
|
1061 |
if (channel == 3) |
1062 |
return;
|
1063 |
s = &pit_channels[channel]; |
1064 |
access = (val >> 4) & 3; |
1065 |
switch(access) {
|
1066 |
case 0: |
1067 |
s->latched_count = pit_get_count(s); |
1068 |
s->rw_state = RW_STATE_LATCHED_WORD0; |
1069 |
break;
|
1070 |
default:
|
1071 |
s->mode = (val >> 1) & 7; |
1072 |
s->bcd = val & 1;
|
1073 |
s->rw_state = access - 1 + RW_STATE_LSB;
|
1074 |
break;
|
1075 |
} |
1076 |
} else {
|
1077 |
s = &pit_channels[addr]; |
1078 |
switch(s->rw_state) {
|
1079 |
case RW_STATE_LSB:
|
1080 |
pit_load_count(s, val); |
1081 |
break;
|
1082 |
case RW_STATE_MSB:
|
1083 |
pit_load_count(s, val << 8);
|
1084 |
break;
|
1085 |
case RW_STATE_WORD0:
|
1086 |
case RW_STATE_WORD1:
|
1087 |
if (s->rw_state & 1) { |
1088 |
pit_load_count(s, (s->latched_count & 0xff) | (val << 8)); |
1089 |
} else {
|
1090 |
s->latched_count = val; |
1091 |
} |
1092 |
s->rw_state ^= 1;
|
1093 |
break;
|
1094 |
} |
1095 |
} |
1096 |
} |
1097 |
|
1098 |
uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr) |
1099 |
{ |
1100 |
int ret, count;
|
1101 |
PITChannelState *s; |
1102 |
|
1103 |
addr &= 3;
|
1104 |
s = &pit_channels[addr]; |
1105 |
switch(s->rw_state) {
|
1106 |
case RW_STATE_LSB:
|
1107 |
case RW_STATE_MSB:
|
1108 |
case RW_STATE_WORD0:
|
1109 |
case RW_STATE_WORD1:
|
1110 |
count = pit_get_count(s); |
1111 |
if (s->rw_state & 1) |
1112 |
ret = (count >> 8) & 0xff; |
1113 |
else
|
1114 |
ret = count & 0xff;
|
1115 |
if (s->rw_state & 2) |
1116 |
s->rw_state ^= 1;
|
1117 |
break;
|
1118 |
default:
|
1119 |
case RW_STATE_LATCHED_WORD0:
|
1120 |
case RW_STATE_LATCHED_WORD1:
|
1121 |
if (s->rw_state & 1) |
1122 |
ret = s->latched_count >> 8;
|
1123 |
else
|
1124 |
ret = s->latched_count & 0xff;
|
1125 |
s->rw_state ^= 1;
|
1126 |
break;
|
1127 |
} |
1128 |
return ret;
|
1129 |
} |
1130 |
|
1131 |
void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1132 |
{ |
1133 |
speaker_data_on = (val >> 1) & 1; |
1134 |
pit_channels[2].gate = val & 1; |
1135 |
} |
1136 |
|
1137 |
uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr) |
1138 |
{ |
1139 |
int out;
|
1140 |
out = pit_get_out(&pit_channels[2]);
|
1141 |
dummy_refresh_clock ^= 1;
|
1142 |
return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) | |
1143 |
(dummy_refresh_clock << 4);
|
1144 |
} |
1145 |
|
1146 |
void pit_init(void) |
1147 |
{ |
1148 |
PITChannelState *s; |
1149 |
int i;
|
1150 |
|
1151 |
cpu_calibrate_ticks(); |
1152 |
|
1153 |
for(i = 0;i < 3; i++) { |
1154 |
s = &pit_channels[i]; |
1155 |
s->mode = 3;
|
1156 |
s->gate = (i != 2);
|
1157 |
pit_load_count(s, 0);
|
1158 |
} |
1159 |
|
1160 |
register_ioport_write(0x40, 4, pit_ioport_write, 1); |
1161 |
register_ioport_read(0x40, 3, pit_ioport_read, 1); |
1162 |
|
1163 |
register_ioport_read(0x61, 1, speaker_ioport_read, 1); |
1164 |
register_ioport_write(0x61, 1, speaker_ioport_write, 1); |
1165 |
} |
1166 |
|
1167 |
/***********************************************************/
|
1168 |
/* serial port emulation */
|
1169 |
|
1170 |
#define UART_IRQ 4 |
1171 |
|
1172 |
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
1173 |
|
1174 |
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
1175 |
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
1176 |
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
1177 |
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
1178 |
|
1179 |
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
1180 |
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
1181 |
|
1182 |
#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
1183 |
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
1184 |
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
1185 |
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
1186 |
|
1187 |
#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
1188 |
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
1189 |
#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
1190 |
#define UART_LSR_FE 0x08 /* Frame error indicator */ |
1191 |
#define UART_LSR_PE 0x04 /* Parity error indicator */ |
1192 |
#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
1193 |
#define UART_LSR_DR 0x01 /* Receiver data ready */ |
1194 |
|
1195 |
typedef struct SerialState { |
1196 |
uint8_t divider; |
1197 |
uint8_t rbr; /* receive register */
|
1198 |
uint8_t ier; |
1199 |
uint8_t iir; /* read only */
|
1200 |
uint8_t lcr; |
1201 |
uint8_t mcr; |
1202 |
uint8_t lsr; /* read only */
|
1203 |
uint8_t msr; |
1204 |
uint8_t scr; |
1205 |
} SerialState; |
1206 |
|
1207 |
SerialState serial_ports[1];
|
1208 |
|
1209 |
void serial_update_irq(void) |
1210 |
{ |
1211 |
SerialState *s = &serial_ports[0];
|
1212 |
|
1213 |
if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
|
1214 |
s->iir = UART_IIR_RDI; |
1215 |
} else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) { |
1216 |
s->iir = UART_IIR_THRI; |
1217 |
} else {
|
1218 |
s->iir = UART_IIR_NO_INT; |
1219 |
} |
1220 |
if (s->iir != UART_IIR_NO_INT) {
|
1221 |
pic_set_irq(UART_IRQ, 1);
|
1222 |
} else {
|
1223 |
pic_set_irq(UART_IRQ, 0);
|
1224 |
} |
1225 |
} |
1226 |
|
1227 |
void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1228 |
{ |
1229 |
SerialState *s = &serial_ports[0];
|
1230 |
unsigned char ch; |
1231 |
int ret;
|
1232 |
|
1233 |
addr &= 7;
|
1234 |
switch(addr) {
|
1235 |
default:
|
1236 |
case 0: |
1237 |
if (s->lcr & UART_LCR_DLAB) {
|
1238 |
s->divider = (s->divider & 0xff00) | val;
|
1239 |
} else {
|
1240 |
s->lsr &= ~UART_LSR_THRE; |
1241 |
serial_update_irq(); |
1242 |
|
1243 |
ch = val; |
1244 |
do {
|
1245 |
ret = write(1, &ch, 1); |
1246 |
} while (ret != 1); |
1247 |
s->lsr |= UART_LSR_THRE; |
1248 |
s->lsr |= UART_LSR_TEMT; |
1249 |
serial_update_irq(); |
1250 |
} |
1251 |
break;
|
1252 |
case 1: |
1253 |
if (s->lcr & UART_LCR_DLAB) {
|
1254 |
s->divider = (s->divider & 0x00ff) | (val << 8); |
1255 |
} else {
|
1256 |
s->ier = val; |
1257 |
serial_update_irq(); |
1258 |
} |
1259 |
break;
|
1260 |
case 2: |
1261 |
break;
|
1262 |
case 3: |
1263 |
s->lcr = val; |
1264 |
break;
|
1265 |
case 4: |
1266 |
s->mcr = val; |
1267 |
break;
|
1268 |
case 5: |
1269 |
break;
|
1270 |
case 6: |
1271 |
s->msr = val; |
1272 |
break;
|
1273 |
case 7: |
1274 |
s->scr = val; |
1275 |
break;
|
1276 |
} |
1277 |
} |
1278 |
|
1279 |
uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr) |
1280 |
{ |
1281 |
SerialState *s = &serial_ports[0];
|
1282 |
uint32_t ret; |
1283 |
|
1284 |
addr &= 7;
|
1285 |
switch(addr) {
|
1286 |
default:
|
1287 |
case 0: |
1288 |
if (s->lcr & UART_LCR_DLAB) {
|
1289 |
ret = s->divider & 0xff;
|
1290 |
} else {
|
1291 |
ret = s->rbr; |
1292 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
1293 |
serial_update_irq(); |
1294 |
} |
1295 |
break;
|
1296 |
case 1: |
1297 |
if (s->lcr & UART_LCR_DLAB) {
|
1298 |
ret = (s->divider >> 8) & 0xff; |
1299 |
} else {
|
1300 |
ret = s->ier; |
1301 |
} |
1302 |
break;
|
1303 |
case 2: |
1304 |
ret = s->iir; |
1305 |
break;
|
1306 |
case 3: |
1307 |
ret = s->lcr; |
1308 |
break;
|
1309 |
case 4: |
1310 |
ret = s->mcr; |
1311 |
break;
|
1312 |
case 5: |
1313 |
ret = s->lsr; |
1314 |
break;
|
1315 |
case 6: |
1316 |
ret = s->msr; |
1317 |
break;
|
1318 |
case 7: |
1319 |
ret = s->scr; |
1320 |
break;
|
1321 |
} |
1322 |
return ret;
|
1323 |
} |
1324 |
|
1325 |
#define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */ |
1326 |
static int term_got_escape; |
1327 |
|
1328 |
void term_print_help(void) |
1329 |
{ |
1330 |
printf("\n"
|
1331 |
"C-a h print this help\n"
|
1332 |
"C-a x exit emulatior\n"
|
1333 |
"C-a s save disk data back to file (if -snapshot)\n"
|
1334 |
"C-a b send break (magic sysrq)\n"
|
1335 |
"C-a C-a send C-a\n"
|
1336 |
); |
1337 |
} |
1338 |
|
1339 |
/* called when a char is received */
|
1340 |
void serial_received_byte(SerialState *s, int ch) |
1341 |
{ |
1342 |
if (term_got_escape) {
|
1343 |
term_got_escape = 0;
|
1344 |
switch(ch) {
|
1345 |
case 'h': |
1346 |
term_print_help(); |
1347 |
break;
|
1348 |
case 'x': |
1349 |
exit(0);
|
1350 |
break;
|
1351 |
case 's': |
1352 |
{ |
1353 |
int i;
|
1354 |
for (i = 0; i < MAX_DISKS; i++) { |
1355 |
if (bs_table[i])
|
1356 |
bdrv_commit(bs_table[i]); |
1357 |
} |
1358 |
} |
1359 |
break;
|
1360 |
case 'b': |
1361 |
/* send break */
|
1362 |
s->rbr = 0;
|
1363 |
s->lsr |= UART_LSR_BI | UART_LSR_DR; |
1364 |
serial_update_irq(); |
1365 |
break;
|
1366 |
case TERM_ESCAPE:
|
1367 |
goto send_char;
|
1368 |
} |
1369 |
} else if (ch == TERM_ESCAPE) { |
1370 |
term_got_escape = 1;
|
1371 |
} else {
|
1372 |
send_char:
|
1373 |
s->rbr = ch; |
1374 |
s->lsr |= UART_LSR_DR; |
1375 |
serial_update_irq(); |
1376 |
} |
1377 |
} |
1378 |
|
1379 |
void serial_init(void) |
1380 |
{ |
1381 |
SerialState *s = &serial_ports[0];
|
1382 |
|
1383 |
s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
1384 |
|
1385 |
register_ioport_write(0x3f8, 8, serial_ioport_write, 1); |
1386 |
register_ioport_read(0x3f8, 8, serial_ioport_read, 1); |
1387 |
} |
1388 |
|
1389 |
/***********************************************************/
|
1390 |
/* ne2000 emulation */
|
1391 |
|
1392 |
#define NE2000_IOPORT 0x300 |
1393 |
#define NE2000_IRQ 9 |
1394 |
|
1395 |
#define MAX_ETH_FRAME_SIZE 1514 |
1396 |
|
1397 |
#define E8390_CMD 0x00 /* The command register (for all pages) */ |
1398 |
/* Page 0 register offsets. */
|
1399 |
#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
1400 |
#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
1401 |
#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
1402 |
#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
1403 |
#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
1404 |
#define EN0_TSR 0x04 /* Transmit status reg RD */ |
1405 |
#define EN0_TPSR 0x04 /* Transmit starting page WR */ |
1406 |
#define EN0_NCR 0x05 /* Number of collision reg RD */ |
1407 |
#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
1408 |
#define EN0_FIFO 0x06 /* FIFO RD */ |
1409 |
#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
1410 |
#define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
1411 |
#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
1412 |
#define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
1413 |
#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
1414 |
#define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
1415 |
#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
1416 |
#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
1417 |
#define EN0_RSR 0x0c /* rx status reg RD */ |
1418 |
#define EN0_RXCR 0x0c /* RX configuration reg WR */ |
1419 |
#define EN0_TXCR 0x0d /* TX configuration reg WR */ |
1420 |
#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
1421 |
#define EN0_DCFG 0x0e /* Data configuration reg WR */ |
1422 |
#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
1423 |
#define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
1424 |
#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
1425 |
|
1426 |
#define EN1_PHYS 0x11 |
1427 |
#define EN1_CURPAG 0x17 |
1428 |
#define EN1_MULT 0x18 |
1429 |
|
1430 |
/* Register accessed at EN_CMD, the 8390 base addr. */
|
1431 |
#define E8390_STOP 0x01 /* Stop and reset the chip */ |
1432 |
#define E8390_START 0x02 /* Start the chip, clear reset */ |
1433 |
#define E8390_TRANS 0x04 /* Transmit a frame */ |
1434 |
#define E8390_RREAD 0x08 /* Remote read */ |
1435 |
#define E8390_RWRITE 0x10 /* Remote write */ |
1436 |
#define E8390_NODMA 0x20 /* Remote DMA */ |
1437 |
#define E8390_PAGE0 0x00 /* Select page chip registers */ |
1438 |
#define E8390_PAGE1 0x40 /* using the two high-order bits */ |
1439 |
#define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
1440 |
|
1441 |
/* Bits in EN0_ISR - Interrupt status register */
|
1442 |
#define ENISR_RX 0x01 /* Receiver, no error */ |
1443 |
#define ENISR_TX 0x02 /* Transmitter, no error */ |
1444 |
#define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
1445 |
#define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
1446 |
#define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
1447 |
#define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
1448 |
#define ENISR_RDC 0x40 /* remote dma complete */ |
1449 |
#define ENISR_RESET 0x80 /* Reset completed */ |
1450 |
#define ENISR_ALL 0x3f /* Interrupts we will enable */ |
1451 |
|
1452 |
/* Bits in received packet status byte and EN0_RSR*/
|
1453 |
#define ENRSR_RXOK 0x01 /* Received a good packet */ |
1454 |
#define ENRSR_CRC 0x02 /* CRC error */ |
1455 |
#define ENRSR_FAE 0x04 /* frame alignment error */ |
1456 |
#define ENRSR_FO 0x08 /* FIFO overrun */ |
1457 |
#define ENRSR_MPA 0x10 /* missed pkt */ |
1458 |
#define ENRSR_PHY 0x20 /* physical/multicast address */ |
1459 |
#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
1460 |
#define ENRSR_DEF 0x80 /* deferring */ |
1461 |
|
1462 |
/* Transmitted packet status, EN0_TSR. */
|
1463 |
#define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
1464 |
#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
1465 |
#define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
1466 |
#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
1467 |
#define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
1468 |
#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
1469 |
#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
1470 |
#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
1471 |
|
1472 |
#define NE2000_MEM_SIZE 32768 |
1473 |
|
1474 |
typedef struct NE2000State { |
1475 |
uint8_t cmd; |
1476 |
uint32_t start; |
1477 |
uint32_t stop; |
1478 |
uint8_t boundary; |
1479 |
uint8_t tsr; |
1480 |
uint8_t tpsr; |
1481 |
uint16_t tcnt; |
1482 |
uint16_t rcnt; |
1483 |
uint32_t rsar; |
1484 |
uint8_t isr; |
1485 |
uint8_t dcfg; |
1486 |
uint8_t imr; |
1487 |
uint8_t phys[6]; /* mac address */ |
1488 |
uint8_t curpag; |
1489 |
uint8_t mult[8]; /* multicast mask array */ |
1490 |
uint8_t mem[NE2000_MEM_SIZE]; |
1491 |
} NE2000State; |
1492 |
|
1493 |
NE2000State ne2000_state; |
1494 |
int net_fd = -1; |
1495 |
char network_script[1024]; |
1496 |
|
1497 |
void ne2000_reset(void) |
1498 |
{ |
1499 |
NE2000State *s = &ne2000_state; |
1500 |
int i;
|
1501 |
|
1502 |
s->isr = ENISR_RESET; |
1503 |
s->mem[0] = 0x52; |
1504 |
s->mem[1] = 0x54; |
1505 |
s->mem[2] = 0x00; |
1506 |
s->mem[3] = 0x12; |
1507 |
s->mem[4] = 0x34; |
1508 |
s->mem[5] = 0x56; |
1509 |
s->mem[14] = 0x57; |
1510 |
s->mem[15] = 0x57; |
1511 |
|
1512 |
/* duplicate prom data */
|
1513 |
for(i = 15;i >= 0; i--) { |
1514 |
s->mem[2 * i] = s->mem[i];
|
1515 |
s->mem[2 * i + 1] = s->mem[i]; |
1516 |
} |
1517 |
} |
1518 |
|
1519 |
void ne2000_update_irq(NE2000State *s)
|
1520 |
{ |
1521 |
int isr;
|
1522 |
isr = s->isr & s->imr; |
1523 |
if (isr)
|
1524 |
pic_set_irq(NE2000_IRQ, 1);
|
1525 |
else
|
1526 |
pic_set_irq(NE2000_IRQ, 0);
|
1527 |
} |
1528 |
|
1529 |
int net_init(void) |
1530 |
{ |
1531 |
struct ifreq ifr;
|
1532 |
int fd, ret, pid, status;
|
1533 |
|
1534 |
fd = open("/dev/net/tun", O_RDWR);
|
1535 |
if (fd < 0) { |
1536 |
fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
|
1537 |
return -1; |
1538 |
} |
1539 |
memset(&ifr, 0, sizeof(ifr)); |
1540 |
ifr.ifr_flags = IFF_TAP | IFF_NO_PI; |
1541 |
pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
|
1542 |
ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
|
1543 |
if (ret != 0) { |
1544 |
fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
|
1545 |
close(fd); |
1546 |
return -1; |
1547 |
} |
1548 |
printf("Connected to host network interface: %s\n", ifr.ifr_name);
|
1549 |
fcntl(fd, F_SETFL, O_NONBLOCK); |
1550 |
net_fd = fd; |
1551 |
|
1552 |
/* try to launch network init script */
|
1553 |
pid = fork(); |
1554 |
if (pid >= 0) { |
1555 |
if (pid == 0) { |
1556 |
execl(network_script, network_script, ifr.ifr_name, NULL);
|
1557 |
exit(1);
|
1558 |
} |
1559 |
while (waitpid(pid, &status, 0) != pid); |
1560 |
if (!WIFEXITED(status) ||
|
1561 |
WEXITSTATUS(status) != 0) {
|
1562 |
fprintf(stderr, "%s: could not launch network script for '%s'\n",
|
1563 |
network_script, ifr.ifr_name); |
1564 |
} |
1565 |
} |
1566 |
return 0; |
1567 |
} |
1568 |
|
1569 |
void net_send_packet(NE2000State *s, const uint8_t *buf, int size) |
1570 |
{ |
1571 |
#ifdef DEBUG_NE2000
|
1572 |
printf("NE2000: sending packet size=%d\n", size);
|
1573 |
#endif
|
1574 |
write(net_fd, buf, size); |
1575 |
} |
1576 |
|
1577 |
/* return true if the NE2000 can receive more data */
|
1578 |
int ne2000_can_receive(NE2000State *s)
|
1579 |
{ |
1580 |
int avail, index, boundary;
|
1581 |
|
1582 |
if (s->cmd & E8390_STOP)
|
1583 |
return 0; |
1584 |
index = s->curpag << 8;
|
1585 |
boundary = s->boundary << 8;
|
1586 |
if (index < boundary)
|
1587 |
avail = boundary - index; |
1588 |
else
|
1589 |
avail = (s->stop - s->start) - (index - boundary); |
1590 |
if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
1591 |
return 0; |
1592 |
return 1; |
1593 |
} |
1594 |
|
1595 |
void ne2000_receive(NE2000State *s, uint8_t *buf, int size) |
1596 |
{ |
1597 |
uint8_t *p; |
1598 |
int total_len, next, avail, len, index;
|
1599 |
|
1600 |
#if defined(DEBUG_NE2000)
|
1601 |
printf("NE2000: received len=%d\n", size);
|
1602 |
#endif
|
1603 |
|
1604 |
index = s->curpag << 8;
|
1605 |
/* 4 bytes for header */
|
1606 |
total_len = size + 4;
|
1607 |
/* address for next packet (4 bytes for CRC) */
|
1608 |
next = index + ((total_len + 4 + 255) & ~0xff); |
1609 |
if (next >= s->stop)
|
1610 |
next -= (s->stop - s->start); |
1611 |
/* prepare packet header */
|
1612 |
p = s->mem + index; |
1613 |
p[0] = ENRSR_RXOK; /* receive status */ |
1614 |
p[1] = next >> 8; |
1615 |
p[2] = total_len;
|
1616 |
p[3] = total_len >> 8; |
1617 |
index += 4;
|
1618 |
|
1619 |
/* write packet data */
|
1620 |
while (size > 0) { |
1621 |
avail = s->stop - index; |
1622 |
len = size; |
1623 |
if (len > avail)
|
1624 |
len = avail; |
1625 |
memcpy(s->mem + index, buf, len); |
1626 |
buf += len; |
1627 |
index += len; |
1628 |
if (index == s->stop)
|
1629 |
index = s->start; |
1630 |
size -= len; |
1631 |
} |
1632 |
s->curpag = next >> 8;
|
1633 |
|
1634 |
/* now we can signal we have receive something */
|
1635 |
s->isr |= ENISR_RX; |
1636 |
ne2000_update_irq(s); |
1637 |
} |
1638 |
|
1639 |
void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1640 |
{ |
1641 |
NE2000State *s = &ne2000_state; |
1642 |
int offset, page;
|
1643 |
|
1644 |
addr &= 0xf;
|
1645 |
#ifdef DEBUG_NE2000
|
1646 |
printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
|
1647 |
#endif
|
1648 |
if (addr == E8390_CMD) {
|
1649 |
/* control register */
|
1650 |
s->cmd = val; |
1651 |
if (val & E8390_START) {
|
1652 |
/* test specific case: zero length transfert */
|
1653 |
if ((val & (E8390_RREAD | E8390_RWRITE)) &&
|
1654 |
s->rcnt == 0) {
|
1655 |
s->isr |= ENISR_RDC; |
1656 |
ne2000_update_irq(s); |
1657 |
} |
1658 |
if (val & E8390_TRANS) {
|
1659 |
net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
|
1660 |
/* signal end of transfert */
|
1661 |
s->tsr = ENTSR_PTX; |
1662 |
s->isr |= ENISR_TX; |
1663 |
ne2000_update_irq(s); |
1664 |
} |
1665 |
} |
1666 |
} else {
|
1667 |
page = s->cmd >> 6;
|
1668 |
offset = addr | (page << 4);
|
1669 |
switch(offset) {
|
1670 |
case EN0_STARTPG:
|
1671 |
s->start = val << 8;
|
1672 |
break;
|
1673 |
case EN0_STOPPG:
|
1674 |
s->stop = val << 8;
|
1675 |
break;
|
1676 |
case EN0_BOUNDARY:
|
1677 |
s->boundary = val; |
1678 |
break;
|
1679 |
case EN0_IMR:
|
1680 |
s->imr = val; |
1681 |
ne2000_update_irq(s); |
1682 |
break;
|
1683 |
case EN0_TPSR:
|
1684 |
s->tpsr = val; |
1685 |
break;
|
1686 |
case EN0_TCNTLO:
|
1687 |
s->tcnt = (s->tcnt & 0xff00) | val;
|
1688 |
break;
|
1689 |
case EN0_TCNTHI:
|
1690 |
s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
1691 |
break;
|
1692 |
case EN0_RSARLO:
|
1693 |
s->rsar = (s->rsar & 0xff00) | val;
|
1694 |
break;
|
1695 |
case EN0_RSARHI:
|
1696 |
s->rsar = (s->rsar & 0x00ff) | (val << 8); |
1697 |
break;
|
1698 |
case EN0_RCNTLO:
|
1699 |
s->rcnt = (s->rcnt & 0xff00) | val;
|
1700 |
break;
|
1701 |
case EN0_RCNTHI:
|
1702 |
s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
1703 |
break;
|
1704 |
case EN0_DCFG:
|
1705 |
s->dcfg = val; |
1706 |
break;
|
1707 |
case EN0_ISR:
|
1708 |
s->isr &= ~val; |
1709 |
ne2000_update_irq(s); |
1710 |
break;
|
1711 |
case EN1_PHYS ... EN1_PHYS + 5: |
1712 |
s->phys[offset - EN1_PHYS] = val; |
1713 |
break;
|
1714 |
case EN1_CURPAG:
|
1715 |
s->curpag = val; |
1716 |
break;
|
1717 |
case EN1_MULT ... EN1_MULT + 7: |
1718 |
s->mult[offset - EN1_MULT] = val; |
1719 |
break;
|
1720 |
} |
1721 |
} |
1722 |
} |
1723 |
|
1724 |
uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr) |
1725 |
{ |
1726 |
NE2000State *s = &ne2000_state; |
1727 |
int offset, page, ret;
|
1728 |
|
1729 |
addr &= 0xf;
|
1730 |
if (addr == E8390_CMD) {
|
1731 |
ret = s->cmd; |
1732 |
} else {
|
1733 |
page = s->cmd >> 6;
|
1734 |
offset = addr | (page << 4);
|
1735 |
switch(offset) {
|
1736 |
case EN0_TSR:
|
1737 |
ret = s->tsr; |
1738 |
break;
|
1739 |
case EN0_BOUNDARY:
|
1740 |
ret = s->boundary; |
1741 |
break;
|
1742 |
case EN0_ISR:
|
1743 |
ret = s->isr; |
1744 |
break;
|
1745 |
case EN1_PHYS ... EN1_PHYS + 5: |
1746 |
ret = s->phys[offset - EN1_PHYS]; |
1747 |
break;
|
1748 |
case EN1_CURPAG:
|
1749 |
ret = s->curpag; |
1750 |
break;
|
1751 |
case EN1_MULT ... EN1_MULT + 7: |
1752 |
ret = s->mult[offset - EN1_MULT]; |
1753 |
break;
|
1754 |
default:
|
1755 |
ret = 0x00;
|
1756 |
break;
|
1757 |
} |
1758 |
} |
1759 |
#ifdef DEBUG_NE2000
|
1760 |
printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
1761 |
#endif
|
1762 |
return ret;
|
1763 |
} |
1764 |
|
1765 |
void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1766 |
{ |
1767 |
NE2000State *s = &ne2000_state; |
1768 |
uint8_t *p; |
1769 |
|
1770 |
#ifdef DEBUG_NE2000
|
1771 |
printf("NE2000: asic write val=0x%04x\n", val);
|
1772 |
#endif
|
1773 |
p = s->mem + s->rsar; |
1774 |
if (s->dcfg & 0x01) { |
1775 |
/* 16 bit access */
|
1776 |
p[0] = val;
|
1777 |
p[1] = val >> 8; |
1778 |
s->rsar += 2;
|
1779 |
s->rcnt -= 2;
|
1780 |
} else {
|
1781 |
/* 8 bit access */
|
1782 |
p[0] = val;
|
1783 |
s->rsar++; |
1784 |
s->rcnt--; |
1785 |
} |
1786 |
/* wrap */
|
1787 |
if (s->rsar == s->stop)
|
1788 |
s->rsar = s->start; |
1789 |
if (s->rcnt == 0) { |
1790 |
/* signal end of transfert */
|
1791 |
s->isr |= ENISR_RDC; |
1792 |
ne2000_update_irq(s); |
1793 |
} |
1794 |
} |
1795 |
|
1796 |
uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr) |
1797 |
{ |
1798 |
NE2000State *s = &ne2000_state; |
1799 |
uint8_t *p; |
1800 |
int ret;
|
1801 |
|
1802 |
p = s->mem + s->rsar; |
1803 |
if (s->dcfg & 0x01) { |
1804 |
/* 16 bit access */
|
1805 |
ret = p[0] | (p[1] << 8); |
1806 |
s->rsar += 2;
|
1807 |
s->rcnt -= 2;
|
1808 |
} else {
|
1809 |
/* 8 bit access */
|
1810 |
ret = p[0];
|
1811 |
s->rsar++; |
1812 |
s->rcnt--; |
1813 |
} |
1814 |
/* wrap */
|
1815 |
if (s->rsar == s->stop)
|
1816 |
s->rsar = s->start; |
1817 |
if (s->rcnt == 0) { |
1818 |
/* signal end of transfert */
|
1819 |
s->isr |= ENISR_RDC; |
1820 |
ne2000_update_irq(s); |
1821 |
} |
1822 |
#ifdef DEBUG_NE2000
|
1823 |
printf("NE2000: asic read val=0x%04x\n", ret);
|
1824 |
#endif
|
1825 |
return ret;
|
1826 |
} |
1827 |
|
1828 |
void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1829 |
{ |
1830 |
/* nothing to do (end of reset pulse) */
|
1831 |
} |
1832 |
|
1833 |
uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr) |
1834 |
{ |
1835 |
ne2000_reset(); |
1836 |
return 0; |
1837 |
} |
1838 |
|
1839 |
void ne2000_init(void) |
1840 |
{ |
1841 |
register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1); |
1842 |
register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1); |
1843 |
|
1844 |
register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1); |
1845 |
register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1); |
1846 |
register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2); |
1847 |
register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2); |
1848 |
|
1849 |
register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1); |
1850 |
register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1); |
1851 |
ne2000_reset(); |
1852 |
} |
1853 |
|
1854 |
/***********************************************************/
|
1855 |
/* ide emulation */
|
1856 |
|
1857 |
/* Bits of HD_STATUS */
|
1858 |
#define ERR_STAT 0x01 |
1859 |
#define INDEX_STAT 0x02 |
1860 |
#define ECC_STAT 0x04 /* Corrected error */ |
1861 |
#define DRQ_STAT 0x08 |
1862 |
#define SEEK_STAT 0x10 |
1863 |
#define SRV_STAT 0x10 |
1864 |
#define WRERR_STAT 0x20 |
1865 |
#define READY_STAT 0x40 |
1866 |
#define BUSY_STAT 0x80 |
1867 |
|
1868 |
/* Bits for HD_ERROR */
|
1869 |
#define MARK_ERR 0x01 /* Bad address mark */ |
1870 |
#define TRK0_ERR 0x02 /* couldn't find track 0 */ |
1871 |
#define ABRT_ERR 0x04 /* Command aborted */ |
1872 |
#define MCR_ERR 0x08 /* media change request */ |
1873 |
#define ID_ERR 0x10 /* ID field not found */ |
1874 |
#define MC_ERR 0x20 /* media changed */ |
1875 |
#define ECC_ERR 0x40 /* Uncorrectable ECC error */ |
1876 |
#define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */ |
1877 |
#define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */ |
1878 |
|
1879 |
/* Bits of HD_NSECTOR */
|
1880 |
#define CD 0x01 |
1881 |
#define IO 0x02 |
1882 |
#define REL 0x04 |
1883 |
#define TAG_MASK 0xf8 |
1884 |
|
1885 |
#define IDE_CMD_RESET 0x04 |
1886 |
#define IDE_CMD_DISABLE_IRQ 0x02 |
1887 |
|
1888 |
/* ATA/ATAPI Commands pre T13 Spec */
|
1889 |
#define WIN_NOP 0x00 |
1890 |
/*
|
1891 |
* 0x01->0x02 Reserved
|
1892 |
*/
|
1893 |
#define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */ |
1894 |
/*
|
1895 |
* 0x04->0x07 Reserved
|
1896 |
*/
|
1897 |
#define WIN_SRST 0x08 /* ATAPI soft reset command */ |
1898 |
#define WIN_DEVICE_RESET 0x08 |
1899 |
/*
|
1900 |
* 0x09->0x0F Reserved
|
1901 |
*/
|
1902 |
#define WIN_RECAL 0x10 |
1903 |
#define WIN_RESTORE WIN_RECAL
|
1904 |
/*
|
1905 |
* 0x10->0x1F Reserved
|
1906 |
*/
|
1907 |
#define WIN_READ 0x20 /* 28-Bit */ |
1908 |
#define WIN_READ_ONCE 0x21 /* 28-Bit without retries */ |
1909 |
#define WIN_READ_LONG 0x22 /* 28-Bit */ |
1910 |
#define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */ |
1911 |
#define WIN_READ_EXT 0x24 /* 48-Bit */ |
1912 |
#define WIN_READDMA_EXT 0x25 /* 48-Bit */ |
1913 |
#define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */ |
1914 |
#define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */ |
1915 |
/*
|
1916 |
* 0x28
|
1917 |
*/
|
1918 |
#define WIN_MULTREAD_EXT 0x29 /* 48-Bit */ |
1919 |
/*
|
1920 |
* 0x2A->0x2F Reserved
|
1921 |
*/
|
1922 |
#define WIN_WRITE 0x30 /* 28-Bit */ |
1923 |
#define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */ |
1924 |
#define WIN_WRITE_LONG 0x32 /* 28-Bit */ |
1925 |
#define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */ |
1926 |
#define WIN_WRITE_EXT 0x34 /* 48-Bit */ |
1927 |
#define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */ |
1928 |
#define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */ |
1929 |
#define WIN_SET_MAX_EXT 0x37 /* 48-Bit */ |
1930 |
#define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */ |
1931 |
#define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */ |
1932 |
/*
|
1933 |
* 0x3A->0x3B Reserved
|
1934 |
*/
|
1935 |
#define WIN_WRITE_VERIFY 0x3C /* 28-Bit */ |
1936 |
/*
|
1937 |
* 0x3D->0x3F Reserved
|
1938 |
*/
|
1939 |
#define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */ |
1940 |
#define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */ |
1941 |
#define WIN_VERIFY_EXT 0x42 /* 48-Bit */ |
1942 |
/*
|
1943 |
* 0x43->0x4F Reserved
|
1944 |
*/
|
1945 |
#define WIN_FORMAT 0x50 |
1946 |
/*
|
1947 |
* 0x51->0x5F Reserved
|
1948 |
*/
|
1949 |
#define WIN_INIT 0x60 |
1950 |
/*
|
1951 |
* 0x61->0x5F Reserved
|
1952 |
*/
|
1953 |
#define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */ |
1954 |
#define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */ |
1955 |
#define WIN_DIAGNOSE 0x90 |
1956 |
#define WIN_SPECIFY 0x91 /* set drive geometry translation */ |
1957 |
#define WIN_DOWNLOAD_MICROCODE 0x92 |
1958 |
#define WIN_STANDBYNOW2 0x94 |
1959 |
#define WIN_STANDBY2 0x96 |
1960 |
#define WIN_SETIDLE2 0x97 |
1961 |
#define WIN_CHECKPOWERMODE2 0x98 |
1962 |
#define WIN_SLEEPNOW2 0x99 |
1963 |
/*
|
1964 |
* 0x9A VENDOR
|
1965 |
*/
|
1966 |
#define WIN_PACKETCMD 0xA0 /* Send a packet command. */ |
1967 |
#define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */ |
1968 |
#define WIN_QUEUED_SERVICE 0xA2 |
1969 |
#define WIN_SMART 0xB0 /* self-monitoring and reporting */ |
1970 |
#define CFA_ERASE_SECTORS 0xC0 |
1971 |
#define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/ |
1972 |
#define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */ |
1973 |
#define WIN_SETMULT 0xC6 /* enable/disable multiple mode */ |
1974 |
#define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */ |
1975 |
#define WIN_READDMA 0xC8 /* read sectors using DMA transfers */ |
1976 |
#define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */ |
1977 |
#define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */ |
1978 |
#define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */ |
1979 |
#define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */ |
1980 |
#define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */ |
1981 |
#define WIN_GETMEDIASTATUS 0xDA |
1982 |
#define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */ |
1983 |
#define WIN_POSTBOOT 0xDC |
1984 |
#define WIN_PREBOOT 0xDD |
1985 |
#define WIN_DOORLOCK 0xDE /* lock door on removable drives */ |
1986 |
#define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */ |
1987 |
#define WIN_STANDBYNOW1 0xE0 |
1988 |
#define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */ |
1989 |
#define WIN_STANDBY 0xE2 /* Set device in Standby Mode */ |
1990 |
#define WIN_SETIDLE1 0xE3 |
1991 |
#define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */ |
1992 |
#define WIN_CHECKPOWERMODE1 0xE5 |
1993 |
#define WIN_SLEEPNOW1 0xE6 |
1994 |
#define WIN_FLUSH_CACHE 0xE7 |
1995 |
#define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */ |
1996 |
#define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */ |
1997 |
/* SET_FEATURES 0x22 or 0xDD */
|
1998 |
#define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */ |
1999 |
#define WIN_IDENTIFY 0xEC /* ask drive to identify itself */ |
2000 |
#define WIN_MEDIAEJECT 0xED |
2001 |
#define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */ |
2002 |
#define WIN_SETFEATURES 0xEF /* set special drive features */ |
2003 |
#define EXABYTE_ENABLE_NEST 0xF0 |
2004 |
#define WIN_SECURITY_SET_PASS 0xF1 |
2005 |
#define WIN_SECURITY_UNLOCK 0xF2 |
2006 |
#define WIN_SECURITY_ERASE_PREPARE 0xF3 |
2007 |
#define WIN_SECURITY_ERASE_UNIT 0xF4 |
2008 |
#define WIN_SECURITY_FREEZE_LOCK 0xF5 |
2009 |
#define WIN_SECURITY_DISABLE 0xF6 |
2010 |
#define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */ |
2011 |
#define WIN_SET_MAX 0xF9 |
2012 |
#define DISABLE_SEAGATE 0xFB |
2013 |
|
2014 |
/* set to 1 set disable mult support */
|
2015 |
#define MAX_MULT_SECTORS 8 |
2016 |
|
2017 |
struct IDEState;
|
2018 |
|
2019 |
typedef void EndTransferFunc(struct IDEState *); |
2020 |
|
2021 |
typedef struct IDEState { |
2022 |
/* ide config */
|
2023 |
int cylinders, heads, sectors;
|
2024 |
int64_t nb_sectors; |
2025 |
int mult_sectors;
|
2026 |
int irq;
|
2027 |
/* ide regs */
|
2028 |
uint8_t feature; |
2029 |
uint8_t error; |
2030 |
uint16_t nsector; /* 0 is 256 to ease computations */
|
2031 |
uint8_t sector; |
2032 |
uint8_t lcyl; |
2033 |
uint8_t hcyl; |
2034 |
uint8_t select; |
2035 |
uint8_t status; |
2036 |
/* 0x3f6 command, only meaningful for drive 0 */
|
2037 |
uint8_t cmd; |
2038 |
/* depends on bit 4 in select, only meaningful for drive 0 */
|
2039 |
struct IDEState *cur_drive;
|
2040 |
BlockDriverState *bs; |
2041 |
int req_nb_sectors; /* number of sectors per interrupt */ |
2042 |
EndTransferFunc *end_transfer_func; |
2043 |
uint8_t *data_ptr; |
2044 |
uint8_t *data_end; |
2045 |
uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4]; |
2046 |
} IDEState; |
2047 |
|
2048 |
IDEState ide_state[MAX_DISKS]; |
2049 |
|
2050 |
static void padstr(char *str, const char *src, int len) |
2051 |
{ |
2052 |
int i, v;
|
2053 |
for(i = 0; i < len; i++) { |
2054 |
if (*src)
|
2055 |
v = *src++; |
2056 |
else
|
2057 |
v = ' ';
|
2058 |
*(char *)((long)str ^ 1) = v; |
2059 |
str++; |
2060 |
} |
2061 |
} |
2062 |
|
2063 |
static void ide_identify(IDEState *s) |
2064 |
{ |
2065 |
uint16_t *p; |
2066 |
unsigned int oldsize; |
2067 |
|
2068 |
memset(s->io_buffer, 0, 512); |
2069 |
p = (uint16_t *)s->io_buffer; |
2070 |
stw_raw(p + 0, 0x0040); |
2071 |
stw_raw(p + 1, s->cylinders);
|
2072 |
stw_raw(p + 3, s->heads);
|
2073 |
stw_raw(p + 4, 512 * s->sectors); /* sectors */ |
2074 |
stw_raw(p + 5, 512); /* sector size */ |
2075 |
stw_raw(p + 6, s->sectors);
|
2076 |
stw_raw(p + 20, 3); /* buffer type */ |
2077 |
stw_raw(p + 21, 512); /* cache size in sectors */ |
2078 |
stw_raw(p + 22, 4); /* ecc bytes */ |
2079 |
padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40); |
2080 |
#if MAX_MULT_SECTORS > 1 |
2081 |
stw_raw(p + 47, MAX_MULT_SECTORS);
|
2082 |
#endif
|
2083 |
stw_raw(p + 48, 1); /* dword I/O */ |
2084 |
stw_raw(p + 49, 1 << 9); /* LBA supported, no DMA */ |
2085 |
stw_raw(p + 51, 0x200); /* PIO transfer cycle */ |
2086 |
stw_raw(p + 52, 0x200); /* DMA transfer cycle */ |
2087 |
stw_raw(p + 54, s->cylinders);
|
2088 |
stw_raw(p + 55, s->heads);
|
2089 |
stw_raw(p + 56, s->sectors);
|
2090 |
oldsize = s->cylinders * s->heads * s->sectors; |
2091 |
stw_raw(p + 57, oldsize);
|
2092 |
stw_raw(p + 58, oldsize >> 16); |
2093 |
if (s->mult_sectors)
|
2094 |
stw_raw(p + 59, 0x100 | s->mult_sectors); |
2095 |
stw_raw(p + 60, s->nb_sectors);
|
2096 |
stw_raw(p + 61, s->nb_sectors >> 16); |
2097 |
stw_raw(p + 80, (1 << 1) | (1 << 2)); |
2098 |
stw_raw(p + 82, (1 << 14)); |
2099 |
stw_raw(p + 83, (1 << 14)); |
2100 |
stw_raw(p + 84, (1 << 14)); |
2101 |
stw_raw(p + 85, (1 << 14)); |
2102 |
stw_raw(p + 86, 0); |
2103 |
stw_raw(p + 87, (1 << 14)); |
2104 |
} |
2105 |
|
2106 |
static inline void ide_abort_command(IDEState *s) |
2107 |
{ |
2108 |
s->status = READY_STAT | ERR_STAT; |
2109 |
s->error = ABRT_ERR; |
2110 |
} |
2111 |
|
2112 |
static inline void ide_set_irq(IDEState *s) |
2113 |
{ |
2114 |
if (!(ide_state[0].cmd & IDE_CMD_DISABLE_IRQ)) { |
2115 |
pic_set_irq(s->irq, 1);
|
2116 |
} |
2117 |
} |
2118 |
|
2119 |
/* prepare data transfer and tell what to do after */
|
2120 |
static void ide_transfer_start(IDEState *s, int size, |
2121 |
EndTransferFunc *end_transfer_func) |
2122 |
{ |
2123 |
s->end_transfer_func = end_transfer_func; |
2124 |
s->data_ptr = s->io_buffer; |
2125 |
s->data_end = s->io_buffer + size; |
2126 |
s->status |= DRQ_STAT; |
2127 |
} |
2128 |
|
2129 |
static void ide_transfer_stop(IDEState *s) |
2130 |
{ |
2131 |
s->end_transfer_func = ide_transfer_stop; |
2132 |
s->data_ptr = s->io_buffer; |
2133 |
s->data_end = s->io_buffer; |
2134 |
s->status &= ~DRQ_STAT; |
2135 |
} |
2136 |
|
2137 |
static int64_t ide_get_sector(IDEState *s)
|
2138 |
{ |
2139 |
int64_t sector_num; |
2140 |
if (s->select & 0x40) { |
2141 |
/* lba */
|
2142 |
sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | |
2143 |
(s->lcyl << 8) | s->sector;
|
2144 |
} else {
|
2145 |
sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
|
2146 |
(s->select & 0x0f) * s->sectors +
|
2147 |
(s->sector - 1);
|
2148 |
} |
2149 |
return sector_num;
|
2150 |
} |
2151 |
|
2152 |
static void ide_set_sector(IDEState *s, int64_t sector_num) |
2153 |
{ |
2154 |
unsigned int cyl, r; |
2155 |
if (s->select & 0x40) { |
2156 |
s->select = (s->select & 0xf0) | (sector_num >> 24); |
2157 |
s->hcyl = (sector_num >> 16);
|
2158 |
s->lcyl = (sector_num >> 8);
|
2159 |
s->sector = (sector_num); |
2160 |
} else {
|
2161 |
cyl = sector_num / (s->heads * s->sectors); |
2162 |
r = sector_num % (s->heads * s->sectors); |
2163 |
s->hcyl = cyl >> 8;
|
2164 |
s->lcyl = cyl; |
2165 |
s->select = (s->select & 0xf0) | (r / s->sectors);
|
2166 |
s->sector = (r % s->sectors) + 1;
|
2167 |
} |
2168 |
} |
2169 |
|
2170 |
static void ide_sector_read(IDEState *s) |
2171 |
{ |
2172 |
int64_t sector_num; |
2173 |
int ret, n;
|
2174 |
|
2175 |
s->status = READY_STAT | SEEK_STAT; |
2176 |
sector_num = ide_get_sector(s); |
2177 |
n = s->nsector; |
2178 |
if (n == 0) { |
2179 |
/* no more sector to read from disk */
|
2180 |
ide_transfer_stop(s); |
2181 |
} else {
|
2182 |
#if defined(DEBUG_IDE)
|
2183 |
printf("read sector=%Ld\n", sector_num);
|
2184 |
#endif
|
2185 |
if (n > s->req_nb_sectors)
|
2186 |
n = s->req_nb_sectors; |
2187 |
ret = bdrv_read(s->bs, sector_num, s->io_buffer, n); |
2188 |
ide_transfer_start(s, 512 * n, ide_sector_read);
|
2189 |
ide_set_irq(s); |
2190 |
ide_set_sector(s, sector_num + n); |
2191 |
s->nsector -= n; |
2192 |
} |
2193 |
} |
2194 |
|
2195 |
static void ide_sector_write(IDEState *s) |
2196 |
{ |
2197 |
int64_t sector_num; |
2198 |
int ret, n, n1;
|
2199 |
|
2200 |
s->status = READY_STAT | SEEK_STAT; |
2201 |
sector_num = ide_get_sector(s); |
2202 |
#if defined(DEBUG_IDE)
|
2203 |
printf("write sector=%Ld\n", sector_num);
|
2204 |
#endif
|
2205 |
n = s->nsector; |
2206 |
if (n > s->req_nb_sectors)
|
2207 |
n = s->req_nb_sectors; |
2208 |
ret = bdrv_write(s->bs, sector_num, s->io_buffer, n); |
2209 |
s->nsector -= n; |
2210 |
if (s->nsector == 0) { |
2211 |
/* no more sector to write */
|
2212 |
ide_transfer_stop(s); |
2213 |
} else {
|
2214 |
n1 = s->nsector; |
2215 |
if (n1 > s->req_nb_sectors)
|
2216 |
n1 = s->req_nb_sectors; |
2217 |
ide_transfer_start(s, 512 * n1, ide_sector_write);
|
2218 |
} |
2219 |
ide_set_sector(s, sector_num + n); |
2220 |
ide_set_irq(s); |
2221 |
} |
2222 |
|
2223 |
void ide_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
2224 |
{ |
2225 |
IDEState *s = ide_state[0].cur_drive;
|
2226 |
int unit, n;
|
2227 |
|
2228 |
addr &= 7;
|
2229 |
#ifdef DEBUG_IDE
|
2230 |
printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
|
2231 |
#endif
|
2232 |
switch(addr) {
|
2233 |
case 0: |
2234 |
break;
|
2235 |
case 1: |
2236 |
s->feature = val; |
2237 |
break;
|
2238 |
case 2: |
2239 |
if (val == 0) |
2240 |
val = 256;
|
2241 |
s->nsector = val; |
2242 |
break;
|
2243 |
case 3: |
2244 |
s->sector = val; |
2245 |
break;
|
2246 |
case 4: |
2247 |
s->lcyl = val; |
2248 |
break;
|
2249 |
case 5: |
2250 |
s->hcyl = val; |
2251 |
break;
|
2252 |
case 6: |
2253 |
/* select drive */
|
2254 |
unit = (val >> 4) & 1; |
2255 |
s = &ide_state[unit]; |
2256 |
ide_state[0].cur_drive = s;
|
2257 |
s->select = val; |
2258 |
break;
|
2259 |
default:
|
2260 |
case 7: |
2261 |
/* command */
|
2262 |
#if defined(DEBUG_IDE)
|
2263 |
printf("ide: CMD=%02x\n", val);
|
2264 |
#endif
|
2265 |
switch(val) {
|
2266 |
case WIN_PIDENTIFY:
|
2267 |
case WIN_IDENTIFY:
|
2268 |
if (s->bs) {
|
2269 |
ide_identify(s); |
2270 |
s->status = READY_STAT; |
2271 |
ide_transfer_start(s, 512, ide_transfer_stop);
|
2272 |
} else {
|
2273 |
ide_abort_command(s); |
2274 |
} |
2275 |
ide_set_irq(s); |
2276 |
break;
|
2277 |
case WIN_SPECIFY:
|
2278 |
case WIN_RECAL:
|
2279 |
s->status = READY_STAT; |
2280 |
ide_set_irq(s); |
2281 |
break;
|
2282 |
case WIN_SETMULT:
|
2283 |
if (s->nsector > MAX_MULT_SECTORS ||
|
2284 |
s->nsector == 0 ||
|
2285 |
(s->nsector & (s->nsector - 1)) != 0) { |
2286 |
ide_abort_command(s); |
2287 |
} else {
|
2288 |
s->mult_sectors = s->nsector; |
2289 |
s->status = READY_STAT; |
2290 |
} |
2291 |
ide_set_irq(s); |
2292 |
break;
|
2293 |
case WIN_READ:
|
2294 |
case WIN_READ_ONCE:
|
2295 |
s->req_nb_sectors = 1;
|
2296 |
ide_sector_read(s); |
2297 |
break;
|
2298 |
case WIN_WRITE:
|
2299 |
case WIN_WRITE_ONCE:
|
2300 |
s->status = SEEK_STAT; |
2301 |
s->req_nb_sectors = 1;
|
2302 |
ide_transfer_start(s, 512, ide_sector_write);
|
2303 |
break;
|
2304 |
case WIN_MULTREAD:
|
2305 |
if (!s->mult_sectors)
|
2306 |
goto abort_cmd;
|
2307 |
s->req_nb_sectors = s->mult_sectors; |
2308 |
ide_sector_read(s); |
2309 |
break;
|
2310 |
case WIN_MULTWRITE:
|
2311 |
if (!s->mult_sectors)
|
2312 |
goto abort_cmd;
|
2313 |
s->status = SEEK_STAT; |
2314 |
s->req_nb_sectors = s->mult_sectors; |
2315 |
n = s->nsector; |
2316 |
if (n > s->req_nb_sectors)
|
2317 |
n = s->req_nb_sectors; |
2318 |
ide_transfer_start(s, 512 * n, ide_sector_write);
|
2319 |
break;
|
2320 |
case WIN_READ_NATIVE_MAX:
|
2321 |
ide_set_sector(s, s->nb_sectors - 1);
|
2322 |
s->status = READY_STAT; |
2323 |
ide_set_irq(s); |
2324 |
break;
|
2325 |
default:
|
2326 |
abort_cmd:
|
2327 |
ide_abort_command(s); |
2328 |
ide_set_irq(s); |
2329 |
break;
|
2330 |
} |
2331 |
} |
2332 |
} |
2333 |
|
2334 |
uint32_t ide_ioport_read(CPUX86State *env, uint32_t addr) |
2335 |
{ |
2336 |
IDEState *s = ide_state[0].cur_drive;
|
2337 |
int ret;
|
2338 |
|
2339 |
addr &= 7;
|
2340 |
switch(addr) {
|
2341 |
case 0: |
2342 |
ret = 0xff;
|
2343 |
break;
|
2344 |
case 1: |
2345 |
ret = s->error; |
2346 |
break;
|
2347 |
case 2: |
2348 |
ret = s->nsector & 0xff;
|
2349 |
break;
|
2350 |
case 3: |
2351 |
ret = s->sector; |
2352 |
break;
|
2353 |
case 4: |
2354 |
ret = s->lcyl; |
2355 |
break;
|
2356 |
case 5: |
2357 |
ret = s->hcyl; |
2358 |
break;
|
2359 |
case 6: |
2360 |
ret = s->select; |
2361 |
break;
|
2362 |
default:
|
2363 |
case 7: |
2364 |
ret = s->status; |
2365 |
pic_set_irq(s->irq, 0);
|
2366 |
break;
|
2367 |
} |
2368 |
#ifdef DEBUG_IDE
|
2369 |
printf("ide: read addr=0x%x val=%02x\n", addr, ret);
|
2370 |
#endif
|
2371 |
return ret;
|
2372 |
} |
2373 |
|
2374 |
uint32_t ide_status_read(CPUX86State *env, uint32_t addr) |
2375 |
{ |
2376 |
IDEState *s = ide_state[0].cur_drive;
|
2377 |
int ret;
|
2378 |
ret = s->status; |
2379 |
#ifdef DEBUG_IDE
|
2380 |
printf("ide: read status val=%02x\n", ret);
|
2381 |
#endif
|
2382 |
return ret;
|
2383 |
} |
2384 |
|
2385 |
void ide_cmd_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
2386 |
{ |
2387 |
IDEState *s; |
2388 |
int i;
|
2389 |
|
2390 |
#ifdef DEBUG_IDE
|
2391 |
printf("ide: write control val=%02x\n", val);
|
2392 |
#endif
|
2393 |
/* common for both drives */
|
2394 |
if (!(ide_state[0].cmd & IDE_CMD_RESET) && |
2395 |
(val & IDE_CMD_RESET)) { |
2396 |
/* reset low to high */
|
2397 |
for(i = 0;i < 2; i++) { |
2398 |
s = &ide_state[i]; |
2399 |
s->status = BUSY_STAT | SEEK_STAT; |
2400 |
s->error = 0x01;
|
2401 |
} |
2402 |
} else if ((ide_state[0].cmd & IDE_CMD_RESET) && |
2403 |
!(val & IDE_CMD_RESET)) { |
2404 |
/* high to low */
|
2405 |
for(i = 0;i < 2; i++) { |
2406 |
s = &ide_state[i]; |
2407 |
s->status = READY_STAT; |
2408 |
/* set hard disk drive ID */
|
2409 |
s->select &= 0xf0; /* clear head */ |
2410 |
s->nsector = 1;
|
2411 |
s->sector = 1;
|
2412 |
if (s->nb_sectors == 0) { |
2413 |
/* no disk present */
|
2414 |
s->lcyl = 0x12;
|
2415 |
s->hcyl = 0x34;
|
2416 |
} else {
|
2417 |
s->lcyl = 0;
|
2418 |
s->hcyl = 0;
|
2419 |
} |
2420 |
} |
2421 |
} |
2422 |
|
2423 |
ide_state[0].cmd = val;
|
2424 |
} |
2425 |
|
2426 |
void ide_data_writew(CPUX86State *env, uint32_t addr, uint32_t val)
|
2427 |
{ |
2428 |
IDEState *s = ide_state[0].cur_drive;
|
2429 |
uint8_t *p; |
2430 |
|
2431 |
p = s->data_ptr; |
2432 |
*(uint16_t *)p = tswap16(val); |
2433 |
p += 2;
|
2434 |
s->data_ptr = p; |
2435 |
if (p >= s->data_end)
|
2436 |
s->end_transfer_func(s); |
2437 |
} |
2438 |
|
2439 |
uint32_t ide_data_readw(CPUX86State *env, uint32_t addr) |
2440 |
{ |
2441 |
IDEState *s = ide_state[0].cur_drive;
|
2442 |
uint8_t *p; |
2443 |
int ret;
|
2444 |
|
2445 |
p = s->data_ptr; |
2446 |
ret = tswap16(*(uint16_t *)p); |
2447 |
p += 2;
|
2448 |
s->data_ptr = p; |
2449 |
if (p >= s->data_end)
|
2450 |
s->end_transfer_func(s); |
2451 |
return ret;
|
2452 |
} |
2453 |
|
2454 |
void ide_data_writel(CPUX86State *env, uint32_t addr, uint32_t val)
|
2455 |
{ |
2456 |
IDEState *s = ide_state[0].cur_drive;
|
2457 |
uint8_t *p; |
2458 |
|
2459 |
p = s->data_ptr; |
2460 |
*(uint32_t *)p = tswap32(val); |
2461 |
p += 4;
|
2462 |
s->data_ptr = p; |
2463 |
if (p >= s->data_end)
|
2464 |
s->end_transfer_func(s); |
2465 |
} |
2466 |
|
2467 |
uint32_t ide_data_readl(CPUX86State *env, uint32_t addr) |
2468 |
{ |
2469 |
IDEState *s = ide_state[0].cur_drive;
|
2470 |
uint8_t *p; |
2471 |
int ret;
|
2472 |
|
2473 |
p = s->data_ptr; |
2474 |
ret = tswap32(*(uint32_t *)p); |
2475 |
p += 4;
|
2476 |
s->data_ptr = p; |
2477 |
if (p >= s->data_end)
|
2478 |
s->end_transfer_func(s); |
2479 |
return ret;
|
2480 |
} |
2481 |
|
2482 |
void ide_reset(IDEState *s)
|
2483 |
{ |
2484 |
s->mult_sectors = MAX_MULT_SECTORS; |
2485 |
s->status = READY_STAT; |
2486 |
s->cur_drive = s; |
2487 |
s->select = 0xa0;
|
2488 |
} |
2489 |
|
2490 |
struct partition {
|
2491 |
uint8_t boot_ind; /* 0x80 - active */
|
2492 |
uint8_t head; /* starting head */
|
2493 |
uint8_t sector; /* starting sector */
|
2494 |
uint8_t cyl; /* starting cylinder */
|
2495 |
uint8_t sys_ind; /* What partition type */
|
2496 |
uint8_t end_head; /* end head */
|
2497 |
uint8_t end_sector; /* end sector */
|
2498 |
uint8_t end_cyl; /* end cylinder */
|
2499 |
uint32_t start_sect; /* starting sector counting from 0 */
|
2500 |
uint32_t nr_sects; /* nr of sectors in partition */
|
2501 |
} __attribute__((packed)); |
2502 |
|
2503 |
/* try to guess the IDE geometry from the MSDOS partition table */
|
2504 |
void ide_guess_geometry(IDEState *s)
|
2505 |
{ |
2506 |
uint8_t buf[512];
|
2507 |
int ret, i;
|
2508 |
struct partition *p;
|
2509 |
uint32_t nr_sects; |
2510 |
|
2511 |
if (s->cylinders != 0) |
2512 |
return;
|
2513 |
ret = bdrv_read(s->bs, 0, buf, 1); |
2514 |
if (ret < 0) |
2515 |
return;
|
2516 |
/* test msdos magic */
|
2517 |
if (buf[510] != 0x55 || buf[511] != 0xaa) |
2518 |
return;
|
2519 |
for(i = 0; i < 4; i++) { |
2520 |
p = ((struct partition *)(buf + 0x1be)) + i; |
2521 |
nr_sects = tswap32(p->nr_sects); |
2522 |
if (nr_sects && p->end_head) {
|
2523 |
/* We make the assumption that the partition terminates on
|
2524 |
a cylinder boundary */
|
2525 |
s->heads = p->end_head + 1;
|
2526 |
s->sectors = p->end_sector & 63;
|
2527 |
s->cylinders = s->nb_sectors / (s->heads * s->sectors); |
2528 |
#if 0
|
2529 |
printf("guessed partition: CHS=%d %d %d\n",
|
2530 |
s->cylinders, s->heads, s->sectors);
|
2531 |
#endif
|
2532 |
} |
2533 |
} |
2534 |
} |
2535 |
|
2536 |
void ide_init(void) |
2537 |
{ |
2538 |
IDEState *s; |
2539 |
int i, cylinders;
|
2540 |
int64_t nb_sectors; |
2541 |
|
2542 |
for(i = 0; i < MAX_DISKS; i++) { |
2543 |
s = &ide_state[i]; |
2544 |
s->bs = bs_table[i]; |
2545 |
if (s->bs) {
|
2546 |
bdrv_get_geometry(s->bs, &nb_sectors); |
2547 |
s->nb_sectors = nb_sectors; |
2548 |
ide_guess_geometry(s); |
2549 |
if (s->cylinders == 0) { |
2550 |
/* if no geometry, use a LBA compatible one */
|
2551 |
cylinders = nb_sectors / (16 * 63); |
2552 |
if (cylinders > 16383) |
2553 |
cylinders = 16383;
|
2554 |
else if (cylinders < 2) |
2555 |
cylinders = 2;
|
2556 |
s->cylinders = cylinders; |
2557 |
s->heads = 16;
|
2558 |
s->sectors = 63;
|
2559 |
} |
2560 |
} |
2561 |
s->irq = 14;
|
2562 |
ide_reset(s); |
2563 |
} |
2564 |
register_ioport_write(0x1f0, 8, ide_ioport_write, 1); |
2565 |
register_ioport_read(0x1f0, 8, ide_ioport_read, 1); |
2566 |
register_ioport_read(0x3f6, 1, ide_status_read, 1); |
2567 |
register_ioport_write(0x3f6, 1, ide_cmd_write, 1); |
2568 |
|
2569 |
/* data ports */
|
2570 |
register_ioport_write(0x1f0, 2, ide_data_writew, 2); |
2571 |
register_ioport_read(0x1f0, 2, ide_data_readw, 2); |
2572 |
register_ioport_write(0x1f0, 4, ide_data_writel, 4); |
2573 |
register_ioport_read(0x1f0, 4, ide_data_readl, 4); |
2574 |
} |
2575 |
|
2576 |
/***********************************************************/
|
2577 |
/* keyboard emulation */
|
2578 |
|
2579 |
/* Keyboard Controller Commands */
|
2580 |
#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ |
2581 |
#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ |
2582 |
#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ |
2583 |
#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ |
2584 |
#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ |
2585 |
#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ |
2586 |
#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ |
2587 |
#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ |
2588 |
#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ |
2589 |
#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ |
2590 |
#define KBD_CCMD_READ_INPORT 0xC0 /* read input port */ |
2591 |
#define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */ |
2592 |
#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */ |
2593 |
#define KBD_CCMD_WRITE_OBUF 0xD2 |
2594 |
#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if |
2595 |
initiated by the auxiliary device */
|
2596 |
#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ |
2597 |
#define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */ |
2598 |
#define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */ |
2599 |
#define KBD_CCMD_RESET 0xFE |
2600 |
|
2601 |
/* Keyboard Commands */
|
2602 |
#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ |
2603 |
#define KBD_CMD_ECHO 0xEE |
2604 |
#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ |
2605 |
#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ |
2606 |
#define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */ |
2607 |
#define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */ |
2608 |
#define KBD_CMD_RESET 0xFF /* Reset */ |
2609 |
|
2610 |
/* Keyboard Replies */
|
2611 |
#define KBD_REPLY_POR 0xAA /* Power on reset */ |
2612 |
#define KBD_REPLY_ACK 0xFA /* Command ACK */ |
2613 |
#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ |
2614 |
|
2615 |
/* Status Register Bits */
|
2616 |
#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ |
2617 |
#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ |
2618 |
#define KBD_STAT_SELFTEST 0x04 /* Self test successful */ |
2619 |
#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ |
2620 |
#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ |
2621 |
#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ |
2622 |
#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ |
2623 |
#define KBD_STAT_PERR 0x80 /* Parity error */ |
2624 |
|
2625 |
/* Controller Mode Register Bits */
|
2626 |
#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ |
2627 |
#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ |
2628 |
#define KBD_MODE_SYS 0x04 /* The system flag (?) */ |
2629 |
#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ |
2630 |
#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ |
2631 |
#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ |
2632 |
#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ |
2633 |
#define KBD_MODE_RFU 0x80 |
2634 |
|
2635 |
/* Mouse Commands */
|
2636 |
#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */ |
2637 |
#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */ |
2638 |
#define AUX_SET_RES 0xE8 /* Set resolution */ |
2639 |
#define AUX_GET_SCALE 0xE9 /* Get scaling factor */ |
2640 |
#define AUX_SET_STREAM 0xEA /* Set stream mode */ |
2641 |
#define AUX_POLL 0xEB /* Poll */ |
2642 |
#define AUX_RESET_WRAP 0xEC /* Reset wrap mode */ |
2643 |
#define AUX_SET_WRAP 0xEE /* Set wrap mode */ |
2644 |
#define AUX_SET_REMOTE 0xF0 /* Set remote mode */ |
2645 |
#define AUX_GET_TYPE 0xF2 /* Get type */ |
2646 |
#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */ |
2647 |
#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */ |
2648 |
#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */ |
2649 |
#define AUX_SET_DEFAULT 0xF6 |
2650 |
#define AUX_RESET 0xFF /* Reset aux device */ |
2651 |
#define AUX_ACK 0xFA /* Command byte ACK. */ |
2652 |
|
2653 |
#define MOUSE_STATUS_REMOTE 0x40 |
2654 |
#define MOUSE_STATUS_ENABLED 0x20 |
2655 |
#define MOUSE_STATUS_SCALE21 0x10 |
2656 |
|
2657 |
#define KBD_QUEUE_SIZE 256 |
2658 |
|
2659 |
typedef struct { |
2660 |
uint8_t data[KBD_QUEUE_SIZE]; |
2661 |
int rptr, wptr, count;
|
2662 |
} KBDQueue; |
2663 |
|
2664 |
typedef struct KBDState { |
2665 |
KBDQueue queues[2];
|
2666 |
uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
|
2667 |
uint8_t status; |
2668 |
uint8_t mode; |
2669 |
/* keyboard state */
|
2670 |
int kbd_write_cmd;
|
2671 |
int scan_enabled;
|
2672 |
/* mouse state */
|
2673 |
int mouse_write_cmd;
|
2674 |
uint8_t mouse_status; |
2675 |
uint8_t mouse_resolution; |
2676 |
uint8_t mouse_sample_rate; |
2677 |
uint8_t mouse_wrap; |
2678 |
uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
|
2679 |
uint8_t mouse_detect_state; |
2680 |
int mouse_dx; /* current values, needed for 'poll' mode */ |
2681 |
int mouse_dy;
|
2682 |
int mouse_dz;
|
2683 |
uint8_t mouse_buttons; |
2684 |
} KBDState; |
2685 |
|
2686 |
KBDState kbd_state; |
2687 |
int reset_requested;
|
2688 |
|
2689 |
/* update irq and KBD_STAT_[MOUSE_]OBF */
|
2690 |
static void kbd_update_irq(KBDState *s) |
2691 |
{ |
2692 |
int irq12_level, irq1_level;
|
2693 |
|
2694 |
irq1_level = 0;
|
2695 |
irq12_level = 0;
|
2696 |
s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF); |
2697 |
if (s->queues[0].count != 0 || |
2698 |
s->queues[1].count != 0) { |
2699 |
s->status |= KBD_STAT_OBF; |
2700 |
if (s->queues[1].count != 0) { |
2701 |
s->status |= KBD_STAT_MOUSE_OBF; |
2702 |
if (s->mode & KBD_MODE_MOUSE_INT)
|
2703 |
irq12_level = 1;
|
2704 |
} else {
|
2705 |
if (s->mode & KBD_MODE_KBD_INT)
|
2706 |
irq1_level = 1;
|
2707 |
} |
2708 |
} |
2709 |
pic_set_irq(1, irq1_level);
|
2710 |
pic_set_irq(12, irq12_level);
|
2711 |
} |
2712 |
|
2713 |
static void kbd_queue(KBDState *s, int b, int aux) |
2714 |
{ |
2715 |
KBDQueue *q = &kbd_state.queues[aux]; |
2716 |
|
2717 |
#if defined(DEBUG_MOUSE) || defined(DEBUG_KBD)
|
2718 |
if (aux)
|
2719 |
printf("mouse event: 0x%02x\n", b);
|
2720 |
#ifdef DEBUG_KBD
|
2721 |
else
|
2722 |
printf("kbd event: 0x%02x\n", b);
|
2723 |
#endif
|
2724 |
#endif
|
2725 |
if (q->count >= KBD_QUEUE_SIZE)
|
2726 |
return;
|
2727 |
q->data[q->wptr] = b; |
2728 |
if (++q->wptr == KBD_QUEUE_SIZE)
|
2729 |
q->wptr = 0;
|
2730 |
q->count++; |
2731 |
kbd_update_irq(s); |
2732 |
} |
2733 |
|
2734 |
void kbd_put_keycode(int keycode) |
2735 |
{ |
2736 |
KBDState *s = &kbd_state; |
2737 |
kbd_queue(s, keycode, 0);
|
2738 |
} |
2739 |
|
2740 |
uint32_t kbd_read_status(CPUX86State *env, uint32_t addr) |
2741 |
{ |
2742 |
KBDState *s = &kbd_state; |
2743 |
int val;
|
2744 |
val = s->status; |
2745 |
#if defined(DEBUG_KBD) && 0 |
2746 |
printf("kbd: read status=0x%02x\n", val);
|
2747 |
#endif
|
2748 |
return val;
|
2749 |
} |
2750 |
|
2751 |
void kbd_write_command(CPUX86State *env, uint32_t addr, uint32_t val)
|
2752 |
{ |
2753 |
KBDState *s = &kbd_state; |
2754 |
|
2755 |
#ifdef DEBUG_KBD
|
2756 |
printf("kbd: write cmd=0x%02x\n", val);
|
2757 |
#endif
|
2758 |
switch(val) {
|
2759 |
case KBD_CCMD_READ_MODE:
|
2760 |
kbd_queue(s, s->mode, 0);
|
2761 |
break;
|
2762 |
case KBD_CCMD_WRITE_MODE:
|
2763 |
case KBD_CCMD_WRITE_OBUF:
|
2764 |
case KBD_CCMD_WRITE_AUX_OBUF:
|
2765 |
case KBD_CCMD_WRITE_MOUSE:
|
2766 |
case KBD_CCMD_WRITE_OUTPORT:
|
2767 |
s->write_cmd = val; |
2768 |
break;
|
2769 |
case KBD_CCMD_MOUSE_DISABLE:
|
2770 |
s->mode |= KBD_MODE_DISABLE_MOUSE; |
2771 |
break;
|
2772 |
case KBD_CCMD_MOUSE_ENABLE:
|
2773 |
s->mode &= ~KBD_MODE_DISABLE_MOUSE; |
2774 |
break;
|
2775 |
case KBD_CCMD_TEST_MOUSE:
|
2776 |
kbd_queue(s, 0x00, 0); |
2777 |
break;
|
2778 |
case KBD_CCMD_SELF_TEST:
|
2779 |
s->status |= KBD_STAT_SELFTEST; |
2780 |
kbd_queue(s, 0x55, 0); |
2781 |
break;
|
2782 |
case KBD_CCMD_KBD_TEST:
|
2783 |
kbd_queue(s, 0x00, 0); |
2784 |
break;
|
2785 |
case KBD_CCMD_KBD_DISABLE:
|
2786 |
s->mode |= KBD_MODE_DISABLE_KBD; |
2787 |
break;
|
2788 |
case KBD_CCMD_KBD_ENABLE:
|
2789 |
s->mode &= ~KBD_MODE_DISABLE_KBD; |
2790 |
break;
|
2791 |
case KBD_CCMD_READ_INPORT:
|
2792 |
kbd_queue(s, 0x00, 0); |
2793 |
break;
|
2794 |
case KBD_CCMD_READ_OUTPORT:
|
2795 |
/* XXX: check that */
|
2796 |
val = 0x01 | (a20_enabled << 1); |
2797 |
if (s->status & KBD_STAT_OBF)
|
2798 |
val |= 0x10;
|
2799 |
if (s->status & KBD_STAT_MOUSE_OBF)
|
2800 |
val |= 0x20;
|
2801 |
kbd_queue(s, val, 0);
|
2802 |
break;
|
2803 |
case KBD_CCMD_ENABLE_A20:
|
2804 |
cpu_x86_set_a20(env, 1);
|
2805 |
break;
|
2806 |
case KBD_CCMD_DISABLE_A20:
|
2807 |
cpu_x86_set_a20(env, 0);
|
2808 |
break;
|
2809 |
case KBD_CCMD_RESET:
|
2810 |
reset_requested = 1;
|
2811 |
cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); |
2812 |
break;
|
2813 |
default:
|
2814 |
fprintf(stderr, "vl: unsupported keyboard cmd=0x%02x\n", val);
|
2815 |
break;
|
2816 |
} |
2817 |
} |
2818 |
|
2819 |
uint32_t kbd_read_data(CPUX86State *env, uint32_t addr) |
2820 |
{ |
2821 |
KBDState *s = &kbd_state; |
2822 |
KBDQueue *q; |
2823 |
int val;
|
2824 |
|
2825 |
q = &s->queues[0]; /* first check KBD data */ |
2826 |
if (q->count == 0) |
2827 |
q = &s->queues[1]; /* then check AUX data */ |
2828 |
if (q->count == 0) { |
2829 |
/* XXX: return something else ? */
|
2830 |
val = 0;
|
2831 |
} else {
|
2832 |
val = q->data[q->rptr]; |
2833 |
if (++q->rptr == KBD_QUEUE_SIZE)
|
2834 |
q->rptr = 0;
|
2835 |
q->count--; |
2836 |
/* reading deasserts IRQ */
|
2837 |
if (q == &s->queues[0]) |
2838 |
pic_set_irq(1, 0); |
2839 |
else
|
2840 |
pic_set_irq(12, 0); |
2841 |
} |
2842 |
/* reassert IRQs if data left */
|
2843 |
kbd_update_irq(s); |
2844 |
#ifdef DEBUG_KBD
|
2845 |
printf("kbd: read data=0x%02x\n", val);
|
2846 |
#endif
|
2847 |
return val;
|
2848 |
} |
2849 |
|
2850 |
static void kbd_reset_keyboard(KBDState *s) |
2851 |
{ |
2852 |
s->scan_enabled = 1;
|
2853 |
} |
2854 |
|
2855 |
static void kbd_write_keyboard(KBDState *s, int val) |
2856 |
{ |
2857 |
switch(s->kbd_write_cmd) {
|
2858 |
default:
|
2859 |
case -1: |
2860 |
switch(val) {
|
2861 |
case 0x00: |
2862 |
kbd_queue(s, KBD_REPLY_ACK, 0);
|
2863 |
break;
|
2864 |
case 0x05: |
2865 |
kbd_queue(s, KBD_REPLY_RESEND, 0);
|
2866 |
break;
|
2867 |
case KBD_CMD_ECHO:
|
2868 |
kbd_queue(s, KBD_CMD_ECHO, 0);
|
2869 |
break;
|
2870 |
case KBD_CMD_ENABLE:
|
2871 |
s->scan_enabled = 1;
|
2872 |
kbd_queue(s, KBD_REPLY_ACK, 0);
|
2873 |
break;
|
2874 |
case KBD_CMD_SET_LEDS:
|
2875 |
case KBD_CMD_SET_RATE:
|
2876 |
s->kbd_write_cmd = val; |
2877 |
kbd_queue(s, KBD_REPLY_ACK, 0);
|
2878 |
break;
|
2879 |
case KBD_CMD_RESET_DISABLE:
|
2880 |
kbd_reset_keyboard(s); |
2881 |
s->scan_enabled = 0;
|
2882 |
kbd_queue(s, KBD_REPLY_ACK, 0);
|
2883 |
break;
|
2884 |
case KBD_CMD_RESET_ENABLE:
|
2885 |
kbd_reset_keyboard(s); |
2886 |
s->scan_enabled = 1;
|
2887 |
kbd_queue(s, KBD_REPLY_ACK, 0);
|
2888 |
break;
|
2889 |
case KBD_CMD_RESET:
|
2890 |
kbd_reset_keyboard(s); |
2891 |
kbd_queue(s, KBD_REPLY_ACK, 0);
|
2892 |
kbd_queue(s, KBD_REPLY_POR, 0);
|
2893 |
break;
|
2894 |
default:
|
2895 |
kbd_queue(s, KBD_REPLY_ACK, 0);
|
2896 |
break;
|
2897 |
} |
2898 |
break;
|
2899 |
case KBD_CMD_SET_LEDS:
|
2900 |
kbd_queue(s, KBD_REPLY_ACK, 0);
|
2901 |
s->kbd_write_cmd = -1;
|
2902 |
break;
|
2903 |
case KBD_CMD_SET_RATE:
|
2904 |
kbd_queue(s, KBD_REPLY_ACK, 0);
|
2905 |
s->kbd_write_cmd = -1;
|
2906 |
break;
|
2907 |
} |
2908 |
} |
2909 |
|
2910 |
static void kbd_mouse_send_packet(KBDState *s) |
2911 |
{ |
2912 |
unsigned int b; |
2913 |
int dx1, dy1, dz1;
|
2914 |
|
2915 |
dx1 = s->mouse_dx; |
2916 |
dy1 = s->mouse_dy; |
2917 |
dz1 = s->mouse_dz; |
2918 |
/* XXX: increase range to 8 bits ? */
|
2919 |
if (dx1 > 127) |
2920 |
dx1 = 127;
|
2921 |
else if (dx1 < -127) |
2922 |
dx1 = -127;
|
2923 |
if (dy1 > 127) |
2924 |
dy1 = 127;
|
2925 |
else if (dy1 < -127) |
2926 |
dy1 = -127;
|
2927 |
b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07); |
2928 |
kbd_queue(s, b, 1);
|
2929 |
kbd_queue(s, dx1 & 0xff, 1); |
2930 |
kbd_queue(s, dy1 & 0xff, 1); |
2931 |
/* extra byte for IMPS/2 or IMEX */
|
2932 |
switch(s->mouse_type) {
|
2933 |
default:
|
2934 |
break;
|
2935 |
case 3: |
2936 |
if (dz1 > 127) |
2937 |
dz1 = 127;
|
2938 |
else if (dz1 < -127) |
2939 |
dz1 = -127;
|
2940 |
kbd_queue(s, dz1 & 0xff, 1); |
2941 |
break;
|
2942 |
case 4: |
2943 |
if (dz1 > 7) |
2944 |
dz1 = 7;
|
2945 |
else if (dz1 < -7) |
2946 |
dz1 = -7;
|
2947 |
b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1); |
2948 |
kbd_queue(s, b, 1);
|
2949 |
break;
|
2950 |
} |
2951 |
|
2952 |
/* update deltas */
|
2953 |
s->mouse_dx -= dx1; |
2954 |
s->mouse_dy -= dy1; |
2955 |
s->mouse_dz -= dz1; |
2956 |
} |
2957 |
|
2958 |
void kbd_mouse_event(int dx, int dy, int dz, int buttons_state) |
2959 |
{ |
2960 |
KBDState *s = &kbd_state; |
2961 |
|
2962 |
/* check if deltas are recorded when disabled */
|
2963 |
if (!(s->mouse_status & MOUSE_STATUS_ENABLED))
|
2964 |
return;
|
2965 |
|
2966 |
s->mouse_dx += dx; |
2967 |
s->mouse_dy -= dy; |
2968 |
s->mouse_dz += dz; |
2969 |
s->mouse_buttons = buttons_state; |
2970 |
|
2971 |
if (!(s->mouse_status & MOUSE_STATUS_REMOTE) &&
|
2972 |
(s->queues[1].count < (KBD_QUEUE_SIZE - 16))) { |
2973 |
for(;;) {
|
2974 |
/* if not remote, send event. Multiple events are sent if
|
2975 |
too big deltas */
|
2976 |
kbd_mouse_send_packet(s); |
2977 |
if (s->mouse_dx == 0 && s->mouse_dy == 0 && s->mouse_dz == 0) |
2978 |
break;
|
2979 |
} |
2980 |
} |
2981 |
} |
2982 |
|
2983 |
static void kbd_write_mouse(KBDState *s, int val) |
2984 |
{ |
2985 |
#ifdef DEBUG_MOUSE
|
2986 |
printf("kbd: write mouse 0x%02x\n", val);
|
2987 |
#endif
|
2988 |
switch(s->mouse_write_cmd) {
|
2989 |
default:
|
2990 |
case -1: |
2991 |
/* mouse command */
|
2992 |
if (s->mouse_wrap) {
|
2993 |
if (val == AUX_RESET_WRAP) {
|
2994 |
s->mouse_wrap = 0;
|
2995 |
kbd_queue(s, AUX_ACK, 1);
|
2996 |
return;
|
2997 |
} else if (val != AUX_RESET) { |
2998 |
kbd_queue(s, val, 1);
|
2999 |
return;
|
3000 |
} |
3001 |
} |
3002 |
switch(val) {
|
3003 |
case AUX_SET_SCALE11:
|
3004 |
s->mouse_status &= ~MOUSE_STATUS_SCALE21; |
3005 |
kbd_queue(s, AUX_ACK, 1);
|
3006 |
break;
|
3007 |
case AUX_SET_SCALE21:
|
3008 |
s->mouse_status |= MOUSE_STATUS_SCALE21; |
3009 |
kbd_queue(s, AUX_ACK, 1);
|
3010 |
break;
|
3011 |
case AUX_SET_STREAM:
|
3012 |
s->mouse_status &= ~MOUSE_STATUS_REMOTE; |
3013 |
kbd_queue(s, AUX_ACK, 1);
|
3014 |
break;
|
3015 |
case AUX_SET_WRAP:
|
3016 |
s->mouse_wrap = 1;
|
3017 |
kbd_queue(s, AUX_ACK, 1);
|
3018 |
break;
|
3019 |
case AUX_SET_REMOTE:
|
3020 |
s->mouse_status |= MOUSE_STATUS_REMOTE; |
3021 |
kbd_queue(s, AUX_ACK, 1);
|
3022 |
break;
|
3023 |
case AUX_GET_TYPE:
|
3024 |
kbd_queue(s, AUX_ACK, 1);
|
3025 |
kbd_queue(s, s->mouse_type, 1);
|
3026 |
break;
|
3027 |
case AUX_SET_RES:
|
3028 |
case AUX_SET_SAMPLE:
|
3029 |
s->mouse_write_cmd = val; |
3030 |
kbd_queue(s, AUX_ACK, 1);
|
3031 |
break;
|
3032 |
case AUX_GET_SCALE:
|
3033 |
kbd_queue(s, AUX_ACK, 1);
|
3034 |
kbd_queue(s, s->mouse_status, 1);
|
3035 |
kbd_queue(s, s->mouse_resolution, 1);
|
3036 |
kbd_queue(s, s->mouse_sample_rate, 1);
|
3037 |
break;
|
3038 |
case AUX_POLL:
|
3039 |
kbd_queue(s, AUX_ACK, 1);
|
3040 |
kbd_mouse_send_packet(s); |
3041 |
break;
|
3042 |
case AUX_ENABLE_DEV:
|
3043 |
s->mouse_status |= MOUSE_STATUS_ENABLED; |
3044 |
kbd_queue(s, AUX_ACK, 1);
|
3045 |
break;
|
3046 |
case AUX_DISABLE_DEV:
|
3047 |
s->mouse_status &= ~MOUSE_STATUS_ENABLED; |
3048 |
kbd_queue(s, AUX_ACK, 1);
|
3049 |
break;
|
3050 |
case AUX_SET_DEFAULT:
|
3051 |
s->mouse_sample_rate = 100;
|
3052 |
s->mouse_resolution = 2;
|
3053 |
s->mouse_status = 0;
|
3054 |
kbd_queue(s, AUX_ACK, 1);
|
3055 |
break;
|
3056 |
case AUX_RESET:
|
3057 |
s->mouse_sample_rate = 100;
|
3058 |
s->mouse_resolution = 2;
|
3059 |
s->mouse_status = 0;
|
3060 |
kbd_queue(s, AUX_ACK, 1);
|
3061 |
kbd_queue(s, 0xaa, 1); |
3062 |
kbd_queue(s, s->mouse_type, 1);
|
3063 |
break;
|
3064 |
default:
|
3065 |
break;
|
3066 |
} |
3067 |
break;
|
3068 |
case AUX_SET_SAMPLE:
|
3069 |
s->mouse_sample_rate = val; |
3070 |
#if 0
|
3071 |
/* detect IMPS/2 or IMEX */
|
3072 |
switch(s->mouse_detect_state) {
|
3073 |
default:
|
3074 |
case 0:
|
3075 |
if (val == 200)
|
3076 |
s->mouse_detect_state = 1;
|
3077 |
break;
|
3078 |
case 1:
|
3079 |
if (val == 100)
|
3080 |
s->mouse_detect_state = 2;
|
3081 |
else if (val == 200)
|
3082 |
s->mouse_detect_state = 3;
|
3083 |
else
|
3084 |
s->mouse_detect_state = 0;
|
3085 |
break;
|
3086 |
case 2:
|
3087 |
if (val == 80)
|
3088 |
s->mouse_type = 3; /* IMPS/2 */
|
3089 |
s->mouse_detect_state = 0;
|
3090 |
break;
|
3091 |
case 3:
|
3092 |
if (val == 80)
|
3093 |
s->mouse_type = 4; /* IMEX */
|
3094 |
s->mouse_detect_state = 0;
|
3095 |
break;
|
3096 |
}
|
3097 |
#endif
|
3098 |
kbd_queue(s, AUX_ACK, 1);
|
3099 |
s->mouse_write_cmd = -1;
|
3100 |
break;
|
3101 |
case AUX_SET_RES:
|
3102 |
s->mouse_resolution = val; |
3103 |
kbd_queue(s, AUX_ACK, 1);
|
3104 |
s->mouse_write_cmd = -1;
|
3105 |
break;
|
3106 |
} |
3107 |
} |
3108 |
|
3109 |
void kbd_write_data(CPUX86State *env, uint32_t addr, uint32_t val)
|
3110 |
{ |
3111 |
KBDState *s = &kbd_state; |
3112 |
|
3113 |
#ifdef DEBUG_KBD
|
3114 |
printf("kbd: write data=0x%02x\n", val);
|
3115 |
#endif
|
3116 |
|
3117 |
switch(s->write_cmd) {
|
3118 |
case 0: |
3119 |
kbd_write_keyboard(s, val); |
3120 |
break;
|
3121 |
case KBD_CCMD_WRITE_MODE:
|
3122 |
s->mode = val; |
3123 |
kbd_update_irq(s); |
3124 |
break;
|
3125 |
case KBD_CCMD_WRITE_OBUF:
|
3126 |
kbd_queue(s, val, 0);
|
3127 |
break;
|
3128 |
case KBD_CCMD_WRITE_AUX_OBUF:
|
3129 |
kbd_queue(s, val, 1);
|
3130 |
break;
|
3131 |
case KBD_CCMD_WRITE_OUTPORT:
|
3132 |
cpu_x86_set_a20(env, (val >> 1) & 1); |
3133 |
if (!(val & 1)) { |
3134 |
reset_requested = 1;
|
3135 |
cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); |
3136 |
} |
3137 |
break;
|
3138 |
case KBD_CCMD_WRITE_MOUSE:
|
3139 |
kbd_write_mouse(s, val); |
3140 |
break;
|
3141 |
default:
|
3142 |
break;
|
3143 |
} |
3144 |
s->write_cmd = 0;
|
3145 |
} |
3146 |
|
3147 |
void kbd_reset(KBDState *s)
|
3148 |
{ |
3149 |
KBDQueue *q; |
3150 |
int i;
|
3151 |
|
3152 |
s->kbd_write_cmd = -1;
|
3153 |
s->mouse_write_cmd = -1;
|
3154 |
s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT; |
3155 |
s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED; |
3156 |
for(i = 0; i < 2; i++) { |
3157 |
q = &s->queues[i]; |
3158 |
q->rptr = 0;
|
3159 |
q->wptr = 0;
|
3160 |
q->count = 0;
|
3161 |
} |
3162 |
} |
3163 |
|
3164 |
void kbd_init(void) |
3165 |
{ |
3166 |
kbd_reset(&kbd_state); |
3167 |
register_ioport_read(0x60, 1, kbd_read_data, 1); |
3168 |
register_ioport_write(0x60, 1, kbd_write_data, 1); |
3169 |
register_ioport_read(0x64, 1, kbd_read_status, 1); |
3170 |
register_ioport_write(0x64, 1, kbd_write_command, 1); |
3171 |
} |
3172 |
|
3173 |
/***********************************************************/
|
3174 |
/* Bochs BIOS debug ports */
|
3175 |
|
3176 |
void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
3177 |
{ |
3178 |
switch(addr) {
|
3179 |
/* Bochs BIOS messages */
|
3180 |
case 0x400: |
3181 |
case 0x401: |
3182 |
fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
|
3183 |
exit(1);
|
3184 |
case 0x402: |
3185 |
case 0x403: |
3186 |
#ifdef DEBUG_BIOS
|
3187 |
fprintf(stderr, "%c", val);
|
3188 |
#endif
|
3189 |
break;
|
3190 |
|
3191 |
/* LGPL'ed VGA BIOS messages */
|
3192 |
case 0x501: |
3193 |
case 0x502: |
3194 |
fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
3195 |
exit(1);
|
3196 |
case 0x500: |
3197 |
case 0x503: |
3198 |
#ifdef DEBUG_BIOS
|
3199 |
fprintf(stderr, "%c", val);
|
3200 |
#endif
|
3201 |
break;
|
3202 |
} |
3203 |
} |
3204 |
|
3205 |
void bochs_bios_init(void) |
3206 |
{ |
3207 |
register_ioport_write(0x400, 1, bochs_bios_write, 2); |
3208 |
register_ioport_write(0x401, 1, bochs_bios_write, 2); |
3209 |
register_ioport_write(0x402, 1, bochs_bios_write, 1); |
3210 |
register_ioport_write(0x403, 1, bochs_bios_write, 1); |
3211 |
|
3212 |
register_ioport_write(0x501, 1, bochs_bios_write, 2); |
3213 |
register_ioport_write(0x502, 1, bochs_bios_write, 2); |
3214 |
register_ioport_write(0x500, 1, bochs_bios_write, 1); |
3215 |
register_ioport_write(0x503, 1, bochs_bios_write, 1); |
3216 |
} |
3217 |
|
3218 |
/***********************************************************/
|
3219 |
/* dumb display */
|
3220 |
|
3221 |
/* init terminal so that we can grab keys */
|
3222 |
static struct termios oldtty; |
3223 |
|
3224 |
static void term_exit(void) |
3225 |
{ |
3226 |
tcsetattr (0, TCSANOW, &oldtty);
|
3227 |
} |
3228 |
|
3229 |
static void term_init(void) |
3230 |
{ |
3231 |
struct termios tty;
|
3232 |
|
3233 |
tcgetattr (0, &tty);
|
3234 |
oldtty = tty; |
3235 |
|
3236 |
tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP |
3237 |
|INLCR|IGNCR|ICRNL|IXON); |
3238 |
tty.c_oflag |= OPOST; |
3239 |
tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN); |
3240 |
/* if graphical mode, we allow Ctrl-C handling */
|
3241 |
if (nographic)
|
3242 |
tty.c_lflag &= ~ISIG; |
3243 |
tty.c_cflag &= ~(CSIZE|PARENB); |
3244 |
tty.c_cflag |= CS8; |
3245 |
tty.c_cc[VMIN] = 1;
|
3246 |
tty.c_cc[VTIME] = 0;
|
3247 |
|
3248 |
tcsetattr (0, TCSANOW, &tty);
|
3249 |
|
3250 |
atexit(term_exit); |
3251 |
|
3252 |
fcntl(0, F_SETFL, O_NONBLOCK);
|
3253 |
} |
3254 |
|
3255 |
static void dumb_update(DisplayState *ds, int x, int y, int w, int h) |
3256 |
{ |
3257 |
} |
3258 |
|
3259 |
static void dumb_resize(DisplayState *ds, int w, int h) |
3260 |
{ |
3261 |
} |
3262 |
|
3263 |
static void dumb_refresh(DisplayState *ds) |
3264 |
{ |
3265 |
vga_update_display(); |
3266 |
} |
3267 |
|
3268 |
void dumb_display_init(DisplayState *ds)
|
3269 |
{ |
3270 |
ds->data = NULL;
|
3271 |
ds->linesize = 0;
|
3272 |
ds->depth = 0;
|
3273 |
ds->dpy_update = dumb_update; |
3274 |
ds->dpy_resize = dumb_resize; |
3275 |
ds->dpy_refresh = dumb_refresh; |
3276 |
} |
3277 |
|
3278 |
#if !defined(CONFIG_SOFTMMU)
|
3279 |
/***********************************************************/
|
3280 |
/* cpu signal handler */
|
3281 |
static void host_segv_handler(int host_signum, siginfo_t *info, |
3282 |
void *puc)
|
3283 |
{ |
3284 |
if (cpu_signal_handler(host_signum, info, puc))
|
3285 |
return;
|
3286 |
term_exit(); |
3287 |
abort(); |
3288 |
} |
3289 |
#endif
|
3290 |
|
3291 |
static int timer_irq_pending; |
3292 |
static int timer_irq_count; |
3293 |
|
3294 |
static int timer_ms; |
3295 |
static int gui_refresh_pending, gui_refresh_count; |
3296 |
|
3297 |
static void host_alarm_handler(int host_signum, siginfo_t *info, |
3298 |
void *puc)
|
3299 |
{ |
3300 |
/* NOTE: since usually the OS asks a 100 Hz clock, there can be
|
3301 |
some drift between cpu_get_ticks() and the interrupt time. So
|
3302 |
we queue some interrupts to avoid missing some */
|
3303 |
timer_irq_count += pit_get_out_edges(&pit_channels[0]);
|
3304 |
if (timer_irq_count) {
|
3305 |
if (timer_irq_count > 2) |
3306 |
timer_irq_count = 2;
|
3307 |
timer_irq_count--; |
3308 |
timer_irq_pending = 1;
|
3309 |
} |
3310 |
gui_refresh_count += timer_ms; |
3311 |
if (gui_refresh_count >= GUI_REFRESH_INTERVAL) {
|
3312 |
gui_refresh_count = 0;
|
3313 |
gui_refresh_pending = 1;
|
3314 |
} |
3315 |
|
3316 |
if (gui_refresh_pending || timer_irq_pending) {
|
3317 |
/* just exit from the cpu to have a chance to handle timers */
|
3318 |
cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); |
3319 |
} |
3320 |
} |
3321 |
|
3322 |
#ifdef CONFIG_SOFTMMU
|
3323 |
void *get_mmap_addr(unsigned long size) |
3324 |
{ |
3325 |
return NULL; |
3326 |
} |
3327 |
#else
|
3328 |
unsigned long mmap_addr = PHYS_RAM_BASE; |
3329 |
|
3330 |
void *get_mmap_addr(unsigned long size) |
3331 |
{ |
3332 |
unsigned long addr; |
3333 |
addr = mmap_addr; |
3334 |
mmap_addr += ((size + 4095) & ~4095) + 4096; |
3335 |
return (void *)addr; |
3336 |
} |
3337 |
#endif
|
3338 |
|
3339 |
/* main execution loop */
|
3340 |
|
3341 |
CPUState *cpu_gdbstub_get_env(void *opaque)
|
3342 |
{ |
3343 |
return global_env;
|
3344 |
} |
3345 |
|
3346 |
int main_loop(void *opaque) |
3347 |
{ |
3348 |
struct pollfd ufds[3], *pf, *serial_ufd, *net_ufd, *gdb_ufd; |
3349 |
int ret, n, timeout, serial_ok;
|
3350 |
uint8_t ch; |
3351 |
CPUState *env = global_env; |
3352 |
|
3353 |
if (!term_inited) {
|
3354 |
/* initialize terminal only there so that the user has a
|
3355 |
chance to stop QEMU with Ctrl-C before the gdb connection
|
3356 |
is launched */
|
3357 |
term_inited = 1;
|
3358 |
term_init(); |
3359 |
} |
3360 |
|
3361 |
serial_ok = 1;
|
3362 |
cpu_enable_ticks(); |
3363 |
for(;;) {
|
3364 |
ret = cpu_x86_exec(env); |
3365 |
if (reset_requested) {
|
3366 |
ret = EXCP_INTERRUPT; |
3367 |
break;
|
3368 |
} |
3369 |
if (ret == EXCP_DEBUG) {
|
3370 |
ret = EXCP_DEBUG; |
3371 |
break;
|
3372 |
} |
3373 |
/* if hlt instruction, we wait until the next IRQ */
|
3374 |
if (ret == EXCP_HLT)
|
3375 |
timeout = 10;
|
3376 |
else
|
3377 |
timeout = 0;
|
3378 |
/* poll any events */
|
3379 |
serial_ufd = NULL;
|
3380 |
pf = ufds; |
3381 |
if (serial_ok && !(serial_ports[0].lsr & UART_LSR_DR)) { |
3382 |
serial_ufd = pf; |
3383 |
pf->fd = 0;
|
3384 |
pf->events = POLLIN; |
3385 |
pf++; |
3386 |
} |
3387 |
net_ufd = NULL;
|
3388 |
if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) { |
3389 |
net_ufd = pf; |
3390 |
pf->fd = net_fd; |
3391 |
pf->events = POLLIN; |
3392 |
pf++; |
3393 |
} |
3394 |
gdb_ufd = NULL;
|
3395 |
if (gdbstub_fd > 0) { |
3396 |
gdb_ufd = pf; |
3397 |
pf->fd = gdbstub_fd; |
3398 |
pf->events = POLLIN; |
3399 |
pf++; |
3400 |
} |
3401 |
|
3402 |
ret = poll(ufds, pf - ufds, timeout); |
3403 |
if (ret > 0) { |
3404 |
if (serial_ufd && (serial_ufd->revents & POLLIN)) {
|
3405 |
n = read(0, &ch, 1); |
3406 |
if (n == 1) { |
3407 |
serial_received_byte(&serial_ports[0], ch);
|
3408 |
} else {
|
3409 |
/* Closed, stop polling. */
|
3410 |
serial_ok = 0;
|
3411 |
} |
3412 |
} |
3413 |
if (net_ufd && (net_ufd->revents & POLLIN)) {
|
3414 |
uint8_t buf[MAX_ETH_FRAME_SIZE]; |
3415 |
|
3416 |
n = read(net_fd, buf, MAX_ETH_FRAME_SIZE); |
3417 |
if (n > 0) { |
3418 |
if (n < 60) { |
3419 |
memset(buf + n, 0, 60 - n); |
3420 |
n = 60;
|
3421 |
} |
3422 |
ne2000_receive(&ne2000_state, buf, n); |
3423 |
} |
3424 |
} |
3425 |
if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
|
3426 |
uint8_t buf[1];
|
3427 |
/* stop emulation if requested by gdb */
|
3428 |
n = read(gdbstub_fd, buf, 1);
|
3429 |
if (n == 1) { |
3430 |
ret = EXCP_INTERRUPT; |
3431 |
break;
|
3432 |
} |
3433 |
} |
3434 |
} |
3435 |
|
3436 |
/* timer IRQ */
|
3437 |
if (timer_irq_pending) {
|
3438 |
pic_set_irq(0, 1); |
3439 |
pic_set_irq(0, 0); |
3440 |
timer_irq_pending = 0;
|
3441 |
} |
3442 |
|
3443 |
/* VGA */
|
3444 |
if (gui_refresh_pending) {
|
3445 |
display_state.dpy_refresh(&display_state); |
3446 |
gui_refresh_pending = 0;
|
3447 |
} |
3448 |
} |
3449 |
cpu_disable_ticks(); |
3450 |
return ret;
|
3451 |
} |
3452 |
|
3453 |
void help(void) |
3454 |
{ |
3455 |
printf("QEMU PC emulator version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n" |
3456 |
"usage: %s [options] [disk_image]\n"
|
3457 |
"\n"
|
3458 |
"'disk_image' is a raw hard image image for IDE hard disk 0\n"
|
3459 |
"\n"
|
3460 |
"Standard options:\n"
|
3461 |
"-hda file use 'file' as IDE hard disk 0 image\n"
|
3462 |
"-hdb file use 'file' as IDE hard disk 1 image\n"
|
3463 |
"-snapshot write to temporary files instead of disk image files\n"
|
3464 |
"-m megs set virtual RAM size to megs MB\n"
|
3465 |
"-n script set network init script [default=%s]\n"
|
3466 |
"-tun-fd fd this fd talks to tap/tun, use it.\n"
|
3467 |
"-nographic disable graphical output\n"
|
3468 |
"\n"
|
3469 |
"Linux boot specific (does not require PC BIOS):\n"
|
3470 |
"-kernel bzImage use 'bzImage' as kernel image\n"
|
3471 |
"-append cmdline use 'cmdline' as kernel command line\n"
|
3472 |
"-initrd file use 'file' as initial ram disk\n"
|
3473 |
"\n"
|
3474 |
"Debug/Expert options:\n"
|
3475 |
"-s wait gdb connection to port %d\n"
|
3476 |
"-p port change gdb connection port\n"
|
3477 |
"-d output log in /tmp/vl.log\n"
|
3478 |
"-hdachs c,h,s force hard disk 0 geometry (usually qemu can guess it)\n"
|
3479 |
"-L path set the directory for the BIOS and VGA BIOS\n"
|
3480 |
"\n"
|
3481 |
"During emulation, use C-a h to get terminal commands:\n",
|
3482 |
#ifdef CONFIG_SOFTMMU
|
3483 |
"qemu",
|
3484 |
#else
|
3485 |
"qemu-fast",
|
3486 |
#endif
|
3487 |
DEFAULT_NETWORK_SCRIPT, |
3488 |
DEFAULT_GDBSTUB_PORT); |
3489 |
term_print_help(); |
3490 |
#ifndef CONFIG_SOFTMMU
|
3491 |
printf("\n"
|
3492 |
"NOTE: this version of QEMU is faster but it needs slightly patched OSes to\n"
|
3493 |
"work. Please use the 'qemu' executable to have a more accurate (but slower)\n"
|
3494 |
"PC emulation.\n");
|
3495 |
#endif
|
3496 |
exit(1);
|
3497 |
} |
3498 |
|
3499 |
struct option long_options[] = {
|
3500 |
{ "initrd", 1, NULL, 0, }, |
3501 |
{ "hda", 1, NULL, 0, }, |
3502 |
{ "hdb", 1, NULL, 0, }, |
3503 |
{ "snapshot", 0, NULL, 0, }, |
3504 |
{ "hdachs", 1, NULL, 0, }, |
3505 |
{ "nographic", 0, NULL, 0, }, |
3506 |
{ "kernel", 1, NULL, 0, }, |
3507 |
{ "append", 1, NULL, 0, }, |
3508 |
{ "tun-fd", 1, NULL, 0, }, |
3509 |
{ NULL, 0, NULL, 0 }, |
3510 |
}; |
3511 |
|
3512 |
#ifdef CONFIG_SDL
|
3513 |
/* SDL use the pthreads and they modify sigaction. We don't
|
3514 |
want that. */
|
3515 |
#if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3) |
3516 |
extern void __libc_sigaction(); |
3517 |
#define sigaction(sig, act, oact) __libc_sigaction(sig, act, oact)
|
3518 |
#else
|
3519 |
extern void __sigaction(); |
3520 |
#define sigaction(sig, act, oact) __sigaction(sig, act, oact)
|
3521 |
#endif
|
3522 |
#endif /* CONFIG_SDL */ |
3523 |
|
3524 |
int main(int argc, char **argv) |
3525 |
{ |
3526 |
int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
|
3527 |
int snapshot, linux_boot, total_ram_size;
|
3528 |
struct linux_params *params;
|
3529 |
struct sigaction act;
|
3530 |
struct itimerval itv;
|
3531 |
CPUX86State *env; |
3532 |
const char *initrd_filename; |
3533 |
const char *hd_filename[MAX_DISKS]; |
3534 |
const char *kernel_filename, *kernel_cmdline; |
3535 |
DisplayState *ds = &display_state; |
3536 |
|
3537 |
/* we never want that malloc() uses mmap() */
|
3538 |
mallopt(M_MMAP_THRESHOLD, 4096 * 1024); |
3539 |
initrd_filename = NULL;
|
3540 |
for(i = 0; i < MAX_DISKS; i++) |
3541 |
hd_filename[i] = NULL;
|
3542 |
phys_ram_size = 32 * 1024 * 1024; |
3543 |
vga_ram_size = VGA_RAM_SIZE; |
3544 |
pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
|
3545 |
use_gdbstub = 0;
|
3546 |
gdbstub_port = DEFAULT_GDBSTUB_PORT; |
3547 |
snapshot = 0;
|
3548 |
nographic = 0;
|
3549 |
kernel_filename = NULL;
|
3550 |
kernel_cmdline = "";
|
3551 |
for(;;) {
|
3552 |
c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index);
|
3553 |
if (c == -1) |
3554 |
break;
|
3555 |
switch(c) {
|
3556 |
case 0: |
3557 |
switch(long_index) {
|
3558 |
case 0: |
3559 |
initrd_filename = optarg; |
3560 |
break;
|
3561 |
case 1: |
3562 |
hd_filename[0] = optarg;
|
3563 |
break;
|
3564 |
case 2: |
3565 |
hd_filename[1] = optarg;
|
3566 |
break;
|
3567 |
case 3: |
3568 |
snapshot = 1;
|
3569 |
break;
|
3570 |
case 4: |
3571 |
{ |
3572 |
int cyls, heads, secs;
|
3573 |
const char *p; |
3574 |
p = optarg; |
3575 |
cyls = strtol(p, (char **)&p, 0); |
3576 |
if (*p != ',') |
3577 |
goto chs_fail;
|
3578 |
p++; |
3579 |
heads = strtol(p, (char **)&p, 0); |
3580 |
if (*p != ',') |
3581 |
goto chs_fail;
|
3582 |
p++; |
3583 |
secs = strtol(p, (char **)&p, 0); |
3584 |
if (*p != '\0') |
3585 |
goto chs_fail;
|
3586 |
ide_state[0].cylinders = cyls;
|
3587 |
ide_state[0].heads = heads;
|
3588 |
ide_state[0].sectors = secs;
|
3589 |
chs_fail: ;
|
3590 |
} |
3591 |
break;
|
3592 |
case 5: |
3593 |
nographic = 1;
|
3594 |
break;
|
3595 |
case 6: |
3596 |
kernel_filename = optarg; |
3597 |
break;
|
3598 |
case 7: |
3599 |
kernel_cmdline = optarg; |
3600 |
break;
|
3601 |
case 8: |
3602 |
net_fd = atoi(optarg); |
3603 |
break;
|
3604 |
} |
3605 |
break;
|
3606 |
case 'h': |
3607 |
help(); |
3608 |
break;
|
3609 |
case 'm': |
3610 |
phys_ram_size = atoi(optarg) * 1024 * 1024; |
3611 |
if (phys_ram_size <= 0) |
3612 |
help(); |
3613 |
if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
|
3614 |
fprintf(stderr, "vl: at most %d MB RAM can be simulated\n",
|
3615 |
PHYS_RAM_MAX_SIZE / (1024 * 1024)); |
3616 |
exit(1);
|
3617 |
} |
3618 |
break;
|
3619 |
case 'd': |
3620 |
cpu_set_log(CPU_LOG_ALL); |
3621 |
break;
|
3622 |
case 'n': |
3623 |
pstrcpy(network_script, sizeof(network_script), optarg);
|
3624 |
break;
|
3625 |
case 's': |
3626 |
use_gdbstub = 1;
|
3627 |
break;
|
3628 |
case 'p': |
3629 |
gdbstub_port = atoi(optarg); |
3630 |
break;
|
3631 |
case 'L': |
3632 |
bios_dir = optarg; |
3633 |
break;
|
3634 |
} |
3635 |
} |
3636 |
|
3637 |
if (optind < argc) {
|
3638 |
hd_filename[0] = argv[optind++];
|
3639 |
} |
3640 |
|
3641 |
linux_boot = (kernel_filename != NULL);
|
3642 |
|
3643 |
if (!linux_boot && hd_filename[0] == '\0') |
3644 |
help(); |
3645 |
|
3646 |
/* init debug */
|
3647 |
setvbuf(stdout, NULL, _IOLBF, 0); |
3648 |
|
3649 |
/* init network tun interface */
|
3650 |
if (net_fd < 0) |
3651 |
net_init(); |
3652 |
|
3653 |
/* init the memory */
|
3654 |
total_ram_size = phys_ram_size + vga_ram_size; |
3655 |
|
3656 |
#ifdef CONFIG_SOFTMMU
|
3657 |
phys_ram_base = malloc(total_ram_size); |
3658 |
if (!phys_ram_base) {
|
3659 |
fprintf(stderr, "Could not allocate physical memory\n");
|
3660 |
exit(1);
|
3661 |
} |
3662 |
#else
|
3663 |
/* as we must map the same page at several addresses, we must use
|
3664 |
a fd */
|
3665 |
{ |
3666 |
const char *tmpdir; |
3667 |
|
3668 |
tmpdir = getenv("QEMU_TMPDIR");
|
3669 |
if (!tmpdir)
|
3670 |
tmpdir = "/tmp";
|
3671 |
snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir); |
3672 |
if (mkstemp(phys_ram_file) < 0) { |
3673 |
fprintf(stderr, "Could not create temporary memory file '%s'\n",
|
3674 |
phys_ram_file); |
3675 |
exit(1);
|
3676 |
} |
3677 |
phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
|
3678 |
if (phys_ram_fd < 0) { |
3679 |
fprintf(stderr, "Could not open temporary memory file '%s'\n",
|
3680 |
phys_ram_file); |
3681 |
exit(1);
|
3682 |
} |
3683 |
ftruncate(phys_ram_fd, total_ram_size); |
3684 |
unlink(phys_ram_file); |
3685 |
phys_ram_base = mmap(get_mmap_addr(total_ram_size), |
3686 |
total_ram_size, |
3687 |
PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED, |
3688 |
phys_ram_fd, 0);
|
3689 |
if (phys_ram_base == MAP_FAILED) {
|
3690 |
fprintf(stderr, "Could not map physical memory\n");
|
3691 |
exit(1);
|
3692 |
} |
3693 |
} |
3694 |
#endif
|
3695 |
|
3696 |
/* open the virtual block devices */
|
3697 |
for(i = 0; i < MAX_DISKS; i++) { |
3698 |
if (hd_filename[i]) {
|
3699 |
bs_table[i] = bdrv_open(hd_filename[i], snapshot); |
3700 |
if (!bs_table[i]) {
|
3701 |
fprintf(stderr, "vl: could not open hard disk image '%s\n",
|
3702 |
hd_filename[i]); |
3703 |
exit(1);
|
3704 |
} |
3705 |
} |
3706 |
} |
3707 |
|
3708 |
/* init CPU state */
|
3709 |
env = cpu_init(); |
3710 |
global_env = env; |
3711 |
cpu_single_env = env; |
3712 |
|
3713 |
init_ioports(); |
3714 |
|
3715 |
/* allocate RAM */
|
3716 |
cpu_register_physical_memory(0, phys_ram_size, 0); |
3717 |
|
3718 |
if (linux_boot) {
|
3719 |
/* now we can load the kernel */
|
3720 |
ret = load_kernel(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
3721 |
if (ret < 0) { |
3722 |
fprintf(stderr, "vl: could not load kernel '%s'\n",
|
3723 |
kernel_filename); |
3724 |
exit(1);
|
3725 |
} |
3726 |
|
3727 |
/* load initrd */
|
3728 |
initrd_size = 0;
|
3729 |
if (initrd_filename) {
|
3730 |
initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
3731 |
if (initrd_size < 0) { |
3732 |
fprintf(stderr, "vl: could not load initial ram disk '%s'\n",
|
3733 |
initrd_filename); |
3734 |
exit(1);
|
3735 |
} |
3736 |
} |
3737 |
|
3738 |
/* init kernel params */
|
3739 |
params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
|
3740 |
memset(params, 0, sizeof(struct linux_params)); |
3741 |
params->mount_root_rdonly = 0;
|
3742 |
stw_raw(¶ms->cl_magic, 0xA33F);
|
3743 |
stw_raw(¶ms->cl_offset, params->commandline - (uint8_t *)params); |
3744 |
stl_raw(¶ms->alt_mem_k, (phys_ram_size / 1024) - 1024); |
3745 |
pstrcat(params->commandline, sizeof(params->commandline), kernel_cmdline);
|
3746 |
params->loader_type = 0x01;
|
3747 |
if (initrd_size > 0) { |
3748 |
stl_raw(¶ms->initrd_start, INITRD_LOAD_ADDR); |
3749 |
stl_raw(¶ms->initrd_size, initrd_size); |
3750 |
} |
3751 |
params->orig_video_lines = 25;
|
3752 |
params->orig_video_cols = 80;
|
3753 |
|
3754 |
/* setup basic memory access */
|
3755 |
env->cr[0] = 0x00000033; |
3756 |
cpu_x86_init_mmu(env); |
3757 |
|
3758 |
memset(params->idt_table, 0, sizeof(params->idt_table)); |
3759 |
|
3760 |
stq_raw(¶ms->gdt_table[2], 0x00cf9a000000ffffLL); /* KERNEL_CS */ |
3761 |
stq_raw(¶ms->gdt_table[3], 0x00cf92000000ffffLL); /* KERNEL_DS */ |
3762 |
/* for newer kernels (2.6.0) CS/DS are at different addresses */
|
3763 |
stq_raw(¶ms->gdt_table[12], 0x00cf9a000000ffffLL); /* KERNEL_CS */ |
3764 |
stq_raw(¶ms->gdt_table[13], 0x00cf92000000ffffLL); /* KERNEL_DS */ |
3765 |
|
3766 |
env->idt.base = (void *)((uint8_t *)params->idt_table - phys_ram_base);
|
3767 |
env->idt.limit = sizeof(params->idt_table) - 1; |
3768 |
env->gdt.base = (void *)((uint8_t *)params->gdt_table - phys_ram_base);
|
3769 |
env->gdt.limit = sizeof(params->gdt_table) - 1; |
3770 |
|
3771 |
cpu_x86_load_seg_cache(env, R_CS, KERNEL_CS, NULL, 0xffffffff, 0x00cf9a00); |
3772 |
cpu_x86_load_seg_cache(env, R_DS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); |
3773 |
cpu_x86_load_seg_cache(env, R_ES, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); |
3774 |
cpu_x86_load_seg_cache(env, R_SS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); |
3775 |
cpu_x86_load_seg_cache(env, R_FS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); |
3776 |
cpu_x86_load_seg_cache(env, R_GS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); |
3777 |
|
3778 |
env->eip = KERNEL_LOAD_ADDR; |
3779 |
env->regs[R_ESI] = KERNEL_PARAMS_ADDR; |
3780 |
env->eflags = 0x2;
|
3781 |
|
3782 |
} else {
|
3783 |
char buf[1024]; |
3784 |
|
3785 |
/* RAW PC boot */
|
3786 |
|
3787 |
/* BIOS load */
|
3788 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
3789 |
ret = load_image(buf, phys_ram_base + 0x000f0000);
|
3790 |
if (ret != 0x10000) { |
3791 |
fprintf(stderr, "vl: could not load PC bios '%s'\n", buf);
|
3792 |
exit(1);
|
3793 |
} |
3794 |
|
3795 |
/* VGA BIOS load */
|
3796 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
3797 |
ret = load_image(buf, phys_ram_base + 0x000c0000);
|
3798 |
|
3799 |
/* setup basic memory access */
|
3800 |
env->cr[0] = 0x60000010; |
3801 |
cpu_x86_init_mmu(env); |
3802 |
|
3803 |
env->idt.limit = 0xffff;
|
3804 |
env->gdt.limit = 0xffff;
|
3805 |
env->ldt.limit = 0xffff;
|
3806 |
|
3807 |
/* not correct (CS base=0xffff0000) */
|
3808 |
cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0); |
3809 |
cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0); |
3810 |
cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0); |
3811 |
cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0); |
3812 |
cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0); |
3813 |
cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0); |
3814 |
|
3815 |
env->eip = 0xfff0;
|
3816 |
env->regs[R_EDX] = 0x600; /* indicate P6 processor */ |
3817 |
|
3818 |
env->eflags = 0x2;
|
3819 |
|
3820 |
bochs_bios_init(); |
3821 |
} |
3822 |
|
3823 |
/* terminal init */
|
3824 |
if (nographic) {
|
3825 |
dumb_display_init(ds); |
3826 |
} else {
|
3827 |
#ifdef CONFIG_SDL
|
3828 |
sdl_display_init(ds); |
3829 |
#else
|
3830 |
dumb_display_init(ds); |
3831 |
#endif
|
3832 |
} |
3833 |
/* init basic PC hardware */
|
3834 |
register_ioport_write(0x80, 1, ioport80_write, 1); |
3835 |
|
3836 |
vga_init(ds, phys_ram_base + phys_ram_size, phys_ram_size, |
3837 |
vga_ram_size); |
3838 |
cmos_init(); |
3839 |
pic_init(); |
3840 |
pit_init(); |
3841 |
serial_init(); |
3842 |
ne2000_init(); |
3843 |
ide_init(); |
3844 |
kbd_init(); |
3845 |
|
3846 |
/* setup cpu signal handlers for MMU / self modifying code handling */
|
3847 |
sigfillset(&act.sa_mask); |
3848 |
act.sa_flags = SA_SIGINFO; |
3849 |
#if !defined(CONFIG_SOFTMMU)
|
3850 |
act.sa_sigaction = host_segv_handler; |
3851 |
sigaction(SIGSEGV, &act, NULL);
|
3852 |
sigaction(SIGBUS, &act, NULL);
|
3853 |
#endif
|
3854 |
|
3855 |
act.sa_sigaction = host_alarm_handler; |
3856 |
sigaction(SIGALRM, &act, NULL);
|
3857 |
|
3858 |
itv.it_interval.tv_sec = 0;
|
3859 |
itv.it_interval.tv_usec = 1000;
|
3860 |
itv.it_value.tv_sec = 0;
|
3861 |
itv.it_value.tv_usec = 10 * 1000; |
3862 |
setitimer(ITIMER_REAL, &itv, NULL);
|
3863 |
/* we probe the tick duration of the kernel to inform the user if
|
3864 |
the emulated kernel requested a too high timer frequency */
|
3865 |
getitimer(ITIMER_REAL, &itv); |
3866 |
timer_ms = itv.it_interval.tv_usec / 1000;
|
3867 |
pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) / |
3868 |
1000000;
|
3869 |
|
3870 |
if (use_gdbstub) {
|
3871 |
cpu_gdbstub(NULL, main_loop, gdbstub_port);
|
3872 |
} else {
|
3873 |
main_loop(NULL);
|
3874 |
} |
3875 |
return 0; |
3876 |
} |