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/*
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 *  CRIS helper routines
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 *
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 *  Copyright (c) 2007 AXIS Communications
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 *  Written by Edgar E. Iglesias
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "exec.h"
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#include "mmu.h"
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#include "helper.h"
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#include "host-utils.h"
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//#define CRIS_OP_HELPER_DEBUG
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#ifdef CRIS_OP_HELPER_DEBUG
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#define D(x) x
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#define D_LOG(...) qemu_log(__VA__ARGS__)
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#else
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#define D(x)
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#define D_LOG(...) do { } while (0)
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#endif
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#if !defined(CONFIG_USER_ONLY)
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#define MMUSUFFIX _mmu
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#define SHIFT 0
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#include "softmmu_template.h"
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#define SHIFT 1
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#include "softmmu_template.h"
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#define SHIFT 2
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#include "softmmu_template.h"
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#define SHIFT 3
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#include "softmmu_template.h"
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/* Try to fill the TLB and return an exception if error. If retaddr is
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   NULL, it means that the function was called in C code (i.e. not
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   from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
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{
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    TranslationBlock *tb;
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    CPUState *saved_env;
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    unsigned long pc;
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    int ret;
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    /* XXX: hack to restore env in all cases, even if not called from
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       generated code */
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    saved_env = env;
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    env = cpu_single_env;
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    D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__, 
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             env->pc, env->debug1, retaddr);
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    ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
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    if (unlikely(ret)) {
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        if (retaddr) {
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            /* now we have a real cpu fault */
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            pc = (unsigned long)retaddr;
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            tb = tb_find_pc(pc);
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            if (tb) {
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                /* the PC is inside the translated code. It means that we have
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                   a virtual CPU fault */
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                cpu_restore_state(tb, env, pc);
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                /* Evaluate flags after retranslation.  */
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                helper_top_evaluate_flags();
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            }
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        }
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        cpu_loop_exit();
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    }
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    env = saved_env;
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}
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#endif
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void helper_raise_exception(uint32_t index)
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{
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        env->exception_index = index;
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        cpu_loop_exit();
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}
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void helper_tlb_flush_pid(uint32_t pid)
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{
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#if !defined(CONFIG_USER_ONLY)
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        pid &= 0xff;
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        if (pid != (env->pregs[PR_PID] & 0xff))
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                cris_mmu_flush_pid(env, env->pregs[PR_PID]);
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#endif
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}
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void helper_spc_write(uint32_t new_spc)
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{
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#if !defined(CONFIG_USER_ONLY)
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        tlb_flush_page(env, env->pregs[PR_SPC]);
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        tlb_flush_page(env, new_spc);
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#endif
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}
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void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
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{
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        qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
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}
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/* Used by the tlb decoder.  */
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#define EXTRACT_FIELD(src, start, end) \
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            (((src) >> start) & ((1 << (end - start + 1)) - 1))
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void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
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{
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        uint32_t srs;
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        srs = env->pregs[PR_SRS];
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        srs &= 3;
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        env->sregs[srs][sreg] = env->regs[reg];
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#if !defined(CONFIG_USER_ONLY)
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        if (srs == 1 || srs == 2) {
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                if (sreg == 6) {
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                        /* Writes to tlb-hi write to mm_cause as a side 
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                           effect.  */
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                        env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
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                        env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
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                }
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                else if (sreg == 5) {
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                        uint32_t set;
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                        uint32_t idx;
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                        uint32_t lo, hi;
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                        uint32_t vaddr;
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                        int tlb_v;
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                        idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
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                        set >>= 4;
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                        set &= 3;
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                        idx &= 15;
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                        /* We've just made a write to tlb_lo.  */
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                        lo = env->sregs[SFR_RW_MM_TLB_LO];
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                        /* Writes are done via r_mm_cause.  */
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                        hi = env->sregs[SFR_R_MM_CAUSE];
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                        vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
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                                              13, 31);
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                        vaddr <<= TARGET_PAGE_BITS;
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                        tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
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                                            3, 3);
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                        env->tlbsets[srs - 1][set][idx].lo = lo;
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                        env->tlbsets[srs - 1][set][idx].hi = hi;
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                        D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", 
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                                  vaddr, tlb_v, env->pc);
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                        if (tlb_v) {
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                                tlb_flush_page(env, vaddr);
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                        }
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                }
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        }
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#endif
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}
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void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
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{
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        uint32_t srs;
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        env->pregs[PR_SRS] &= 3;
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        srs = env->pregs[PR_SRS];
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#if !defined(CONFIG_USER_ONLY)
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        if (srs == 1 || srs == 2)
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        {
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                uint32_t set;
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                uint32_t idx;
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                uint32_t lo, hi;
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                idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
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                set >>= 4;
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                set &= 3;
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                idx &= 15;
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                /* Update the mirror regs.  */
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                hi = env->tlbsets[srs - 1][set][idx].hi;
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                lo = env->tlbsets[srs - 1][set][idx].lo;
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                env->sregs[SFR_RW_MM_TLB_HI] = hi;
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                env->sregs[SFR_RW_MM_TLB_LO] = lo;
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        }
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#endif
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        env->regs[reg] = env->sregs[srs][sreg];
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}
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static void cris_ccs_rshift(CPUState *env)
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{
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        uint32_t ccs;
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        /* Apply the ccs shift.  */
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        ccs = env->pregs[PR_CCS];
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        ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
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        if (ccs & U_FLAG)
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        {
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                /* Enter user mode.  */
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                env->ksp = env->regs[R_SP];
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                env->regs[R_SP] = env->pregs[PR_USP];
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        }
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        env->pregs[PR_CCS] = ccs;
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}
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void helper_rfe(void)
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{
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        int rflag = env->pregs[PR_CCS] & R_FLAG;
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        D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n", 
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                 env->pregs[PR_ERP], env->pregs[PR_PID],
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                 env->pregs[PR_CCS],
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                 env->btarget);
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        cris_ccs_rshift(env);
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        /* RFE sets the P_FLAG only if the R_FLAG is not set.  */
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        if (!rflag)
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                env->pregs[PR_CCS] |= P_FLAG;
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}
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void helper_rfn(void)
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{
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        int rflag = env->pregs[PR_CCS] & R_FLAG;
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        D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n", 
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                 env->pregs[PR_ERP], env->pregs[PR_PID],
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                 env->pregs[PR_CCS],
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                 env->btarget);
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        cris_ccs_rshift(env);
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        /* Set the P_FLAG only if the R_FLAG is not set.  */
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        if (!rflag)
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                env->pregs[PR_CCS] |= P_FLAG;
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    /* Always set the M flag.  */
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    env->pregs[PR_CCS] |= M_FLAG;
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}
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uint32_t helper_lz(uint32_t t0)
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{
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        return clz32(t0);
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}
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uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
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{
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        /* FIXME: clean this up.  */
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        /* des ref:
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           The N flag is set according to the selected bit in the dest reg.
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           The Z flag is set if the selected bit and all bits to the right are
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           zero.
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           The X flag is cleared.
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           Other flags are left untouched.
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           The destination reg is not affected.*/
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        unsigned int fz, sbit, bset, mask, masked_t0;
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        sbit = t1 & 31;
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        bset = !!(t0 & (1 << sbit));
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        mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
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        masked_t0 = t0 & mask;
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        fz = !(masked_t0 | bset);
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        /* Clear the X, N and Z flags.  */
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        ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
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        if (env->pregs[PR_VR] < 32)
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                ccs &= ~(V_FLAG | C_FLAG);
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        /* Set the N and Z flags accordingly.  */
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        ccs |= (bset << 3) | (fz << 2);
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        return ccs;
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}
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static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
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{
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        unsigned int x, z, mask;
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        /* Extended arithmetics, leave the z flag alone.  */
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        x = env->cc_x;
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        mask = env->cc_mask | X_FLAG;
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        if (x) {
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                z = flags & Z_FLAG;
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                mask = mask & ~z;
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        }
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        flags &= mask;
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        /* all insn clear the x-flag except setf or clrf.  */
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        ccs &= ~mask;
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        ccs |= flags;
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        return ccs;
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}
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uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
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{
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        uint32_t flags = 0;
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        int64_t tmp;
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        int dneg;
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        dneg = ((int32_t)res) < 0;
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        tmp = mof;
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        tmp <<= 32;
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        tmp |= res;
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        if (tmp == 0)
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                flags |= Z_FLAG;
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        else if (tmp < 0)
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                flags |= N_FLAG;
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        if ((dneg && mof != -1)
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            || (!dneg && mof != 0))
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                flags |= V_FLAG;
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        return evaluate_flags_writeback(flags, ccs);
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}
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uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
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{
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        uint32_t flags = 0;
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        uint64_t tmp;
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        tmp = mof;
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        tmp <<= 32;
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        tmp |= res;
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        if (tmp == 0)
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                flags |= Z_FLAG;
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        else if (tmp >> 63)
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                flags |= N_FLAG;
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        if (mof)
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                flags |= V_FLAG;
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        return evaluate_flags_writeback(flags, ccs);
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}
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uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
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                                   uint32_t src, uint32_t dst, uint32_t res)
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{
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        uint32_t flags = 0;
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        src = src & 0x80000000;
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        dst = dst & 0x80000000;
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        if ((res & 0x80000000L) != 0L)
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        {
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                flags |= N_FLAG;
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                if (!src && !dst)
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                        flags |= V_FLAG;
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                else if (src & dst)
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                        flags |= R_FLAG;
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        }
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        else
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        {
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                if (res == 0L)
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                        flags |= Z_FLAG;
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                if (src & dst) 
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                        flags |= V_FLAG;
368 a8cf66bb edgar_igl
                if (dst | src) 
369 b41f7df0 edgar_igl
                        flags |= R_FLAG;
370 b41f7df0 edgar_igl
        }
371 b41f7df0 edgar_igl
372 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
373 b41f7df0 edgar_igl
}
374 b41f7df0 edgar_igl
375 6231868b edgar_igl
uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
376 6231868b edgar_igl
                                     uint32_t src, uint32_t dst, uint32_t res)
377 b41f7df0 edgar_igl
{
378 b41f7df0 edgar_igl
        uint32_t flags = 0;
379 b41f7df0 edgar_igl
380 6231868b edgar_igl
        src = src & 0x80000000;
381 6231868b edgar_igl
        dst = dst & 0x80000000;
382 30abcfc7 edgar_igl
383 a8cf66bb edgar_igl
        if ((res & 0x80000000L) != 0L)
384 30abcfc7 edgar_igl
        {
385 a8cf66bb edgar_igl
                flags |= N_FLAG;
386 a8cf66bb edgar_igl
                if (!src && !dst)
387 a8cf66bb edgar_igl
                        flags |= V_FLAG;
388 a8cf66bb edgar_igl
                else if (src & dst)
389 a8cf66bb edgar_igl
                        flags |= C_FLAG;
390 a8cf66bb edgar_igl
        }
391 a8cf66bb edgar_igl
        else
392 a8cf66bb edgar_igl
        {
393 a8cf66bb edgar_igl
                if (res == 0L)
394 a8cf66bb edgar_igl
                        flags |= Z_FLAG;
395 a8cf66bb edgar_igl
                if (src & dst) 
396 a8cf66bb edgar_igl
                        flags |= V_FLAG;
397 a8cf66bb edgar_igl
                if (dst | src) 
398 a8cf66bb edgar_igl
                        flags |= C_FLAG;
399 30abcfc7 edgar_igl
        }
400 30abcfc7 edgar_igl
401 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
402 a8cf66bb edgar_igl
}
403 a8cf66bb edgar_igl
404 6231868b edgar_igl
uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
405 6231868b edgar_igl
                                     uint32_t src, uint32_t dst, uint32_t res)
406 a8cf66bb edgar_igl
{
407 a8cf66bb edgar_igl
        uint32_t flags = 0;
408 a8cf66bb edgar_igl
409 6231868b edgar_igl
        src = (~src) & 0x80000000;
410 6231868b edgar_igl
        dst = dst & 0x80000000;
411 b41f7df0 edgar_igl
412 b41f7df0 edgar_igl
        if ((res & 0x80000000L) != 0L)
413 b41f7df0 edgar_igl
        {
414 b41f7df0 edgar_igl
                flags |= N_FLAG;
415 a8cf66bb edgar_igl
                if (!src && !dst)
416 b41f7df0 edgar_igl
                        flags |= V_FLAG;
417 a8cf66bb edgar_igl
                else if (src & dst)
418 b41f7df0 edgar_igl
                        flags |= C_FLAG;
419 b41f7df0 edgar_igl
        }
420 b41f7df0 edgar_igl
        else
421 b41f7df0 edgar_igl
        {
422 b41f7df0 edgar_igl
                if (res == 0L)
423 b41f7df0 edgar_igl
                        flags |= Z_FLAG;
424 a8cf66bb edgar_igl
                if (src & dst) 
425 b41f7df0 edgar_igl
                        flags |= V_FLAG;
426 a8cf66bb edgar_igl
                if (dst | src) 
427 b41f7df0 edgar_igl
                        flags |= C_FLAG;
428 b41f7df0 edgar_igl
        }
429 b41f7df0 edgar_igl
430 a8cf66bb edgar_igl
        flags ^= C_FLAG;
431 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
432 b41f7df0 edgar_igl
}
433 b41f7df0 edgar_igl
434 6231868b edgar_igl
uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
435 b41f7df0 edgar_igl
{
436 b41f7df0 edgar_igl
        uint32_t flags = 0;
437 b41f7df0 edgar_igl
438 b41f7df0 edgar_igl
        if ((int32_t)res < 0)
439 b41f7df0 edgar_igl
                flags |= N_FLAG;
440 b41f7df0 edgar_igl
        else if (res == 0L)
441 b41f7df0 edgar_igl
                flags |= Z_FLAG;
442 b41f7df0 edgar_igl
443 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
444 b41f7df0 edgar_igl
}
445 6231868b edgar_igl
uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
446 b41f7df0 edgar_igl
{
447 b41f7df0 edgar_igl
        uint32_t flags = 0;
448 b41f7df0 edgar_igl
449 b41f7df0 edgar_igl
        if ((int16_t)res < 0L)
450 b41f7df0 edgar_igl
                flags |= N_FLAG;
451 b41f7df0 edgar_igl
        else if (res == 0)
452 b41f7df0 edgar_igl
                flags |= Z_FLAG;
453 b41f7df0 edgar_igl
454 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
455 b41f7df0 edgar_igl
}
456 b41f7df0 edgar_igl
457 b41f7df0 edgar_igl
/* TODO: This is expensive. We could split things up and only evaluate part of
458 b41f7df0 edgar_igl
   CCR on a need to know basis. For now, we simply re-evaluate everything.  */
459 6231868b edgar_igl
void  helper_evaluate_flags(void)
460 b41f7df0 edgar_igl
{
461 6231868b edgar_igl
        uint32_t src, dst, res;
462 b41f7df0 edgar_igl
        uint32_t flags = 0;
463 b41f7df0 edgar_igl
464 b41f7df0 edgar_igl
        src = env->cc_src;
465 b41f7df0 edgar_igl
        dst = env->cc_dest;
466 b41f7df0 edgar_igl
        res = env->cc_result;
467 b41f7df0 edgar_igl
468 30abcfc7 edgar_igl
        if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
469 30abcfc7 edgar_igl
                src = ~src;
470 b41f7df0 edgar_igl
471 b41f7df0 edgar_igl
        /* Now, evaluate the flags. This stuff is based on
472 b41f7df0 edgar_igl
           Per Zander's CRISv10 simulator.  */
473 b41f7df0 edgar_igl
        switch (env->cc_size)
474 b41f7df0 edgar_igl
        {
475 b41f7df0 edgar_igl
                case 1:
476 b41f7df0 edgar_igl
                        if ((res & 0x80L) != 0L)
477 b41f7df0 edgar_igl
                        {
478 b41f7df0 edgar_igl
                                flags |= N_FLAG;
479 b41f7df0 edgar_igl
                                if (((src & 0x80L) == 0L)
480 b41f7df0 edgar_igl
                                    && ((dst & 0x80L) == 0L))
481 b41f7df0 edgar_igl
                                {
482 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
483 b41f7df0 edgar_igl
                                }
484 b41f7df0 edgar_igl
                                else if (((src & 0x80L) != 0L)
485 b41f7df0 edgar_igl
                                         && ((dst & 0x80L) != 0L))
486 b41f7df0 edgar_igl
                                {
487 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
488 b41f7df0 edgar_igl
                                }
489 b41f7df0 edgar_igl
                        }
490 b41f7df0 edgar_igl
                        else
491 b41f7df0 edgar_igl
                        {
492 b41f7df0 edgar_igl
                                if ((res & 0xFFL) == 0L)
493 b41f7df0 edgar_igl
                                {
494 b41f7df0 edgar_igl
                                        flags |= Z_FLAG;
495 b41f7df0 edgar_igl
                                }
496 b41f7df0 edgar_igl
                                if (((src & 0x80L) != 0L)
497 b41f7df0 edgar_igl
                                    && ((dst & 0x80L) != 0L))
498 b41f7df0 edgar_igl
                                {
499 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
500 b41f7df0 edgar_igl
                                }
501 b41f7df0 edgar_igl
                                if ((dst & 0x80L) != 0L
502 b41f7df0 edgar_igl
                                    || (src & 0x80L) != 0L)
503 b41f7df0 edgar_igl
                                {
504 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
505 b41f7df0 edgar_igl
                                }
506 b41f7df0 edgar_igl
                        }
507 b41f7df0 edgar_igl
                        break;
508 b41f7df0 edgar_igl
                case 2:
509 b41f7df0 edgar_igl
                        if ((res & 0x8000L) != 0L)
510 b41f7df0 edgar_igl
                        {
511 b41f7df0 edgar_igl
                                flags |= N_FLAG;
512 b41f7df0 edgar_igl
                                if (((src & 0x8000L) == 0L)
513 b41f7df0 edgar_igl
                                    && ((dst & 0x8000L) == 0L))
514 b41f7df0 edgar_igl
                                {
515 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
516 b41f7df0 edgar_igl
                                }
517 b41f7df0 edgar_igl
                                else if (((src & 0x8000L) != 0L)
518 b41f7df0 edgar_igl
                                         && ((dst & 0x8000L) != 0L))
519 b41f7df0 edgar_igl
                                {
520 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
521 b41f7df0 edgar_igl
                                }
522 b41f7df0 edgar_igl
                        }
523 b41f7df0 edgar_igl
                        else
524 b41f7df0 edgar_igl
                        {
525 b41f7df0 edgar_igl
                                if ((res & 0xFFFFL) == 0L)
526 b41f7df0 edgar_igl
                                {
527 b41f7df0 edgar_igl
                                        flags |= Z_FLAG;
528 b41f7df0 edgar_igl
                                }
529 b41f7df0 edgar_igl
                                if (((src & 0x8000L) != 0L)
530 b41f7df0 edgar_igl
                                    && ((dst & 0x8000L) != 0L))
531 b41f7df0 edgar_igl
                                {
532 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
533 b41f7df0 edgar_igl
                                }
534 b41f7df0 edgar_igl
                                if ((dst & 0x8000L) != 0L
535 b41f7df0 edgar_igl
                                    || (src & 0x8000L) != 0L)
536 b41f7df0 edgar_igl
                                {
537 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
538 b41f7df0 edgar_igl
                                }
539 b41f7df0 edgar_igl
                        }
540 b41f7df0 edgar_igl
                        break;
541 b41f7df0 edgar_igl
                case 4:
542 b41f7df0 edgar_igl
                        if ((res & 0x80000000L) != 0L)
543 b41f7df0 edgar_igl
                        {
544 b41f7df0 edgar_igl
                                flags |= N_FLAG;
545 b41f7df0 edgar_igl
                                if (((src & 0x80000000L) == 0L)
546 b41f7df0 edgar_igl
                                    && ((dst & 0x80000000L) == 0L))
547 b41f7df0 edgar_igl
                                {
548 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
549 b41f7df0 edgar_igl
                                }
550 b41f7df0 edgar_igl
                                else if (((src & 0x80000000L) != 0L) &&
551 b41f7df0 edgar_igl
                                         ((dst & 0x80000000L) != 0L))
552 b41f7df0 edgar_igl
                                {
553 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
554 b41f7df0 edgar_igl
                                }
555 b41f7df0 edgar_igl
                        }
556 b41f7df0 edgar_igl
                        else
557 b41f7df0 edgar_igl
                        {
558 b41f7df0 edgar_igl
                                if (res == 0L)
559 b41f7df0 edgar_igl
                                        flags |= Z_FLAG;
560 b41f7df0 edgar_igl
                                if (((src & 0x80000000L) != 0L)
561 b41f7df0 edgar_igl
                                    && ((dst & 0x80000000L) != 0L))
562 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
563 b41f7df0 edgar_igl
                                if ((dst & 0x80000000L) != 0L
564 b41f7df0 edgar_igl
                                    || (src & 0x80000000L) != 0L)
565 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
566 b41f7df0 edgar_igl
                        }
567 b41f7df0 edgar_igl
                        break;
568 b41f7df0 edgar_igl
                default:
569 b41f7df0 edgar_igl
                        break;
570 b41f7df0 edgar_igl
        }
571 b41f7df0 edgar_igl
572 6231868b edgar_igl
        if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
573 b41f7df0 edgar_igl
                flags ^= C_FLAG;
574 6231868b edgar_igl
575 6231868b edgar_igl
        env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
576 b41f7df0 edgar_igl
}
577 30abcfc7 edgar_igl
578 30abcfc7 edgar_igl
void helper_top_evaluate_flags(void)
579 30abcfc7 edgar_igl
{
580 30abcfc7 edgar_igl
        switch (env->cc_op)
581 30abcfc7 edgar_igl
        {
582 30abcfc7 edgar_igl
                case CC_OP_MCP:
583 6231868b edgar_igl
                        env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
584 6231868b edgar_igl
                                        env->pregs[PR_CCS], env->cc_src,
585 6231868b edgar_igl
                                        env->cc_dest, env->cc_result);
586 30abcfc7 edgar_igl
                        break;
587 30abcfc7 edgar_igl
                case CC_OP_MULS:
588 6231868b edgar_igl
                        env->pregs[PR_CCS] = helper_evaluate_flags_muls(
589 6231868b edgar_igl
                                        env->pregs[PR_CCS], env->cc_result,
590 6231868b edgar_igl
                                        env->pregs[PR_MOF]);
591 30abcfc7 edgar_igl
                        break;
592 30abcfc7 edgar_igl
                case CC_OP_MULU:
593 6231868b edgar_igl
                        env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
594 6231868b edgar_igl
                                        env->pregs[PR_CCS], env->cc_result,
595 6231868b edgar_igl
                                        env->pregs[PR_MOF]);
596 30abcfc7 edgar_igl
                        break;
597 30abcfc7 edgar_igl
                case CC_OP_MOVE:
598 30abcfc7 edgar_igl
                case CC_OP_AND:
599 30abcfc7 edgar_igl
                case CC_OP_OR:
600 30abcfc7 edgar_igl
                case CC_OP_XOR:
601 30abcfc7 edgar_igl
                case CC_OP_ASR:
602 30abcfc7 edgar_igl
                case CC_OP_LSR:
603 30abcfc7 edgar_igl
                case CC_OP_LSL:
604 6231868b edgar_igl
                switch (env->cc_size)
605 6231868b edgar_igl
                {
606 6231868b edgar_igl
                        case 4:
607 6231868b edgar_igl
                                env->pregs[PR_CCS] =
608 6231868b edgar_igl
                                        helper_evaluate_flags_move_4(
609 6231868b edgar_igl
                                                        env->pregs[PR_CCS],
610 6231868b edgar_igl
                                                        env->cc_result);
611 6231868b edgar_igl
                                break;
612 6231868b edgar_igl
                        case 2:
613 6231868b edgar_igl
                                env->pregs[PR_CCS] =
614 6231868b edgar_igl
                                        helper_evaluate_flags_move_2(
615 6231868b edgar_igl
                                                        env->pregs[PR_CCS],
616 6231868b edgar_igl
                                                        env->cc_result);
617 6231868b edgar_igl
                                break;
618 6231868b edgar_igl
                        default:
619 6231868b edgar_igl
                                helper_evaluate_flags();
620 6231868b edgar_igl
                                break;
621 6231868b edgar_igl
                }
622 6231868b edgar_igl
                break;
623 30abcfc7 edgar_igl
                case CC_OP_FLAGS:
624 30abcfc7 edgar_igl
                        /* live.  */
625 30abcfc7 edgar_igl
                        break;
626 a8cf66bb edgar_igl
                case CC_OP_SUB:
627 a8cf66bb edgar_igl
                case CC_OP_CMP:
628 a8cf66bb edgar_igl
                        if (env->cc_size == 4)
629 6231868b edgar_igl
                                env->pregs[PR_CCS] =
630 6231868b edgar_igl
                                        helper_evaluate_flags_sub_4(
631 6231868b edgar_igl
                                                env->pregs[PR_CCS],
632 6231868b edgar_igl
                                                env->cc_src, env->cc_dest,
633 6231868b edgar_igl
                                                env->cc_result);
634 a8cf66bb edgar_igl
                        else
635 a8cf66bb edgar_igl
                                helper_evaluate_flags();
636 a8cf66bb edgar_igl
                        break;
637 30abcfc7 edgar_igl
                default:
638 30abcfc7 edgar_igl
                {
639 30abcfc7 edgar_igl
                        switch (env->cc_size)
640 30abcfc7 edgar_igl
                        {
641 6231868b edgar_igl
                        case 4:
642 6231868b edgar_igl
                                env->pregs[PR_CCS] =
643 6231868b edgar_igl
                                        helper_evaluate_flags_alu_4(
644 6231868b edgar_igl
                                                env->pregs[PR_CCS],
645 6231868b edgar_igl
                                                env->cc_src, env->cc_dest,
646 6231868b edgar_igl
                                                env->cc_result);
647 6231868b edgar_igl
                                break;
648 6231868b edgar_igl
                        default:
649 6231868b edgar_igl
                                helper_evaluate_flags();
650 6231868b edgar_igl
                                break;
651 30abcfc7 edgar_igl
                        }
652 30abcfc7 edgar_igl
                }
653 30abcfc7 edgar_igl
                break;
654 30abcfc7 edgar_igl
        }
655 30abcfc7 edgar_igl
}