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1 | 7a3f1944 | bellard | /*
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2 | 7a3f1944 | bellard | SPARC translation
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3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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5 | 3475187d | bellard | Copyright (C) 2003-2005 Fabrice Bellard
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6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 7a3f1944 | bellard | Lesser General Public License for more details.
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16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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18 | 7a3f1944 | bellard | License along with this library; if not, write to the Free Software
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19 | 7a3f1944 | bellard | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 7a3f1944 | bellard | */
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21 | 7a3f1944 | bellard | |
22 | 7a3f1944 | bellard | /*
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23 | 7a3f1944 | bellard | TODO-list:
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24 | 7a3f1944 | bellard | |
25 | 3475187d | bellard | Rest of V9 instructions, VIS instructions
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26 | bd497938 | bellard | NPC/PC static optimisations (use JUMP_TB when possible)
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27 | 7a3f1944 | bellard | Optimize synthetic instructions
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28 | bd497938 | bellard | */
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29 | 7a3f1944 | bellard | |
30 | 7a3f1944 | bellard | #include <stdarg.h> |
31 | 7a3f1944 | bellard | #include <stdlib.h> |
32 | 7a3f1944 | bellard | #include <stdio.h> |
33 | 7a3f1944 | bellard | #include <string.h> |
34 | 7a3f1944 | bellard | #include <inttypes.h> |
35 | 7a3f1944 | bellard | |
36 | 7a3f1944 | bellard | #include "cpu.h" |
37 | 7a3f1944 | bellard | #include "exec-all.h" |
38 | 7a3f1944 | bellard | #include "disas.h" |
39 | 7a3f1944 | bellard | |
40 | 7a3f1944 | bellard | #define DEBUG_DISAS
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41 | 7a3f1944 | bellard | |
42 | 72cbca10 | bellard | #define DYNAMIC_PC 1 /* dynamic pc value */ |
43 | 72cbca10 | bellard | #define JUMP_PC 2 /* dynamic pc value which takes only two values |
44 | 72cbca10 | bellard | according to jump_pc[T2] */
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45 | 72cbca10 | bellard | |
46 | 7a3f1944 | bellard | typedef struct DisasContext { |
47 | 0f8a249a | blueswir1 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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48 | 0f8a249a | blueswir1 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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49 | 72cbca10 | bellard | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
50 | cf495bcf | bellard | int is_br;
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51 | e8af50a3 | bellard | int mem_idx;
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52 | a80dde08 | bellard | int fpu_enabled;
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53 | cf495bcf | bellard | struct TranslationBlock *tb;
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54 | 7a3f1944 | bellard | } DisasContext; |
55 | 7a3f1944 | bellard | |
56 | aaed909a | bellard | typedef struct sparc_def_t sparc_def_t; |
57 | aaed909a | bellard | |
58 | 62724a37 | blueswir1 | struct sparc_def_t {
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59 | 62724a37 | blueswir1 | const unsigned char *name; |
60 | 62724a37 | blueswir1 | target_ulong iu_version; |
61 | 62724a37 | blueswir1 | uint32_t fpu_version; |
62 | 62724a37 | blueswir1 | uint32_t mmu_version; |
63 | 6d5f237a | blueswir1 | uint32_t mmu_bm; |
64 | 62724a37 | blueswir1 | }; |
65 | 62724a37 | blueswir1 | |
66 | aaed909a | bellard | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name); |
67 | aaed909a | bellard | |
68 | 7a3f1944 | bellard | static uint16_t *gen_opc_ptr;
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69 | 7a3f1944 | bellard | static uint32_t *gen_opparam_ptr;
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70 | 7a3f1944 | bellard | extern FILE *logfile;
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71 | 7a3f1944 | bellard | extern int loglevel; |
72 | 7a3f1944 | bellard | |
73 | 7a3f1944 | bellard | enum {
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74 | 7a3f1944 | bellard | #define DEF(s,n,copy_size) INDEX_op_ ## s, |
75 | 7a3f1944 | bellard | #include "opc.h" |
76 | 7a3f1944 | bellard | #undef DEF
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77 | cf495bcf | bellard | NB_OPS |
78 | 7a3f1944 | bellard | }; |
79 | 7a3f1944 | bellard | |
80 | 7a3f1944 | bellard | #include "gen-op.h" |
81 | 7a3f1944 | bellard | |
82 | 3475187d | bellard | // This function uses non-native bit order
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83 | 7a3f1944 | bellard | #define GET_FIELD(X, FROM, TO) \
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84 | 7a3f1944 | bellard | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
85 | 7a3f1944 | bellard | |
86 | 3475187d | bellard | // This function uses the order in the manuals, i.e. bit 0 is 2^0
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87 | 3475187d | bellard | #define GET_FIELD_SP(X, FROM, TO) \
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88 | 3475187d | bellard | GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
89 | 3475187d | bellard | |
90 | 3475187d | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
91 | 46d38ba8 | blueswir1 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
92 | 3475187d | bellard | |
93 | 3475187d | bellard | #ifdef TARGET_SPARC64
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94 | 0387d928 | blueswir1 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
95 | 1f587329 | blueswir1 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
96 | 3475187d | bellard | #else
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97 | c185970a | blueswir1 | #define DFPREG(r) (r & 0x1e) |
98 | 1f587329 | blueswir1 | #define QFPREG(r) (r & 0x1c) |
99 | 3475187d | bellard | #endif
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100 | 3475187d | bellard | |
101 | 83469015 | bellard | #ifdef USE_DIRECT_JUMP
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102 | 83469015 | bellard | #define TBPARAM(x)
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103 | 83469015 | bellard | #else
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104 | 83469015 | bellard | #define TBPARAM(x) (long)(x) |
105 | 83469015 | bellard | #endif
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106 | 83469015 | bellard | |
107 | 3475187d | bellard | static int sign_extend(int x, int len) |
108 | 3475187d | bellard | { |
109 | 3475187d | bellard | len = 32 - len;
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110 | 3475187d | bellard | return (x << len) >> len;
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111 | 3475187d | bellard | } |
112 | 3475187d | bellard | |
113 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
114 | 7a3f1944 | bellard | |
115 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc); |
116 | 7a3f1944 | bellard | |
117 | a68156d0 | blueswir1 | static GenOpFunc * const gen_op_movl_TN_reg[2][32] = { |
118 | cf495bcf | bellard | { |
119 | cf495bcf | bellard | gen_op_movl_g0_T0, |
120 | cf495bcf | bellard | gen_op_movl_g1_T0, |
121 | cf495bcf | bellard | gen_op_movl_g2_T0, |
122 | cf495bcf | bellard | gen_op_movl_g3_T0, |
123 | cf495bcf | bellard | gen_op_movl_g4_T0, |
124 | cf495bcf | bellard | gen_op_movl_g5_T0, |
125 | cf495bcf | bellard | gen_op_movl_g6_T0, |
126 | cf495bcf | bellard | gen_op_movl_g7_T0, |
127 | cf495bcf | bellard | gen_op_movl_o0_T0, |
128 | cf495bcf | bellard | gen_op_movl_o1_T0, |
129 | cf495bcf | bellard | gen_op_movl_o2_T0, |
130 | cf495bcf | bellard | gen_op_movl_o3_T0, |
131 | cf495bcf | bellard | gen_op_movl_o4_T0, |
132 | cf495bcf | bellard | gen_op_movl_o5_T0, |
133 | cf495bcf | bellard | gen_op_movl_o6_T0, |
134 | cf495bcf | bellard | gen_op_movl_o7_T0, |
135 | cf495bcf | bellard | gen_op_movl_l0_T0, |
136 | cf495bcf | bellard | gen_op_movl_l1_T0, |
137 | cf495bcf | bellard | gen_op_movl_l2_T0, |
138 | cf495bcf | bellard | gen_op_movl_l3_T0, |
139 | cf495bcf | bellard | gen_op_movl_l4_T0, |
140 | cf495bcf | bellard | gen_op_movl_l5_T0, |
141 | cf495bcf | bellard | gen_op_movl_l6_T0, |
142 | cf495bcf | bellard | gen_op_movl_l7_T0, |
143 | cf495bcf | bellard | gen_op_movl_i0_T0, |
144 | cf495bcf | bellard | gen_op_movl_i1_T0, |
145 | cf495bcf | bellard | gen_op_movl_i2_T0, |
146 | cf495bcf | bellard | gen_op_movl_i3_T0, |
147 | cf495bcf | bellard | gen_op_movl_i4_T0, |
148 | cf495bcf | bellard | gen_op_movl_i5_T0, |
149 | cf495bcf | bellard | gen_op_movl_i6_T0, |
150 | cf495bcf | bellard | gen_op_movl_i7_T0, |
151 | cf495bcf | bellard | }, |
152 | cf495bcf | bellard | { |
153 | cf495bcf | bellard | gen_op_movl_g0_T1, |
154 | cf495bcf | bellard | gen_op_movl_g1_T1, |
155 | cf495bcf | bellard | gen_op_movl_g2_T1, |
156 | cf495bcf | bellard | gen_op_movl_g3_T1, |
157 | cf495bcf | bellard | gen_op_movl_g4_T1, |
158 | cf495bcf | bellard | gen_op_movl_g5_T1, |
159 | cf495bcf | bellard | gen_op_movl_g6_T1, |
160 | cf495bcf | bellard | gen_op_movl_g7_T1, |
161 | cf495bcf | bellard | gen_op_movl_o0_T1, |
162 | cf495bcf | bellard | gen_op_movl_o1_T1, |
163 | cf495bcf | bellard | gen_op_movl_o2_T1, |
164 | cf495bcf | bellard | gen_op_movl_o3_T1, |
165 | cf495bcf | bellard | gen_op_movl_o4_T1, |
166 | cf495bcf | bellard | gen_op_movl_o5_T1, |
167 | cf495bcf | bellard | gen_op_movl_o6_T1, |
168 | cf495bcf | bellard | gen_op_movl_o7_T1, |
169 | cf495bcf | bellard | gen_op_movl_l0_T1, |
170 | cf495bcf | bellard | gen_op_movl_l1_T1, |
171 | cf495bcf | bellard | gen_op_movl_l2_T1, |
172 | cf495bcf | bellard | gen_op_movl_l3_T1, |
173 | cf495bcf | bellard | gen_op_movl_l4_T1, |
174 | cf495bcf | bellard | gen_op_movl_l5_T1, |
175 | cf495bcf | bellard | gen_op_movl_l6_T1, |
176 | cf495bcf | bellard | gen_op_movl_l7_T1, |
177 | cf495bcf | bellard | gen_op_movl_i0_T1, |
178 | cf495bcf | bellard | gen_op_movl_i1_T1, |
179 | cf495bcf | bellard | gen_op_movl_i2_T1, |
180 | cf495bcf | bellard | gen_op_movl_i3_T1, |
181 | cf495bcf | bellard | gen_op_movl_i4_T1, |
182 | cf495bcf | bellard | gen_op_movl_i5_T1, |
183 | cf495bcf | bellard | gen_op_movl_i6_T1, |
184 | cf495bcf | bellard | gen_op_movl_i7_T1, |
185 | cf495bcf | bellard | } |
186 | 7a3f1944 | bellard | }; |
187 | 7a3f1944 | bellard | |
188 | a68156d0 | blueswir1 | static GenOpFunc * const gen_op_movl_reg_TN[3][32] = { |
189 | cf495bcf | bellard | { |
190 | cf495bcf | bellard | gen_op_movl_T0_g0, |
191 | cf495bcf | bellard | gen_op_movl_T0_g1, |
192 | cf495bcf | bellard | gen_op_movl_T0_g2, |
193 | cf495bcf | bellard | gen_op_movl_T0_g3, |
194 | cf495bcf | bellard | gen_op_movl_T0_g4, |
195 | cf495bcf | bellard | gen_op_movl_T0_g5, |
196 | cf495bcf | bellard | gen_op_movl_T0_g6, |
197 | cf495bcf | bellard | gen_op_movl_T0_g7, |
198 | cf495bcf | bellard | gen_op_movl_T0_o0, |
199 | cf495bcf | bellard | gen_op_movl_T0_o1, |
200 | cf495bcf | bellard | gen_op_movl_T0_o2, |
201 | cf495bcf | bellard | gen_op_movl_T0_o3, |
202 | cf495bcf | bellard | gen_op_movl_T0_o4, |
203 | cf495bcf | bellard | gen_op_movl_T0_o5, |
204 | cf495bcf | bellard | gen_op_movl_T0_o6, |
205 | cf495bcf | bellard | gen_op_movl_T0_o7, |
206 | cf495bcf | bellard | gen_op_movl_T0_l0, |
207 | cf495bcf | bellard | gen_op_movl_T0_l1, |
208 | cf495bcf | bellard | gen_op_movl_T0_l2, |
209 | cf495bcf | bellard | gen_op_movl_T0_l3, |
210 | cf495bcf | bellard | gen_op_movl_T0_l4, |
211 | cf495bcf | bellard | gen_op_movl_T0_l5, |
212 | cf495bcf | bellard | gen_op_movl_T0_l6, |
213 | cf495bcf | bellard | gen_op_movl_T0_l7, |
214 | cf495bcf | bellard | gen_op_movl_T0_i0, |
215 | cf495bcf | bellard | gen_op_movl_T0_i1, |
216 | cf495bcf | bellard | gen_op_movl_T0_i2, |
217 | cf495bcf | bellard | gen_op_movl_T0_i3, |
218 | cf495bcf | bellard | gen_op_movl_T0_i4, |
219 | cf495bcf | bellard | gen_op_movl_T0_i5, |
220 | cf495bcf | bellard | gen_op_movl_T0_i6, |
221 | cf495bcf | bellard | gen_op_movl_T0_i7, |
222 | cf495bcf | bellard | }, |
223 | cf495bcf | bellard | { |
224 | cf495bcf | bellard | gen_op_movl_T1_g0, |
225 | cf495bcf | bellard | gen_op_movl_T1_g1, |
226 | cf495bcf | bellard | gen_op_movl_T1_g2, |
227 | cf495bcf | bellard | gen_op_movl_T1_g3, |
228 | cf495bcf | bellard | gen_op_movl_T1_g4, |
229 | cf495bcf | bellard | gen_op_movl_T1_g5, |
230 | cf495bcf | bellard | gen_op_movl_T1_g6, |
231 | cf495bcf | bellard | gen_op_movl_T1_g7, |
232 | cf495bcf | bellard | gen_op_movl_T1_o0, |
233 | cf495bcf | bellard | gen_op_movl_T1_o1, |
234 | cf495bcf | bellard | gen_op_movl_T1_o2, |
235 | cf495bcf | bellard | gen_op_movl_T1_o3, |
236 | cf495bcf | bellard | gen_op_movl_T1_o4, |
237 | cf495bcf | bellard | gen_op_movl_T1_o5, |
238 | cf495bcf | bellard | gen_op_movl_T1_o6, |
239 | cf495bcf | bellard | gen_op_movl_T1_o7, |
240 | cf495bcf | bellard | gen_op_movl_T1_l0, |
241 | cf495bcf | bellard | gen_op_movl_T1_l1, |
242 | cf495bcf | bellard | gen_op_movl_T1_l2, |
243 | cf495bcf | bellard | gen_op_movl_T1_l3, |
244 | cf495bcf | bellard | gen_op_movl_T1_l4, |
245 | cf495bcf | bellard | gen_op_movl_T1_l5, |
246 | cf495bcf | bellard | gen_op_movl_T1_l6, |
247 | cf495bcf | bellard | gen_op_movl_T1_l7, |
248 | cf495bcf | bellard | gen_op_movl_T1_i0, |
249 | cf495bcf | bellard | gen_op_movl_T1_i1, |
250 | cf495bcf | bellard | gen_op_movl_T1_i2, |
251 | cf495bcf | bellard | gen_op_movl_T1_i3, |
252 | cf495bcf | bellard | gen_op_movl_T1_i4, |
253 | cf495bcf | bellard | gen_op_movl_T1_i5, |
254 | cf495bcf | bellard | gen_op_movl_T1_i6, |
255 | cf495bcf | bellard | gen_op_movl_T1_i7, |
256 | cf495bcf | bellard | }, |
257 | cf495bcf | bellard | { |
258 | cf495bcf | bellard | gen_op_movl_T2_g0, |
259 | cf495bcf | bellard | gen_op_movl_T2_g1, |
260 | cf495bcf | bellard | gen_op_movl_T2_g2, |
261 | cf495bcf | bellard | gen_op_movl_T2_g3, |
262 | cf495bcf | bellard | gen_op_movl_T2_g4, |
263 | cf495bcf | bellard | gen_op_movl_T2_g5, |
264 | cf495bcf | bellard | gen_op_movl_T2_g6, |
265 | cf495bcf | bellard | gen_op_movl_T2_g7, |
266 | cf495bcf | bellard | gen_op_movl_T2_o0, |
267 | cf495bcf | bellard | gen_op_movl_T2_o1, |
268 | cf495bcf | bellard | gen_op_movl_T2_o2, |
269 | cf495bcf | bellard | gen_op_movl_T2_o3, |
270 | cf495bcf | bellard | gen_op_movl_T2_o4, |
271 | cf495bcf | bellard | gen_op_movl_T2_o5, |
272 | cf495bcf | bellard | gen_op_movl_T2_o6, |
273 | cf495bcf | bellard | gen_op_movl_T2_o7, |
274 | cf495bcf | bellard | gen_op_movl_T2_l0, |
275 | cf495bcf | bellard | gen_op_movl_T2_l1, |
276 | cf495bcf | bellard | gen_op_movl_T2_l2, |
277 | cf495bcf | bellard | gen_op_movl_T2_l3, |
278 | cf495bcf | bellard | gen_op_movl_T2_l4, |
279 | cf495bcf | bellard | gen_op_movl_T2_l5, |
280 | cf495bcf | bellard | gen_op_movl_T2_l6, |
281 | cf495bcf | bellard | gen_op_movl_T2_l7, |
282 | cf495bcf | bellard | gen_op_movl_T2_i0, |
283 | cf495bcf | bellard | gen_op_movl_T2_i1, |
284 | cf495bcf | bellard | gen_op_movl_T2_i2, |
285 | cf495bcf | bellard | gen_op_movl_T2_i3, |
286 | cf495bcf | bellard | gen_op_movl_T2_i4, |
287 | cf495bcf | bellard | gen_op_movl_T2_i5, |
288 | cf495bcf | bellard | gen_op_movl_T2_i6, |
289 | cf495bcf | bellard | gen_op_movl_T2_i7, |
290 | cf495bcf | bellard | } |
291 | 7a3f1944 | bellard | }; |
292 | 7a3f1944 | bellard | |
293 | a68156d0 | blueswir1 | static GenOpFunc1 * const gen_op_movl_TN_im[3] = { |
294 | cf495bcf | bellard | gen_op_movl_T0_im, |
295 | cf495bcf | bellard | gen_op_movl_T1_im, |
296 | cf495bcf | bellard | gen_op_movl_T2_im |
297 | 7a3f1944 | bellard | }; |
298 | 7a3f1944 | bellard | |
299 | 3475187d | bellard | // Sign extending version
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300 | 3475187d | bellard | static GenOpFunc1 * const gen_op_movl_TN_sim[3] = { |
301 | 3475187d | bellard | gen_op_movl_T0_sim, |
302 | 3475187d | bellard | gen_op_movl_T1_sim, |
303 | 3475187d | bellard | gen_op_movl_T2_sim |
304 | 3475187d | bellard | }; |
305 | 3475187d | bellard | |
306 | 3475187d | bellard | #ifdef TARGET_SPARC64
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307 | 3475187d | bellard | #define GEN32(func, NAME) \
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308 | a68156d0 | blueswir1 | static GenOpFunc * const NAME ## _table [64] = { \ |
309 | 3475187d | bellard | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
310 | 3475187d | bellard | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
311 | 3475187d | bellard | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
312 | 3475187d | bellard | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
313 | 3475187d | bellard | NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ |
314 | 3475187d | bellard | NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ |
315 | 3475187d | bellard | NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ |
316 | 3475187d | bellard | NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ |
317 | 3475187d | bellard | NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \ |
318 | 3475187d | bellard | NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \ |
319 | 3475187d | bellard | NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \ |
320 | 3475187d | bellard | NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \ |
321 | 3475187d | bellard | }; \ |
322 | 3475187d | bellard | static inline void func(int n) \ |
323 | 3475187d | bellard | { \ |
324 | 3475187d | bellard | NAME ## _table[n](); \ |
325 | 3475187d | bellard | } |
326 | 3475187d | bellard | #else
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327 | e8af50a3 | bellard | #define GEN32(func, NAME) \
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328 | a68156d0 | blueswir1 | static GenOpFunc *const NAME ## _table [32] = { \ |
329 | e8af50a3 | bellard | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
330 | e8af50a3 | bellard | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
331 | e8af50a3 | bellard | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
332 | e8af50a3 | bellard | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
333 | e8af50a3 | bellard | NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ |
334 | e8af50a3 | bellard | NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ |
335 | e8af50a3 | bellard | NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ |
336 | e8af50a3 | bellard | NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ |
337 | e8af50a3 | bellard | }; \ |
338 | e8af50a3 | bellard | static inline void func(int n) \ |
339 | e8af50a3 | bellard | { \ |
340 | e8af50a3 | bellard | NAME ## _table[n](); \ |
341 | e8af50a3 | bellard | } |
342 | 3475187d | bellard | #endif
|
343 | e8af50a3 | bellard | |
344 | e8af50a3 | bellard | /* floating point registers moves */
|
345 | e8af50a3 | bellard | GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf); |
346 | e8af50a3 | bellard | GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf); |
347 | e8af50a3 | bellard | GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf); |
348 | e8af50a3 | bellard | GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf); |
349 | e8af50a3 | bellard | |
350 | e8af50a3 | bellard | GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf); |
351 | e8af50a3 | bellard | GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf); |
352 | e8af50a3 | bellard | GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf); |
353 | e8af50a3 | bellard | GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf); |
354 | e8af50a3 | bellard | |
355 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
356 | 1f587329 | blueswir1 | GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf); |
357 | 1f587329 | blueswir1 | GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf); |
358 | 1f587329 | blueswir1 | GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf); |
359 | 1f587329 | blueswir1 | GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf); |
360 | 1f587329 | blueswir1 | #endif
|
361 | 1f587329 | blueswir1 | |
362 | 81ad8ba2 | blueswir1 | /* moves */
|
363 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
|
364 | 3475187d | bellard | #define supervisor(dc) 0 |
365 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
|
366 | e9ebed4d | blueswir1 | #define hypervisor(dc) 0 |
367 | 81ad8ba2 | blueswir1 | #endif
|
368 | 3475187d | bellard | #define gen_op_ldst(name) gen_op_##name##_raw() |
369 | 3475187d | bellard | #else
|
370 | 6f27aba6 | blueswir1 | #define supervisor(dc) (dc->mem_idx >= 1) |
371 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
|
372 | 81ad8ba2 | blueswir1 | #define hypervisor(dc) (dc->mem_idx == 2) |
373 | 6f27aba6 | blueswir1 | #define OP_LD_TABLE(width) \
|
374 | 6f27aba6 | blueswir1 | static GenOpFunc * const gen_op_##width[] = { \ |
375 | 6f27aba6 | blueswir1 | &gen_op_##width##_user, \ |
376 | 6f27aba6 | blueswir1 | &gen_op_##width##_kernel, \ |
377 | 6f27aba6 | blueswir1 | &gen_op_##width##_hypv, \ |
378 | 6f27aba6 | blueswir1 | }; |
379 | 6f27aba6 | blueswir1 | #else
|
380 | 0f8a249a | blueswir1 | #define OP_LD_TABLE(width) \
|
381 | a68156d0 | blueswir1 | static GenOpFunc * const gen_op_##width[] = { \ |
382 | 0f8a249a | blueswir1 | &gen_op_##width##_user, \ |
383 | 0f8a249a | blueswir1 | &gen_op_##width##_kernel, \ |
384 | 81ad8ba2 | blueswir1 | }; |
385 | 3475187d | bellard | #endif
|
386 | 6f27aba6 | blueswir1 | #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])() |
387 | 6f27aba6 | blueswir1 | #endif
|
388 | e8af50a3 | bellard | |
389 | 81ad8ba2 | blueswir1 | #ifndef CONFIG_USER_ONLY
|
390 | e8af50a3 | bellard | OP_LD_TABLE(ld); |
391 | e8af50a3 | bellard | OP_LD_TABLE(st); |
392 | e8af50a3 | bellard | OP_LD_TABLE(ldub); |
393 | e8af50a3 | bellard | OP_LD_TABLE(lduh); |
394 | e8af50a3 | bellard | OP_LD_TABLE(ldsb); |
395 | e8af50a3 | bellard | OP_LD_TABLE(ldsh); |
396 | e8af50a3 | bellard | OP_LD_TABLE(stb); |
397 | e8af50a3 | bellard | OP_LD_TABLE(sth); |
398 | e8af50a3 | bellard | OP_LD_TABLE(std); |
399 | e8af50a3 | bellard | OP_LD_TABLE(ldstub); |
400 | e8af50a3 | bellard | OP_LD_TABLE(swap); |
401 | e8af50a3 | bellard | OP_LD_TABLE(ldd); |
402 | e8af50a3 | bellard | OP_LD_TABLE(stf); |
403 | e8af50a3 | bellard | OP_LD_TABLE(stdf); |
404 | e8af50a3 | bellard | OP_LD_TABLE(ldf); |
405 | e8af50a3 | bellard | OP_LD_TABLE(lddf); |
406 | e8af50a3 | bellard | |
407 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
408 | dc011987 | blueswir1 | OP_LD_TABLE(lduw); |
409 | 3475187d | bellard | OP_LD_TABLE(ldsw); |
410 | 3475187d | bellard | OP_LD_TABLE(ldx); |
411 | 3475187d | bellard | OP_LD_TABLE(stx); |
412 | 81ad8ba2 | blueswir1 | #endif
|
413 | 81ad8ba2 | blueswir1 | #endif
|
414 | 81ad8ba2 | blueswir1 | |
415 | 81ad8ba2 | blueswir1 | /* asi moves */
|
416 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
|
417 | 81ad8ba2 | blueswir1 | static inline void gen_ld_asi(int insn, int size, int sign) |
418 | 81ad8ba2 | blueswir1 | { |
419 | 81ad8ba2 | blueswir1 | int asi, offset;
|
420 | 81ad8ba2 | blueswir1 | |
421 | 81ad8ba2 | blueswir1 | if (IS_IMM) {
|
422 | 81ad8ba2 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
423 | 81ad8ba2 | blueswir1 | gen_op_ld_asi_reg(offset, size, sign); |
424 | 81ad8ba2 | blueswir1 | } else {
|
425 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
426 | 81ad8ba2 | blueswir1 | gen_op_ld_asi(asi, size, sign); |
427 | 81ad8ba2 | blueswir1 | } |
428 | 81ad8ba2 | blueswir1 | } |
429 | 81ad8ba2 | blueswir1 | |
430 | 81ad8ba2 | blueswir1 | static inline void gen_st_asi(int insn, int size) |
431 | 81ad8ba2 | blueswir1 | { |
432 | 81ad8ba2 | blueswir1 | int asi, offset;
|
433 | 81ad8ba2 | blueswir1 | |
434 | 81ad8ba2 | blueswir1 | if (IS_IMM) {
|
435 | 81ad8ba2 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
436 | 81ad8ba2 | blueswir1 | gen_op_st_asi_reg(offset, size); |
437 | 81ad8ba2 | blueswir1 | } else {
|
438 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
439 | 81ad8ba2 | blueswir1 | gen_op_st_asi(asi, size); |
440 | 81ad8ba2 | blueswir1 | } |
441 | 81ad8ba2 | blueswir1 | } |
442 | 81ad8ba2 | blueswir1 | |
443 | 3391c818 | blueswir1 | static inline void gen_ldf_asi(int insn, int size) |
444 | 3391c818 | blueswir1 | { |
445 | 3391c818 | blueswir1 | int asi, offset, rd;
|
446 | 3391c818 | blueswir1 | |
447 | 0387d928 | blueswir1 | rd = DFPREG(GET_FIELD(insn, 2, 6)); |
448 | 3391c818 | blueswir1 | if (IS_IMM) {
|
449 | 3391c818 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
450 | 3391c818 | blueswir1 | gen_op_ldf_asi_reg(offset, size, rd); |
451 | 3391c818 | blueswir1 | } else {
|
452 | 3391c818 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
453 | 3391c818 | blueswir1 | gen_op_ldf_asi(asi, size, rd); |
454 | 3391c818 | blueswir1 | } |
455 | 3391c818 | blueswir1 | } |
456 | 3391c818 | blueswir1 | |
457 | 3391c818 | blueswir1 | static inline void gen_stf_asi(int insn, int size) |
458 | 3391c818 | blueswir1 | { |
459 | 3391c818 | blueswir1 | int asi, offset, rd;
|
460 | 3391c818 | blueswir1 | |
461 | 0387d928 | blueswir1 | rd = DFPREG(GET_FIELD(insn, 2, 6)); |
462 | 3391c818 | blueswir1 | if (IS_IMM) {
|
463 | 3391c818 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
464 | 3391c818 | blueswir1 | gen_op_stf_asi_reg(offset, size, rd); |
465 | 3391c818 | blueswir1 | } else {
|
466 | 3391c818 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
467 | 3391c818 | blueswir1 | gen_op_stf_asi(asi, size, rd); |
468 | 3391c818 | blueswir1 | } |
469 | 3391c818 | blueswir1 | } |
470 | 3391c818 | blueswir1 | |
471 | 81ad8ba2 | blueswir1 | static inline void gen_swap_asi(int insn) |
472 | 81ad8ba2 | blueswir1 | { |
473 | 81ad8ba2 | blueswir1 | int asi, offset;
|
474 | 81ad8ba2 | blueswir1 | |
475 | 81ad8ba2 | blueswir1 | if (IS_IMM) {
|
476 | 81ad8ba2 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
477 | 81ad8ba2 | blueswir1 | gen_op_swap_asi_reg(offset); |
478 | 81ad8ba2 | blueswir1 | } else {
|
479 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
480 | 81ad8ba2 | blueswir1 | gen_op_swap_asi(asi); |
481 | 81ad8ba2 | blueswir1 | } |
482 | 81ad8ba2 | blueswir1 | } |
483 | 81ad8ba2 | blueswir1 | |
484 | 81ad8ba2 | blueswir1 | static inline void gen_ldstub_asi(int insn) |
485 | 81ad8ba2 | blueswir1 | { |
486 | 81ad8ba2 | blueswir1 | int asi, offset;
|
487 | 81ad8ba2 | blueswir1 | |
488 | 81ad8ba2 | blueswir1 | if (IS_IMM) {
|
489 | 81ad8ba2 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
490 | 81ad8ba2 | blueswir1 | gen_op_ldstub_asi_reg(offset); |
491 | 81ad8ba2 | blueswir1 | } else {
|
492 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
493 | 81ad8ba2 | blueswir1 | gen_op_ldstub_asi(asi); |
494 | 81ad8ba2 | blueswir1 | } |
495 | 81ad8ba2 | blueswir1 | } |
496 | 81ad8ba2 | blueswir1 | |
497 | 81ad8ba2 | blueswir1 | static inline void gen_ldda_asi(int insn) |
498 | 81ad8ba2 | blueswir1 | { |
499 | 81ad8ba2 | blueswir1 | int asi, offset;
|
500 | 81ad8ba2 | blueswir1 | |
501 | 81ad8ba2 | blueswir1 | if (IS_IMM) {
|
502 | 81ad8ba2 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
503 | 81ad8ba2 | blueswir1 | gen_op_ldda_asi_reg(offset); |
504 | 81ad8ba2 | blueswir1 | } else {
|
505 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
506 | 81ad8ba2 | blueswir1 | gen_op_ldda_asi(asi); |
507 | 81ad8ba2 | blueswir1 | } |
508 | 81ad8ba2 | blueswir1 | } |
509 | 81ad8ba2 | blueswir1 | |
510 | 81ad8ba2 | blueswir1 | static inline void gen_stda_asi(int insn) |
511 | 81ad8ba2 | blueswir1 | { |
512 | 81ad8ba2 | blueswir1 | int asi, offset;
|
513 | 81ad8ba2 | blueswir1 | |
514 | 81ad8ba2 | blueswir1 | if (IS_IMM) {
|
515 | 81ad8ba2 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
516 | 81ad8ba2 | blueswir1 | gen_op_stda_asi_reg(offset); |
517 | 81ad8ba2 | blueswir1 | } else {
|
518 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
519 | 81ad8ba2 | blueswir1 | gen_op_stda_asi(asi); |
520 | 81ad8ba2 | blueswir1 | } |
521 | 81ad8ba2 | blueswir1 | } |
522 | 81ad8ba2 | blueswir1 | |
523 | 81ad8ba2 | blueswir1 | static inline void gen_cas_asi(int insn) |
524 | 81ad8ba2 | blueswir1 | { |
525 | 81ad8ba2 | blueswir1 | int asi, offset;
|
526 | 81ad8ba2 | blueswir1 | |
527 | 81ad8ba2 | blueswir1 | if (IS_IMM) {
|
528 | 81ad8ba2 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
529 | 81ad8ba2 | blueswir1 | gen_op_cas_asi_reg(offset); |
530 | 81ad8ba2 | blueswir1 | } else {
|
531 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
532 | 81ad8ba2 | blueswir1 | gen_op_cas_asi(asi); |
533 | 81ad8ba2 | blueswir1 | } |
534 | 81ad8ba2 | blueswir1 | } |
535 | 81ad8ba2 | blueswir1 | |
536 | 81ad8ba2 | blueswir1 | static inline void gen_casx_asi(int insn) |
537 | 81ad8ba2 | blueswir1 | { |
538 | 81ad8ba2 | blueswir1 | int asi, offset;
|
539 | 81ad8ba2 | blueswir1 | |
540 | 81ad8ba2 | blueswir1 | if (IS_IMM) {
|
541 | 81ad8ba2 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
542 | 81ad8ba2 | blueswir1 | gen_op_casx_asi_reg(offset); |
543 | 81ad8ba2 | blueswir1 | } else {
|
544 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
545 | 81ad8ba2 | blueswir1 | gen_op_casx_asi(asi); |
546 | 81ad8ba2 | blueswir1 | } |
547 | 81ad8ba2 | blueswir1 | } |
548 | 81ad8ba2 | blueswir1 | |
549 | 81ad8ba2 | blueswir1 | #elif !defined(CONFIG_USER_ONLY)
|
550 | 81ad8ba2 | blueswir1 | |
551 | 81ad8ba2 | blueswir1 | static inline void gen_ld_asi(int insn, int size, int sign) |
552 | 81ad8ba2 | blueswir1 | { |
553 | 81ad8ba2 | blueswir1 | int asi;
|
554 | 81ad8ba2 | blueswir1 | |
555 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
556 | 81ad8ba2 | blueswir1 | gen_op_ld_asi(asi, size, sign); |
557 | 81ad8ba2 | blueswir1 | } |
558 | 81ad8ba2 | blueswir1 | |
559 | 81ad8ba2 | blueswir1 | static inline void gen_st_asi(int insn, int size) |
560 | 81ad8ba2 | blueswir1 | { |
561 | 81ad8ba2 | blueswir1 | int asi;
|
562 | 81ad8ba2 | blueswir1 | |
563 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
564 | 81ad8ba2 | blueswir1 | gen_op_st_asi(asi, size); |
565 | 81ad8ba2 | blueswir1 | } |
566 | 81ad8ba2 | blueswir1 | |
567 | 81ad8ba2 | blueswir1 | static inline void gen_ldstub_asi(int insn) |
568 | 81ad8ba2 | blueswir1 | { |
569 | 81ad8ba2 | blueswir1 | int asi;
|
570 | 81ad8ba2 | blueswir1 | |
571 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
572 | 81ad8ba2 | blueswir1 | gen_op_ldstub_asi(asi); |
573 | 81ad8ba2 | blueswir1 | } |
574 | 81ad8ba2 | blueswir1 | |
575 | 81ad8ba2 | blueswir1 | static inline void gen_swap_asi(int insn) |
576 | 81ad8ba2 | blueswir1 | { |
577 | 81ad8ba2 | blueswir1 | int asi;
|
578 | 81ad8ba2 | blueswir1 | |
579 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
580 | 81ad8ba2 | blueswir1 | gen_op_swap_asi(asi); |
581 | 81ad8ba2 | blueswir1 | } |
582 | 81ad8ba2 | blueswir1 | |
583 | 81ad8ba2 | blueswir1 | static inline void gen_ldda_asi(int insn) |
584 | 81ad8ba2 | blueswir1 | { |
585 | 81ad8ba2 | blueswir1 | int asi;
|
586 | 81ad8ba2 | blueswir1 | |
587 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
588 | 81ad8ba2 | blueswir1 | gen_op_ld_asi(asi, 8, 0); |
589 | 81ad8ba2 | blueswir1 | } |
590 | 81ad8ba2 | blueswir1 | |
591 | 81ad8ba2 | blueswir1 | static inline void gen_stda_asi(int insn) |
592 | 81ad8ba2 | blueswir1 | { |
593 | 81ad8ba2 | blueswir1 | int asi;
|
594 | 81ad8ba2 | blueswir1 | |
595 | 81ad8ba2 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
596 | 81ad8ba2 | blueswir1 | gen_op_st_asi(asi, 8);
|
597 | 81ad8ba2 | blueswir1 | } |
598 | 3475187d | bellard | #endif
|
599 | 3475187d | bellard | |
600 | 3475187d | bellard | static inline void gen_movl_imm_TN(int reg, uint32_t imm) |
601 | 7a3f1944 | bellard | { |
602 | 83469015 | bellard | gen_op_movl_TN_im[reg](imm); |
603 | 7a3f1944 | bellard | } |
604 | 7a3f1944 | bellard | |
605 | 3475187d | bellard | static inline void gen_movl_imm_T1(uint32_t val) |
606 | 7a3f1944 | bellard | { |
607 | cf495bcf | bellard | gen_movl_imm_TN(1, val);
|
608 | 7a3f1944 | bellard | } |
609 | 7a3f1944 | bellard | |
610 | 3475187d | bellard | static inline void gen_movl_imm_T0(uint32_t val) |
611 | 7a3f1944 | bellard | { |
612 | cf495bcf | bellard | gen_movl_imm_TN(0, val);
|
613 | 7a3f1944 | bellard | } |
614 | 7a3f1944 | bellard | |
615 | 3475187d | bellard | static inline void gen_movl_simm_TN(int reg, int32_t imm) |
616 | 3475187d | bellard | { |
617 | 3475187d | bellard | gen_op_movl_TN_sim[reg](imm); |
618 | 3475187d | bellard | } |
619 | 3475187d | bellard | |
620 | 3475187d | bellard | static inline void gen_movl_simm_T1(int32_t val) |
621 | 3475187d | bellard | { |
622 | 3475187d | bellard | gen_movl_simm_TN(1, val);
|
623 | 3475187d | bellard | } |
624 | 3475187d | bellard | |
625 | 3475187d | bellard | static inline void gen_movl_simm_T0(int32_t val) |
626 | 3475187d | bellard | { |
627 | 3475187d | bellard | gen_movl_simm_TN(0, val);
|
628 | 3475187d | bellard | } |
629 | 3475187d | bellard | |
630 | cf495bcf | bellard | static inline void gen_movl_reg_TN(int reg, int t) |
631 | 7a3f1944 | bellard | { |
632 | cf495bcf | bellard | if (reg)
|
633 | 0f8a249a | blueswir1 | gen_op_movl_reg_TN[t][reg] (); |
634 | cf495bcf | bellard | else
|
635 | 0f8a249a | blueswir1 | gen_movl_imm_TN(t, 0);
|
636 | 7a3f1944 | bellard | } |
637 | 7a3f1944 | bellard | |
638 | cf495bcf | bellard | static inline void gen_movl_reg_T0(int reg) |
639 | 7a3f1944 | bellard | { |
640 | cf495bcf | bellard | gen_movl_reg_TN(reg, 0);
|
641 | 7a3f1944 | bellard | } |
642 | 7a3f1944 | bellard | |
643 | cf495bcf | bellard | static inline void gen_movl_reg_T1(int reg) |
644 | 7a3f1944 | bellard | { |
645 | cf495bcf | bellard | gen_movl_reg_TN(reg, 1);
|
646 | 7a3f1944 | bellard | } |
647 | 7a3f1944 | bellard | |
648 | cf495bcf | bellard | static inline void gen_movl_reg_T2(int reg) |
649 | 7a3f1944 | bellard | { |
650 | cf495bcf | bellard | gen_movl_reg_TN(reg, 2);
|
651 | 7a3f1944 | bellard | } |
652 | 7a3f1944 | bellard | |
653 | cf495bcf | bellard | static inline void gen_movl_TN_reg(int reg, int t) |
654 | 7a3f1944 | bellard | { |
655 | cf495bcf | bellard | if (reg)
|
656 | 0f8a249a | blueswir1 | gen_op_movl_TN_reg[t][reg] (); |
657 | 7a3f1944 | bellard | } |
658 | 7a3f1944 | bellard | |
659 | cf495bcf | bellard | static inline void gen_movl_T0_reg(int reg) |
660 | 7a3f1944 | bellard | { |
661 | cf495bcf | bellard | gen_movl_TN_reg(reg, 0);
|
662 | 7a3f1944 | bellard | } |
663 | 7a3f1944 | bellard | |
664 | cf495bcf | bellard | static inline void gen_movl_T1_reg(int reg) |
665 | 7a3f1944 | bellard | { |
666 | cf495bcf | bellard | gen_movl_TN_reg(reg, 1);
|
667 | 7a3f1944 | bellard | } |
668 | 7a3f1944 | bellard | |
669 | 3475187d | bellard | static inline void gen_jmp_im(target_ulong pc) |
670 | 3475187d | bellard | { |
671 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
672 | 3475187d | bellard | if (pc == (uint32_t)pc) {
|
673 | 3475187d | bellard | gen_op_jmp_im(pc); |
674 | 3475187d | bellard | } else {
|
675 | 3475187d | bellard | gen_op_jmp_im64(pc >> 32, pc);
|
676 | 3475187d | bellard | } |
677 | 3475187d | bellard | #else
|
678 | 3475187d | bellard | gen_op_jmp_im(pc); |
679 | 3475187d | bellard | #endif
|
680 | 3475187d | bellard | } |
681 | 3475187d | bellard | |
682 | 3475187d | bellard | static inline void gen_movl_npc_im(target_ulong npc) |
683 | 3475187d | bellard | { |
684 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
685 | 3475187d | bellard | if (npc == (uint32_t)npc) {
|
686 | 3475187d | bellard | gen_op_movl_npc_im(npc); |
687 | 3475187d | bellard | } else {
|
688 | 3475187d | bellard | gen_op_movq_npc_im64(npc >> 32, npc);
|
689 | 3475187d | bellard | } |
690 | 3475187d | bellard | #else
|
691 | 3475187d | bellard | gen_op_movl_npc_im(npc); |
692 | 3475187d | bellard | #endif
|
693 | 3475187d | bellard | } |
694 | 3475187d | bellard | |
695 | 5fafdf24 | ths | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
696 | 6e256c93 | bellard | target_ulong pc, target_ulong npc) |
697 | 6e256c93 | bellard | { |
698 | 6e256c93 | bellard | TranslationBlock *tb; |
699 | 6e256c93 | bellard | |
700 | 6e256c93 | bellard | tb = s->tb; |
701 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
|
702 | 6e256c93 | bellard | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { |
703 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
|
704 | 6e256c93 | bellard | if (tb_num == 0) |
705 | 6e256c93 | bellard | gen_op_goto_tb0(TBPARAM(tb)); |
706 | 6e256c93 | bellard | else
|
707 | 6e256c93 | bellard | gen_op_goto_tb1(TBPARAM(tb)); |
708 | 6e256c93 | bellard | gen_jmp_im(pc); |
709 | 6e256c93 | bellard | gen_movl_npc_im(npc); |
710 | 6e256c93 | bellard | gen_op_movl_T0_im((long)tb + tb_num);
|
711 | 6e256c93 | bellard | gen_op_exit_tb(); |
712 | 6e256c93 | bellard | } else {
|
713 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
|
714 | 6e256c93 | bellard | gen_jmp_im(pc); |
715 | 6e256c93 | bellard | gen_movl_npc_im(npc); |
716 | 6e256c93 | bellard | gen_op_movl_T0_0(); |
717 | 6e256c93 | bellard | gen_op_exit_tb(); |
718 | 6e256c93 | bellard | } |
719 | 6e256c93 | bellard | } |
720 | 6e256c93 | bellard | |
721 | 46525e1f | blueswir1 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
722 | 46525e1f | blueswir1 | target_ulong pc2) |
723 | 83469015 | bellard | { |
724 | 83469015 | bellard | int l1;
|
725 | 83469015 | bellard | |
726 | 83469015 | bellard | l1 = gen_new_label(); |
727 | 83469015 | bellard | |
728 | 83469015 | bellard | gen_op_jz_T2_label(l1); |
729 | 83469015 | bellard | |
730 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
731 | 83469015 | bellard | |
732 | 83469015 | bellard | gen_set_label(l1); |
733 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
734 | 83469015 | bellard | } |
735 | 83469015 | bellard | |
736 | 46525e1f | blueswir1 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
737 | 46525e1f | blueswir1 | target_ulong pc2) |
738 | 83469015 | bellard | { |
739 | 83469015 | bellard | int l1;
|
740 | 83469015 | bellard | |
741 | 83469015 | bellard | l1 = gen_new_label(); |
742 | 83469015 | bellard | |
743 | 83469015 | bellard | gen_op_jz_T2_label(l1); |
744 | 83469015 | bellard | |
745 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc2, pc1);
|
746 | 83469015 | bellard | |
747 | 83469015 | bellard | gen_set_label(l1); |
748 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
749 | 83469015 | bellard | } |
750 | 83469015 | bellard | |
751 | 46525e1f | blueswir1 | static inline void gen_branch(DisasContext *dc, target_ulong pc, |
752 | 46525e1f | blueswir1 | target_ulong npc) |
753 | 83469015 | bellard | { |
754 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc, npc);
|
755 | 83469015 | bellard | } |
756 | 83469015 | bellard | |
757 | 46525e1f | blueswir1 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2) |
758 | 83469015 | bellard | { |
759 | 83469015 | bellard | int l1, l2;
|
760 | 83469015 | bellard | |
761 | 83469015 | bellard | l1 = gen_new_label(); |
762 | 83469015 | bellard | l2 = gen_new_label(); |
763 | 83469015 | bellard | gen_op_jz_T2_label(l1); |
764 | 83469015 | bellard | |
765 | 83469015 | bellard | gen_movl_npc_im(npc1); |
766 | 83469015 | bellard | gen_op_jmp_label(l2); |
767 | 83469015 | bellard | |
768 | 83469015 | bellard | gen_set_label(l1); |
769 | 83469015 | bellard | gen_movl_npc_im(npc2); |
770 | 83469015 | bellard | gen_set_label(l2); |
771 | 83469015 | bellard | } |
772 | 83469015 | bellard | |
773 | 83469015 | bellard | /* call this function before using T2 as it may have been set for a jump */
|
774 | 83469015 | bellard | static inline void flush_T2(DisasContext * dc) |
775 | 83469015 | bellard | { |
776 | 83469015 | bellard | if (dc->npc == JUMP_PC) {
|
777 | 46525e1f | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); |
778 | 83469015 | bellard | dc->npc = DYNAMIC_PC; |
779 | 83469015 | bellard | } |
780 | 83469015 | bellard | } |
781 | 83469015 | bellard | |
782 | 72cbca10 | bellard | static inline void save_npc(DisasContext * dc) |
783 | 72cbca10 | bellard | { |
784 | 72cbca10 | bellard | if (dc->npc == JUMP_PC) {
|
785 | 46525e1f | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); |
786 | 72cbca10 | bellard | dc->npc = DYNAMIC_PC; |
787 | 72cbca10 | bellard | } else if (dc->npc != DYNAMIC_PC) { |
788 | 3475187d | bellard | gen_movl_npc_im(dc->npc); |
789 | 72cbca10 | bellard | } |
790 | 72cbca10 | bellard | } |
791 | 72cbca10 | bellard | |
792 | 72cbca10 | bellard | static inline void save_state(DisasContext * dc) |
793 | 72cbca10 | bellard | { |
794 | 3475187d | bellard | gen_jmp_im(dc->pc); |
795 | 72cbca10 | bellard | save_npc(dc); |
796 | 72cbca10 | bellard | } |
797 | 72cbca10 | bellard | |
798 | 0bee699e | bellard | static inline void gen_mov_pc_npc(DisasContext * dc) |
799 | 0bee699e | bellard | { |
800 | 0bee699e | bellard | if (dc->npc == JUMP_PC) {
|
801 | 46525e1f | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); |
802 | 0bee699e | bellard | gen_op_mov_pc_npc(); |
803 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
804 | 0bee699e | bellard | } else if (dc->npc == DYNAMIC_PC) { |
805 | 0bee699e | bellard | gen_op_mov_pc_npc(); |
806 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
807 | 0bee699e | bellard | } else {
|
808 | 0bee699e | bellard | dc->pc = dc->npc; |
809 | 0bee699e | bellard | } |
810 | 0bee699e | bellard | } |
811 | 0bee699e | bellard | |
812 | 3475187d | bellard | static GenOpFunc * const gen_cond[2][16] = { |
813 | 3475187d | bellard | { |
814 | 0f8a249a | blueswir1 | gen_op_eval_bn, |
815 | 0f8a249a | blueswir1 | gen_op_eval_be, |
816 | 0f8a249a | blueswir1 | gen_op_eval_ble, |
817 | 0f8a249a | blueswir1 | gen_op_eval_bl, |
818 | 0f8a249a | blueswir1 | gen_op_eval_bleu, |
819 | 0f8a249a | blueswir1 | gen_op_eval_bcs, |
820 | 0f8a249a | blueswir1 | gen_op_eval_bneg, |
821 | 0f8a249a | blueswir1 | gen_op_eval_bvs, |
822 | 0f8a249a | blueswir1 | gen_op_eval_ba, |
823 | 0f8a249a | blueswir1 | gen_op_eval_bne, |
824 | 0f8a249a | blueswir1 | gen_op_eval_bg, |
825 | 0f8a249a | blueswir1 | gen_op_eval_bge, |
826 | 0f8a249a | blueswir1 | gen_op_eval_bgu, |
827 | 0f8a249a | blueswir1 | gen_op_eval_bcc, |
828 | 0f8a249a | blueswir1 | gen_op_eval_bpos, |
829 | 0f8a249a | blueswir1 | gen_op_eval_bvc, |
830 | 3475187d | bellard | }, |
831 | 3475187d | bellard | { |
832 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
833 | 0f8a249a | blueswir1 | gen_op_eval_bn, |
834 | 0f8a249a | blueswir1 | gen_op_eval_xbe, |
835 | 0f8a249a | blueswir1 | gen_op_eval_xble, |
836 | 0f8a249a | blueswir1 | gen_op_eval_xbl, |
837 | 0f8a249a | blueswir1 | gen_op_eval_xbleu, |
838 | 0f8a249a | blueswir1 | gen_op_eval_xbcs, |
839 | 0f8a249a | blueswir1 | gen_op_eval_xbneg, |
840 | 0f8a249a | blueswir1 | gen_op_eval_xbvs, |
841 | 0f8a249a | blueswir1 | gen_op_eval_ba, |
842 | 0f8a249a | blueswir1 | gen_op_eval_xbne, |
843 | 0f8a249a | blueswir1 | gen_op_eval_xbg, |
844 | 0f8a249a | blueswir1 | gen_op_eval_xbge, |
845 | 0f8a249a | blueswir1 | gen_op_eval_xbgu, |
846 | 0f8a249a | blueswir1 | gen_op_eval_xbcc, |
847 | 0f8a249a | blueswir1 | gen_op_eval_xbpos, |
848 | 0f8a249a | blueswir1 | gen_op_eval_xbvc, |
849 | 3475187d | bellard | #endif
|
850 | 3475187d | bellard | }, |
851 | 3475187d | bellard | }; |
852 | 3475187d | bellard | |
853 | 3475187d | bellard | static GenOpFunc * const gen_fcond[4][16] = { |
854 | 3475187d | bellard | { |
855 | 0f8a249a | blueswir1 | gen_op_eval_bn, |
856 | 0f8a249a | blueswir1 | gen_op_eval_fbne, |
857 | 0f8a249a | blueswir1 | gen_op_eval_fblg, |
858 | 0f8a249a | blueswir1 | gen_op_eval_fbul, |
859 | 0f8a249a | blueswir1 | gen_op_eval_fbl, |
860 | 0f8a249a | blueswir1 | gen_op_eval_fbug, |
861 | 0f8a249a | blueswir1 | gen_op_eval_fbg, |
862 | 0f8a249a | blueswir1 | gen_op_eval_fbu, |
863 | 0f8a249a | blueswir1 | gen_op_eval_ba, |
864 | 0f8a249a | blueswir1 | gen_op_eval_fbe, |
865 | 0f8a249a | blueswir1 | gen_op_eval_fbue, |
866 | 0f8a249a | blueswir1 | gen_op_eval_fbge, |
867 | 0f8a249a | blueswir1 | gen_op_eval_fbuge, |
868 | 0f8a249a | blueswir1 | gen_op_eval_fble, |
869 | 0f8a249a | blueswir1 | gen_op_eval_fbule, |
870 | 0f8a249a | blueswir1 | gen_op_eval_fbo, |
871 | 3475187d | bellard | }, |
872 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
873 | 3475187d | bellard | { |
874 | 0f8a249a | blueswir1 | gen_op_eval_bn, |
875 | 0f8a249a | blueswir1 | gen_op_eval_fbne_fcc1, |
876 | 0f8a249a | blueswir1 | gen_op_eval_fblg_fcc1, |
877 | 0f8a249a | blueswir1 | gen_op_eval_fbul_fcc1, |
878 | 0f8a249a | blueswir1 | gen_op_eval_fbl_fcc1, |
879 | 0f8a249a | blueswir1 | gen_op_eval_fbug_fcc1, |
880 | 0f8a249a | blueswir1 | gen_op_eval_fbg_fcc1, |
881 | 0f8a249a | blueswir1 | gen_op_eval_fbu_fcc1, |
882 | 0f8a249a | blueswir1 | gen_op_eval_ba, |
883 | 0f8a249a | blueswir1 | gen_op_eval_fbe_fcc1, |
884 | 0f8a249a | blueswir1 | gen_op_eval_fbue_fcc1, |
885 | 0f8a249a | blueswir1 | gen_op_eval_fbge_fcc1, |
886 | 0f8a249a | blueswir1 | gen_op_eval_fbuge_fcc1, |
887 | 0f8a249a | blueswir1 | gen_op_eval_fble_fcc1, |
888 | 0f8a249a | blueswir1 | gen_op_eval_fbule_fcc1, |
889 | 0f8a249a | blueswir1 | gen_op_eval_fbo_fcc1, |
890 | 3475187d | bellard | }, |
891 | 3475187d | bellard | { |
892 | 0f8a249a | blueswir1 | gen_op_eval_bn, |
893 | 0f8a249a | blueswir1 | gen_op_eval_fbne_fcc2, |
894 | 0f8a249a | blueswir1 | gen_op_eval_fblg_fcc2, |
895 | 0f8a249a | blueswir1 | gen_op_eval_fbul_fcc2, |
896 | 0f8a249a | blueswir1 | gen_op_eval_fbl_fcc2, |
897 | 0f8a249a | blueswir1 | gen_op_eval_fbug_fcc2, |
898 | 0f8a249a | blueswir1 | gen_op_eval_fbg_fcc2, |
899 | 0f8a249a | blueswir1 | gen_op_eval_fbu_fcc2, |
900 | 0f8a249a | blueswir1 | gen_op_eval_ba, |
901 | 0f8a249a | blueswir1 | gen_op_eval_fbe_fcc2, |
902 | 0f8a249a | blueswir1 | gen_op_eval_fbue_fcc2, |
903 | 0f8a249a | blueswir1 | gen_op_eval_fbge_fcc2, |
904 | 0f8a249a | blueswir1 | gen_op_eval_fbuge_fcc2, |
905 | 0f8a249a | blueswir1 | gen_op_eval_fble_fcc2, |
906 | 0f8a249a | blueswir1 | gen_op_eval_fbule_fcc2, |
907 | 0f8a249a | blueswir1 | gen_op_eval_fbo_fcc2, |
908 | 3475187d | bellard | }, |
909 | 3475187d | bellard | { |
910 | 0f8a249a | blueswir1 | gen_op_eval_bn, |
911 | 0f8a249a | blueswir1 | gen_op_eval_fbne_fcc3, |
912 | 0f8a249a | blueswir1 | gen_op_eval_fblg_fcc3, |
913 | 0f8a249a | blueswir1 | gen_op_eval_fbul_fcc3, |
914 | 0f8a249a | blueswir1 | gen_op_eval_fbl_fcc3, |
915 | 0f8a249a | blueswir1 | gen_op_eval_fbug_fcc3, |
916 | 0f8a249a | blueswir1 | gen_op_eval_fbg_fcc3, |
917 | 0f8a249a | blueswir1 | gen_op_eval_fbu_fcc3, |
918 | 0f8a249a | blueswir1 | gen_op_eval_ba, |
919 | 0f8a249a | blueswir1 | gen_op_eval_fbe_fcc3, |
920 | 0f8a249a | blueswir1 | gen_op_eval_fbue_fcc3, |
921 | 0f8a249a | blueswir1 | gen_op_eval_fbge_fcc3, |
922 | 0f8a249a | blueswir1 | gen_op_eval_fbuge_fcc3, |
923 | 0f8a249a | blueswir1 | gen_op_eval_fble_fcc3, |
924 | 0f8a249a | blueswir1 | gen_op_eval_fbule_fcc3, |
925 | 0f8a249a | blueswir1 | gen_op_eval_fbo_fcc3, |
926 | 3475187d | bellard | }, |
927 | 3475187d | bellard | #else
|
928 | 3475187d | bellard | {}, {}, {}, |
929 | 3475187d | bellard | #endif
|
930 | 3475187d | bellard | }; |
931 | 7a3f1944 | bellard | |
932 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
933 | 3475187d | bellard | static void gen_cond_reg(int cond) |
934 | e8af50a3 | bellard | { |
935 | 0f8a249a | blueswir1 | switch (cond) {
|
936 | 0f8a249a | blueswir1 | case 0x1: |
937 | 0f8a249a | blueswir1 | gen_op_eval_brz(); |
938 | 0f8a249a | blueswir1 | break;
|
939 | 0f8a249a | blueswir1 | case 0x2: |
940 | 0f8a249a | blueswir1 | gen_op_eval_brlez(); |
941 | 0f8a249a | blueswir1 | break;
|
942 | 0f8a249a | blueswir1 | case 0x3: |
943 | 0f8a249a | blueswir1 | gen_op_eval_brlz(); |
944 | 0f8a249a | blueswir1 | break;
|
945 | 0f8a249a | blueswir1 | case 0x5: |
946 | 0f8a249a | blueswir1 | gen_op_eval_brnz(); |
947 | 0f8a249a | blueswir1 | break;
|
948 | 0f8a249a | blueswir1 | case 0x6: |
949 | 0f8a249a | blueswir1 | gen_op_eval_brgz(); |
950 | 0f8a249a | blueswir1 | break;
|
951 | e8af50a3 | bellard | default:
|
952 | 0f8a249a | blueswir1 | case 0x7: |
953 | 0f8a249a | blueswir1 | gen_op_eval_brgez(); |
954 | 0f8a249a | blueswir1 | break;
|
955 | 0f8a249a | blueswir1 | } |
956 | e8af50a3 | bellard | } |
957 | 3475187d | bellard | #endif
|
958 | cf495bcf | bellard | |
959 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
960 | 3475187d | bellard | static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
961 | 7a3f1944 | bellard | { |
962 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
963 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
964 | 5fafdf24 | ths | |
965 | cf495bcf | bellard | if (cond == 0x0) { |
966 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
967 | 0f8a249a | blueswir1 | if (a) {
|
968 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
969 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
970 | 0f8a249a | blueswir1 | } else {
|
971 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
972 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
973 | 0f8a249a | blueswir1 | } |
974 | cf495bcf | bellard | } else if (cond == 0x8) { |
975 | 0f8a249a | blueswir1 | /* unconditional taken */
|
976 | 0f8a249a | blueswir1 | if (a) {
|
977 | 0f8a249a | blueswir1 | dc->pc = target; |
978 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
979 | 0f8a249a | blueswir1 | } else {
|
980 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
981 | 0f8a249a | blueswir1 | dc->npc = target; |
982 | 0f8a249a | blueswir1 | } |
983 | cf495bcf | bellard | } else {
|
984 | 72cbca10 | bellard | flush_T2(dc); |
985 | 3475187d | bellard | gen_cond[cc][cond](); |
986 | 0f8a249a | blueswir1 | if (a) {
|
987 | 0f8a249a | blueswir1 | gen_branch_a(dc, target, dc->npc); |
988 | cf495bcf | bellard | dc->is_br = 1;
|
989 | 0f8a249a | blueswir1 | } else {
|
990 | cf495bcf | bellard | dc->pc = dc->npc; |
991 | 72cbca10 | bellard | dc->jump_pc[0] = target;
|
992 | 72cbca10 | bellard | dc->jump_pc[1] = dc->npc + 4; |
993 | 72cbca10 | bellard | dc->npc = JUMP_PC; |
994 | 0f8a249a | blueswir1 | } |
995 | cf495bcf | bellard | } |
996 | 7a3f1944 | bellard | } |
997 | 7a3f1944 | bellard | |
998 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
999 | 3475187d | bellard | static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
1000 | e8af50a3 | bellard | { |
1001 | e8af50a3 | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1002 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1003 | af7bf89b | bellard | |
1004 | e8af50a3 | bellard | if (cond == 0x0) { |
1005 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1006 | 0f8a249a | blueswir1 | if (a) {
|
1007 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1008 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1009 | 0f8a249a | blueswir1 | } else {
|
1010 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1011 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1012 | 0f8a249a | blueswir1 | } |
1013 | e8af50a3 | bellard | } else if (cond == 0x8) { |
1014 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1015 | 0f8a249a | blueswir1 | if (a) {
|
1016 | 0f8a249a | blueswir1 | dc->pc = target; |
1017 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1018 | 0f8a249a | blueswir1 | } else {
|
1019 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1020 | 0f8a249a | blueswir1 | dc->npc = target; |
1021 | 0f8a249a | blueswir1 | } |
1022 | e8af50a3 | bellard | } else {
|
1023 | e8af50a3 | bellard | flush_T2(dc); |
1024 | 3475187d | bellard | gen_fcond[cc][cond](); |
1025 | 0f8a249a | blueswir1 | if (a) {
|
1026 | 0f8a249a | blueswir1 | gen_branch_a(dc, target, dc->npc); |
1027 | e8af50a3 | bellard | dc->is_br = 1;
|
1028 | 0f8a249a | blueswir1 | } else {
|
1029 | e8af50a3 | bellard | dc->pc = dc->npc; |
1030 | e8af50a3 | bellard | dc->jump_pc[0] = target;
|
1031 | e8af50a3 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1032 | e8af50a3 | bellard | dc->npc = JUMP_PC; |
1033 | 0f8a249a | blueswir1 | } |
1034 | e8af50a3 | bellard | } |
1035 | e8af50a3 | bellard | } |
1036 | e8af50a3 | bellard | |
1037 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1038 | 3475187d | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1039 | 3475187d | bellard | static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn) |
1040 | 7a3f1944 | bellard | { |
1041 | 3475187d | bellard | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1042 | 3475187d | bellard | target_ulong target = dc->pc + offset; |
1043 | 3475187d | bellard | |
1044 | 3475187d | bellard | flush_T2(dc); |
1045 | 3475187d | bellard | gen_cond_reg(cond); |
1046 | 3475187d | bellard | if (a) {
|
1047 | 0f8a249a | blueswir1 | gen_branch_a(dc, target, dc->npc); |
1048 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
1049 | 3475187d | bellard | } else {
|
1050 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1051 | 0f8a249a | blueswir1 | dc->jump_pc[0] = target;
|
1052 | 0f8a249a | blueswir1 | dc->jump_pc[1] = dc->npc + 4; |
1053 | 0f8a249a | blueswir1 | dc->npc = JUMP_PC; |
1054 | 3475187d | bellard | } |
1055 | 7a3f1944 | bellard | } |
1056 | 7a3f1944 | bellard | |
1057 | 3475187d | bellard | static GenOpFunc * const gen_fcmps[4] = { |
1058 | 3475187d | bellard | gen_op_fcmps, |
1059 | 3475187d | bellard | gen_op_fcmps_fcc1, |
1060 | 3475187d | bellard | gen_op_fcmps_fcc2, |
1061 | 3475187d | bellard | gen_op_fcmps_fcc3, |
1062 | 3475187d | bellard | }; |
1063 | 3475187d | bellard | |
1064 | 3475187d | bellard | static GenOpFunc * const gen_fcmpd[4] = { |
1065 | 3475187d | bellard | gen_op_fcmpd, |
1066 | 3475187d | bellard | gen_op_fcmpd_fcc1, |
1067 | 3475187d | bellard | gen_op_fcmpd_fcc2, |
1068 | 3475187d | bellard | gen_op_fcmpd_fcc3, |
1069 | 3475187d | bellard | }; |
1070 | 417454b0 | blueswir1 | |
1071 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1072 | 1f587329 | blueswir1 | static GenOpFunc * const gen_fcmpq[4] = { |
1073 | 1f587329 | blueswir1 | gen_op_fcmpq, |
1074 | 1f587329 | blueswir1 | gen_op_fcmpq_fcc1, |
1075 | 1f587329 | blueswir1 | gen_op_fcmpq_fcc2, |
1076 | 1f587329 | blueswir1 | gen_op_fcmpq_fcc3, |
1077 | 1f587329 | blueswir1 | }; |
1078 | 1f587329 | blueswir1 | #endif
|
1079 | 1f587329 | blueswir1 | |
1080 | 417454b0 | blueswir1 | static GenOpFunc * const gen_fcmpes[4] = { |
1081 | 417454b0 | blueswir1 | gen_op_fcmpes, |
1082 | 417454b0 | blueswir1 | gen_op_fcmpes_fcc1, |
1083 | 417454b0 | blueswir1 | gen_op_fcmpes_fcc2, |
1084 | 417454b0 | blueswir1 | gen_op_fcmpes_fcc3, |
1085 | 417454b0 | blueswir1 | }; |
1086 | 417454b0 | blueswir1 | |
1087 | 417454b0 | blueswir1 | static GenOpFunc * const gen_fcmped[4] = { |
1088 | 417454b0 | blueswir1 | gen_op_fcmped, |
1089 | 417454b0 | blueswir1 | gen_op_fcmped_fcc1, |
1090 | 417454b0 | blueswir1 | gen_op_fcmped_fcc2, |
1091 | 417454b0 | blueswir1 | gen_op_fcmped_fcc3, |
1092 | 417454b0 | blueswir1 | }; |
1093 | 417454b0 | blueswir1 | |
1094 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1095 | 1f587329 | blueswir1 | static GenOpFunc * const gen_fcmpeq[4] = { |
1096 | 1f587329 | blueswir1 | gen_op_fcmpeq, |
1097 | 1f587329 | blueswir1 | gen_op_fcmpeq_fcc1, |
1098 | 1f587329 | blueswir1 | gen_op_fcmpeq_fcc2, |
1099 | 1f587329 | blueswir1 | gen_op_fcmpeq_fcc3, |
1100 | 1f587329 | blueswir1 | }; |
1101 | 1f587329 | blueswir1 | #endif
|
1102 | 3475187d | bellard | #endif
|
1103 | 3475187d | bellard | |
1104 | a80dde08 | bellard | static int gen_trap_ifnofpu(DisasContext * dc) |
1105 | a80dde08 | bellard | { |
1106 | a80dde08 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1107 | a80dde08 | bellard | if (!dc->fpu_enabled) {
|
1108 | a80dde08 | bellard | save_state(dc); |
1109 | a80dde08 | bellard | gen_op_exception(TT_NFPU_INSN); |
1110 | a80dde08 | bellard | dc->is_br = 1;
|
1111 | a80dde08 | bellard | return 1; |
1112 | a80dde08 | bellard | } |
1113 | a80dde08 | bellard | #endif
|
1114 | a80dde08 | bellard | return 0; |
1115 | a80dde08 | bellard | } |
1116 | a80dde08 | bellard | |
1117 | 0bee699e | bellard | /* before an instruction, dc->pc must be static */
|
1118 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc) |
1119 | cf495bcf | bellard | { |
1120 | cf495bcf | bellard | unsigned int insn, opc, rs1, rs2, rd; |
1121 | 7a3f1944 | bellard | |
1122 | 0fa85d43 | bellard | insn = ldl_code(dc->pc); |
1123 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
1124 | 7a3f1944 | bellard | |
1125 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
1126 | cf495bcf | bellard | switch (opc) {
|
1127 | 0f8a249a | blueswir1 | case 0: /* branches/sethi */ |
1128 | 0f8a249a | blueswir1 | { |
1129 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 9); |
1130 | 0f8a249a | blueswir1 | int32_t target; |
1131 | 0f8a249a | blueswir1 | switch (xop) {
|
1132 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1133 | 0f8a249a | blueswir1 | case 0x1: /* V9 BPcc */ |
1134 | 0f8a249a | blueswir1 | { |
1135 | 0f8a249a | blueswir1 | int cc;
|
1136 | 0f8a249a | blueswir1 | |
1137 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1138 | 0f8a249a | blueswir1 | target = sign_extend(target, 18);
|
1139 | 0f8a249a | blueswir1 | target <<= 2;
|
1140 | 0f8a249a | blueswir1 | cc = GET_FIELD_SP(insn, 20, 21); |
1141 | 0f8a249a | blueswir1 | if (cc == 0) |
1142 | 0f8a249a | blueswir1 | do_branch(dc, target, insn, 0);
|
1143 | 0f8a249a | blueswir1 | else if (cc == 2) |
1144 | 0f8a249a | blueswir1 | do_branch(dc, target, insn, 1);
|
1145 | 0f8a249a | blueswir1 | else
|
1146 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1147 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1148 | 0f8a249a | blueswir1 | } |
1149 | 0f8a249a | blueswir1 | case 0x3: /* V9 BPr */ |
1150 | 0f8a249a | blueswir1 | { |
1151 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 13) | |
1152 | 13846e70 | bellard | (GET_FIELD_SP(insn, 20, 21) << 14); |
1153 | 0f8a249a | blueswir1 | target = sign_extend(target, 16);
|
1154 | 0f8a249a | blueswir1 | target <<= 2;
|
1155 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1156 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
1157 | 0f8a249a | blueswir1 | do_branch_reg(dc, target, insn); |
1158 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1159 | 0f8a249a | blueswir1 | } |
1160 | 0f8a249a | blueswir1 | case 0x5: /* V9 FBPcc */ |
1161 | 0f8a249a | blueswir1 | { |
1162 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 20, 21); |
1163 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
1164 | a80dde08 | bellard | goto jmp_insn;
|
1165 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1166 | 0f8a249a | blueswir1 | target = sign_extend(target, 19);
|
1167 | 0f8a249a | blueswir1 | target <<= 2;
|
1168 | 0f8a249a | blueswir1 | do_fbranch(dc, target, insn, cc); |
1169 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1170 | 0f8a249a | blueswir1 | } |
1171 | a4d17f19 | blueswir1 | #else
|
1172 | 0f8a249a | blueswir1 | case 0x7: /* CBN+x */ |
1173 | 0f8a249a | blueswir1 | { |
1174 | 0f8a249a | blueswir1 | goto ncp_insn;
|
1175 | 0f8a249a | blueswir1 | } |
1176 | 0f8a249a | blueswir1 | #endif
|
1177 | 0f8a249a | blueswir1 | case 0x2: /* BN+x */ |
1178 | 0f8a249a | blueswir1 | { |
1179 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1180 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1181 | 0f8a249a | blueswir1 | target <<= 2;
|
1182 | 0f8a249a | blueswir1 | do_branch(dc, target, insn, 0);
|
1183 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1184 | 0f8a249a | blueswir1 | } |
1185 | 0f8a249a | blueswir1 | case 0x6: /* FBN+x */ |
1186 | 0f8a249a | blueswir1 | { |
1187 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
1188 | a80dde08 | bellard | goto jmp_insn;
|
1189 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1190 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1191 | 0f8a249a | blueswir1 | target <<= 2;
|
1192 | 0f8a249a | blueswir1 | do_fbranch(dc, target, insn, 0);
|
1193 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1194 | 0f8a249a | blueswir1 | } |
1195 | 0f8a249a | blueswir1 | case 0x4: /* SETHI */ |
1196 | e80cfcfc | bellard | #define OPTIM
|
1197 | e80cfcfc | bellard | #if defined(OPTIM)
|
1198 | 0f8a249a | blueswir1 | if (rd) { // nop |
1199 | e80cfcfc | bellard | #endif
|
1200 | 0f8a249a | blueswir1 | uint32_t value = GET_FIELD(insn, 10, 31); |
1201 | 0f8a249a | blueswir1 | gen_movl_imm_T0(value << 10);
|
1202 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
1203 | e80cfcfc | bellard | #if defined(OPTIM)
|
1204 | 0f8a249a | blueswir1 | } |
1205 | e80cfcfc | bellard | #endif
|
1206 | 0f8a249a | blueswir1 | break;
|
1207 | 0f8a249a | blueswir1 | case 0x0: /* UNIMPL */ |
1208 | 0f8a249a | blueswir1 | default:
|
1209 | 3475187d | bellard | goto illegal_insn;
|
1210 | 0f8a249a | blueswir1 | } |
1211 | 0f8a249a | blueswir1 | break;
|
1212 | 0f8a249a | blueswir1 | } |
1213 | 0f8a249a | blueswir1 | break;
|
1214 | cf495bcf | bellard | case 1: |
1215 | 0f8a249a | blueswir1 | /*CALL*/ {
|
1216 | 0f8a249a | blueswir1 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
1217 | cf495bcf | bellard | |
1218 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
1219 | 0f8a249a | blueswir1 | if (dc->pc == (uint32_t)dc->pc) {
|
1220 | 0f8a249a | blueswir1 | gen_op_movl_T0_im(dc->pc); |
1221 | 0f8a249a | blueswir1 | } else {
|
1222 | 0f8a249a | blueswir1 | gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
|
1223 | 0f8a249a | blueswir1 | } |
1224 | 83469015 | bellard | #else
|
1225 | 0f8a249a | blueswir1 | gen_op_movl_T0_im(dc->pc); |
1226 | 83469015 | bellard | #endif
|
1227 | 0f8a249a | blueswir1 | gen_movl_T0_reg(15);
|
1228 | 0f8a249a | blueswir1 | target += dc->pc; |
1229 | 0bee699e | bellard | gen_mov_pc_npc(dc); |
1230 | 0f8a249a | blueswir1 | dc->npc = target; |
1231 | 0f8a249a | blueswir1 | } |
1232 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1233 | 0f8a249a | blueswir1 | case 2: /* FPU & Logical Operations */ |
1234 | 0f8a249a | blueswir1 | { |
1235 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
1236 | 0f8a249a | blueswir1 | if (xop == 0x3a) { /* generate trap */ |
1237 | cf495bcf | bellard | int cond;
|
1238 | 3475187d | bellard | |
1239 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
1240 | cf495bcf | bellard | gen_movl_reg_T0(rs1); |
1241 | 0f8a249a | blueswir1 | if (IS_IMM) {
|
1242 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 25, 31); |
1243 | e80cfcfc | bellard | #if defined(OPTIM)
|
1244 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
1245 | e80cfcfc | bellard | #endif
|
1246 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
1247 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
1248 | e80cfcfc | bellard | #if defined(OPTIM)
|
1249 | 0f8a249a | blueswir1 | } |
1250 | e80cfcfc | bellard | #endif
|
1251 | cf495bcf | bellard | } else {
|
1252 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
1253 | e80cfcfc | bellard | #if defined(OPTIM)
|
1254 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
1255 | e80cfcfc | bellard | #endif
|
1256 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
1257 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
1258 | e80cfcfc | bellard | #if defined(OPTIM)
|
1259 | 0f8a249a | blueswir1 | } |
1260 | e80cfcfc | bellard | #endif
|
1261 | cf495bcf | bellard | } |
1262 | cf495bcf | bellard | cond = GET_FIELD(insn, 3, 6); |
1263 | cf495bcf | bellard | if (cond == 0x8) { |
1264 | a80dde08 | bellard | save_state(dc); |
1265 | cf495bcf | bellard | gen_op_trap_T0(); |
1266 | af7bf89b | bellard | } else if (cond != 0) { |
1267 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1268 | 0f8a249a | blueswir1 | /* V9 icc/xcc */
|
1269 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
1270 | 0f8a249a | blueswir1 | flush_T2(dc); |
1271 | a80dde08 | bellard | save_state(dc); |
1272 | 0f8a249a | blueswir1 | if (cc == 0) |
1273 | 0f8a249a | blueswir1 | gen_cond[0][cond]();
|
1274 | 0f8a249a | blueswir1 | else if (cc == 2) |
1275 | 0f8a249a | blueswir1 | gen_cond[1][cond]();
|
1276 | 0f8a249a | blueswir1 | else
|
1277 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1278 | 3475187d | bellard | #else
|
1279 | 0f8a249a | blueswir1 | flush_T2(dc); |
1280 | a80dde08 | bellard | save_state(dc); |
1281 | 0f8a249a | blueswir1 | gen_cond[0][cond]();
|
1282 | 3475187d | bellard | #endif
|
1283 | cf495bcf | bellard | gen_op_trapcc_T0(); |
1284 | cf495bcf | bellard | } |
1285 | a80dde08 | bellard | gen_op_next_insn(); |
1286 | a80dde08 | bellard | gen_op_movl_T0_0(); |
1287 | a80dde08 | bellard | gen_op_exit_tb(); |
1288 | a80dde08 | bellard | dc->is_br = 1;
|
1289 | a80dde08 | bellard | goto jmp_insn;
|
1290 | cf495bcf | bellard | } else if (xop == 0x28) { |
1291 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
1292 | cf495bcf | bellard | switch(rs1) {
|
1293 | cf495bcf | bellard | case 0: /* rdy */ |
1294 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
1295 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
1296 | 65fe7b09 | blueswir1 | manual, rdy on the microSPARC
|
1297 | 65fe7b09 | blueswir1 | II */
|
1298 | 65fe7b09 | blueswir1 | case 0x0f: /* stbar in the SPARCv8 manual, |
1299 | 65fe7b09 | blueswir1 | rdy on the microSPARC II */
|
1300 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent in the |
1301 | 65fe7b09 | blueswir1 | SPARCv8 manual, rdy on the
|
1302 | 65fe7b09 | blueswir1 | microSPARC II */
|
1303 | 65fe7b09 | blueswir1 | #endif
|
1304 | 65fe7b09 | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); |
1305 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
1306 | cf495bcf | bellard | break;
|
1307 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1308 | 0f8a249a | blueswir1 | case 0x2: /* V9 rdccr */ |
1309 | 3475187d | bellard | gen_op_rdccr(); |
1310 | 3475187d | bellard | gen_movl_T0_reg(rd); |
1311 | 3475187d | bellard | break;
|
1312 | 0f8a249a | blueswir1 | case 0x3: /* V9 rdasi */ |
1313 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); |
1314 | 3475187d | bellard | gen_movl_T0_reg(rd); |
1315 | 3475187d | bellard | break;
|
1316 | 0f8a249a | blueswir1 | case 0x4: /* V9 rdtick */ |
1317 | 3475187d | bellard | gen_op_rdtick(); |
1318 | 3475187d | bellard | gen_movl_T0_reg(rd); |
1319 | 3475187d | bellard | break;
|
1320 | 0f8a249a | blueswir1 | case 0x5: /* V9 rdpc */ |
1321 | 0f8a249a | blueswir1 | if (dc->pc == (uint32_t)dc->pc) {
|
1322 | 0f8a249a | blueswir1 | gen_op_movl_T0_im(dc->pc); |
1323 | 0f8a249a | blueswir1 | } else {
|
1324 | 0f8a249a | blueswir1 | gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
|
1325 | 0f8a249a | blueswir1 | } |
1326 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
1327 | 0f8a249a | blueswir1 | break;
|
1328 | 0f8a249a | blueswir1 | case 0x6: /* V9 rdfprs */ |
1329 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); |
1330 | 3475187d | bellard | gen_movl_T0_reg(rd); |
1331 | 3475187d | bellard | break;
|
1332 | 65fe7b09 | blueswir1 | case 0xf: /* V9 membar */ |
1333 | 65fe7b09 | blueswir1 | break; /* no effect */ |
1334 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
1335 | 725cb90b | bellard | if (gen_trap_ifnofpu(dc))
|
1336 | 725cb90b | bellard | goto jmp_insn;
|
1337 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr)); |
1338 | 725cb90b | bellard | gen_movl_T0_reg(rd); |
1339 | 725cb90b | bellard | break;
|
1340 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
1341 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr)); |
1342 | 83469015 | bellard | gen_movl_T0_reg(rd); |
1343 | 83469015 | bellard | break;
|
1344 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
1345 | 20c9f095 | blueswir1 | gen_op_rdstick(); |
1346 | 83469015 | bellard | gen_movl_T0_reg(rd); |
1347 | 83469015 | bellard | break;
|
1348 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
1349 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); |
1350 | 83469015 | bellard | gen_movl_T0_reg(rd); |
1351 | 83469015 | bellard | break;
|
1352 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
1353 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
1354 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
1355 | 0f8a249a | blueswir1 | case 0x14: /* Softint set, WO */ |
1356 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear, WO */ |
1357 | 0f8a249a | blueswir1 | case 0x16: /* Softint write */ |
1358 | 3475187d | bellard | #endif
|
1359 | 3475187d | bellard | default:
|
1360 | cf495bcf | bellard | goto illegal_insn;
|
1361 | cf495bcf | bellard | } |
1362 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1363 | e9ebed4d | blueswir1 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
1364 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
1365 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
1366 | 0f8a249a | blueswir1 | goto priv_insn;
|
1367 | e8af50a3 | bellard | gen_op_rdpsr(); |
1368 | e9ebed4d | blueswir1 | #else
|
1369 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
1370 | e9ebed4d | blueswir1 | goto priv_insn;
|
1371 | e9ebed4d | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1372 | e9ebed4d | blueswir1 | switch (rs1) {
|
1373 | e9ebed4d | blueswir1 | case 0: // hpstate |
1374 | e9ebed4d | blueswir1 | // gen_op_rdhpstate();
|
1375 | e9ebed4d | blueswir1 | break;
|
1376 | e9ebed4d | blueswir1 | case 1: // htstate |
1377 | e9ebed4d | blueswir1 | // gen_op_rdhtstate();
|
1378 | e9ebed4d | blueswir1 | break;
|
1379 | e9ebed4d | blueswir1 | case 3: // hintp |
1380 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp)); |
1381 | e9ebed4d | blueswir1 | break;
|
1382 | e9ebed4d | blueswir1 | case 5: // htba |
1383 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, htba)); |
1384 | e9ebed4d | blueswir1 | break;
|
1385 | e9ebed4d | blueswir1 | case 6: // hver |
1386 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hver)); |
1387 | e9ebed4d | blueswir1 | break;
|
1388 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
1389 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); |
1390 | e9ebed4d | blueswir1 | break;
|
1391 | e9ebed4d | blueswir1 | default:
|
1392 | e9ebed4d | blueswir1 | goto illegal_insn;
|
1393 | e9ebed4d | blueswir1 | } |
1394 | e9ebed4d | blueswir1 | #endif
|
1395 | e8af50a3 | bellard | gen_movl_T0_reg(rd); |
1396 | e8af50a3 | bellard | break;
|
1397 | 3475187d | bellard | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
1398 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
1399 | 0f8a249a | blueswir1 | goto priv_insn;
|
1400 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1401 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
1402 | 0f8a249a | blueswir1 | switch (rs1) {
|
1403 | 0f8a249a | blueswir1 | case 0: // tpc |
1404 | 0f8a249a | blueswir1 | gen_op_rdtpc(); |
1405 | 0f8a249a | blueswir1 | break;
|
1406 | 0f8a249a | blueswir1 | case 1: // tnpc |
1407 | 0f8a249a | blueswir1 | gen_op_rdtnpc(); |
1408 | 0f8a249a | blueswir1 | break;
|
1409 | 0f8a249a | blueswir1 | case 2: // tstate |
1410 | 0f8a249a | blueswir1 | gen_op_rdtstate(); |
1411 | 0f8a249a | blueswir1 | break;
|
1412 | 0f8a249a | blueswir1 | case 3: // tt |
1413 | 0f8a249a | blueswir1 | gen_op_rdtt(); |
1414 | 0f8a249a | blueswir1 | break;
|
1415 | 0f8a249a | blueswir1 | case 4: // tick |
1416 | 0f8a249a | blueswir1 | gen_op_rdtick(); |
1417 | 0f8a249a | blueswir1 | break;
|
1418 | 0f8a249a | blueswir1 | case 5: // tba |
1419 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); |
1420 | 0f8a249a | blueswir1 | break;
|
1421 | 0f8a249a | blueswir1 | case 6: // pstate |
1422 | 0f8a249a | blueswir1 | gen_op_rdpstate(); |
1423 | 0f8a249a | blueswir1 | break;
|
1424 | 0f8a249a | blueswir1 | case 7: // tl |
1425 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); |
1426 | 0f8a249a | blueswir1 | break;
|
1427 | 0f8a249a | blueswir1 | case 8: // pil |
1428 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); |
1429 | 0f8a249a | blueswir1 | break;
|
1430 | 0f8a249a | blueswir1 | case 9: // cwp |
1431 | 0f8a249a | blueswir1 | gen_op_rdcwp(); |
1432 | 0f8a249a | blueswir1 | break;
|
1433 | 0f8a249a | blueswir1 | case 10: // cansave |
1434 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); |
1435 | 0f8a249a | blueswir1 | break;
|
1436 | 0f8a249a | blueswir1 | case 11: // canrestore |
1437 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); |
1438 | 0f8a249a | blueswir1 | break;
|
1439 | 0f8a249a | blueswir1 | case 12: // cleanwin |
1440 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); |
1441 | 0f8a249a | blueswir1 | break;
|
1442 | 0f8a249a | blueswir1 | case 13: // otherwin |
1443 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); |
1444 | 0f8a249a | blueswir1 | break;
|
1445 | 0f8a249a | blueswir1 | case 14: // wstate |
1446 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); |
1447 | 0f8a249a | blueswir1 | break;
|
1448 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
1449 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, gl)); |
1450 | e9ebed4d | blueswir1 | break;
|
1451 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
1452 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
1453 | e9ebed4d | blueswir1 | goto priv_insn;
|
1454 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr)); |
1455 | e9ebed4d | blueswir1 | break;
|
1456 | 0f8a249a | blueswir1 | case 31: // ver |
1457 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); |
1458 | 0f8a249a | blueswir1 | break;
|
1459 | 0f8a249a | blueswir1 | case 15: // fq |
1460 | 0f8a249a | blueswir1 | default:
|
1461 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1462 | 0f8a249a | blueswir1 | } |
1463 | 3475187d | bellard | #else
|
1464 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); |
1465 | 3475187d | bellard | #endif
|
1466 | e8af50a3 | bellard | gen_movl_T0_reg(rd); |
1467 | e8af50a3 | bellard | break;
|
1468 | 3475187d | bellard | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
1469 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1470 | 0f8a249a | blueswir1 | gen_op_flushw(); |
1471 | 3475187d | bellard | #else
|
1472 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
1473 | 0f8a249a | blueswir1 | goto priv_insn;
|
1474 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); |
1475 | e8af50a3 | bellard | gen_movl_T0_reg(rd); |
1476 | 3475187d | bellard | #endif
|
1477 | e8af50a3 | bellard | break;
|
1478 | e8af50a3 | bellard | #endif
|
1479 | 0f8a249a | blueswir1 | } else if (xop == 0x34) { /* FPU Operations */ |
1480 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
1481 | a80dde08 | bellard | goto jmp_insn;
|
1482 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
1483 | e8af50a3 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
1484 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
1485 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
1486 | 0f8a249a | blueswir1 | switch (xop) {
|
1487 | 0f8a249a | blueswir1 | case 0x1: /* fmovs */ |
1488 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs2); |
1489 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1490 | 0f8a249a | blueswir1 | break;
|
1491 | 0f8a249a | blueswir1 | case 0x5: /* fnegs */ |
1492 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1493 | 0f8a249a | blueswir1 | gen_op_fnegs(); |
1494 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1495 | 0f8a249a | blueswir1 | break;
|
1496 | 0f8a249a | blueswir1 | case 0x9: /* fabss */ |
1497 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1498 | 0f8a249a | blueswir1 | gen_op_fabss(); |
1499 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1500 | 0f8a249a | blueswir1 | break;
|
1501 | 0f8a249a | blueswir1 | case 0x29: /* fsqrts */ |
1502 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1503 | 0f8a249a | blueswir1 | gen_op_fsqrts(); |
1504 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1505 | 0f8a249a | blueswir1 | break;
|
1506 | 0f8a249a | blueswir1 | case 0x2a: /* fsqrtd */ |
1507 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1508 | 0f8a249a | blueswir1 | gen_op_fsqrtd(); |
1509 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1510 | 0f8a249a | blueswir1 | break;
|
1511 | 0f8a249a | blueswir1 | case 0x2b: /* fsqrtq */ |
1512 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1513 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1514 | 1f587329 | blueswir1 | gen_op_fsqrtq(); |
1515 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1516 | 1f587329 | blueswir1 | break;
|
1517 | 1f587329 | blueswir1 | #else
|
1518 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1519 | 1f587329 | blueswir1 | #endif
|
1520 | 0f8a249a | blueswir1 | case 0x41: |
1521 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
1522 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1523 | 0f8a249a | blueswir1 | gen_op_fadds(); |
1524 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1525 | 0f8a249a | blueswir1 | break;
|
1526 | 0f8a249a | blueswir1 | case 0x42: |
1527 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
1528 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1529 | 0f8a249a | blueswir1 | gen_op_faddd(); |
1530 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1531 | 0f8a249a | blueswir1 | break;
|
1532 | 0f8a249a | blueswir1 | case 0x43: /* faddq */ |
1533 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1534 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
1535 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1536 | 1f587329 | blueswir1 | gen_op_faddq(); |
1537 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1538 | 1f587329 | blueswir1 | break;
|
1539 | 1f587329 | blueswir1 | #else
|
1540 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1541 | 1f587329 | blueswir1 | #endif
|
1542 | 0f8a249a | blueswir1 | case 0x45: |
1543 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
1544 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1545 | 0f8a249a | blueswir1 | gen_op_fsubs(); |
1546 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1547 | 0f8a249a | blueswir1 | break;
|
1548 | 0f8a249a | blueswir1 | case 0x46: |
1549 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
1550 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1551 | 0f8a249a | blueswir1 | gen_op_fsubd(); |
1552 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1553 | 0f8a249a | blueswir1 | break;
|
1554 | 0f8a249a | blueswir1 | case 0x47: /* fsubq */ |
1555 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1556 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
1557 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1558 | 1f587329 | blueswir1 | gen_op_fsubq(); |
1559 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1560 | 1f587329 | blueswir1 | break;
|
1561 | 1f587329 | blueswir1 | #else
|
1562 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1563 | 1f587329 | blueswir1 | #endif
|
1564 | 0f8a249a | blueswir1 | case 0x49: |
1565 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
1566 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1567 | 0f8a249a | blueswir1 | gen_op_fmuls(); |
1568 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1569 | 0f8a249a | blueswir1 | break;
|
1570 | 0f8a249a | blueswir1 | case 0x4a: |
1571 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
1572 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1573 | 0f8a249a | blueswir1 | gen_op_fmuld(); |
1574 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(rd); |
1575 | 0f8a249a | blueswir1 | break;
|
1576 | 0f8a249a | blueswir1 | case 0x4b: /* fmulq */ |
1577 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1578 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
1579 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1580 | 1f587329 | blueswir1 | gen_op_fmulq(); |
1581 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1582 | 1f587329 | blueswir1 | break;
|
1583 | 1f587329 | blueswir1 | #else
|
1584 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1585 | 1f587329 | blueswir1 | #endif
|
1586 | 0f8a249a | blueswir1 | case 0x4d: |
1587 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
1588 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1589 | 0f8a249a | blueswir1 | gen_op_fdivs(); |
1590 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1591 | 0f8a249a | blueswir1 | break;
|
1592 | 0f8a249a | blueswir1 | case 0x4e: |
1593 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
1594 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1595 | 0f8a249a | blueswir1 | gen_op_fdivd(); |
1596 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1597 | 0f8a249a | blueswir1 | break;
|
1598 | 0f8a249a | blueswir1 | case 0x4f: /* fdivq */ |
1599 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1600 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
1601 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1602 | 1f587329 | blueswir1 | gen_op_fdivq(); |
1603 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1604 | 1f587329 | blueswir1 | break;
|
1605 | 1f587329 | blueswir1 | #else
|
1606 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1607 | 1f587329 | blueswir1 | #endif
|
1608 | 0f8a249a | blueswir1 | case 0x69: |
1609 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
1610 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1611 | 0f8a249a | blueswir1 | gen_op_fsmuld(); |
1612 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1613 | 0f8a249a | blueswir1 | break;
|
1614 | 0f8a249a | blueswir1 | case 0x6e: /* fdmulq */ |
1615 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1616 | 1f587329 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
1617 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1618 | 1f587329 | blueswir1 | gen_op_fdmulq(); |
1619 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1620 | 1f587329 | blueswir1 | break;
|
1621 | 1f587329 | blueswir1 | #else
|
1622 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1623 | 1f587329 | blueswir1 | #endif
|
1624 | 0f8a249a | blueswir1 | case 0xc4: |
1625 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1626 | 0f8a249a | blueswir1 | gen_op_fitos(); |
1627 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1628 | 0f8a249a | blueswir1 | break;
|
1629 | 0f8a249a | blueswir1 | case 0xc6: |
1630 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1631 | 0f8a249a | blueswir1 | gen_op_fdtos(); |
1632 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1633 | 0f8a249a | blueswir1 | break;
|
1634 | 0f8a249a | blueswir1 | case 0xc7: /* fqtos */ |
1635 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1636 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1637 | 1f587329 | blueswir1 | gen_op_fqtos(); |
1638 | 1f587329 | blueswir1 | gen_op_store_FT0_fpr(rd); |
1639 | 1f587329 | blueswir1 | break;
|
1640 | 1f587329 | blueswir1 | #else
|
1641 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1642 | 1f587329 | blueswir1 | #endif
|
1643 | 0f8a249a | blueswir1 | case 0xc8: |
1644 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1645 | 0f8a249a | blueswir1 | gen_op_fitod(); |
1646 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1647 | 0f8a249a | blueswir1 | break;
|
1648 | 0f8a249a | blueswir1 | case 0xc9: |
1649 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1650 | 0f8a249a | blueswir1 | gen_op_fstod(); |
1651 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1652 | 0f8a249a | blueswir1 | break;
|
1653 | 0f8a249a | blueswir1 | case 0xcb: /* fqtod */ |
1654 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1655 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1656 | 1f587329 | blueswir1 | gen_op_fqtod(); |
1657 | 1f587329 | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1658 | 1f587329 | blueswir1 | break;
|
1659 | 1f587329 | blueswir1 | #else
|
1660 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1661 | 1f587329 | blueswir1 | #endif
|
1662 | 0f8a249a | blueswir1 | case 0xcc: /* fitoq */ |
1663 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1664 | 1f587329 | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1665 | 1f587329 | blueswir1 | gen_op_fitoq(); |
1666 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1667 | 1f587329 | blueswir1 | break;
|
1668 | 1f587329 | blueswir1 | #else
|
1669 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1670 | 1f587329 | blueswir1 | #endif
|
1671 | 0f8a249a | blueswir1 | case 0xcd: /* fstoq */ |
1672 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1673 | 1f587329 | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1674 | 1f587329 | blueswir1 | gen_op_fstoq(); |
1675 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1676 | 1f587329 | blueswir1 | break;
|
1677 | 1f587329 | blueswir1 | #else
|
1678 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1679 | 1f587329 | blueswir1 | #endif
|
1680 | 0f8a249a | blueswir1 | case 0xce: /* fdtoq */ |
1681 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1682 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1683 | 1f587329 | blueswir1 | gen_op_fdtoq(); |
1684 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1685 | 1f587329 | blueswir1 | break;
|
1686 | 1f587329 | blueswir1 | #else
|
1687 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1688 | 1f587329 | blueswir1 | #endif
|
1689 | 0f8a249a | blueswir1 | case 0xd1: |
1690 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1691 | 0f8a249a | blueswir1 | gen_op_fstoi(); |
1692 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1693 | 0f8a249a | blueswir1 | break;
|
1694 | 0f8a249a | blueswir1 | case 0xd2: |
1695 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(rs2); |
1696 | 0f8a249a | blueswir1 | gen_op_fdtoi(); |
1697 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1698 | 0f8a249a | blueswir1 | break;
|
1699 | 0f8a249a | blueswir1 | case 0xd3: /* fqtoi */ |
1700 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1701 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1702 | 1f587329 | blueswir1 | gen_op_fqtoi(); |
1703 | 1f587329 | blueswir1 | gen_op_store_FT0_fpr(rd); |
1704 | 1f587329 | blueswir1 | break;
|
1705 | 1f587329 | blueswir1 | #else
|
1706 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1707 | 1f587329 | blueswir1 | #endif
|
1708 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1709 | 0f8a249a | blueswir1 | case 0x2: /* V9 fmovd */ |
1710 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
1711 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1712 | 0f8a249a | blueswir1 | break;
|
1713 | 1f587329 | blueswir1 | case 0x3: /* V9 fmovq */ |
1714 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1715 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
1716 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1717 | 1f587329 | blueswir1 | break;
|
1718 | 1f587329 | blueswir1 | #else
|
1719 | 1f587329 | blueswir1 | goto nfpu_insn;
|
1720 | 1f587329 | blueswir1 | #endif
|
1721 | 0f8a249a | blueswir1 | case 0x6: /* V9 fnegd */ |
1722 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1723 | 0f8a249a | blueswir1 | gen_op_fnegd(); |
1724 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1725 | 0f8a249a | blueswir1 | break;
|
1726 | 1f587329 | blueswir1 | case 0x7: /* V9 fnegq */ |
1727 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1728 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1729 | 1f587329 | blueswir1 | gen_op_fnegq(); |
1730 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1731 | 1f587329 | blueswir1 | break;
|
1732 | 1f587329 | blueswir1 | #else
|
1733 | 1f587329 | blueswir1 | goto nfpu_insn;
|
1734 | 1f587329 | blueswir1 | #endif
|
1735 | 0f8a249a | blueswir1 | case 0xa: /* V9 fabsd */ |
1736 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1737 | 0f8a249a | blueswir1 | gen_op_fabsd(); |
1738 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1739 | 0f8a249a | blueswir1 | break;
|
1740 | 1f587329 | blueswir1 | case 0xb: /* V9 fabsq */ |
1741 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1742 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1743 | 1f587329 | blueswir1 | gen_op_fabsq(); |
1744 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1745 | 1f587329 | blueswir1 | break;
|
1746 | 1f587329 | blueswir1 | #else
|
1747 | 1f587329 | blueswir1 | goto nfpu_insn;
|
1748 | 1f587329 | blueswir1 | #endif
|
1749 | 0f8a249a | blueswir1 | case 0x81: /* V9 fstox */ |
1750 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1751 | 0f8a249a | blueswir1 | gen_op_fstox(); |
1752 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1753 | 0f8a249a | blueswir1 | break;
|
1754 | 0f8a249a | blueswir1 | case 0x82: /* V9 fdtox */ |
1755 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1756 | 0f8a249a | blueswir1 | gen_op_fdtox(); |
1757 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1758 | 0f8a249a | blueswir1 | break;
|
1759 | 1f587329 | blueswir1 | case 0x83: /* V9 fqtox */ |
1760 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1761 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1762 | 1f587329 | blueswir1 | gen_op_fqtox(); |
1763 | 1f587329 | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1764 | 1f587329 | blueswir1 | break;
|
1765 | 1f587329 | blueswir1 | #else
|
1766 | 1f587329 | blueswir1 | goto nfpu_insn;
|
1767 | 1f587329 | blueswir1 | #endif
|
1768 | 0f8a249a | blueswir1 | case 0x84: /* V9 fxtos */ |
1769 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1770 | 0f8a249a | blueswir1 | gen_op_fxtos(); |
1771 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1772 | 0f8a249a | blueswir1 | break;
|
1773 | 0f8a249a | blueswir1 | case 0x88: /* V9 fxtod */ |
1774 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1775 | 0f8a249a | blueswir1 | gen_op_fxtod(); |
1776 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
1777 | 0f8a249a | blueswir1 | break;
|
1778 | 0f8a249a | blueswir1 | case 0x8c: /* V9 fxtoq */ |
1779 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1780 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
1781 | 1f587329 | blueswir1 | gen_op_fxtoq(); |
1782 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1783 | 1f587329 | blueswir1 | break;
|
1784 | 1f587329 | blueswir1 | #else
|
1785 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1786 | 0f8a249a | blueswir1 | #endif
|
1787 | 1f587329 | blueswir1 | #endif
|
1788 | 0f8a249a | blueswir1 | default:
|
1789 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1790 | 0f8a249a | blueswir1 | } |
1791 | 0f8a249a | blueswir1 | } else if (xop == 0x35) { /* FPU Operations */ |
1792 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1793 | 0f8a249a | blueswir1 | int cond;
|
1794 | 3475187d | bellard | #endif
|
1795 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
1796 | a80dde08 | bellard | goto jmp_insn;
|
1797 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
1798 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
1799 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
1800 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
1801 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1802 | 0f8a249a | blueswir1 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
1803 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1804 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rd); |
1805 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1806 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1807 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
1808 | 0f8a249a | blueswir1 | flush_T2(dc); |
1809 | 0f8a249a | blueswir1 | gen_cond_reg(cond); |
1810 | 0f8a249a | blueswir1 | gen_op_fmovs_cc(); |
1811 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1812 | 0f8a249a | blueswir1 | break;
|
1813 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
1814 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1815 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(rd); |
1816 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(rs2); |
1817 | 0f8a249a | blueswir1 | flush_T2(dc); |
1818 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1819 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
1820 | 0f8a249a | blueswir1 | gen_cond_reg(cond); |
1821 | 0f8a249a | blueswir1 | gen_op_fmovs_cc(); |
1822 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(rd); |
1823 | 0f8a249a | blueswir1 | break;
|
1824 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
1825 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1826 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1827 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
1828 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1829 | 1f587329 | blueswir1 | flush_T2(dc); |
1830 | 1f587329 | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1831 | 1f587329 | blueswir1 | gen_movl_reg_T0(rs1); |
1832 | 1f587329 | blueswir1 | gen_cond_reg(cond); |
1833 | 1f587329 | blueswir1 | gen_op_fmovq_cc(); |
1834 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1835 | 1f587329 | blueswir1 | break;
|
1836 | 1f587329 | blueswir1 | #else
|
1837 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1838 | 1f587329 | blueswir1 | #endif
|
1839 | 0f8a249a | blueswir1 | } |
1840 | 0f8a249a | blueswir1 | #endif
|
1841 | 0f8a249a | blueswir1 | switch (xop) {
|
1842 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1843 | 0f8a249a | blueswir1 | case 0x001: /* V9 fmovscc %fcc0 */ |
1844 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1845 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rd); |
1846 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1847 | 0f8a249a | blueswir1 | flush_T2(dc); |
1848 | 0f8a249a | blueswir1 | gen_fcond[0][cond]();
|
1849 | 0f8a249a | blueswir1 | gen_op_fmovs_cc(); |
1850 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1851 | 0f8a249a | blueswir1 | break;
|
1852 | 0f8a249a | blueswir1 | case 0x002: /* V9 fmovdcc %fcc0 */ |
1853 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1854 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(rd); |
1855 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(rs2); |
1856 | 0f8a249a | blueswir1 | flush_T2(dc); |
1857 | 0f8a249a | blueswir1 | gen_fcond[0][cond]();
|
1858 | 0f8a249a | blueswir1 | gen_op_fmovd_cc(); |
1859 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(rd); |
1860 | 0f8a249a | blueswir1 | break;
|
1861 | 0f8a249a | blueswir1 | case 0x003: /* V9 fmovqcc %fcc0 */ |
1862 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1863 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1864 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
1865 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1866 | 1f587329 | blueswir1 | flush_T2(dc); |
1867 | 1f587329 | blueswir1 | gen_fcond[0][cond]();
|
1868 | 1f587329 | blueswir1 | gen_op_fmovq_cc(); |
1869 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1870 | 1f587329 | blueswir1 | break;
|
1871 | 1f587329 | blueswir1 | #else
|
1872 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1873 | 1f587329 | blueswir1 | #endif
|
1874 | 0f8a249a | blueswir1 | case 0x041: /* V9 fmovscc %fcc1 */ |
1875 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1876 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rd); |
1877 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1878 | 0f8a249a | blueswir1 | flush_T2(dc); |
1879 | 0f8a249a | blueswir1 | gen_fcond[1][cond]();
|
1880 | 0f8a249a | blueswir1 | gen_op_fmovs_cc(); |
1881 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1882 | 0f8a249a | blueswir1 | break;
|
1883 | 0f8a249a | blueswir1 | case 0x042: /* V9 fmovdcc %fcc1 */ |
1884 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1885 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(rd); |
1886 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(rs2); |
1887 | 0f8a249a | blueswir1 | flush_T2(dc); |
1888 | 0f8a249a | blueswir1 | gen_fcond[1][cond]();
|
1889 | 0f8a249a | blueswir1 | gen_op_fmovd_cc(); |
1890 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(rd); |
1891 | 0f8a249a | blueswir1 | break;
|
1892 | 0f8a249a | blueswir1 | case 0x043: /* V9 fmovqcc %fcc1 */ |
1893 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1894 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1895 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
1896 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1897 | 1f587329 | blueswir1 | flush_T2(dc); |
1898 | 1f587329 | blueswir1 | gen_fcond[1][cond]();
|
1899 | 1f587329 | blueswir1 | gen_op_fmovq_cc(); |
1900 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1901 | 1f587329 | blueswir1 | break;
|
1902 | 1f587329 | blueswir1 | #else
|
1903 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1904 | 1f587329 | blueswir1 | #endif
|
1905 | 0f8a249a | blueswir1 | case 0x081: /* V9 fmovscc %fcc2 */ |
1906 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1907 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rd); |
1908 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1909 | 0f8a249a | blueswir1 | flush_T2(dc); |
1910 | 0f8a249a | blueswir1 | gen_fcond[2][cond]();
|
1911 | 0f8a249a | blueswir1 | gen_op_fmovs_cc(); |
1912 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1913 | 0f8a249a | blueswir1 | break;
|
1914 | 0f8a249a | blueswir1 | case 0x082: /* V9 fmovdcc %fcc2 */ |
1915 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1916 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(rd); |
1917 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(rs2); |
1918 | 0f8a249a | blueswir1 | flush_T2(dc); |
1919 | 0f8a249a | blueswir1 | gen_fcond[2][cond]();
|
1920 | 0f8a249a | blueswir1 | gen_op_fmovd_cc(); |
1921 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(rd); |
1922 | 0f8a249a | blueswir1 | break;
|
1923 | 0f8a249a | blueswir1 | case 0x083: /* V9 fmovqcc %fcc2 */ |
1924 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1925 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1926 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(rd); |
1927 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(rs2); |
1928 | 1f587329 | blueswir1 | flush_T2(dc); |
1929 | 1f587329 | blueswir1 | gen_fcond[2][cond]();
|
1930 | 1f587329 | blueswir1 | gen_op_fmovq_cc(); |
1931 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(rd); |
1932 | 1f587329 | blueswir1 | break;
|
1933 | 1f587329 | blueswir1 | #else
|
1934 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1935 | 1f587329 | blueswir1 | #endif
|
1936 | 0f8a249a | blueswir1 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
1937 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1938 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rd); |
1939 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1940 | 0f8a249a | blueswir1 | flush_T2(dc); |
1941 | 0f8a249a | blueswir1 | gen_fcond[3][cond]();
|
1942 | 0f8a249a | blueswir1 | gen_op_fmovs_cc(); |
1943 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1944 | 0f8a249a | blueswir1 | break;
|
1945 | 0f8a249a | blueswir1 | case 0x0c2: /* V9 fmovdcc %fcc3 */ |
1946 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1947 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(rd); |
1948 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(rs2); |
1949 | 0f8a249a | blueswir1 | flush_T2(dc); |
1950 | 0f8a249a | blueswir1 | gen_fcond[3][cond]();
|
1951 | 0f8a249a | blueswir1 | gen_op_fmovd_cc(); |
1952 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(rd); |
1953 | 0f8a249a | blueswir1 | break;
|
1954 | 0f8a249a | blueswir1 | case 0x0c3: /* V9 fmovqcc %fcc3 */ |
1955 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1956 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1957 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
1958 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1959 | 1f587329 | blueswir1 | flush_T2(dc); |
1960 | 1f587329 | blueswir1 | gen_fcond[3][cond]();
|
1961 | 1f587329 | blueswir1 | gen_op_fmovq_cc(); |
1962 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
1963 | 1f587329 | blueswir1 | break;
|
1964 | 1f587329 | blueswir1 | #else
|
1965 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1966 | 1f587329 | blueswir1 | #endif
|
1967 | 0f8a249a | blueswir1 | case 0x101: /* V9 fmovscc %icc */ |
1968 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1969 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rd); |
1970 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
1971 | 0f8a249a | blueswir1 | flush_T2(dc); |
1972 | 0f8a249a | blueswir1 | gen_cond[0][cond]();
|
1973 | 0f8a249a | blueswir1 | gen_op_fmovs_cc(); |
1974 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
1975 | 0f8a249a | blueswir1 | break;
|
1976 | 0f8a249a | blueswir1 | case 0x102: /* V9 fmovdcc %icc */ |
1977 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1978 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(rd); |
1979 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(rs2); |
1980 | 0f8a249a | blueswir1 | flush_T2(dc); |
1981 | 0f8a249a | blueswir1 | gen_cond[0][cond]();
|
1982 | 0f8a249a | blueswir1 | gen_op_fmovd_cc(); |
1983 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(rd); |
1984 | 0f8a249a | blueswir1 | break;
|
1985 | 0f8a249a | blueswir1 | case 0x103: /* V9 fmovqcc %icc */ |
1986 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1987 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
1988 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(rd); |
1989 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(rs2); |
1990 | 1f587329 | blueswir1 | flush_T2(dc); |
1991 | 1f587329 | blueswir1 | gen_cond[0][cond]();
|
1992 | 1f587329 | blueswir1 | gen_op_fmovq_cc(); |
1993 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(rd); |
1994 | 1f587329 | blueswir1 | break;
|
1995 | 1f587329 | blueswir1 | #else
|
1996 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
1997 | 1f587329 | blueswir1 | #endif
|
1998 | 0f8a249a | blueswir1 | case 0x181: /* V9 fmovscc %xcc */ |
1999 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2000 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rd); |
2001 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2002 | 0f8a249a | blueswir1 | flush_T2(dc); |
2003 | 0f8a249a | blueswir1 | gen_cond[1][cond]();
|
2004 | 0f8a249a | blueswir1 | gen_op_fmovs_cc(); |
2005 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2006 | 0f8a249a | blueswir1 | break;
|
2007 | 0f8a249a | blueswir1 | case 0x182: /* V9 fmovdcc %xcc */ |
2008 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2009 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(rd); |
2010 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2011 | 0f8a249a | blueswir1 | flush_T2(dc); |
2012 | 0f8a249a | blueswir1 | gen_cond[1][cond]();
|
2013 | 0f8a249a | blueswir1 | gen_op_fmovd_cc(); |
2014 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(rd); |
2015 | 0f8a249a | blueswir1 | break;
|
2016 | 0f8a249a | blueswir1 | case 0x183: /* V9 fmovqcc %xcc */ |
2017 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2018 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2019 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(rd); |
2020 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(rs2); |
2021 | 1f587329 | blueswir1 | flush_T2(dc); |
2022 | 1f587329 | blueswir1 | gen_cond[1][cond]();
|
2023 | 1f587329 | blueswir1 | gen_op_fmovq_cc(); |
2024 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(rd); |
2025 | 1f587329 | blueswir1 | break;
|
2026 | 1f587329 | blueswir1 | #else
|
2027 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2028 | 0f8a249a | blueswir1 | #endif
|
2029 | 1f587329 | blueswir1 | #endif
|
2030 | 1f587329 | blueswir1 | case 0x51: /* fcmps, V9 %fcc */ |
2031 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2032 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2033 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2034 | 0f8a249a | blueswir1 | gen_fcmps[rd & 3]();
|
2035 | 3475187d | bellard | #else
|
2036 | 0f8a249a | blueswir1 | gen_op_fcmps(); |
2037 | 3475187d | bellard | #endif
|
2038 | 0f8a249a | blueswir1 | break;
|
2039 | 1f587329 | blueswir1 | case 0x52: /* fcmpd, V9 %fcc */ |
2040 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2041 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2042 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2043 | 0f8a249a | blueswir1 | gen_fcmpd[rd & 3]();
|
2044 | 3475187d | bellard | #else
|
2045 | 0f8a249a | blueswir1 | gen_op_fcmpd(); |
2046 | 0f8a249a | blueswir1 | #endif
|
2047 | 0f8a249a | blueswir1 | break;
|
2048 | 1f587329 | blueswir1 | case 0x53: /* fcmpq, V9 %fcc */ |
2049 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2050 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2051 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2052 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
2053 | 1f587329 | blueswir1 | gen_fcmpq[rd & 3]();
|
2054 | 1f587329 | blueswir1 | #else
|
2055 | 1f587329 | blueswir1 | gen_op_fcmpq(); |
2056 | 1f587329 | blueswir1 | #endif
|
2057 | 1f587329 | blueswir1 | break;
|
2058 | 1f587329 | blueswir1 | #else /* !defined(CONFIG_USER_ONLY) */ |
2059 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2060 | 1f587329 | blueswir1 | #endif
|
2061 | 0f8a249a | blueswir1 | case 0x55: /* fcmpes, V9 %fcc */ |
2062 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2063 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2064 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2065 | 0f8a249a | blueswir1 | gen_fcmpes[rd & 3]();
|
2066 | 3475187d | bellard | #else
|
2067 | 0f8a249a | blueswir1 | gen_op_fcmpes(); |
2068 | 3475187d | bellard | #endif
|
2069 | 0f8a249a | blueswir1 | break;
|
2070 | 0f8a249a | blueswir1 | case 0x56: /* fcmped, V9 %fcc */ |
2071 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2072 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2073 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2074 | 0f8a249a | blueswir1 | gen_fcmped[rd & 3]();
|
2075 | 3475187d | bellard | #else
|
2076 | 0f8a249a | blueswir1 | gen_op_fcmped(); |
2077 | 0f8a249a | blueswir1 | #endif
|
2078 | 0f8a249a | blueswir1 | break;
|
2079 | 1f587329 | blueswir1 | case 0x57: /* fcmpeq, V9 %fcc */ |
2080 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2081 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2082 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2083 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
2084 | 1f587329 | blueswir1 | gen_fcmpeq[rd & 3]();
|
2085 | 1f587329 | blueswir1 | #else
|
2086 | 1f587329 | blueswir1 | gen_op_fcmpeq(); |
2087 | 1f587329 | blueswir1 | #endif
|
2088 | 1f587329 | blueswir1 | break;
|
2089 | 1f587329 | blueswir1 | #else/* !defined(CONFIG_USER_ONLY) */ |
2090 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2091 | 1f587329 | blueswir1 | #endif
|
2092 | 0f8a249a | blueswir1 | default:
|
2093 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2094 | 0f8a249a | blueswir1 | } |
2095 | e80cfcfc | bellard | #if defined(OPTIM)
|
2096 | 0f8a249a | blueswir1 | } else if (xop == 0x2) { |
2097 | 0f8a249a | blueswir1 | // clr/mov shortcut
|
2098 | e80cfcfc | bellard | |
2099 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2100 | 0f8a249a | blueswir1 | if (rs1 == 0) { |
2101 | 0f8a249a | blueswir1 | // or %g0, x, y -> mov T1, x; mov y, T1
|
2102 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2103 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
2104 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
2105 | 0f8a249a | blueswir1 | } else { /* register */ |
2106 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2107 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
2108 | 0f8a249a | blueswir1 | } |
2109 | 0f8a249a | blueswir1 | gen_movl_T1_reg(rd); |
2110 | 0f8a249a | blueswir1 | } else {
|
2111 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2112 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2113 | 0f8a249a | blueswir1 | // or x, #0, y -> mov T1, x; mov y, T1
|
2114 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
2115 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2116 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
2117 | 0f8a249a | blueswir1 | gen_op_or_T1_T0(); |
2118 | 0f8a249a | blueswir1 | } |
2119 | 0f8a249a | blueswir1 | } else { /* register */ |
2120 | 0f8a249a | blueswir1 | // or x, %g0, y -> mov T1, x; mov y, T1
|
2121 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2122 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2123 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
2124 | 0f8a249a | blueswir1 | gen_op_or_T1_T0(); |
2125 | 0f8a249a | blueswir1 | } |
2126 | 0f8a249a | blueswir1 | } |
2127 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2128 | 0f8a249a | blueswir1 | } |
2129 | e80cfcfc | bellard | #endif
|
2130 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
2131 | 0f8a249a | blueswir1 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
2132 | 83469015 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2133 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2134 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2135 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2136 | 83469015 | bellard | gen_movl_simm_T1(rs2); |
2137 | 0f8a249a | blueswir1 | } else { /* register */ |
2138 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2139 | 83469015 | bellard | gen_movl_reg_T1(rs2); |
2140 | 83469015 | bellard | } |
2141 | 0f8a249a | blueswir1 | if (insn & (1 << 12)) |
2142 | 0f8a249a | blueswir1 | gen_op_sllx(); |
2143 | 0f8a249a | blueswir1 | else
|
2144 | 0f8a249a | blueswir1 | gen_op_sll(); |
2145 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2146 | 0f8a249a | blueswir1 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
2147 | 83469015 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2148 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2149 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2150 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2151 | 83469015 | bellard | gen_movl_simm_T1(rs2); |
2152 | 0f8a249a | blueswir1 | } else { /* register */ |
2153 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2154 | 83469015 | bellard | gen_movl_reg_T1(rs2); |
2155 | 83469015 | bellard | } |
2156 | 0f8a249a | blueswir1 | if (insn & (1 << 12)) |
2157 | 0f8a249a | blueswir1 | gen_op_srlx(); |
2158 | 0f8a249a | blueswir1 | else
|
2159 | 0f8a249a | blueswir1 | gen_op_srl(); |
2160 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2161 | 0f8a249a | blueswir1 | } else if (xop == 0x27) { /* sra, V9 srax */ |
2162 | 83469015 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2163 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2164 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2165 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2166 | 83469015 | bellard | gen_movl_simm_T1(rs2); |
2167 | 0f8a249a | blueswir1 | } else { /* register */ |
2168 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2169 | 83469015 | bellard | gen_movl_reg_T1(rs2); |
2170 | 83469015 | bellard | } |
2171 | 0f8a249a | blueswir1 | if (insn & (1 << 12)) |
2172 | 0f8a249a | blueswir1 | gen_op_srax(); |
2173 | 0f8a249a | blueswir1 | else
|
2174 | 0f8a249a | blueswir1 | gen_op_sra(); |
2175 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2176 | 83469015 | bellard | #endif
|
2177 | fcc72045 | blueswir1 | } else if (xop < 0x36) { |
2178 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2179 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2180 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2181 | cf495bcf | bellard | rs2 = GET_FIELDs(insn, 19, 31); |
2182 | 3475187d | bellard | gen_movl_simm_T1(rs2); |
2183 | 0f8a249a | blueswir1 | } else { /* register */ |
2184 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2185 | cf495bcf | bellard | gen_movl_reg_T1(rs2); |
2186 | cf495bcf | bellard | } |
2187 | cf495bcf | bellard | if (xop < 0x20) { |
2188 | cf495bcf | bellard | switch (xop & ~0x10) { |
2189 | cf495bcf | bellard | case 0x0: |
2190 | cf495bcf | bellard | if (xop & 0x10) |
2191 | cf495bcf | bellard | gen_op_add_T1_T0_cc(); |
2192 | cf495bcf | bellard | else
|
2193 | cf495bcf | bellard | gen_op_add_T1_T0(); |
2194 | cf495bcf | bellard | break;
|
2195 | cf495bcf | bellard | case 0x1: |
2196 | cf495bcf | bellard | gen_op_and_T1_T0(); |
2197 | cf495bcf | bellard | if (xop & 0x10) |
2198 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
2199 | cf495bcf | bellard | break;
|
2200 | cf495bcf | bellard | case 0x2: |
2201 | 0f8a249a | blueswir1 | gen_op_or_T1_T0(); |
2202 | 0f8a249a | blueswir1 | if (xop & 0x10) |
2203 | 0f8a249a | blueswir1 | gen_op_logic_T0_cc(); |
2204 | 0f8a249a | blueswir1 | break;
|
2205 | cf495bcf | bellard | case 0x3: |
2206 | cf495bcf | bellard | gen_op_xor_T1_T0(); |
2207 | cf495bcf | bellard | if (xop & 0x10) |
2208 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
2209 | cf495bcf | bellard | break;
|
2210 | cf495bcf | bellard | case 0x4: |
2211 | cf495bcf | bellard | if (xop & 0x10) |
2212 | cf495bcf | bellard | gen_op_sub_T1_T0_cc(); |
2213 | cf495bcf | bellard | else
|
2214 | cf495bcf | bellard | gen_op_sub_T1_T0(); |
2215 | cf495bcf | bellard | break;
|
2216 | cf495bcf | bellard | case 0x5: |
2217 | cf495bcf | bellard | gen_op_andn_T1_T0(); |
2218 | cf495bcf | bellard | if (xop & 0x10) |
2219 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
2220 | cf495bcf | bellard | break;
|
2221 | cf495bcf | bellard | case 0x6: |
2222 | cf495bcf | bellard | gen_op_orn_T1_T0(); |
2223 | cf495bcf | bellard | if (xop & 0x10) |
2224 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
2225 | cf495bcf | bellard | break;
|
2226 | cf495bcf | bellard | case 0x7: |
2227 | cf495bcf | bellard | gen_op_xnor_T1_T0(); |
2228 | cf495bcf | bellard | if (xop & 0x10) |
2229 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
2230 | cf495bcf | bellard | break;
|
2231 | cf495bcf | bellard | case 0x8: |
2232 | cf495bcf | bellard | if (xop & 0x10) |
2233 | af7bf89b | bellard | gen_op_addx_T1_T0_cc(); |
2234 | af7bf89b | bellard | else
|
2235 | af7bf89b | bellard | gen_op_addx_T1_T0(); |
2236 | cf495bcf | bellard | break;
|
2237 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
2238 | 0f8a249a | blueswir1 | case 0x9: /* V9 mulx */ |
2239 | ded3ab80 | pbrook | gen_op_mulx_T1_T0(); |
2240 | ded3ab80 | pbrook | break;
|
2241 | ded3ab80 | pbrook | #endif
|
2242 | cf495bcf | bellard | case 0xa: |
2243 | cf495bcf | bellard | gen_op_umul_T1_T0(); |
2244 | cf495bcf | bellard | if (xop & 0x10) |
2245 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
2246 | cf495bcf | bellard | break;
|
2247 | cf495bcf | bellard | case 0xb: |
2248 | cf495bcf | bellard | gen_op_smul_T1_T0(); |
2249 | cf495bcf | bellard | if (xop & 0x10) |
2250 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
2251 | cf495bcf | bellard | break;
|
2252 | cf495bcf | bellard | case 0xc: |
2253 | cf495bcf | bellard | if (xop & 0x10) |
2254 | af7bf89b | bellard | gen_op_subx_T1_T0_cc(); |
2255 | af7bf89b | bellard | else
|
2256 | af7bf89b | bellard | gen_op_subx_T1_T0(); |
2257 | cf495bcf | bellard | break;
|
2258 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
2259 | 0f8a249a | blueswir1 | case 0xd: /* V9 udivx */ |
2260 | ded3ab80 | pbrook | gen_op_udivx_T1_T0(); |
2261 | ded3ab80 | pbrook | break;
|
2262 | ded3ab80 | pbrook | #endif
|
2263 | cf495bcf | bellard | case 0xe: |
2264 | cf495bcf | bellard | gen_op_udiv_T1_T0(); |
2265 | cf495bcf | bellard | if (xop & 0x10) |
2266 | cf495bcf | bellard | gen_op_div_cc(); |
2267 | cf495bcf | bellard | break;
|
2268 | cf495bcf | bellard | case 0xf: |
2269 | cf495bcf | bellard | gen_op_sdiv_T1_T0(); |
2270 | cf495bcf | bellard | if (xop & 0x10) |
2271 | cf495bcf | bellard | gen_op_div_cc(); |
2272 | cf495bcf | bellard | break;
|
2273 | cf495bcf | bellard | default:
|
2274 | cf495bcf | bellard | goto illegal_insn;
|
2275 | cf495bcf | bellard | } |
2276 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2277 | cf495bcf | bellard | } else {
|
2278 | cf495bcf | bellard | switch (xop) {
|
2279 | 0f8a249a | blueswir1 | case 0x20: /* taddcc */ |
2280 | 0f8a249a | blueswir1 | gen_op_tadd_T1_T0_cc(); |
2281 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2282 | 0f8a249a | blueswir1 | break;
|
2283 | 0f8a249a | blueswir1 | case 0x21: /* tsubcc */ |
2284 | 0f8a249a | blueswir1 | gen_op_tsub_T1_T0_cc(); |
2285 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2286 | 0f8a249a | blueswir1 | break;
|
2287 | 0f8a249a | blueswir1 | case 0x22: /* taddcctv */ |
2288 | 90251fb9 | blueswir1 | save_state(dc); |
2289 | 0f8a249a | blueswir1 | gen_op_tadd_T1_T0_ccTV(); |
2290 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2291 | 0f8a249a | blueswir1 | break;
|
2292 | 0f8a249a | blueswir1 | case 0x23: /* tsubcctv */ |
2293 | 90251fb9 | blueswir1 | save_state(dc); |
2294 | 0f8a249a | blueswir1 | gen_op_tsub_T1_T0_ccTV(); |
2295 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2296 | 0f8a249a | blueswir1 | break;
|
2297 | cf495bcf | bellard | case 0x24: /* mulscc */ |
2298 | cf495bcf | bellard | gen_op_mulscc_T1_T0(); |
2299 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
2300 | cf495bcf | bellard | break;
|
2301 | 83469015 | bellard | #ifndef TARGET_SPARC64
|
2302 | 0f8a249a | blueswir1 | case 0x25: /* sll */ |
2303 | 0f8a249a | blueswir1 | gen_op_sll(); |
2304 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
2305 | cf495bcf | bellard | break;
|
2306 | 83469015 | bellard | case 0x26: /* srl */ |
2307 | 0f8a249a | blueswir1 | gen_op_srl(); |
2308 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
2309 | cf495bcf | bellard | break;
|
2310 | 83469015 | bellard | case 0x27: /* sra */ |
2311 | 0f8a249a | blueswir1 | gen_op_sra(); |
2312 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
2313 | cf495bcf | bellard | break;
|
2314 | 83469015 | bellard | #endif
|
2315 | cf495bcf | bellard | case 0x30: |
2316 | cf495bcf | bellard | { |
2317 | cf495bcf | bellard | switch(rd) {
|
2318 | 3475187d | bellard | case 0: /* wry */ |
2319 | 0f8a249a | blueswir1 | gen_op_xor_T1_T0(); |
2320 | 0f8a249a | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); |
2321 | cf495bcf | bellard | break;
|
2322 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
2323 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0f: /* undefined in the |
2324 | 65fe7b09 | blueswir1 | SPARCv8 manual, nop
|
2325 | 65fe7b09 | blueswir1 | on the microSPARC
|
2326 | 65fe7b09 | blueswir1 | II */
|
2327 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent |
2328 | 65fe7b09 | blueswir1 | in the SPARCv8
|
2329 | 65fe7b09 | blueswir1 | manual, nop on the
|
2330 | 65fe7b09 | blueswir1 | microSPARC II */
|
2331 | 65fe7b09 | blueswir1 | break;
|
2332 | 65fe7b09 | blueswir1 | #else
|
2333 | 0f8a249a | blueswir1 | case 0x2: /* V9 wrccr */ |
2334 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
2335 | 3475187d | bellard | gen_op_wrccr(); |
2336 | 0f8a249a | blueswir1 | break;
|
2337 | 0f8a249a | blueswir1 | case 0x3: /* V9 wrasi */ |
2338 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
2339 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); |
2340 | 0f8a249a | blueswir1 | break;
|
2341 | 0f8a249a | blueswir1 | case 0x6: /* V9 wrfprs */ |
2342 | 0f8a249a | blueswir1 | gen_op_xor_T1_T0(); |
2343 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); |
2344 | 3299908c | blueswir1 | save_state(dc); |
2345 | 3299908c | blueswir1 | gen_op_next_insn(); |
2346 | 3299908c | blueswir1 | gen_op_movl_T0_0(); |
2347 | 3299908c | blueswir1 | gen_op_exit_tb(); |
2348 | 3299908c | blueswir1 | dc->is_br = 1;
|
2349 | 0f8a249a | blueswir1 | break;
|
2350 | 0f8a249a | blueswir1 | case 0xf: /* V9 sir, nop if user */ |
2351 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY)
|
2352 | 0f8a249a | blueswir1 | if (supervisor(dc))
|
2353 | 0f8a249a | blueswir1 | gen_op_sir(); |
2354 | 3475187d | bellard | #endif
|
2355 | 0f8a249a | blueswir1 | break;
|
2356 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
2357 | 725cb90b | bellard | if (gen_trap_ifnofpu(dc))
|
2358 | 725cb90b | bellard | goto jmp_insn;
|
2359 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
2360 | 0f8a249a | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); |
2361 | 0f8a249a | blueswir1 | break;
|
2362 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
2363 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
2364 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2365 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2366 | 83469015 | bellard | #endif
|
2367 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
2368 | 20c9f095 | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr)); |
2369 | 20c9f095 | blueswir1 | gen_op_wrtick_cmpr(); |
2370 | 0f8a249a | blueswir1 | break;
|
2371 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
2372 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
2373 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2374 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2375 | 83469015 | bellard | #endif
|
2376 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
2377 | 20c9f095 | blueswir1 | gen_op_wrstick(); |
2378 | 0f8a249a | blueswir1 | break;
|
2379 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
2380 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
2381 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2382 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2383 | 3475187d | bellard | #endif
|
2384 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
2385 | 20c9f095 | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr)); |
2386 | 20c9f095 | blueswir1 | gen_op_wrstick_cmpr(); |
2387 | 0f8a249a | blueswir1 | break;
|
2388 | 83469015 | bellard | |
2389 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
2390 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
2391 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
2392 | 0f8a249a | blueswir1 | case 0x14: /* Softint set */ |
2393 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear */ |
2394 | 0f8a249a | blueswir1 | case 0x16: /* Softint write */ |
2395 | 83469015 | bellard | #endif
|
2396 | 3475187d | bellard | default:
|
2397 | cf495bcf | bellard | goto illegal_insn;
|
2398 | cf495bcf | bellard | } |
2399 | cf495bcf | bellard | } |
2400 | cf495bcf | bellard | break;
|
2401 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
2402 | af7bf89b | bellard | case 0x31: /* wrpsr, V9 saved, restored */ |
2403 | e8af50a3 | bellard | { |
2404 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2405 | 0f8a249a | blueswir1 | goto priv_insn;
|
2406 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2407 | 0f8a249a | blueswir1 | switch (rd) {
|
2408 | 0f8a249a | blueswir1 | case 0: |
2409 | 0f8a249a | blueswir1 | gen_op_saved(); |
2410 | 0f8a249a | blueswir1 | break;
|
2411 | 0f8a249a | blueswir1 | case 1: |
2412 | 0f8a249a | blueswir1 | gen_op_restored(); |
2413 | 0f8a249a | blueswir1 | break;
|
2414 | e9ebed4d | blueswir1 | case 2: /* UA2005 allclean */ |
2415 | e9ebed4d | blueswir1 | case 3: /* UA2005 otherw */ |
2416 | e9ebed4d | blueswir1 | case 4: /* UA2005 normalw */ |
2417 | e9ebed4d | blueswir1 | case 5: /* UA2005 invalw */ |
2418 | e9ebed4d | blueswir1 | // XXX
|
2419 | 0f8a249a | blueswir1 | default:
|
2420 | 3475187d | bellard | goto illegal_insn;
|
2421 | 3475187d | bellard | } |
2422 | 3475187d | bellard | #else
|
2423 | e8af50a3 | bellard | gen_op_xor_T1_T0(); |
2424 | e8af50a3 | bellard | gen_op_wrpsr(); |
2425 | 9e61bde5 | bellard | save_state(dc); |
2426 | 9e61bde5 | bellard | gen_op_next_insn(); |
2427 | 0f8a249a | blueswir1 | gen_op_movl_T0_0(); |
2428 | 0f8a249a | blueswir1 | gen_op_exit_tb(); |
2429 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
2430 | 3475187d | bellard | #endif
|
2431 | e8af50a3 | bellard | } |
2432 | e8af50a3 | bellard | break;
|
2433 | af7bf89b | bellard | case 0x32: /* wrwim, V9 wrpr */ |
2434 | e8af50a3 | bellard | { |
2435 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2436 | 0f8a249a | blueswir1 | goto priv_insn;
|
2437 | e8af50a3 | bellard | gen_op_xor_T1_T0(); |
2438 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2439 | 0f8a249a | blueswir1 | switch (rd) {
|
2440 | 0f8a249a | blueswir1 | case 0: // tpc |
2441 | 0f8a249a | blueswir1 | gen_op_wrtpc(); |
2442 | 0f8a249a | blueswir1 | break;
|
2443 | 0f8a249a | blueswir1 | case 1: // tnpc |
2444 | 0f8a249a | blueswir1 | gen_op_wrtnpc(); |
2445 | 0f8a249a | blueswir1 | break;
|
2446 | 0f8a249a | blueswir1 | case 2: // tstate |
2447 | 0f8a249a | blueswir1 | gen_op_wrtstate(); |
2448 | 0f8a249a | blueswir1 | break;
|
2449 | 0f8a249a | blueswir1 | case 3: // tt |
2450 | 0f8a249a | blueswir1 | gen_op_wrtt(); |
2451 | 0f8a249a | blueswir1 | break;
|
2452 | 0f8a249a | blueswir1 | case 4: // tick |
2453 | 0f8a249a | blueswir1 | gen_op_wrtick(); |
2454 | 0f8a249a | blueswir1 | break;
|
2455 | 0f8a249a | blueswir1 | case 5: // tba |
2456 | 0f8a249a | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
2457 | 0f8a249a | blueswir1 | break;
|
2458 | 0f8a249a | blueswir1 | case 6: // pstate |
2459 | 0f8a249a | blueswir1 | gen_op_wrpstate(); |
2460 | ded3ab80 | pbrook | save_state(dc); |
2461 | ded3ab80 | pbrook | gen_op_next_insn(); |
2462 | ded3ab80 | pbrook | gen_op_movl_T0_0(); |
2463 | ded3ab80 | pbrook | gen_op_exit_tb(); |
2464 | ded3ab80 | pbrook | dc->is_br = 1;
|
2465 | 0f8a249a | blueswir1 | break;
|
2466 | 0f8a249a | blueswir1 | case 7: // tl |
2467 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); |
2468 | 0f8a249a | blueswir1 | break;
|
2469 | 0f8a249a | blueswir1 | case 8: // pil |
2470 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); |
2471 | 0f8a249a | blueswir1 | break;
|
2472 | 0f8a249a | blueswir1 | case 9: // cwp |
2473 | 0f8a249a | blueswir1 | gen_op_wrcwp(); |
2474 | 0f8a249a | blueswir1 | break;
|
2475 | 0f8a249a | blueswir1 | case 10: // cansave |
2476 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); |
2477 | 0f8a249a | blueswir1 | break;
|
2478 | 0f8a249a | blueswir1 | case 11: // canrestore |
2479 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); |
2480 | 0f8a249a | blueswir1 | break;
|
2481 | 0f8a249a | blueswir1 | case 12: // cleanwin |
2482 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); |
2483 | 0f8a249a | blueswir1 | break;
|
2484 | 0f8a249a | blueswir1 | case 13: // otherwin |
2485 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); |
2486 | 0f8a249a | blueswir1 | break;
|
2487 | 0f8a249a | blueswir1 | case 14: // wstate |
2488 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); |
2489 | 0f8a249a | blueswir1 | break;
|
2490 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
2491 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, gl)); |
2492 | e9ebed4d | blueswir1 | break;
|
2493 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
2494 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2495 | e9ebed4d | blueswir1 | goto priv_insn;
|
2496 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr)); |
2497 | e9ebed4d | blueswir1 | break;
|
2498 | 0f8a249a | blueswir1 | default:
|
2499 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2500 | 0f8a249a | blueswir1 | } |
2501 | 3475187d | bellard | #else
|
2502 | 0f8a249a | blueswir1 | gen_op_wrwim(); |
2503 | 3475187d | bellard | #endif
|
2504 | e8af50a3 | bellard | } |
2505 | e8af50a3 | bellard | break;
|
2506 | e9ebed4d | blueswir1 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
2507 | e8af50a3 | bellard | { |
2508 | e9ebed4d | blueswir1 | #ifndef TARGET_SPARC64
|
2509 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2510 | 0f8a249a | blueswir1 | goto priv_insn;
|
2511 | e8af50a3 | bellard | gen_op_xor_T1_T0(); |
2512 | e9ebed4d | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
2513 | e9ebed4d | blueswir1 | #else
|
2514 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2515 | e9ebed4d | blueswir1 | goto priv_insn;
|
2516 | e9ebed4d | blueswir1 | gen_op_xor_T1_T0(); |
2517 | e9ebed4d | blueswir1 | switch (rd) {
|
2518 | e9ebed4d | blueswir1 | case 0: // hpstate |
2519 | e9ebed4d | blueswir1 | // XXX gen_op_wrhpstate();
|
2520 | e9ebed4d | blueswir1 | save_state(dc); |
2521 | e9ebed4d | blueswir1 | gen_op_next_insn(); |
2522 | e9ebed4d | blueswir1 | gen_op_movl_T0_0(); |
2523 | e9ebed4d | blueswir1 | gen_op_exit_tb(); |
2524 | e9ebed4d | blueswir1 | dc->is_br = 1;
|
2525 | e9ebed4d | blueswir1 | break;
|
2526 | e9ebed4d | blueswir1 | case 1: // htstate |
2527 | e9ebed4d | blueswir1 | // XXX gen_op_wrhtstate();
|
2528 | e9ebed4d | blueswir1 | break;
|
2529 | e9ebed4d | blueswir1 | case 3: // hintp |
2530 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp)); |
2531 | e9ebed4d | blueswir1 | break;
|
2532 | e9ebed4d | blueswir1 | case 5: // htba |
2533 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); |
2534 | e9ebed4d | blueswir1 | break;
|
2535 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
2536 | 20c9f095 | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); |
2537 | 20c9f095 | blueswir1 | gen_op_wrhstick_cmpr(); |
2538 | e9ebed4d | blueswir1 | break;
|
2539 | e9ebed4d | blueswir1 | case 6: // hver readonly |
2540 | e9ebed4d | blueswir1 | default:
|
2541 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2542 | e9ebed4d | blueswir1 | } |
2543 | e9ebed4d | blueswir1 | #endif
|
2544 | e8af50a3 | bellard | } |
2545 | e8af50a3 | bellard | break;
|
2546 | e8af50a3 | bellard | #endif
|
2547 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2548 | 0f8a249a | blueswir1 | case 0x2c: /* V9 movcc */ |
2549 | 0f8a249a | blueswir1 | { |
2550 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
2551 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 14, 17); |
2552 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2553 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 10); |
2554 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
2555 | 0f8a249a | blueswir1 | } |
2556 | 0f8a249a | blueswir1 | else {
|
2557 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
2558 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
2559 | 0f8a249a | blueswir1 | } |
2560 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rd); |
2561 | 0f8a249a | blueswir1 | flush_T2(dc); |
2562 | 0f8a249a | blueswir1 | if (insn & (1 << 18)) { |
2563 | 0f8a249a | blueswir1 | if (cc == 0) |
2564 | 0f8a249a | blueswir1 | gen_cond[0][cond]();
|
2565 | 0f8a249a | blueswir1 | else if (cc == 2) |
2566 | 0f8a249a | blueswir1 | gen_cond[1][cond]();
|
2567 | 0f8a249a | blueswir1 | else
|
2568 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2569 | 0f8a249a | blueswir1 | } else {
|
2570 | 0f8a249a | blueswir1 | gen_fcond[cc][cond](); |
2571 | 0f8a249a | blueswir1 | } |
2572 | 0f8a249a | blueswir1 | gen_op_mov_cc(); |
2573 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2574 | 0f8a249a | blueswir1 | break;
|
2575 | 0f8a249a | blueswir1 | } |
2576 | 0f8a249a | blueswir1 | case 0x2d: /* V9 sdivx */ |
2577 | 3475187d | bellard | gen_op_sdivx_T1_T0(); |
2578 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2579 | 0f8a249a | blueswir1 | break;
|
2580 | 0f8a249a | blueswir1 | case 0x2e: /* V9 popc */ |
2581 | 0f8a249a | blueswir1 | { |
2582 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2583 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 12); |
2584 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
2585 | 0f8a249a | blueswir1 | // XXX optimize: popc(constant)
|
2586 | 0f8a249a | blueswir1 | } |
2587 | 0f8a249a | blueswir1 | else {
|
2588 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
2589 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
2590 | 0f8a249a | blueswir1 | } |
2591 | 0f8a249a | blueswir1 | gen_op_popc(); |
2592 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2593 | 0f8a249a | blueswir1 | } |
2594 | 0f8a249a | blueswir1 | case 0x2f: /* V9 movr */ |
2595 | 0f8a249a | blueswir1 | { |
2596 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 10, 12); |
2597 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2598 | 0f8a249a | blueswir1 | flush_T2(dc); |
2599 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2600 | 0f8a249a | blueswir1 | gen_cond_reg(cond); |
2601 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2602 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 9); |
2603 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
2604 | 0f8a249a | blueswir1 | } |
2605 | 0f8a249a | blueswir1 | else {
|
2606 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
2607 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
2608 | 0f8a249a | blueswir1 | } |
2609 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rd); |
2610 | 0f8a249a | blueswir1 | gen_op_mov_cc(); |
2611 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2612 | 0f8a249a | blueswir1 | break;
|
2613 | 0f8a249a | blueswir1 | } |
2614 | 0f8a249a | blueswir1 | #endif
|
2615 | 0f8a249a | blueswir1 | default:
|
2616 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2617 | 0f8a249a | blueswir1 | } |
2618 | 0f8a249a | blueswir1 | } |
2619 | 3299908c | blueswir1 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
2620 | 3299908c | blueswir1 | #ifdef TARGET_SPARC64
|
2621 | 3299908c | blueswir1 | int opf = GET_FIELD_SP(insn, 5, 13); |
2622 | 3299908c | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2623 | 3299908c | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2624 | e9ebed4d | blueswir1 | if (gen_trap_ifnofpu(dc))
|
2625 | e9ebed4d | blueswir1 | goto jmp_insn;
|
2626 | 3299908c | blueswir1 | |
2627 | 3299908c | blueswir1 | switch (opf) {
|
2628 | e9ebed4d | blueswir1 | case 0x000: /* VIS I edge8cc */ |
2629 | e9ebed4d | blueswir1 | case 0x001: /* VIS II edge8n */ |
2630 | e9ebed4d | blueswir1 | case 0x002: /* VIS I edge8lcc */ |
2631 | e9ebed4d | blueswir1 | case 0x003: /* VIS II edge8ln */ |
2632 | e9ebed4d | blueswir1 | case 0x004: /* VIS I edge16cc */ |
2633 | e9ebed4d | blueswir1 | case 0x005: /* VIS II edge16n */ |
2634 | e9ebed4d | blueswir1 | case 0x006: /* VIS I edge16lcc */ |
2635 | e9ebed4d | blueswir1 | case 0x007: /* VIS II edge16ln */ |
2636 | e9ebed4d | blueswir1 | case 0x008: /* VIS I edge32cc */ |
2637 | e9ebed4d | blueswir1 | case 0x009: /* VIS II edge32n */ |
2638 | e9ebed4d | blueswir1 | case 0x00a: /* VIS I edge32lcc */ |
2639 | e9ebed4d | blueswir1 | case 0x00b: /* VIS II edge32ln */ |
2640 | e9ebed4d | blueswir1 | // XXX
|
2641 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2642 | e9ebed4d | blueswir1 | case 0x010: /* VIS I array8 */ |
2643 | e9ebed4d | blueswir1 | gen_movl_reg_T0(rs1); |
2644 | e9ebed4d | blueswir1 | gen_movl_reg_T1(rs2); |
2645 | e9ebed4d | blueswir1 | gen_op_array8(); |
2646 | e9ebed4d | blueswir1 | gen_movl_T0_reg(rd); |
2647 | e9ebed4d | blueswir1 | break;
|
2648 | e9ebed4d | blueswir1 | case 0x012: /* VIS I array16 */ |
2649 | e9ebed4d | blueswir1 | gen_movl_reg_T0(rs1); |
2650 | e9ebed4d | blueswir1 | gen_movl_reg_T1(rs2); |
2651 | e9ebed4d | blueswir1 | gen_op_array16(); |
2652 | e9ebed4d | blueswir1 | gen_movl_T0_reg(rd); |
2653 | e9ebed4d | blueswir1 | break;
|
2654 | e9ebed4d | blueswir1 | case 0x014: /* VIS I array32 */ |
2655 | e9ebed4d | blueswir1 | gen_movl_reg_T0(rs1); |
2656 | e9ebed4d | blueswir1 | gen_movl_reg_T1(rs2); |
2657 | e9ebed4d | blueswir1 | gen_op_array32(); |
2658 | e9ebed4d | blueswir1 | gen_movl_T0_reg(rd); |
2659 | e9ebed4d | blueswir1 | break;
|
2660 | 3299908c | blueswir1 | case 0x018: /* VIS I alignaddr */ |
2661 | 3299908c | blueswir1 | gen_movl_reg_T0(rs1); |
2662 | 3299908c | blueswir1 | gen_movl_reg_T1(rs2); |
2663 | 3299908c | blueswir1 | gen_op_alignaddr(); |
2664 | 3299908c | blueswir1 | gen_movl_T0_reg(rd); |
2665 | 3299908c | blueswir1 | break;
|
2666 | e9ebed4d | blueswir1 | case 0x019: /* VIS II bmask */ |
2667 | 3299908c | blueswir1 | case 0x01a: /* VIS I alignaddrl */ |
2668 | 3299908c | blueswir1 | // XXX
|
2669 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2670 | e9ebed4d | blueswir1 | case 0x020: /* VIS I fcmple16 */ |
2671 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2672 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2673 | e9ebed4d | blueswir1 | gen_op_fcmple16(); |
2674 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2675 | e9ebed4d | blueswir1 | break;
|
2676 | e9ebed4d | blueswir1 | case 0x022: /* VIS I fcmpne16 */ |
2677 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2678 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2679 | e9ebed4d | blueswir1 | gen_op_fcmpne16(); |
2680 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2681 | 3299908c | blueswir1 | break;
|
2682 | e9ebed4d | blueswir1 | case 0x024: /* VIS I fcmple32 */ |
2683 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2684 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2685 | e9ebed4d | blueswir1 | gen_op_fcmple32(); |
2686 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2687 | e9ebed4d | blueswir1 | break;
|
2688 | e9ebed4d | blueswir1 | case 0x026: /* VIS I fcmpne32 */ |
2689 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2690 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2691 | e9ebed4d | blueswir1 | gen_op_fcmpne32(); |
2692 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2693 | e9ebed4d | blueswir1 | break;
|
2694 | e9ebed4d | blueswir1 | case 0x028: /* VIS I fcmpgt16 */ |
2695 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2696 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2697 | e9ebed4d | blueswir1 | gen_op_fcmpgt16(); |
2698 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2699 | e9ebed4d | blueswir1 | break;
|
2700 | e9ebed4d | blueswir1 | case 0x02a: /* VIS I fcmpeq16 */ |
2701 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2702 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2703 | e9ebed4d | blueswir1 | gen_op_fcmpeq16(); |
2704 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2705 | e9ebed4d | blueswir1 | break;
|
2706 | e9ebed4d | blueswir1 | case 0x02c: /* VIS I fcmpgt32 */ |
2707 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2708 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2709 | e9ebed4d | blueswir1 | gen_op_fcmpgt32(); |
2710 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2711 | e9ebed4d | blueswir1 | break;
|
2712 | e9ebed4d | blueswir1 | case 0x02e: /* VIS I fcmpeq32 */ |
2713 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2714 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2715 | e9ebed4d | blueswir1 | gen_op_fcmpeq32(); |
2716 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2717 | e9ebed4d | blueswir1 | break;
|
2718 | e9ebed4d | blueswir1 | case 0x031: /* VIS I fmul8x16 */ |
2719 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2720 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2721 | e9ebed4d | blueswir1 | gen_op_fmul8x16(); |
2722 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2723 | e9ebed4d | blueswir1 | break;
|
2724 | e9ebed4d | blueswir1 | case 0x033: /* VIS I fmul8x16au */ |
2725 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2726 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2727 | e9ebed4d | blueswir1 | gen_op_fmul8x16au(); |
2728 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2729 | e9ebed4d | blueswir1 | break;
|
2730 | e9ebed4d | blueswir1 | case 0x035: /* VIS I fmul8x16al */ |
2731 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2732 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2733 | e9ebed4d | blueswir1 | gen_op_fmul8x16al(); |
2734 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2735 | e9ebed4d | blueswir1 | break;
|
2736 | e9ebed4d | blueswir1 | case 0x036: /* VIS I fmul8sux16 */ |
2737 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2738 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2739 | e9ebed4d | blueswir1 | gen_op_fmul8sux16(); |
2740 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2741 | e9ebed4d | blueswir1 | break;
|
2742 | e9ebed4d | blueswir1 | case 0x037: /* VIS I fmul8ulx16 */ |
2743 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2744 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2745 | e9ebed4d | blueswir1 | gen_op_fmul8ulx16(); |
2746 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2747 | e9ebed4d | blueswir1 | break;
|
2748 | e9ebed4d | blueswir1 | case 0x038: /* VIS I fmuld8sux16 */ |
2749 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2750 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2751 | e9ebed4d | blueswir1 | gen_op_fmuld8sux16(); |
2752 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2753 | e9ebed4d | blueswir1 | break;
|
2754 | e9ebed4d | blueswir1 | case 0x039: /* VIS I fmuld8ulx16 */ |
2755 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2756 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2757 | e9ebed4d | blueswir1 | gen_op_fmuld8ulx16(); |
2758 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2759 | e9ebed4d | blueswir1 | break;
|
2760 | e9ebed4d | blueswir1 | case 0x03a: /* VIS I fpack32 */ |
2761 | e9ebed4d | blueswir1 | case 0x03b: /* VIS I fpack16 */ |
2762 | e9ebed4d | blueswir1 | case 0x03d: /* VIS I fpackfix */ |
2763 | e9ebed4d | blueswir1 | case 0x03e: /* VIS I pdist */ |
2764 | e9ebed4d | blueswir1 | // XXX
|
2765 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2766 | 3299908c | blueswir1 | case 0x048: /* VIS I faligndata */ |
2767 | 3299908c | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2768 | 3299908c | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2769 | 3299908c | blueswir1 | gen_op_faligndata(); |
2770 | 3299908c | blueswir1 | gen_op_store_DT0_fpr(rd); |
2771 | 3299908c | blueswir1 | break;
|
2772 | e9ebed4d | blueswir1 | case 0x04b: /* VIS I fpmerge */ |
2773 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2774 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2775 | e9ebed4d | blueswir1 | gen_op_fpmerge(); |
2776 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2777 | e9ebed4d | blueswir1 | break;
|
2778 | e9ebed4d | blueswir1 | case 0x04c: /* VIS II bshuffle */ |
2779 | e9ebed4d | blueswir1 | // XXX
|
2780 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2781 | e9ebed4d | blueswir1 | case 0x04d: /* VIS I fexpand */ |
2782 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2783 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2784 | e9ebed4d | blueswir1 | gen_op_fexpand(); |
2785 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2786 | e9ebed4d | blueswir1 | break;
|
2787 | e9ebed4d | blueswir1 | case 0x050: /* VIS I fpadd16 */ |
2788 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2789 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2790 | e9ebed4d | blueswir1 | gen_op_fpadd16(); |
2791 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2792 | e9ebed4d | blueswir1 | break;
|
2793 | e9ebed4d | blueswir1 | case 0x051: /* VIS I fpadd16s */ |
2794 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2795 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2796 | e9ebed4d | blueswir1 | gen_op_fpadd16s(); |
2797 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2798 | e9ebed4d | blueswir1 | break;
|
2799 | e9ebed4d | blueswir1 | case 0x052: /* VIS I fpadd32 */ |
2800 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2801 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2802 | e9ebed4d | blueswir1 | gen_op_fpadd32(); |
2803 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2804 | e9ebed4d | blueswir1 | break;
|
2805 | e9ebed4d | blueswir1 | case 0x053: /* VIS I fpadd32s */ |
2806 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2807 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2808 | e9ebed4d | blueswir1 | gen_op_fpadd32s(); |
2809 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2810 | e9ebed4d | blueswir1 | break;
|
2811 | e9ebed4d | blueswir1 | case 0x054: /* VIS I fpsub16 */ |
2812 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2813 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2814 | e9ebed4d | blueswir1 | gen_op_fpsub16(); |
2815 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2816 | e9ebed4d | blueswir1 | break;
|
2817 | e9ebed4d | blueswir1 | case 0x055: /* VIS I fpsub16s */ |
2818 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2819 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2820 | e9ebed4d | blueswir1 | gen_op_fpsub16s(); |
2821 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2822 | e9ebed4d | blueswir1 | break;
|
2823 | e9ebed4d | blueswir1 | case 0x056: /* VIS I fpsub32 */ |
2824 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2825 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2826 | e9ebed4d | blueswir1 | gen_op_fpadd32(); |
2827 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2828 | e9ebed4d | blueswir1 | break;
|
2829 | e9ebed4d | blueswir1 | case 0x057: /* VIS I fpsub32s */ |
2830 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2831 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2832 | e9ebed4d | blueswir1 | gen_op_fpsub32s(); |
2833 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2834 | e9ebed4d | blueswir1 | break;
|
2835 | 3299908c | blueswir1 | case 0x060: /* VIS I fzero */ |
2836 | 3299908c | blueswir1 | gen_op_movl_DT0_0(); |
2837 | 3299908c | blueswir1 | gen_op_store_DT0_fpr(rd); |
2838 | 3299908c | blueswir1 | break;
|
2839 | 3299908c | blueswir1 | case 0x061: /* VIS I fzeros */ |
2840 | 3299908c | blueswir1 | gen_op_movl_FT0_0(); |
2841 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
2842 | 3299908c | blueswir1 | break;
|
2843 | e9ebed4d | blueswir1 | case 0x062: /* VIS I fnor */ |
2844 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2845 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2846 | e9ebed4d | blueswir1 | gen_op_fnor(); |
2847 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2848 | e9ebed4d | blueswir1 | break;
|
2849 | e9ebed4d | blueswir1 | case 0x063: /* VIS I fnors */ |
2850 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2851 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2852 | e9ebed4d | blueswir1 | gen_op_fnors(); |
2853 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2854 | e9ebed4d | blueswir1 | break;
|
2855 | e9ebed4d | blueswir1 | case 0x064: /* VIS I fandnot2 */ |
2856 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs1); |
2857 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs2); |
2858 | e9ebed4d | blueswir1 | gen_op_fandnot(); |
2859 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2860 | e9ebed4d | blueswir1 | break;
|
2861 | e9ebed4d | blueswir1 | case 0x065: /* VIS I fandnot2s */ |
2862 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
2863 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs2); |
2864 | e9ebed4d | blueswir1 | gen_op_fandnots(); |
2865 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2866 | e9ebed4d | blueswir1 | break;
|
2867 | e9ebed4d | blueswir1 | case 0x066: /* VIS I fnot2 */ |
2868 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2869 | e9ebed4d | blueswir1 | gen_op_fnot(); |
2870 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2871 | e9ebed4d | blueswir1 | break;
|
2872 | e9ebed4d | blueswir1 | case 0x067: /* VIS I fnot2s */ |
2873 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2874 | e9ebed4d | blueswir1 | gen_op_fnot(); |
2875 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2876 | e9ebed4d | blueswir1 | break;
|
2877 | e9ebed4d | blueswir1 | case 0x068: /* VIS I fandnot1 */ |
2878 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2879 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2880 | e9ebed4d | blueswir1 | gen_op_fandnot(); |
2881 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2882 | e9ebed4d | blueswir1 | break;
|
2883 | e9ebed4d | blueswir1 | case 0x069: /* VIS I fandnot1s */ |
2884 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2885 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2886 | e9ebed4d | blueswir1 | gen_op_fandnots(); |
2887 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2888 | e9ebed4d | blueswir1 | break;
|
2889 | e9ebed4d | blueswir1 | case 0x06a: /* VIS I fnot1 */ |
2890 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs1); |
2891 | e9ebed4d | blueswir1 | gen_op_fnot(); |
2892 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2893 | e9ebed4d | blueswir1 | break;
|
2894 | e9ebed4d | blueswir1 | case 0x06b: /* VIS I fnot1s */ |
2895 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
2896 | e9ebed4d | blueswir1 | gen_op_fnot(); |
2897 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2898 | e9ebed4d | blueswir1 | break;
|
2899 | e9ebed4d | blueswir1 | case 0x06c: /* VIS I fxor */ |
2900 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2901 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2902 | e9ebed4d | blueswir1 | gen_op_fxor(); |
2903 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2904 | e9ebed4d | blueswir1 | break;
|
2905 | e9ebed4d | blueswir1 | case 0x06d: /* VIS I fxors */ |
2906 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2907 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2908 | e9ebed4d | blueswir1 | gen_op_fxors(); |
2909 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2910 | e9ebed4d | blueswir1 | break;
|
2911 | e9ebed4d | blueswir1 | case 0x06e: /* VIS I fnand */ |
2912 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2913 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2914 | e9ebed4d | blueswir1 | gen_op_fnand(); |
2915 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2916 | e9ebed4d | blueswir1 | break;
|
2917 | e9ebed4d | blueswir1 | case 0x06f: /* VIS I fnands */ |
2918 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2919 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2920 | e9ebed4d | blueswir1 | gen_op_fnands(); |
2921 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2922 | e9ebed4d | blueswir1 | break;
|
2923 | e9ebed4d | blueswir1 | case 0x070: /* VIS I fand */ |
2924 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2925 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2926 | e9ebed4d | blueswir1 | gen_op_fand(); |
2927 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2928 | e9ebed4d | blueswir1 | break;
|
2929 | e9ebed4d | blueswir1 | case 0x071: /* VIS I fands */ |
2930 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2931 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2932 | e9ebed4d | blueswir1 | gen_op_fands(); |
2933 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2934 | e9ebed4d | blueswir1 | break;
|
2935 | e9ebed4d | blueswir1 | case 0x072: /* VIS I fxnor */ |
2936 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2937 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2938 | e9ebed4d | blueswir1 | gen_op_fxnor(); |
2939 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2940 | e9ebed4d | blueswir1 | break;
|
2941 | e9ebed4d | blueswir1 | case 0x073: /* VIS I fxnors */ |
2942 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2943 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2944 | e9ebed4d | blueswir1 | gen_op_fxnors(); |
2945 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2946 | e9ebed4d | blueswir1 | break;
|
2947 | 3299908c | blueswir1 | case 0x074: /* VIS I fsrc1 */ |
2948 | 3299908c | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2949 | 3299908c | blueswir1 | gen_op_store_DT0_fpr(rd); |
2950 | 3299908c | blueswir1 | break;
|
2951 | 3299908c | blueswir1 | case 0x075: /* VIS I fsrc1s */ |
2952 | 3299908c | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2953 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
2954 | 3299908c | blueswir1 | break;
|
2955 | e9ebed4d | blueswir1 | case 0x076: /* VIS I fornot2 */ |
2956 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs1); |
2957 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs2); |
2958 | e9ebed4d | blueswir1 | gen_op_fornot(); |
2959 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2960 | e9ebed4d | blueswir1 | break;
|
2961 | e9ebed4d | blueswir1 | case 0x077: /* VIS I fornot2s */ |
2962 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
2963 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs2); |
2964 | e9ebed4d | blueswir1 | gen_op_fornots(); |
2965 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2966 | e9ebed4d | blueswir1 | break;
|
2967 | 3299908c | blueswir1 | case 0x078: /* VIS I fsrc2 */ |
2968 | 3299908c | blueswir1 | gen_op_load_fpr_DT0(rs2); |
2969 | 3299908c | blueswir1 | gen_op_store_DT0_fpr(rd); |
2970 | 3299908c | blueswir1 | break;
|
2971 | 3299908c | blueswir1 | case 0x079: /* VIS I fsrc2s */ |
2972 | 3299908c | blueswir1 | gen_op_load_fpr_FT0(rs2); |
2973 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
2974 | 3299908c | blueswir1 | break;
|
2975 | e9ebed4d | blueswir1 | case 0x07a: /* VIS I fornot1 */ |
2976 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2977 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2978 | e9ebed4d | blueswir1 | gen_op_fornot(); |
2979 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2980 | e9ebed4d | blueswir1 | break;
|
2981 | e9ebed4d | blueswir1 | case 0x07b: /* VIS I fornot1s */ |
2982 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2983 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2984 | e9ebed4d | blueswir1 | gen_op_fornots(); |
2985 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2986 | e9ebed4d | blueswir1 | break;
|
2987 | e9ebed4d | blueswir1 | case 0x07c: /* VIS I for */ |
2988 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT0(rs1); |
2989 | e9ebed4d | blueswir1 | gen_op_load_fpr_DT1(rs2); |
2990 | e9ebed4d | blueswir1 | gen_op_for(); |
2991 | e9ebed4d | blueswir1 | gen_op_store_DT0_fpr(rd); |
2992 | e9ebed4d | blueswir1 | break;
|
2993 | e9ebed4d | blueswir1 | case 0x07d: /* VIS I fors */ |
2994 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2995 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2996 | e9ebed4d | blueswir1 | gen_op_fors(); |
2997 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
2998 | e9ebed4d | blueswir1 | break;
|
2999 | 3299908c | blueswir1 | case 0x07e: /* VIS I fone */ |
3000 | 3299908c | blueswir1 | gen_op_movl_DT0_1(); |
3001 | 3299908c | blueswir1 | gen_op_store_DT0_fpr(rd); |
3002 | 3299908c | blueswir1 | break;
|
3003 | 3299908c | blueswir1 | case 0x07f: /* VIS I fones */ |
3004 | 3299908c | blueswir1 | gen_op_movl_FT0_1(); |
3005 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
3006 | 3299908c | blueswir1 | break;
|
3007 | e9ebed4d | blueswir1 | case 0x080: /* VIS I shutdown */ |
3008 | e9ebed4d | blueswir1 | case 0x081: /* VIS II siam */ |
3009 | e9ebed4d | blueswir1 | // XXX
|
3010 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3011 | 3299908c | blueswir1 | default:
|
3012 | 3299908c | blueswir1 | goto illegal_insn;
|
3013 | 3299908c | blueswir1 | } |
3014 | 3299908c | blueswir1 | #else
|
3015 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3016 | 3299908c | blueswir1 | #endif
|
3017 | 3299908c | blueswir1 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
3018 | fcc72045 | blueswir1 | #ifdef TARGET_SPARC64
|
3019 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3020 | fcc72045 | blueswir1 | #else
|
3021 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3022 | fcc72045 | blueswir1 | #endif
|
3023 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3024 | 0f8a249a | blueswir1 | } else if (xop == 0x39) { /* V9 return */ |
3025 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
3026 | 1ad21e69 | blueswir1 | save_state(dc); |
3027 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
3028 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3029 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
3030 | 3475187d | bellard | #if defined(OPTIM)
|
3031 | 0f8a249a | blueswir1 | if (rs2) {
|
3032 | 3475187d | bellard | #endif
|
3033 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
3034 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
3035 | 3475187d | bellard | #if defined(OPTIM)
|
3036 | 0f8a249a | blueswir1 | } |
3037 | 3475187d | bellard | #endif
|
3038 | 0f8a249a | blueswir1 | } else { /* register */ |
3039 | 3475187d | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3040 | 3475187d | bellard | #if defined(OPTIM)
|
3041 | 0f8a249a | blueswir1 | if (rs2) {
|
3042 | 3475187d | bellard | #endif
|
3043 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
3044 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
3045 | 3475187d | bellard | #if defined(OPTIM)
|
3046 | 0f8a249a | blueswir1 | } |
3047 | 3475187d | bellard | #endif
|
3048 | 3475187d | bellard | } |
3049 | 0f8a249a | blueswir1 | gen_op_restore(); |
3050 | 0f8a249a | blueswir1 | gen_mov_pc_npc(dc); |
3051 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3052 | 0f8a249a | blueswir1 | gen_op_movl_npc_T0(); |
3053 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
3054 | 0f8a249a | blueswir1 | goto jmp_insn;
|
3055 | 3475187d | bellard | #endif
|
3056 | 0f8a249a | blueswir1 | } else {
|
3057 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
3058 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
3059 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3060 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
3061 | e80cfcfc | bellard | #if defined(OPTIM)
|
3062 | 0f8a249a | blueswir1 | if (rs2) {
|
3063 | e8af50a3 | bellard | #endif
|
3064 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
3065 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
3066 | e80cfcfc | bellard | #if defined(OPTIM)
|
3067 | 0f8a249a | blueswir1 | } |
3068 | e8af50a3 | bellard | #endif
|
3069 | 0f8a249a | blueswir1 | } else { /* register */ |
3070 | e80cfcfc | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3071 | e80cfcfc | bellard | #if defined(OPTIM)
|
3072 | 0f8a249a | blueswir1 | if (rs2) {
|
3073 | e80cfcfc | bellard | #endif
|
3074 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
3075 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
3076 | e80cfcfc | bellard | #if defined(OPTIM)
|
3077 | 0f8a249a | blueswir1 | } |
3078 | e8af50a3 | bellard | #endif
|
3079 | cf495bcf | bellard | } |
3080 | 0f8a249a | blueswir1 | switch (xop) {
|
3081 | 0f8a249a | blueswir1 | case 0x38: /* jmpl */ |
3082 | 0f8a249a | blueswir1 | { |
3083 | 0f8a249a | blueswir1 | if (rd != 0) { |
3084 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3085 | ded3ab80 | pbrook | if (dc->pc == (uint32_t)dc->pc) {
|
3086 | ded3ab80 | pbrook | gen_op_movl_T1_im(dc->pc); |
3087 | ded3ab80 | pbrook | } else {
|
3088 | ded3ab80 | pbrook | gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
|
3089 | ded3ab80 | pbrook | } |
3090 | ded3ab80 | pbrook | #else
|
3091 | 0f8a249a | blueswir1 | gen_op_movl_T1_im(dc->pc); |
3092 | ded3ab80 | pbrook | #endif
|
3093 | 0f8a249a | blueswir1 | gen_movl_T1_reg(rd); |
3094 | 0f8a249a | blueswir1 | } |
3095 | 0bee699e | bellard | gen_mov_pc_npc(dc); |
3096 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3097 | 0f8a249a | blueswir1 | gen_op_movl_npc_T0(); |
3098 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
3099 | 0f8a249a | blueswir1 | } |
3100 | 0f8a249a | blueswir1 | goto jmp_insn;
|
3101 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
3102 | 0f8a249a | blueswir1 | case 0x39: /* rett, V9 return */ |
3103 | 0f8a249a | blueswir1 | { |
3104 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3105 | 0f8a249a | blueswir1 | goto priv_insn;
|
3106 | 0bee699e | bellard | gen_mov_pc_npc(dc); |
3107 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3108 | 0f8a249a | blueswir1 | gen_op_movl_npc_T0(); |
3109 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
3110 | 0f8a249a | blueswir1 | gen_op_rett(); |
3111 | 0f8a249a | blueswir1 | } |
3112 | 0f8a249a | blueswir1 | goto jmp_insn;
|
3113 | 0f8a249a | blueswir1 | #endif
|
3114 | 0f8a249a | blueswir1 | case 0x3b: /* flush */ |
3115 | 0f8a249a | blueswir1 | gen_op_flush_T0(); |
3116 | 0f8a249a | blueswir1 | break;
|
3117 | 0f8a249a | blueswir1 | case 0x3c: /* save */ |
3118 | 0f8a249a | blueswir1 | save_state(dc); |
3119 | 0f8a249a | blueswir1 | gen_op_save(); |
3120 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3121 | 0f8a249a | blueswir1 | break;
|
3122 | 0f8a249a | blueswir1 | case 0x3d: /* restore */ |
3123 | 0f8a249a | blueswir1 | save_state(dc); |
3124 | 0f8a249a | blueswir1 | gen_op_restore(); |
3125 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3126 | 0f8a249a | blueswir1 | break;
|
3127 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
3128 | 0f8a249a | blueswir1 | case 0x3e: /* V9 done/retry */ |
3129 | 0f8a249a | blueswir1 | { |
3130 | 0f8a249a | blueswir1 | switch (rd) {
|
3131 | 0f8a249a | blueswir1 | case 0: |
3132 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3133 | 0f8a249a | blueswir1 | goto priv_insn;
|
3134 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
3135 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
3136 | 0f8a249a | blueswir1 | gen_op_done(); |
3137 | 0f8a249a | blueswir1 | goto jmp_insn;
|
3138 | 0f8a249a | blueswir1 | case 1: |
3139 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3140 | 0f8a249a | blueswir1 | goto priv_insn;
|
3141 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
3142 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
3143 | 0f8a249a | blueswir1 | gen_op_retry(); |
3144 | 0f8a249a | blueswir1 | goto jmp_insn;
|
3145 | 0f8a249a | blueswir1 | default:
|
3146 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3147 | 0f8a249a | blueswir1 | } |
3148 | 0f8a249a | blueswir1 | } |
3149 | 0f8a249a | blueswir1 | break;
|
3150 | 0f8a249a | blueswir1 | #endif
|
3151 | 0f8a249a | blueswir1 | default:
|
3152 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3153 | 0f8a249a | blueswir1 | } |
3154 | cf495bcf | bellard | } |
3155 | 0f8a249a | blueswir1 | break;
|
3156 | 0f8a249a | blueswir1 | } |
3157 | 0f8a249a | blueswir1 | break;
|
3158 | 0f8a249a | blueswir1 | case 3: /* load/store instructions */ |
3159 | 0f8a249a | blueswir1 | { |
3160 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
3161 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3162 | 2371aaa2 | blueswir1 | save_state(dc); |
3163 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
3164 | 81ad8ba2 | blueswir1 | if (xop == 0x3c || xop == 0x3e) |
3165 | 81ad8ba2 | blueswir1 | { |
3166 | 81ad8ba2 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3167 | 81ad8ba2 | blueswir1 | gen_movl_reg_T1(rs2); |
3168 | 81ad8ba2 | blueswir1 | } |
3169 | 81ad8ba2 | blueswir1 | else if (IS_IMM) { /* immediate */ |
3170 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
3171 | e80cfcfc | bellard | #if defined(OPTIM)
|
3172 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
3173 | e80cfcfc | bellard | #endif
|
3174 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
3175 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
3176 | e80cfcfc | bellard | #if defined(OPTIM)
|
3177 | 0f8a249a | blueswir1 | } |
3178 | e80cfcfc | bellard | #endif
|
3179 | 0f8a249a | blueswir1 | } else { /* register */ |
3180 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3181 | e80cfcfc | bellard | #if defined(OPTIM)
|
3182 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
3183 | e80cfcfc | bellard | #endif
|
3184 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
3185 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
3186 | e80cfcfc | bellard | #if defined(OPTIM)
|
3187 | 0f8a249a | blueswir1 | } |
3188 | e80cfcfc | bellard | #endif
|
3189 | 0f8a249a | blueswir1 | } |
3190 | 2f2ecb83 | blueswir1 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
3191 | 2f2ecb83 | blueswir1 | (xop > 0x17 && xop <= 0x1d ) || |
3192 | 2f2ecb83 | blueswir1 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
3193 | 0f8a249a | blueswir1 | switch (xop) {
|
3194 | 0f8a249a | blueswir1 | case 0x0: /* load word */ |
3195 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3196 | dc011987 | blueswir1 | #ifndef TARGET_SPARC64
|
3197 | 0f8a249a | blueswir1 | gen_op_ldst(ld); |
3198 | dc011987 | blueswir1 | #else
|
3199 | dc011987 | blueswir1 | gen_op_ldst(lduw); |
3200 | dc011987 | blueswir1 | #endif
|
3201 | 0f8a249a | blueswir1 | break;
|
3202 | 0f8a249a | blueswir1 | case 0x1: /* load unsigned byte */ |
3203 | 0f8a249a | blueswir1 | gen_op_ldst(ldub); |
3204 | 0f8a249a | blueswir1 | break;
|
3205 | 0f8a249a | blueswir1 | case 0x2: /* load unsigned halfword */ |
3206 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
3207 | 0f8a249a | blueswir1 | gen_op_ldst(lduh); |
3208 | 0f8a249a | blueswir1 | break;
|
3209 | 0f8a249a | blueswir1 | case 0x3: /* load double word */ |
3210 | 0f8a249a | blueswir1 | if (rd & 1) |
3211 | d4218d99 | blueswir1 | goto illegal_insn;
|
3212 | 8f577d3d | blueswir1 | gen_op_check_align_T0_7(); |
3213 | 0f8a249a | blueswir1 | gen_op_ldst(ldd); |
3214 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd + 1);
|
3215 | 0f8a249a | blueswir1 | break;
|
3216 | 0f8a249a | blueswir1 | case 0x9: /* load signed byte */ |
3217 | 0f8a249a | blueswir1 | gen_op_ldst(ldsb); |
3218 | 0f8a249a | blueswir1 | break;
|
3219 | 0f8a249a | blueswir1 | case 0xa: /* load signed halfword */ |
3220 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
3221 | 0f8a249a | blueswir1 | gen_op_ldst(ldsh); |
3222 | 0f8a249a | blueswir1 | break;
|
3223 | 0f8a249a | blueswir1 | case 0xd: /* ldstub -- XXX: should be atomically */ |
3224 | 0f8a249a | blueswir1 | gen_op_ldst(ldstub); |
3225 | 0f8a249a | blueswir1 | break;
|
3226 | 0f8a249a | blueswir1 | case 0x0f: /* swap register with memory. Also atomically */ |
3227 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3228 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rd); |
3229 | 0f8a249a | blueswir1 | gen_op_ldst(swap); |
3230 | 0f8a249a | blueswir1 | break;
|
3231 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
3232 | 0f8a249a | blueswir1 | case 0x10: /* load word alternate */ |
3233 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3234 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3235 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3236 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3237 | 0f8a249a | blueswir1 | goto priv_insn;
|
3238 | 6ea4a6c8 | blueswir1 | #endif
|
3239 | 8f577d3d | blueswir1 | gen_op_check_align_T0_3(); |
3240 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 4, 0); |
3241 | 0f8a249a | blueswir1 | break;
|
3242 | 0f8a249a | blueswir1 | case 0x11: /* load unsigned byte alternate */ |
3243 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3244 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3245 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3246 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3247 | 0f8a249a | blueswir1 | goto priv_insn;
|
3248 | 0f8a249a | blueswir1 | #endif
|
3249 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 1, 0); |
3250 | 0f8a249a | blueswir1 | break;
|
3251 | 0f8a249a | blueswir1 | case 0x12: /* load unsigned halfword alternate */ |
3252 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3253 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3254 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3255 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3256 | 0f8a249a | blueswir1 | goto priv_insn;
|
3257 | 6ea4a6c8 | blueswir1 | #endif
|
3258 | 8f577d3d | blueswir1 | gen_op_check_align_T0_1(); |
3259 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 2, 0); |
3260 | 0f8a249a | blueswir1 | break;
|
3261 | 0f8a249a | blueswir1 | case 0x13: /* load double word alternate */ |
3262 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3263 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3264 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3265 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3266 | 0f8a249a | blueswir1 | goto priv_insn;
|
3267 | 3475187d | bellard | #endif
|
3268 | 0f8a249a | blueswir1 | if (rd & 1) |
3269 | d4218d99 | blueswir1 | goto illegal_insn;
|
3270 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
3271 | 81ad8ba2 | blueswir1 | gen_ldda_asi(insn); |
3272 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd + 1);
|
3273 | 0f8a249a | blueswir1 | break;
|
3274 | 0f8a249a | blueswir1 | case 0x19: /* load signed byte alternate */ |
3275 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3276 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3277 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3278 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3279 | 0f8a249a | blueswir1 | goto priv_insn;
|
3280 | 0f8a249a | blueswir1 | #endif
|
3281 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 1, 1); |
3282 | 0f8a249a | blueswir1 | break;
|
3283 | 0f8a249a | blueswir1 | case 0x1a: /* load signed halfword alternate */ |
3284 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3285 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3286 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3287 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3288 | 0f8a249a | blueswir1 | goto priv_insn;
|
3289 | 6ea4a6c8 | blueswir1 | #endif
|
3290 | 8f577d3d | blueswir1 | gen_op_check_align_T0_1(); |
3291 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 2, 1); |
3292 | 0f8a249a | blueswir1 | break;
|
3293 | 0f8a249a | blueswir1 | case 0x1d: /* ldstuba -- XXX: should be atomically */ |
3294 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3295 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3296 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3297 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3298 | 0f8a249a | blueswir1 | goto priv_insn;
|
3299 | 0f8a249a | blueswir1 | #endif
|
3300 | 81ad8ba2 | blueswir1 | gen_ldstub_asi(insn); |
3301 | 0f8a249a | blueswir1 | break;
|
3302 | 0f8a249a | blueswir1 | case 0x1f: /* swap reg with alt. memory. Also atomically */ |
3303 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3304 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3305 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3306 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3307 | 0f8a249a | blueswir1 | goto priv_insn;
|
3308 | 6ea4a6c8 | blueswir1 | #endif
|
3309 | 8f577d3d | blueswir1 | gen_op_check_align_T0_3(); |
3310 | 81ad8ba2 | blueswir1 | gen_movl_reg_T1(rd); |
3311 | 81ad8ba2 | blueswir1 | gen_swap_asi(insn); |
3312 | 0f8a249a | blueswir1 | break;
|
3313 | 3475187d | bellard | |
3314 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3315 | 0f8a249a | blueswir1 | case 0x30: /* ldc */ |
3316 | 0f8a249a | blueswir1 | case 0x31: /* ldcsr */ |
3317 | 0f8a249a | blueswir1 | case 0x33: /* lddc */ |
3318 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3319 | 3475187d | bellard | #endif
|
3320 | 3475187d | bellard | #endif
|
3321 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3322 | 0f8a249a | blueswir1 | case 0x08: /* V9 ldsw */ |
3323 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3324 | 0f8a249a | blueswir1 | gen_op_ldst(ldsw); |
3325 | 0f8a249a | blueswir1 | break;
|
3326 | 0f8a249a | blueswir1 | case 0x0b: /* V9 ldx */ |
3327 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
3328 | 0f8a249a | blueswir1 | gen_op_ldst(ldx); |
3329 | 0f8a249a | blueswir1 | break;
|
3330 | 0f8a249a | blueswir1 | case 0x18: /* V9 ldswa */ |
3331 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3332 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 4, 1); |
3333 | 0f8a249a | blueswir1 | break;
|
3334 | 0f8a249a | blueswir1 | case 0x1b: /* V9 ldxa */ |
3335 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
3336 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 8, 0); |
3337 | 0f8a249a | blueswir1 | break;
|
3338 | 0f8a249a | blueswir1 | case 0x2d: /* V9 prefetch, no effect */ |
3339 | 0f8a249a | blueswir1 | goto skip_move;
|
3340 | 0f8a249a | blueswir1 | case 0x30: /* V9 ldfa */ |
3341 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3342 | 3391c818 | blueswir1 | gen_ldf_asi(insn, 4);
|
3343 | 81ad8ba2 | blueswir1 | goto skip_move;
|
3344 | 0f8a249a | blueswir1 | case 0x33: /* V9 lddfa */ |
3345 | 3391c818 | blueswir1 | gen_op_check_align_T0_3(); |
3346 | 3391c818 | blueswir1 | gen_ldf_asi(insn, 8);
|
3347 | 81ad8ba2 | blueswir1 | goto skip_move;
|
3348 | 0f8a249a | blueswir1 | case 0x3d: /* V9 prefetcha, no effect */ |
3349 | 0f8a249a | blueswir1 | goto skip_move;
|
3350 | 0f8a249a | blueswir1 | case 0x32: /* V9 ldqfa */ |
3351 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
3352 | 1f587329 | blueswir1 | gen_op_check_align_T0_3(); |
3353 | 1f587329 | blueswir1 | gen_ldf_asi(insn, 16);
|
3354 | 1f587329 | blueswir1 | goto skip_move;
|
3355 | 1f587329 | blueswir1 | #else
|
3356 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
3357 | 0f8a249a | blueswir1 | #endif
|
3358 | 1f587329 | blueswir1 | #endif
|
3359 | 0f8a249a | blueswir1 | default:
|
3360 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3361 | 0f8a249a | blueswir1 | } |
3362 | 0f8a249a | blueswir1 | gen_movl_T1_reg(rd); |
3363 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3364 | 0f8a249a | blueswir1 | skip_move: ;
|
3365 | 3475187d | bellard | #endif
|
3366 | 0f8a249a | blueswir1 | } else if (xop >= 0x20 && xop < 0x24) { |
3367 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
3368 | a80dde08 | bellard | goto jmp_insn;
|
3369 | 0f8a249a | blueswir1 | switch (xop) {
|
3370 | 0f8a249a | blueswir1 | case 0x20: /* load fpreg */ |
3371 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3372 | 0f8a249a | blueswir1 | gen_op_ldst(ldf); |
3373 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
3374 | 0f8a249a | blueswir1 | break;
|
3375 | 0f8a249a | blueswir1 | case 0x21: /* load fsr */ |
3376 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3377 | 0f8a249a | blueswir1 | gen_op_ldst(ldf); |
3378 | 0f8a249a | blueswir1 | gen_op_ldfsr(); |
3379 | 0f8a249a | blueswir1 | break;
|
3380 | 0f8a249a | blueswir1 | case 0x22: /* load quad fpreg */ |
3381 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
3382 | 1f587329 | blueswir1 | gen_op_check_align_T0_7(); |
3383 | 1f587329 | blueswir1 | gen_op_ldst(ldqf); |
3384 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
3385 | 1f587329 | blueswir1 | break;
|
3386 | 1f587329 | blueswir1 | #else
|
3387 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
3388 | 1f587329 | blueswir1 | #endif
|
3389 | 0f8a249a | blueswir1 | case 0x23: /* load double fpreg */ |
3390 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
3391 | 0f8a249a | blueswir1 | gen_op_ldst(lddf); |
3392 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3393 | 0f8a249a | blueswir1 | break;
|
3394 | 0f8a249a | blueswir1 | default:
|
3395 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3396 | 0f8a249a | blueswir1 | } |
3397 | 0f8a249a | blueswir1 | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ |
3398 | 0f8a249a | blueswir1 | xop == 0xe || xop == 0x1e) { |
3399 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rd); |
3400 | 0f8a249a | blueswir1 | switch (xop) {
|
3401 | 0f8a249a | blueswir1 | case 0x4: |
3402 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3403 | 0f8a249a | blueswir1 | gen_op_ldst(st); |
3404 | 0f8a249a | blueswir1 | break;
|
3405 | 0f8a249a | blueswir1 | case 0x5: |
3406 | 0f8a249a | blueswir1 | gen_op_ldst(stb); |
3407 | 0f8a249a | blueswir1 | break;
|
3408 | 0f8a249a | blueswir1 | case 0x6: |
3409 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
3410 | 0f8a249a | blueswir1 | gen_op_ldst(sth); |
3411 | 0f8a249a | blueswir1 | break;
|
3412 | 0f8a249a | blueswir1 | case 0x7: |
3413 | 0f8a249a | blueswir1 | if (rd & 1) |
3414 | d4218d99 | blueswir1 | goto illegal_insn;
|
3415 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
3416 | 72cbca10 | bellard | flush_T2(dc); |
3417 | 0f8a249a | blueswir1 | gen_movl_reg_T2(rd + 1);
|
3418 | 0f8a249a | blueswir1 | gen_op_ldst(std); |
3419 | 0f8a249a | blueswir1 | break;
|
3420 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
3421 | 0f8a249a | blueswir1 | case 0x14: |
3422 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3423 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3424 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3425 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3426 | 0f8a249a | blueswir1 | goto priv_insn;
|
3427 | 3475187d | bellard | #endif
|
3428 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3429 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 4);
|
3430 | d39c0b99 | bellard | break;
|
3431 | 0f8a249a | blueswir1 | case 0x15: |
3432 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3433 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3434 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3435 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3436 | 0f8a249a | blueswir1 | goto priv_insn;
|
3437 | 3475187d | bellard | #endif
|
3438 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 1);
|
3439 | d39c0b99 | bellard | break;
|
3440 | 0f8a249a | blueswir1 | case 0x16: |
3441 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3442 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3443 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3444 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3445 | 0f8a249a | blueswir1 | goto priv_insn;
|
3446 | 3475187d | bellard | #endif
|
3447 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
3448 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 2);
|
3449 | d39c0b99 | bellard | break;
|
3450 | 0f8a249a | blueswir1 | case 0x17: |
3451 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3452 | 0f8a249a | blueswir1 | if (IS_IMM)
|
3453 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3454 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3455 | 0f8a249a | blueswir1 | goto priv_insn;
|
3456 | 3475187d | bellard | #endif
|
3457 | 0f8a249a | blueswir1 | if (rd & 1) |
3458 | d4218d99 | blueswir1 | goto illegal_insn;
|
3459 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
3460 | e8af50a3 | bellard | flush_T2(dc); |
3461 | 0f8a249a | blueswir1 | gen_movl_reg_T2(rd + 1);
|
3462 | 81ad8ba2 | blueswir1 | gen_stda_asi(insn); |
3463 | d39c0b99 | bellard | break;
|
3464 | e80cfcfc | bellard | #endif
|
3465 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3466 | 0f8a249a | blueswir1 | case 0x0e: /* V9 stx */ |
3467 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
3468 | 0f8a249a | blueswir1 | gen_op_ldst(stx); |
3469 | 0f8a249a | blueswir1 | break;
|
3470 | 0f8a249a | blueswir1 | case 0x1e: /* V9 stxa */ |
3471 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
3472 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 8);
|
3473 | 0f8a249a | blueswir1 | break;
|
3474 | 3475187d | bellard | #endif
|
3475 | 0f8a249a | blueswir1 | default:
|
3476 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3477 | 0f8a249a | blueswir1 | } |
3478 | 0f8a249a | blueswir1 | } else if (xop > 0x23 && xop < 0x28) { |
3479 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
3480 | a80dde08 | bellard | goto jmp_insn;
|
3481 | 0f8a249a | blueswir1 | switch (xop) {
|
3482 | 0f8a249a | blueswir1 | case 0x24: |
3483 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3484 | e8af50a3 | bellard | gen_op_load_fpr_FT0(rd); |
3485 | 0f8a249a | blueswir1 | gen_op_ldst(stf); |
3486 | 0f8a249a | blueswir1 | break;
|
3487 | 0f8a249a | blueswir1 | case 0x25: /* stfsr, V9 stxfsr */ |
3488 | 6ea4a6c8 | blueswir1 | #ifdef CONFIG_USER_ONLY
|
3489 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3490 | 6ea4a6c8 | blueswir1 | #endif
|
3491 | 0f8a249a | blueswir1 | gen_op_stfsr(); |
3492 | 0f8a249a | blueswir1 | gen_op_ldst(stf); |
3493 | 0f8a249a | blueswir1 | break;
|
3494 | 1f587329 | blueswir1 | case 0x26: |
3495 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
3496 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
3497 | 1f587329 | blueswir1 | /* V9 stqf, store quad fpreg */
|
3498 | 1f587329 | blueswir1 | gen_op_check_align_T0_7(); |
3499 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
3500 | 1f587329 | blueswir1 | gen_op_ldst(stqf); |
3501 | 1f587329 | blueswir1 | break;
|
3502 | 1f587329 | blueswir1 | #else
|
3503 | 1f587329 | blueswir1 | goto nfpu_insn;
|
3504 | 1f587329 | blueswir1 | #endif
|
3505 | 1f587329 | blueswir1 | #else /* !TARGET_SPARC64 */ |
3506 | 1f587329 | blueswir1 | /* stdfq, store floating point queue */
|
3507 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
3508 | 1f587329 | blueswir1 | goto illegal_insn;
|
3509 | 1f587329 | blueswir1 | #else
|
3510 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3511 | 0f8a249a | blueswir1 | goto priv_insn;
|
3512 | 0f8a249a | blueswir1 | if (gen_trap_ifnofpu(dc))
|
3513 | 0f8a249a | blueswir1 | goto jmp_insn;
|
3514 | 0f8a249a | blueswir1 | goto nfq_insn;
|
3515 | 0f8a249a | blueswir1 | #endif
|
3516 | 1f587329 | blueswir1 | #endif
|
3517 | 0f8a249a | blueswir1 | case 0x27: |
3518 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
3519 | 3475187d | bellard | gen_op_load_fpr_DT0(DFPREG(rd)); |
3520 | 0f8a249a | blueswir1 | gen_op_ldst(stdf); |
3521 | 0f8a249a | blueswir1 | break;
|
3522 | 0f8a249a | blueswir1 | default:
|
3523 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3524 | 0f8a249a | blueswir1 | } |
3525 | 0f8a249a | blueswir1 | } else if (xop > 0x33 && xop < 0x3f) { |
3526 | 0f8a249a | blueswir1 | switch (xop) {
|
3527 | a4d17f19 | blueswir1 | #ifdef TARGET_SPARC64
|
3528 | 0f8a249a | blueswir1 | case 0x34: /* V9 stfa */ |
3529 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3530 | 3391c818 | blueswir1 | gen_op_load_fpr_FT0(rd); |
3531 | 3391c818 | blueswir1 | gen_stf_asi(insn, 4);
|
3532 | 0f8a249a | blueswir1 | break;
|
3533 | 1f587329 | blueswir1 | case 0x36: /* V9 stqfa */ |
3534 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
3535 | 1f587329 | blueswir1 | gen_op_check_align_T0_7(); |
3536 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
3537 | 1f587329 | blueswir1 | gen_stf_asi(insn, 16);
|
3538 | 1f587329 | blueswir1 | break;
|
3539 | 1f587329 | blueswir1 | #else
|
3540 | 1f587329 | blueswir1 | goto nfpu_insn;
|
3541 | 1f587329 | blueswir1 | #endif
|
3542 | 0f8a249a | blueswir1 | case 0x37: /* V9 stdfa */ |
3543 | 3391c818 | blueswir1 | gen_op_check_align_T0_3(); |
3544 | 3391c818 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
3545 | 3391c818 | blueswir1 | gen_stf_asi(insn, 8);
|
3546 | 0f8a249a | blueswir1 | break;
|
3547 | 0f8a249a | blueswir1 | case 0x3c: /* V9 casa */ |
3548 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3549 | 81ad8ba2 | blueswir1 | flush_T2(dc); |
3550 | 81ad8ba2 | blueswir1 | gen_movl_reg_T2(rd); |
3551 | 81ad8ba2 | blueswir1 | gen_cas_asi(insn); |
3552 | 81ad8ba2 | blueswir1 | gen_movl_T1_reg(rd); |
3553 | 0f8a249a | blueswir1 | break;
|
3554 | 0f8a249a | blueswir1 | case 0x3e: /* V9 casxa */ |
3555 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
3556 | 81ad8ba2 | blueswir1 | flush_T2(dc); |
3557 | 81ad8ba2 | blueswir1 | gen_movl_reg_T2(rd); |
3558 | 81ad8ba2 | blueswir1 | gen_casx_asi(insn); |
3559 | 81ad8ba2 | blueswir1 | gen_movl_T1_reg(rd); |
3560 | 0f8a249a | blueswir1 | break;
|
3561 | a4d17f19 | blueswir1 | #else
|
3562 | 0f8a249a | blueswir1 | case 0x34: /* stc */ |
3563 | 0f8a249a | blueswir1 | case 0x35: /* stcsr */ |
3564 | 0f8a249a | blueswir1 | case 0x36: /* stdcq */ |
3565 | 0f8a249a | blueswir1 | case 0x37: /* stdc */ |
3566 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3567 | 0f8a249a | blueswir1 | #endif
|
3568 | 0f8a249a | blueswir1 | default:
|
3569 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3570 | 0f8a249a | blueswir1 | } |
3571 | e8af50a3 | bellard | } |
3572 | 0f8a249a | blueswir1 | else
|
3573 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3574 | 0f8a249a | blueswir1 | } |
3575 | 0f8a249a | blueswir1 | break;
|
3576 | cf495bcf | bellard | } |
3577 | cf495bcf | bellard | /* default case for non jump instructions */
|
3578 | 72cbca10 | bellard | if (dc->npc == DYNAMIC_PC) {
|
3579 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
3580 | 0f8a249a | blueswir1 | gen_op_next_insn(); |
3581 | 72cbca10 | bellard | } else if (dc->npc == JUMP_PC) { |
3582 | 72cbca10 | bellard | /* we can do a static jump */
|
3583 | 46525e1f | blueswir1 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]); |
3584 | 72cbca10 | bellard | dc->is_br = 1;
|
3585 | 72cbca10 | bellard | } else {
|
3586 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
3587 | 0f8a249a | blueswir1 | dc->npc = dc->npc + 4;
|
3588 | cf495bcf | bellard | } |
3589 | e80cfcfc | bellard | jmp_insn:
|
3590 | cf495bcf | bellard | return;
|
3591 | cf495bcf | bellard | illegal_insn:
|
3592 | 72cbca10 | bellard | save_state(dc); |
3593 | cf495bcf | bellard | gen_op_exception(TT_ILL_INSN); |
3594 | cf495bcf | bellard | dc->is_br = 1;
|
3595 | e8af50a3 | bellard | return;
|
3596 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
|
3597 | e8af50a3 | bellard | priv_insn:
|
3598 | e8af50a3 | bellard | save_state(dc); |
3599 | e8af50a3 | bellard | gen_op_exception(TT_PRIV_INSN); |
3600 | e8af50a3 | bellard | dc->is_br = 1;
|
3601 | e80cfcfc | bellard | return;
|
3602 | e80cfcfc | bellard | nfpu_insn:
|
3603 | e80cfcfc | bellard | save_state(dc); |
3604 | e80cfcfc | bellard | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
3605 | e80cfcfc | bellard | dc->is_br = 1;
|
3606 | fcc72045 | blueswir1 | return;
|
3607 | 1f587329 | blueswir1 | #ifndef TARGET_SPARC64
|
3608 | 9143e598 | blueswir1 | nfq_insn:
|
3609 | 9143e598 | blueswir1 | save_state(dc); |
3610 | 9143e598 | blueswir1 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
3611 | 9143e598 | blueswir1 | dc->is_br = 1;
|
3612 | 9143e598 | blueswir1 | return;
|
3613 | 9143e598 | blueswir1 | #endif
|
3614 | 1f587329 | blueswir1 | #endif
|
3615 | fcc72045 | blueswir1 | #ifndef TARGET_SPARC64
|
3616 | fcc72045 | blueswir1 | ncp_insn:
|
3617 | fcc72045 | blueswir1 | save_state(dc); |
3618 | fcc72045 | blueswir1 | gen_op_exception(TT_NCP_INSN); |
3619 | fcc72045 | blueswir1 | dc->is_br = 1;
|
3620 | fcc72045 | blueswir1 | return;
|
3621 | fcc72045 | blueswir1 | #endif
|
3622 | 7a3f1944 | bellard | } |
3623 | 7a3f1944 | bellard | |
3624 | cf495bcf | bellard | static inline int gen_intermediate_code_internal(TranslationBlock * tb, |
3625 | 0f8a249a | blueswir1 | int spc, CPUSPARCState *env)
|
3626 | 7a3f1944 | bellard | { |
3627 | 72cbca10 | bellard | target_ulong pc_start, last_pc; |
3628 | cf495bcf | bellard | uint16_t *gen_opc_end; |
3629 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
3630 | e8af50a3 | bellard | int j, lj = -1; |
3631 | cf495bcf | bellard | |
3632 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
3633 | cf495bcf | bellard | dc->tb = tb; |
3634 | 72cbca10 | bellard | pc_start = tb->pc; |
3635 | cf495bcf | bellard | dc->pc = pc_start; |
3636 | e80cfcfc | bellard | last_pc = dc->pc; |
3637 | 72cbca10 | bellard | dc->npc = (target_ulong) tb->cs_base; |
3638 | 6f27aba6 | blueswir1 | dc->mem_idx = cpu_mmu_index(env); |
3639 | 6f27aba6 | blueswir1 | dc->fpu_enabled = cpu_fpu_enabled(env); |
3640 | cf495bcf | bellard | gen_opc_ptr = gen_opc_buf; |
3641 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
3642 | cf495bcf | bellard | gen_opparam_ptr = gen_opparam_buf; |
3643 | 83469015 | bellard | nb_gen_labels = 0;
|
3644 | cf495bcf | bellard | |
3645 | cf495bcf | bellard | do {
|
3646 | e8af50a3 | bellard | if (env->nb_breakpoints > 0) { |
3647 | e8af50a3 | bellard | for(j = 0; j < env->nb_breakpoints; j++) { |
3648 | e8af50a3 | bellard | if (env->breakpoints[j] == dc->pc) {
|
3649 | 0f8a249a | blueswir1 | if (dc->pc != pc_start)
|
3650 | 0f8a249a | blueswir1 | save_state(dc); |
3651 | e80cfcfc | bellard | gen_op_debug(); |
3652 | 0f8a249a | blueswir1 | gen_op_movl_T0_0(); |
3653 | 0f8a249a | blueswir1 | gen_op_exit_tb(); |
3654 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
3655 | e80cfcfc | bellard | goto exit_gen_loop;
|
3656 | e8af50a3 | bellard | } |
3657 | e8af50a3 | bellard | } |
3658 | e8af50a3 | bellard | } |
3659 | e8af50a3 | bellard | if (spc) {
|
3660 | e8af50a3 | bellard | if (loglevel > 0) |
3661 | e8af50a3 | bellard | fprintf(logfile, "Search PC...\n");
|
3662 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
3663 | e8af50a3 | bellard | if (lj < j) {
|
3664 | e8af50a3 | bellard | lj++; |
3665 | e8af50a3 | bellard | while (lj < j)
|
3666 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
3667 | e8af50a3 | bellard | gen_opc_pc[lj] = dc->pc; |
3668 | e8af50a3 | bellard | gen_opc_npc[lj] = dc->npc; |
3669 | e8af50a3 | bellard | gen_opc_instr_start[lj] = 1;
|
3670 | e8af50a3 | bellard | } |
3671 | e8af50a3 | bellard | } |
3672 | 0f8a249a | blueswir1 | last_pc = dc->pc; |
3673 | 0f8a249a | blueswir1 | disas_sparc_insn(dc); |
3674 | 0f8a249a | blueswir1 | |
3675 | 0f8a249a | blueswir1 | if (dc->is_br)
|
3676 | 0f8a249a | blueswir1 | break;
|
3677 | 0f8a249a | blueswir1 | /* if the next PC is different, we abort now */
|
3678 | 0f8a249a | blueswir1 | if (dc->pc != (last_pc + 4)) |
3679 | 0f8a249a | blueswir1 | break;
|
3680 | d39c0b99 | bellard | /* if we reach a page boundary, we stop generation so that the
|
3681 | d39c0b99 | bellard | PC of a TT_TFAULT exception is always in the right page */
|
3682 | d39c0b99 | bellard | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
3683 | d39c0b99 | bellard | break;
|
3684 | e80cfcfc | bellard | /* if single step mode, we generate only one instruction and
|
3685 | e80cfcfc | bellard | generate an exception */
|
3686 | e80cfcfc | bellard | if (env->singlestep_enabled) {
|
3687 | 3475187d | bellard | gen_jmp_im(dc->pc); |
3688 | e80cfcfc | bellard | gen_op_movl_T0_0(); |
3689 | e80cfcfc | bellard | gen_op_exit_tb(); |
3690 | e80cfcfc | bellard | break;
|
3691 | e80cfcfc | bellard | } |
3692 | cf495bcf | bellard | } while ((gen_opc_ptr < gen_opc_end) &&
|
3693 | 0f8a249a | blueswir1 | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
|
3694 | e80cfcfc | bellard | |
3695 | e80cfcfc | bellard | exit_gen_loop:
|
3696 | 72cbca10 | bellard | if (!dc->is_br) {
|
3697 | 5fafdf24 | ths | if (dc->pc != DYNAMIC_PC &&
|
3698 | 72cbca10 | bellard | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
3699 | 72cbca10 | bellard | /* static PC and NPC: we can use direct chaining */
|
3700 | 46525e1f | blueswir1 | gen_branch(dc, dc->pc, dc->npc); |
3701 | 72cbca10 | bellard | } else {
|
3702 | 72cbca10 | bellard | if (dc->pc != DYNAMIC_PC)
|
3703 | 3475187d | bellard | gen_jmp_im(dc->pc); |
3704 | 72cbca10 | bellard | save_npc(dc); |
3705 | 72cbca10 | bellard | gen_op_movl_T0_0(); |
3706 | 72cbca10 | bellard | gen_op_exit_tb(); |
3707 | 72cbca10 | bellard | } |
3708 | 72cbca10 | bellard | } |
3709 | cf495bcf | bellard | *gen_opc_ptr = INDEX_op_end; |
3710 | e8af50a3 | bellard | if (spc) {
|
3711 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
3712 | e8af50a3 | bellard | lj++; |
3713 | e8af50a3 | bellard | while (lj <= j)
|
3714 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
3715 | e8af50a3 | bellard | #if 0
|
3716 | e8af50a3 | bellard | if (loglevel > 0) {
|
3717 | e8af50a3 | bellard | page_dump(logfile);
|
3718 | e8af50a3 | bellard | }
|
3719 | e8af50a3 | bellard | #endif
|
3720 | c3278b7b | bellard | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
3721 | c3278b7b | bellard | gen_opc_jump_pc[1] = dc->jump_pc[1]; |
3722 | e8af50a3 | bellard | } else {
|
3723 | e80cfcfc | bellard | tb->size = last_pc + 4 - pc_start;
|
3724 | e8af50a3 | bellard | } |
3725 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
3726 | e19e89a5 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
3727 | 0f8a249a | blueswir1 | fprintf(logfile, "--------------\n");
|
3728 | 0f8a249a | blueswir1 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
3729 | 0f8a249a | blueswir1 | target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); |
3730 | 0f8a249a | blueswir1 | fprintf(logfile, "\n");
|
3731 | e19e89a5 | bellard | if (loglevel & CPU_LOG_TB_OP) {
|
3732 | e19e89a5 | bellard | fprintf(logfile, "OP:\n");
|
3733 | e19e89a5 | bellard | dump_ops(gen_opc_buf, gen_opparam_buf); |
3734 | e19e89a5 | bellard | fprintf(logfile, "\n");
|
3735 | e19e89a5 | bellard | } |
3736 | cf495bcf | bellard | } |
3737 | 7a3f1944 | bellard | #endif
|
3738 | cf495bcf | bellard | return 0; |
3739 | 7a3f1944 | bellard | } |
3740 | 7a3f1944 | bellard | |
3741 | cf495bcf | bellard | int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
3742 | 7a3f1944 | bellard | { |
3743 | e8af50a3 | bellard | return gen_intermediate_code_internal(tb, 0, env); |
3744 | 7a3f1944 | bellard | } |
3745 | 7a3f1944 | bellard | |
3746 | cf495bcf | bellard | int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
3747 | 7a3f1944 | bellard | { |
3748 | e8af50a3 | bellard | return gen_intermediate_code_internal(tb, 1, env); |
3749 | 7a3f1944 | bellard | } |
3750 | 7a3f1944 | bellard | |
3751 | e80cfcfc | bellard | extern int ram_size; |
3752 | cf495bcf | bellard | |
3753 | e80cfcfc | bellard | void cpu_reset(CPUSPARCState *env)
|
3754 | e80cfcfc | bellard | { |
3755 | bb05683b | bellard | tlb_flush(env, 1);
|
3756 | cf495bcf | bellard | env->cwp = 0;
|
3757 | cf495bcf | bellard | env->wim = 1;
|
3758 | cf495bcf | bellard | env->regwptr = env->regbase + (env->cwp * 16);
|
3759 | e8af50a3 | bellard | #if defined(CONFIG_USER_ONLY)
|
3760 | cf495bcf | bellard | env->user_mode_only = 1;
|
3761 | 5ef54116 | bellard | #ifdef TARGET_SPARC64
|
3762 | 6ef905f6 | blueswir1 | env->cleanwin = NWINDOWS - 2;
|
3763 | 6ef905f6 | blueswir1 | env->cansave = NWINDOWS - 2;
|
3764 | 6ef905f6 | blueswir1 | env->pstate = PS_RMO | PS_PEF | PS_IE; |
3765 | 6ef905f6 | blueswir1 | env->asi = 0x82; // Primary no-fault |
3766 | 5ef54116 | bellard | #endif
|
3767 | e8af50a3 | bellard | #else
|
3768 | 32af58f9 | blueswir1 | env->psret = 0;
|
3769 | e8af50a3 | bellard | env->psrs = 1;
|
3770 | 0bee699e | bellard | env->psrps = 1;
|
3771 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3772 | 83469015 | bellard | env->pstate = PS_PRIV; |
3773 | 6f27aba6 | blueswir1 | env->hpstate = HS_PRIV; |
3774 | 83469015 | bellard | env->pc = 0x1fff0000000ULL;
|
3775 | 3475187d | bellard | #else
|
3776 | 40ce0a9a | blueswir1 | env->pc = 0;
|
3777 | 32af58f9 | blueswir1 | env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
3778 | 6d5f237a | blueswir1 | env->mmuregs[0] |= env->mmu_bm;
|
3779 | 3475187d | bellard | #endif
|
3780 | 83469015 | bellard | env->npc = env->pc + 4;
|
3781 | e8af50a3 | bellard | #endif
|
3782 | e80cfcfc | bellard | } |
3783 | e80cfcfc | bellard | |
3784 | aaed909a | bellard | CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
3785 | e80cfcfc | bellard | { |
3786 | e80cfcfc | bellard | CPUSPARCState *env; |
3787 | aaed909a | bellard | const sparc_def_t *def;
|
3788 | aaed909a | bellard | |
3789 | aaed909a | bellard | def = cpu_sparc_find_by_name(cpu_model); |
3790 | aaed909a | bellard | if (!def)
|
3791 | aaed909a | bellard | return NULL; |
3792 | e80cfcfc | bellard | |
3793 | c68ea704 | bellard | env = qemu_mallocz(sizeof(CPUSPARCState));
|
3794 | c68ea704 | bellard | if (!env)
|
3795 | 0f8a249a | blueswir1 | return NULL; |
3796 | c68ea704 | bellard | cpu_exec_init(env); |
3797 | aaed909a | bellard | env->version = def->iu_version; |
3798 | aaed909a | bellard | env->fsr = def->fpu_version; |
3799 | aaed909a | bellard | #if !defined(TARGET_SPARC64)
|
3800 | aaed909a | bellard | env->mmu_bm = def->mmu_bm; |
3801 | aaed909a | bellard | env->mmuregs[0] |= def->mmu_version;
|
3802 | aaed909a | bellard | cpu_sparc_set_id(env, 0);
|
3803 | aaed909a | bellard | #endif
|
3804 | aaed909a | bellard | cpu_reset(env); |
3805 | aaed909a | bellard | |
3806 | aaed909a | bellard | return env;
|
3807 | aaed909a | bellard | } |
3808 | aaed909a | bellard | |
3809 | aaed909a | bellard | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
3810 | aaed909a | bellard | { |
3811 | aaed909a | bellard | #if !defined(TARGET_SPARC64)
|
3812 | aaed909a | bellard | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
3813 | aaed909a | bellard | #endif
|
3814 | 7a3f1944 | bellard | } |
3815 | 7a3f1944 | bellard | |
3816 | 62724a37 | blueswir1 | static const sparc_def_t sparc_defs[] = { |
3817 | 62724a37 | blueswir1 | #ifdef TARGET_SPARC64
|
3818 | 62724a37 | blueswir1 | { |
3819 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64",
|
3820 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) |
3821 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3822 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3823 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3824 | 7d77bf20 | blueswir1 | }, |
3825 | 7d77bf20 | blueswir1 | { |
3826 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64 III",
|
3827 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) |
3828 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3829 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3830 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3831 | 7d77bf20 | blueswir1 | }, |
3832 | 7d77bf20 | blueswir1 | { |
3833 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64 IV",
|
3834 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) |
3835 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3836 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3837 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3838 | 7d77bf20 | blueswir1 | }, |
3839 | 7d77bf20 | blueswir1 | { |
3840 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64 V",
|
3841 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) |
3842 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3843 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3844 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3845 | 7d77bf20 | blueswir1 | }, |
3846 | 7d77bf20 | blueswir1 | { |
3847 | 7d77bf20 | blueswir1 | .name = "TI UltraSparc I",
|
3848 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
3849 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3850 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3851 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3852 | 7d77bf20 | blueswir1 | }, |
3853 | 7d77bf20 | blueswir1 | { |
3854 | 62724a37 | blueswir1 | .name = "TI UltraSparc II",
|
3855 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) |
3856 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3857 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3858 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3859 | 7d77bf20 | blueswir1 | }, |
3860 | 7d77bf20 | blueswir1 | { |
3861 | 7d77bf20 | blueswir1 | .name = "TI UltraSparc IIi",
|
3862 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) |
3863 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3864 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3865 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3866 | 7d77bf20 | blueswir1 | }, |
3867 | 7d77bf20 | blueswir1 | { |
3868 | 7d77bf20 | blueswir1 | .name = "TI UltraSparc IIe",
|
3869 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) |
3870 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3871 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3872 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3873 | 7d77bf20 | blueswir1 | }, |
3874 | 7d77bf20 | blueswir1 | { |
3875 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc III",
|
3876 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) |
3877 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3878 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3879 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3880 | 7d77bf20 | blueswir1 | }, |
3881 | 7d77bf20 | blueswir1 | { |
3882 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc III Cu",
|
3883 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) |
3884 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3885 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3886 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3887 | 7d77bf20 | blueswir1 | }, |
3888 | 7d77bf20 | blueswir1 | { |
3889 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IIIi",
|
3890 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) |
3891 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3892 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3893 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3894 | 7d77bf20 | blueswir1 | }, |
3895 | 7d77bf20 | blueswir1 | { |
3896 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IV",
|
3897 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) |
3898 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3899 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3900 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3901 | 7d77bf20 | blueswir1 | }, |
3902 | 7d77bf20 | blueswir1 | { |
3903 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IV+",
|
3904 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) |
3905 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3906 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3907 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3908 | 7d77bf20 | blueswir1 | }, |
3909 | 7d77bf20 | blueswir1 | { |
3910 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IIIi+",
|
3911 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) |
3912 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3913 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
3914 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
3915 | 7d77bf20 | blueswir1 | }, |
3916 | 7d77bf20 | blueswir1 | { |
3917 | 7d77bf20 | blueswir1 | .name = "NEC UltraSparc I",
|
3918 | 7d77bf20 | blueswir1 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
3919 | 62724a37 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
3920 | 62724a37 | blueswir1 | .fpu_version = 0x00000000,
|
3921 | 62724a37 | blueswir1 | .mmu_version = 0,
|
3922 | 62724a37 | blueswir1 | }, |
3923 | 62724a37 | blueswir1 | #else
|
3924 | 62724a37 | blueswir1 | { |
3925 | 406f82e8 | blueswir1 | .name = "Fujitsu MB86900",
|
3926 | 406f82e8 | blueswir1 | .iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
3927 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
3928 | 406f82e8 | blueswir1 | .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
3929 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
3930 | 406f82e8 | blueswir1 | }, |
3931 | 406f82e8 | blueswir1 | { |
3932 | 62724a37 | blueswir1 | .name = "Fujitsu MB86904",
|
3933 | 62724a37 | blueswir1 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
3934 | 62724a37 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
3935 | 62724a37 | blueswir1 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
3936 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
3937 | 62724a37 | blueswir1 | }, |
3938 | e0353fe2 | blueswir1 | { |
3939 | 5ef62c5c | blueswir1 | .name = "Fujitsu MB86907",
|
3940 | 5ef62c5c | blueswir1 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
3941 | 5ef62c5c | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
3942 | 5ef62c5c | blueswir1 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
3943 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
3944 | 5ef62c5c | blueswir1 | }, |
3945 | 5ef62c5c | blueswir1 | { |
3946 | 406f82e8 | blueswir1 | .name = "LSI L64811",
|
3947 | 406f82e8 | blueswir1 | .iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
3948 | 406f82e8 | blueswir1 | .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
3949 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
3950 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
3951 | 406f82e8 | blueswir1 | }, |
3952 | 406f82e8 | blueswir1 | { |
3953 | 406f82e8 | blueswir1 | .name = "Cypress CY7C601",
|
3954 | 406f82e8 | blueswir1 | .iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
3955 | 406f82e8 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
3956 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
3957 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
3958 | 406f82e8 | blueswir1 | }, |
3959 | 406f82e8 | blueswir1 | { |
3960 | 406f82e8 | blueswir1 | .name = "Cypress CY7C611",
|
3961 | 406f82e8 | blueswir1 | .iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
3962 | 406f82e8 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
3963 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
3964 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
3965 | 406f82e8 | blueswir1 | }, |
3966 | 406f82e8 | blueswir1 | { |
3967 | 406f82e8 | blueswir1 | .name = "TI SuperSparc II",
|
3968 | 406f82e8 | blueswir1 | .iu_version = 0x40000000,
|
3969 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, |
3970 | 406f82e8 | blueswir1 | .mmu_version = 0x04000000,
|
3971 | 406f82e8 | blueswir1 | .mmu_bm = 0x00002000,
|
3972 | 406f82e8 | blueswir1 | }, |
3973 | 406f82e8 | blueswir1 | { |
3974 | 5ef62c5c | blueswir1 | .name = "TI MicroSparc I",
|
3975 | 5ef62c5c | blueswir1 | .iu_version = 0x41000000,
|
3976 | 5ef62c5c | blueswir1 | .fpu_version = 4 << 17, |
3977 | 5ef62c5c | blueswir1 | .mmu_version = 0x41000000,
|
3978 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
3979 | 5ef62c5c | blueswir1 | }, |
3980 | 5ef62c5c | blueswir1 | { |
3981 | 406f82e8 | blueswir1 | .name = "TI MicroSparc II",
|
3982 | 406f82e8 | blueswir1 | .iu_version = 0x42000000,
|
3983 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, |
3984 | 406f82e8 | blueswir1 | .mmu_version = 0x02000000,
|
3985 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
3986 | 406f82e8 | blueswir1 | }, |
3987 | 406f82e8 | blueswir1 | { |
3988 | 406f82e8 | blueswir1 | .name = "TI MicroSparc IIep",
|
3989 | 406f82e8 | blueswir1 | .iu_version = 0x42000000,
|
3990 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, |
3991 | 406f82e8 | blueswir1 | .mmu_version = 0x04000000,
|
3992 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
3993 | 406f82e8 | blueswir1 | }, |
3994 | 406f82e8 | blueswir1 | { |
3995 | 406f82e8 | blueswir1 | .name = "TI SuperSparc 51",
|
3996 | 406f82e8 | blueswir1 | .iu_version = 0x43000000,
|
3997 | 5ef62c5c | blueswir1 | .fpu_version = 0 << 17, |
3998 | 5ef62c5c | blueswir1 | .mmu_version = 0x04000000,
|
3999 | 6d5f237a | blueswir1 | .mmu_bm = 0x00002000,
|
4000 | 5ef62c5c | blueswir1 | }, |
4001 | 5ef62c5c | blueswir1 | { |
4002 | 406f82e8 | blueswir1 | .name = "TI SuperSparc 61",
|
4003 | 406f82e8 | blueswir1 | .iu_version = 0x44000000,
|
4004 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, |
4005 | 406f82e8 | blueswir1 | .mmu_version = 0x04000000,
|
4006 | 406f82e8 | blueswir1 | .mmu_bm = 0x00002000,
|
4007 | 406f82e8 | blueswir1 | }, |
4008 | 406f82e8 | blueswir1 | { |
4009 | 406f82e8 | blueswir1 | .name = "Ross RT625",
|
4010 | 5ef62c5c | blueswir1 | .iu_version = 0x1e000000,
|
4011 | 5ef62c5c | blueswir1 | .fpu_version = 1 << 17, |
4012 | 406f82e8 | blueswir1 | .mmu_version = 0x1e000000,
|
4013 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4014 | 406f82e8 | blueswir1 | }, |
4015 | 406f82e8 | blueswir1 | { |
4016 | 406f82e8 | blueswir1 | .name = "Ross RT620",
|
4017 | 406f82e8 | blueswir1 | .iu_version = 0x1f000000,
|
4018 | 406f82e8 | blueswir1 | .fpu_version = 1 << 17, |
4019 | 406f82e8 | blueswir1 | .mmu_version = 0x1f000000,
|
4020 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4021 | 406f82e8 | blueswir1 | }, |
4022 | 406f82e8 | blueswir1 | { |
4023 | 406f82e8 | blueswir1 | .name = "BIT B5010",
|
4024 | 406f82e8 | blueswir1 | .iu_version = 0x20000000,
|
4025 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
4026 | 406f82e8 | blueswir1 | .mmu_version = 0x20000000,
|
4027 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4028 | 406f82e8 | blueswir1 | }, |
4029 | 406f82e8 | blueswir1 | { |
4030 | 406f82e8 | blueswir1 | .name = "Matsushita MN10501",
|
4031 | 406f82e8 | blueswir1 | .iu_version = 0x50000000,
|
4032 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, |
4033 | 406f82e8 | blueswir1 | .mmu_version = 0x50000000,
|
4034 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4035 | 406f82e8 | blueswir1 | }, |
4036 | 406f82e8 | blueswir1 | { |
4037 | 406f82e8 | blueswir1 | .name = "Weitek W8601",
|
4038 | 406f82e8 | blueswir1 | .iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
4039 | 406f82e8 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
4040 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
4041 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4042 | 406f82e8 | blueswir1 | }, |
4043 | 406f82e8 | blueswir1 | { |
4044 | 406f82e8 | blueswir1 | .name = "LEON2",
|
4045 | 406f82e8 | blueswir1 | .iu_version = 0xf2000000,
|
4046 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
4047 | 406f82e8 | blueswir1 | .mmu_version = 0xf2000000,
|
4048 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4049 | 406f82e8 | blueswir1 | }, |
4050 | 406f82e8 | blueswir1 | { |
4051 | 406f82e8 | blueswir1 | .name = "LEON3",
|
4052 | 406f82e8 | blueswir1 | .iu_version = 0xf3000000,
|
4053 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
4054 | 406f82e8 | blueswir1 | .mmu_version = 0xf3000000,
|
4055 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
4056 | e0353fe2 | blueswir1 | }, |
4057 | 62724a37 | blueswir1 | #endif
|
4058 | 62724a37 | blueswir1 | }; |
4059 | 62724a37 | blueswir1 | |
4060 | aaed909a | bellard | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name) |
4061 | 62724a37 | blueswir1 | { |
4062 | 62724a37 | blueswir1 | unsigned int i; |
4063 | 62724a37 | blueswir1 | |
4064 | 62724a37 | blueswir1 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
4065 | 62724a37 | blueswir1 | if (strcasecmp(name, sparc_defs[i].name) == 0) { |
4066 | aaed909a | bellard | return &sparc_defs[i];
|
4067 | 62724a37 | blueswir1 | } |
4068 | 62724a37 | blueswir1 | } |
4069 | aaed909a | bellard | return NULL; |
4070 | 62724a37 | blueswir1 | } |
4071 | 62724a37 | blueswir1 | |
4072 | 62724a37 | blueswir1 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
4073 | 62724a37 | blueswir1 | { |
4074 | 62724a37 | blueswir1 | unsigned int i; |
4075 | 62724a37 | blueswir1 | |
4076 | 62724a37 | blueswir1 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
4077 | 62724a37 | blueswir1 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n", |
4078 | 62724a37 | blueswir1 | sparc_defs[i].name, |
4079 | 62724a37 | blueswir1 | sparc_defs[i].iu_version, |
4080 | 62724a37 | blueswir1 | sparc_defs[i].fpu_version, |
4081 | 62724a37 | blueswir1 | sparc_defs[i].mmu_version); |
4082 | 62724a37 | blueswir1 | } |
4083 | 62724a37 | blueswir1 | } |
4084 | 62724a37 | blueswir1 | |
4085 | 7a3f1944 | bellard | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
4086 | 7a3f1944 | bellard | |
4087 | 5fafdf24 | ths | void cpu_dump_state(CPUState *env, FILE *f,
|
4088 | 7fe48483 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
4089 | 7fe48483 | bellard | int flags)
|
4090 | 7a3f1944 | bellard | { |
4091 | cf495bcf | bellard | int i, x;
|
4092 | cf495bcf | bellard | |
4093 | af7bf89b | bellard | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
4094 | 7fe48483 | bellard | cpu_fprintf(f, "General Registers:\n");
|
4095 | cf495bcf | bellard | for (i = 0; i < 4; i++) |
4096 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
4097 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
4098 | cf495bcf | bellard | for (; i < 8; i++) |
4099 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
4100 | 7fe48483 | bellard | cpu_fprintf(f, "\nCurrent Register Window:\n");
|
4101 | cf495bcf | bellard | for (x = 0; x < 3; x++) { |
4102 | 0f8a249a | blueswir1 | for (i = 0; i < 4; i++) |
4103 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
4104 | 0f8a249a | blueswir1 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
4105 | 0f8a249a | blueswir1 | env->regwptr[i + x * 8]);
|
4106 | 0f8a249a | blueswir1 | cpu_fprintf(f, "\n");
|
4107 | 0f8a249a | blueswir1 | for (; i < 8; i++) |
4108 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
4109 | 0f8a249a | blueswir1 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
4110 | 0f8a249a | blueswir1 | env->regwptr[i + x * 8]);
|
4111 | 0f8a249a | blueswir1 | cpu_fprintf(f, "\n");
|
4112 | cf495bcf | bellard | } |
4113 | 7fe48483 | bellard | cpu_fprintf(f, "\nFloating Point Registers:\n");
|
4114 | e8af50a3 | bellard | for (i = 0; i < 32; i++) { |
4115 | e8af50a3 | bellard | if ((i & 3) == 0) |
4116 | 7fe48483 | bellard | cpu_fprintf(f, "%%f%02d:", i);
|
4117 | 7fe48483 | bellard | cpu_fprintf(f, " %016lf", env->fpr[i]);
|
4118 | e8af50a3 | bellard | if ((i & 3) == 3) |
4119 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
4120 | e8af50a3 | bellard | } |
4121 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
4122 | 3299908c | blueswir1 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
|
4123 | 0f8a249a | blueswir1 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
4124 | ded3ab80 | pbrook | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
|
4125 | 0f8a249a | blueswir1 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
4126 | 0f8a249a | blueswir1 | env->cleanwin, NWINDOWS - 1 - env->cwp);
|
4127 | ded3ab80 | pbrook | #else
|
4128 | 7fe48483 | bellard | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
|
4129 | 0f8a249a | blueswir1 | GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
4130 | 0f8a249a | blueswir1 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
4131 | 0f8a249a | blueswir1 | env->psrs?'S':'-', env->psrps?'P':'-', |
4132 | 0f8a249a | blueswir1 | env->psret?'E':'-', env->wim); |
4133 | ded3ab80 | pbrook | #endif
|
4134 | 3475187d | bellard | cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
|
4135 | 7a3f1944 | bellard | } |
4136 | edfcbd99 | bellard | |
4137 | e80cfcfc | bellard | #if defined(CONFIG_USER_ONLY)
|
4138 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
4139 | edfcbd99 | bellard | { |
4140 | edfcbd99 | bellard | return addr;
|
4141 | edfcbd99 | bellard | } |
4142 | 658138bc | bellard | |
4143 | e80cfcfc | bellard | #else
|
4144 | af7bf89b | bellard | extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
4145 | af7bf89b | bellard | int *access_index, target_ulong address, int rw, |
4146 | 6ebbf390 | j_mayer | int mmu_idx);
|
4147 | 0fa85d43 | bellard | |
4148 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
4149 | e80cfcfc | bellard | { |
4150 | af7bf89b | bellard | target_phys_addr_t phys_addr; |
4151 | e80cfcfc | bellard | int prot, access_index;
|
4152 | e80cfcfc | bellard | |
4153 | e80cfcfc | bellard | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0) |
4154 | 6b1575b7 | bellard | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0) |
4155 | 6b1575b7 | bellard | return -1; |
4156 | 6c36d3fa | blueswir1 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
4157 | 6c36d3fa | blueswir1 | return -1; |
4158 | e80cfcfc | bellard | return phys_addr;
|
4159 | e80cfcfc | bellard | } |
4160 | e80cfcfc | bellard | #endif
|
4161 | e80cfcfc | bellard | |
4162 | 658138bc | bellard | void helper_flush(target_ulong addr)
|
4163 | 658138bc | bellard | { |
4164 | 658138bc | bellard | addr &= ~7;
|
4165 | 658138bc | bellard | tb_invalidate_page_range(addr, addr + 8);
|
4166 | 658138bc | bellard | } |