root / target-sparc / fop_template.h @ 1f587329
History | View | Annotate | Download (2.9 kB)
| 1 |
/*
|
|---|---|
| 2 |
* SPARC micro operations (templates for various register related
|
| 3 |
* operations)
|
| 4 |
*
|
| 5 |
* Copyright (c) 2003 Fabrice Bellard
|
| 6 |
*
|
| 7 |
* This library is free software; you can redistribute it and/or
|
| 8 |
* modify it under the terms of the GNU Lesser General Public
|
| 9 |
* License as published by the Free Software Foundation; either
|
| 10 |
* version 2 of the License, or (at your option) any later version.
|
| 11 |
*
|
| 12 |
* This library is distributed in the hope that it will be useful,
|
| 13 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 14 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
| 15 |
* Lesser General Public License for more details.
|
| 16 |
*
|
| 17 |
* You should have received a copy of the GNU Lesser General Public
|
| 18 |
* License along with this library; if not, write to the Free Software
|
| 19 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
| 20 |
*/
|
| 21 |
|
| 22 |
/* floating point registers moves */
|
| 23 |
void OPPROTO glue(op_load_fpr_FT0_fpr, REGNAME)(void) |
| 24 |
{
|
| 25 |
FT0 = REG; |
| 26 |
} |
| 27 |
|
| 28 |
void OPPROTO glue(op_store_FT0_fpr_fpr, REGNAME)(void) |
| 29 |
{
|
| 30 |
REG = FT0; |
| 31 |
} |
| 32 |
|
| 33 |
void OPPROTO glue(op_load_fpr_FT1_fpr, REGNAME)(void) |
| 34 |
{
|
| 35 |
FT1 = REG; |
| 36 |
} |
| 37 |
|
| 38 |
void OPPROTO glue(op_store_FT1_fpr_fpr, REGNAME)(void) |
| 39 |
{
|
| 40 |
REG = FT1; |
| 41 |
} |
| 42 |
|
| 43 |
/* double floating point registers moves */
|
| 44 |
void OPPROTO glue(op_load_fpr_DT0_fpr, REGNAME)(void) |
| 45 |
{
|
| 46 |
CPU_DoubleU u; |
| 47 |
uint32_t *p = (uint32_t *)® |
| 48 |
u.l.lower = *(p +1);
|
| 49 |
u.l.upper = *p; |
| 50 |
DT0 = u.d; |
| 51 |
} |
| 52 |
|
| 53 |
void OPPROTO glue(op_store_DT0_fpr_fpr, REGNAME)(void) |
| 54 |
{
|
| 55 |
CPU_DoubleU u; |
| 56 |
uint32_t *p = (uint32_t *)® |
| 57 |
u.d = DT0; |
| 58 |
*(p +1) = u.l.lower;
|
| 59 |
*p = u.l.upper; |
| 60 |
} |
| 61 |
|
| 62 |
void OPPROTO glue(op_load_fpr_DT1_fpr, REGNAME)(void) |
| 63 |
{
|
| 64 |
CPU_DoubleU u; |
| 65 |
uint32_t *p = (uint32_t *)® |
| 66 |
u.l.lower = *(p +1);
|
| 67 |
u.l.upper = *p; |
| 68 |
DT1 = u.d; |
| 69 |
} |
| 70 |
|
| 71 |
void OPPROTO glue(op_store_DT1_fpr_fpr, REGNAME)(void) |
| 72 |
{
|
| 73 |
CPU_DoubleU u; |
| 74 |
uint32_t *p = (uint32_t *)® |
| 75 |
u.d = DT1; |
| 76 |
*(p +1) = u.l.lower;
|
| 77 |
*p = u.l.upper; |
| 78 |
} |
| 79 |
|
| 80 |
#if defined(CONFIG_USER_ONLY)
|
| 81 |
/* quad floating point registers moves */
|
| 82 |
void OPPROTO glue(op_load_fpr_QT0_fpr, REGNAME)(void) |
| 83 |
{
|
| 84 |
CPU_QuadU u; |
| 85 |
uint32_t *p = (uint32_t *)® |
| 86 |
u.l.lowest = *(p + 3);
|
| 87 |
u.l.lower = *(p + 2);
|
| 88 |
u.l.upper = *(p + 1);
|
| 89 |
u.l.upmost = *p; |
| 90 |
QT0 = u.q; |
| 91 |
} |
| 92 |
|
| 93 |
void OPPROTO glue(op_store_QT0_fpr_fpr, REGNAME)(void) |
| 94 |
{
|
| 95 |
CPU_QuadU u; |
| 96 |
uint32_t *p = (uint32_t *)® |
| 97 |
u.q = QT0; |
| 98 |
*(p + 3) = u.l.lowest;
|
| 99 |
*(p + 2) = u.l.lower;
|
| 100 |
*(p + 1) = u.l.upper;
|
| 101 |
*p = u.l.upmost; |
| 102 |
} |
| 103 |
|
| 104 |
void OPPROTO glue(op_load_fpr_QT1_fpr, REGNAME)(void) |
| 105 |
{
|
| 106 |
CPU_QuadU u; |
| 107 |
uint32_t *p = (uint32_t *)® |
| 108 |
u.l.lowest = *(p + 3);
|
| 109 |
u.l.lower = *(p + 2);
|
| 110 |
u.l.upper = *(p + 1);
|
| 111 |
u.l.upmost = *p; |
| 112 |
QT1 = u.q; |
| 113 |
} |
| 114 |
|
| 115 |
void OPPROTO glue(op_store_QT1_fpr_fpr, REGNAME)(void) |
| 116 |
{
|
| 117 |
CPU_QuadU u; |
| 118 |
uint32_t *p = (uint32_t *)® |
| 119 |
u.q = QT1; |
| 120 |
*(p + 3) = u.l.lowest;
|
| 121 |
*(p + 2) = u.l.lower;
|
| 122 |
*(p + 1) = u.l.upper;
|
| 123 |
*p = u.l.upmost; |
| 124 |
} |
| 125 |
#endif
|
| 126 |
|
| 127 |
#undef REG
|
| 128 |
#undef REGNAME
|