Revision 1f6f408c
| b/hw/apic.c | ||
|---|---|---|
| 223 | 223 |
} |
| 224 | 224 |
|
| 225 | 225 |
static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
| 226 |
uint8_t delivery_mode, |
|
| 227 |
uint8_t vector_num, uint8_t polarity, |
|
| 226 |
uint8_t delivery_mode, uint8_t vector_num, |
|
| 228 | 227 |
uint8_t trigger_mode) |
| 229 | 228 |
{
|
| 230 | 229 |
APICState *apic_iter; |
| ... | ... | |
| 281 | 280 |
apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
| 282 | 281 |
} |
| 283 | 282 |
|
| 284 |
void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, |
|
| 285 |
uint8_t delivery_mode, uint8_t vector_num, |
|
| 286 |
uint8_t polarity, uint8_t trigger_mode) |
|
| 283 |
void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, |
|
| 284 |
uint8_t vector_num, uint8_t trigger_mode) |
|
| 287 | 285 |
{
|
| 288 | 286 |
uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
| 289 | 287 |
|
| 290 | 288 |
trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, |
| 291 |
polarity, trigger_mode);
|
|
| 289 |
trigger_mode); |
|
| 292 | 290 |
|
| 293 | 291 |
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
| 294 |
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
|
| 295 |
trigger_mode); |
|
| 292 |
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
|
| 296 | 293 |
} |
| 297 | 294 |
|
| 298 | 295 |
void cpu_set_apic_base(DeviceState *d, uint64_t val) |
| ... | ... | |
| 549 | 546 |
|
| 550 | 547 |
static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, |
| 551 | 548 |
uint8_t delivery_mode, uint8_t vector_num, |
| 552 |
uint8_t polarity, uint8_t trigger_mode)
|
|
| 549 |
uint8_t trigger_mode) |
|
| 553 | 550 |
{
|
| 554 | 551 |
APICState *s = DO_UPCAST(APICState, busdev.qdev, d); |
| 555 | 552 |
uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
| ... | ... | |
| 592 | 589 |
return; |
| 593 | 590 |
} |
| 594 | 591 |
|
| 595 |
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
|
| 596 |
trigger_mode); |
|
| 592 |
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
|
| 597 | 593 |
} |
| 598 | 594 |
|
| 599 | 595 |
int apic_get_interrupt(DeviceState *d) |
| ... | ... | |
| 795 | 791 |
uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; |
| 796 | 792 |
uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; |
| 797 | 793 |
/* XXX: Ignore redirection hint. */ |
| 798 |
apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
|
|
| 794 |
apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); |
|
| 799 | 795 |
} |
| 800 | 796 |
|
| 801 | 797 |
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| ... | ... | |
| 856 | 852 |
s->icr[0] = val; |
| 857 | 853 |
apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
| 858 | 854 |
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
| 859 |
(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
|
|
| 855 |
(s->icr[0] >> 15) & 1); |
|
| 860 | 856 |
break; |
| 861 | 857 |
case 0x31: |
| 862 | 858 |
s->icr[1] = val; |
| b/hw/apic.h | ||
|---|---|---|
| 4 | 4 |
#include "qemu-common.h" |
| 5 | 5 |
|
| 6 | 6 |
/* apic.c */ |
| 7 |
void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, |
|
| 8 |
uint8_t delivery_mode, |
|
| 9 |
uint8_t vector_num, uint8_t polarity, |
|
| 10 |
uint8_t trigger_mode); |
|
| 7 |
void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, |
|
| 8 |
uint8_t vector_num, uint8_t trigger_mode); |
|
| 11 | 9 |
int apic_accept_pic_intr(DeviceState *s); |
| 12 | 10 |
void apic_deliver_pic_intr(DeviceState *s, int level); |
| 13 | 11 |
int apic_get_interrupt(DeviceState *s); |
| b/hw/ioapic.c | ||
|---|---|---|
| 104 | 104 |
uint64_t entry; |
| 105 | 105 |
uint8_t dest; |
| 106 | 106 |
uint8_t dest_mode; |
| 107 |
uint8_t polarity; |
|
| 108 | 107 |
|
| 109 | 108 |
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
|
| 110 | 109 |
mask = 1 << i; |
| ... | ... | |
| 116 | 115 |
dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; |
| 117 | 116 |
delivery_mode = |
| 118 | 117 |
(entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK; |
| 119 |
polarity = (entry >> IOAPIC_LVT_POLARITY_SHIFT) & 1; |
|
| 120 | 118 |
if (trig_mode == IOAPIC_TRIGGER_EDGE) {
|
| 121 | 119 |
s->irr &= ~mask; |
| 122 | 120 |
} else {
|
| ... | ... | |
| 128 | 126 |
vector = entry & IOAPIC_VECTOR_MASK; |
| 129 | 127 |
} |
| 130 | 128 |
apic_deliver_irq(dest, dest_mode, delivery_mode, |
| 131 |
vector, polarity, trig_mode);
|
|
| 129 |
vector, trig_mode); |
|
| 132 | 130 |
} |
| 133 | 131 |
} |
| 134 | 132 |
} |
| b/trace-events | ||
|---|---|---|
| 90 | 90 |
|
| 91 | 91 |
# hw/apic.c |
| 92 | 92 |
disable apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d" |
| 93 |
disable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t polarity, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d polarity %d trigger_mode %d"
|
|
| 93 |
disable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d trigger_mode %d"
|
|
| 94 | 94 |
disable cpu_set_apic_base(uint64_t val) "%016"PRIx64"" |
| 95 | 95 |
disable cpu_get_apic_base(uint64_t val) "%016"PRIx64"" |
| 96 | 96 |
disable apic_mem_readl(uint64_t addr, uint32_t val) "%"PRIx64" = %08x" |
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