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/*
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* ARM virtual CPU header
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_ARM_H
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#define CPU_ARM_H
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#include "config.h" |
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#include "kvm-consts.h" |
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#if defined(TARGET_AARCH64)
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/* AArch64 definitions */
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# define TARGET_LONG_BITS 64 |
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# define ELF_MACHINE EM_AARCH64
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#else
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# define TARGET_LONG_BITS 32 |
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# define ELF_MACHINE EM_ARM
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#endif
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#define CPUArchState struct CPUARMState |
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#include "qemu-common.h" |
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#include "exec/cpu-defs.h" |
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#include "fpu/softfloat.h" |
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#define TARGET_HAS_ICE 1 |
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#define EXCP_UDEF 1 /* undefined instruction */ |
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#define EXCP_SWI 2 /* software interrupt */ |
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#define EXCP_PREFETCH_ABORT 3 |
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#define EXCP_DATA_ABORT 4 |
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#define EXCP_IRQ 5 |
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#define EXCP_FIQ 6 |
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#define EXCP_BKPT 7 |
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#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
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#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
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#define EXCP_STREX 10 |
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#define ARMV7M_EXCP_RESET 1 |
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#define ARMV7M_EXCP_NMI 2 |
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#define ARMV7M_EXCP_HARD 3 |
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#define ARMV7M_EXCP_MEM 4 |
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#define ARMV7M_EXCP_BUS 5 |
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#define ARMV7M_EXCP_USAGE 6 |
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#define ARMV7M_EXCP_SVC 11 |
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#define ARMV7M_EXCP_DEBUG 12 |
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#define ARMV7M_EXCP_PENDSV 14 |
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#define ARMV7M_EXCP_SYSTICK 15 |
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/* ARM-specific interrupt pending bits. */
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#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
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/* The usual mapping for an AArch64 system register to its AArch32
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* counterpart is for the 32 bit world to have access to the lower
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* half only (with writes leaving the upper half untouched). It's
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* therefore useful to be able to pass TCG the offset of the least
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* significant half of a uint64_t struct member.
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*/
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#ifdef HOST_WORDS_BIGENDIAN
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#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) |
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#define offsetofhigh32(S, M) offsetof(S, M)
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#else
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#define offsetoflow32(S, M) offsetof(S, M)
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#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) |
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#endif
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/* Meanings of the ARMCPU object's two inbound GPIO lines */
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#define ARM_CPU_IRQ 0 |
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#define ARM_CPU_FIQ 1 |
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typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
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int srcreg, int operand, uint32_t value); |
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typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, |
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int dstreg, int operand); |
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struct arm_boot_info;
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#define NB_MMU_MODES 2 |
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/* We currently assume float and double are IEEE single and double
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precision respectively.
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Doing runtime conversions is tricky because VFP registers may contain
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integer values (eg. as the result of a FTOSI instruction).
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s<2n> maps to the least significant half of d<n>
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s<2n+1> maps to the most significant half of d<n>
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*/
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/* CPU state for each instance of a generic timer (in cp15 c14) */
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typedef struct ARMGenericTimer { |
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uint64_t cval; /* Timer CompareValue register */
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uint64_t ctl; /* Timer Control register */
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} ARMGenericTimer; |
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#define GTIMER_PHYS 0 |
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#define GTIMER_VIRT 1 |
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#define NUM_GTIMERS 2 |
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/* Scale factor for generic timers, ie number of ns per tick.
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* This gives a 62.5MHz timer.
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*/
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#define GTIMER_SCALE 16 |
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typedef struct CPUARMState { |
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/* Regs for current mode. */
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uint32_t regs[16];
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/* 32/64 switch only happens when taking and returning from
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* exceptions so the overlap semantics are taken care of then
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* instead of having a complicated union.
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*/
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/* Regs for A64 mode. */
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uint64_t xregs[32];
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uint64_t pc; |
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/* PSTATE isn't an architectural register for ARMv8. However, it is
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* convenient for us to assemble the underlying state into a 32 bit format
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* identical to the architectural format used for the SPSR. (This is also
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* what the Linux kernel's 'pstate' field in signal handlers and KVM's
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* 'pstate' register are.) Of the PSTATE bits:
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* NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
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* semantics as for AArch32, as described in the comments on each field)
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* nRW (also known as M[4]) is kept, inverted, in env->aarch64
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* DAIF (exception masks) are kept in env->daif
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* all other bits are stored in their correct places in env->pstate
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*/
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uint32_t pstate; |
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uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
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/* Frequently accessed CPSR bits are stored separately for efficiency.
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This contains all the other bits. Use cpsr_{read,write} to access
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the whole CPSR. */
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uint32_t uncached_cpsr; |
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uint32_t spsr; |
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/* Banked registers. */
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uint32_t banked_spsr[6];
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uint32_t banked_r13[6];
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uint32_t banked_r14[6];
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/* These hold r8-r12. */
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uint32_t usr_regs[5];
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uint32_t fiq_regs[5];
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/* cpsr flag cache for faster execution */
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uint32_t CF; /* 0 or 1 */
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uint32_t VF; /* V is the bit 31. All other bits are undefined */
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uint32_t NF; /* N is bit 31. All other bits are undefined. */
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uint32_t ZF; /* Z set if zero. */
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uint32_t QF; /* 0 or 1 */
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uint32_t GE; /* cpsr[19:16] */
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uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
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uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
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uint32_t daif; /* exception masks, in the bits they are in in PSTATE */
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/* System control coprocessor (cp15) */
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struct {
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uint32_t c0_cpuid; |
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uint64_t c0_cssel; /* Cache size selection. */
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uint64_t c1_sys; /* System control register. */
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uint64_t c1_coproc; /* Coprocessor access register. */
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uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
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uint32_t c1_scr; /* secure config register. */
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uint64_t ttbr0_el1; /* MMU translation table base 0. */
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uint64_t ttbr1_el1; /* MMU translation table base 1. */
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uint64_t c2_control; /* MMU translation table base control. */
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uint32_t c2_mask; /* MMU translation table base selection mask. */
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uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
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uint32_t c2_data; /* MPU data cachable bits. */
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uint32_t c2_insn; /* MPU instruction cachable bits. */
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uint32_t c3; /* MMU domain access control register
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MPU write buffer control. */
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uint32_t c5_insn; /* Fault status registers. */
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uint32_t c5_data; |
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uint32_t c6_region[8]; /* MPU base/size registers. */ |
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uint32_t c6_insn; /* Fault address registers. */
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uint32_t c6_data; |
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uint32_t c7_par; /* Translation result. */
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uint32_t c7_par_hi; /* Translation result, high 32 bits */
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uint32_t c9_insn; /* Cache lockdown registers. */
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uint32_t c9_data; |
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uint32_t c9_pmcr; /* performance monitor control register */
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uint32_t c9_pmcnten; /* perf monitor counter enables */
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uint32_t c9_pmovsr; /* perf monitor overflow status */
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uint32_t c9_pmxevtyper; /* perf monitor event type */
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uint32_t c9_pmuserenr; /* perf monitor user enable */
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uint32_t c9_pminten; /* perf monitor interrupt enables */
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uint64_t mair_el1; |
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uint64_t c12_vbar; /* vector base address register */
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uint32_t c13_fcse; /* FCSE PID. */
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uint32_t c13_context; /* Context ID. */
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uint64_t tpidr_el0; /* User RW Thread register. */
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uint64_t tpidrro_el0; /* User RO Thread register. */
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uint64_t tpidr_el1; /* Privileged Thread register. */
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uint64_t c14_cntfrq; /* Counter Frequency register */
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uint64_t c14_cntkctl; /* Timer Control register */
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ARMGenericTimer c14_timer[NUM_GTIMERS]; |
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uint32_t c15_cpar; /* XScale Coprocessor Access Register */
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uint32_t c15_ticonfig; /* TI925T configuration byte. */
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uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
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uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
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uint32_t c15_threadid; /* TI debugger thread-ID. */
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uint32_t c15_config_base_address; /* SCU base address. */
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uint32_t c15_diagnostic; /* diagnostic register */
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uint32_t c15_power_diagnostic; |
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uint32_t c15_power_control; /* power control */
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uint64_t dbgbvr[16]; /* breakpoint value registers */ |
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uint64_t dbgbcr[16]; /* breakpoint control registers */ |
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uint64_t dbgwvr[16]; /* watchpoint value registers */ |
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uint64_t dbgwcr[16]; /* watchpoint control registers */ |
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} cp15; |
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struct {
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uint32_t other_sp; |
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uint32_t vecbase; |
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uint32_t basepri; |
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uint32_t control; |
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int current_sp;
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int exception;
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int pending_exception;
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} v7m; |
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/* Thumb-2 EE state. */
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uint32_t teecr; |
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uint32_t teehbr; |
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/* VFP coprocessor state. */
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struct {
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/* VFP/Neon register state. Note that the mapping between S, D and Q
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* views of the register bank differs between AArch64 and AArch32:
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* In AArch32:
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* Qn = regs[2n+1]:regs[2n]
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* Dn = regs[n]
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* Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
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* (and regs[32] to regs[63] are inaccessible)
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* In AArch64:
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* Qn = regs[2n+1]:regs[2n]
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* Dn = regs[2n]
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* Sn = regs[2n] bits 31..0
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* This corresponds to the architecturally defined mapping between
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* the two execution states, and means we do not need to explicitly
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* map these registers when changing states.
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*/
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float64 regs[64];
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uint32_t xregs[16];
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/* We store these fpcsr fields separately for convenience. */
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int vec_len;
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int vec_stride;
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/* scratch space when Tn are not sufficient. */
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uint32_t scratch[8];
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/* fp_status is the "normal" fp status. standard_fp_status retains
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* values corresponding to the ARM "Standard FPSCR Value", ie
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* default-NaN, flush-to-zero, round-to-nearest and is used by
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* any operations (generally Neon) which the architecture defines
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* as controlled by the standard FPSCR value rather than the FPSCR.
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*
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* To avoid having to transfer exception bits around, we simply
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* say that the FPSCR cumulative exception flags are the logical
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* OR of the flags in the two fp statuses. This relies on the
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* only thing which needs to read the exception flags being
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* an explicit FPSCR read.
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*/
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float_status fp_status; |
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float_status standard_fp_status; |
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} vfp; |
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uint64_t exclusive_addr; |
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uint64_t exclusive_val; |
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uint64_t exclusive_high; |
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#if defined(CONFIG_USER_ONLY)
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uint64_t exclusive_test; |
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uint32_t exclusive_info; |
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#endif
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/* iwMMXt coprocessor state. */
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struct {
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uint64_t regs[16];
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uint64_t val; |
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uint32_t cregs[16];
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} iwmmxt; |
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/* For mixed endian mode. */
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bool bswap_code;
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#if defined(CONFIG_USER_ONLY)
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/* For usermode syscall translation. */
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int eabi;
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#endif
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CPU_COMMON |
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/* These fields after the common ones so they are preserved on reset. */
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/* Internal CPU feature flags. */
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uint64_t features; |
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void *nvic;
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const struct arm_boot_info *boot_info; |
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} CPUARMState; |
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#include "cpu-qom.h" |
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ARMCPU *cpu_arm_init(const char *cpu_model); |
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void arm_translate_init(void); |
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void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
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int cpu_arm_exec(CPUARMState *s);
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int bank_number(int mode); |
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void switch_mode(CPUARMState *, int); |
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uint32_t do_arm_semihosting(CPUARMState *env); |
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static inline bool is_a64(CPUARMState *env) |
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{ |
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return env->aarch64;
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} |
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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int cpu_arm_signal_handler(int host_signum, void *pinfo, |
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void *puc);
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int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
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int mmu_idx);
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#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
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/* SCTLR bit meanings. Several bits have been reused in newer
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* versions of the architecture; in that case we define constants
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* for both old and new bit meanings. Code which tests against those
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* bits should probably check or otherwise arrange that the CPU
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* is the architectural version it expects.
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*/
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#define SCTLR_M (1U << 0) |
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#define SCTLR_A (1U << 1) |
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#define SCTLR_C (1U << 2) |
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#define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ |
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#define SCTLR_SA (1U << 3) |
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#define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ |
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#define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ |
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#define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ |
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#define SCTLR_CP15BEN (1U << 5) /* v7 onward */ |
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#define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ |
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#define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ |
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#define SCTLR_ITD (1U << 7) /* v8 onward */ |
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#define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ |
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#define SCTLR_SED (1U << 8) /* v8 onward */ |
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#define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ |
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#define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ |
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#define SCTLR_F (1U << 10) /* up to v6 */ |
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#define SCTLR_SW (1U << 10) /* v7 onward */ |
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#define SCTLR_Z (1U << 11) |
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#define SCTLR_I (1U << 12) |
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#define SCTLR_V (1U << 13) |
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#define SCTLR_RR (1U << 14) /* up to v7 */ |
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#define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ |
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#define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ |
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#define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ |
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#define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ |
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#define SCTLR_nTWI (1U << 16) /* v8 onward */ |
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#define SCTLR_HA (1U << 17) |
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#define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ |
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#define SCTLR_nTWE (1U << 18) /* v8 onward */ |
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#define SCTLR_WXN (1U << 19) |
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#define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ |
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#define SCTLR_UWXN (1U << 20) /* v7 onward */ |
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#define SCTLR_FI (1U << 21) |
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#define SCTLR_U (1U << 22) |
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#define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ |
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#define SCTLR_VE (1U << 24) /* up to v7 */ |
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#define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ |
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#define SCTLR_EE (1U << 25) |
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#define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ |
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#define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ |
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#define SCTLR_NMFI (1U << 27) |
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#define SCTLR_TRE (1U << 28) |
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#define SCTLR_AFE (1U << 29) |
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#define SCTLR_TE (1U << 30) |
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|
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#define CPSR_M (0x1fU) |
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#define CPSR_T (1U << 5) |
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#define CPSR_F (1U << 6) |
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#define CPSR_I (1U << 7) |
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#define CPSR_A (1U << 8) |
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#define CPSR_E (1U << 9) |
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#define CPSR_IT_2_7 (0xfc00U) |
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#define CPSR_GE (0xfU << 16) |
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#define CPSR_RESERVED (0xfU << 20) |
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#define CPSR_J (1U << 24) |
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#define CPSR_IT_0_1 (3U << 25) |
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#define CPSR_Q (1U << 27) |
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#define CPSR_V (1U << 28) |
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#define CPSR_C (1U << 29) |
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#define CPSR_Z (1U << 30) |
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#define CPSR_N (1U << 31) |
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#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
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#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
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|
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#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
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#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
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| CPSR_NZCV) |
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/* Bits writable in user mode. */
|
417 |
#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
|
418 |
/* Execution state bits. MRS read as zero, MSR writes ignored. */
|
419 |
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
|
420 |
|
421 |
/* Bit definitions for ARMv8 SPSR (PSTATE) format.
|
422 |
* Only these are valid when in AArch64 mode; in
|
423 |
* AArch32 mode SPSRs are basically CPSR-format.
|
424 |
*/
|
425 |
#define PSTATE_M (0xFU) |
426 |
#define PSTATE_nRW (1U << 4) |
427 |
#define PSTATE_F (1U << 6) |
428 |
#define PSTATE_I (1U << 7) |
429 |
#define PSTATE_A (1U << 8) |
430 |
#define PSTATE_D (1U << 9) |
431 |
#define PSTATE_IL (1U << 20) |
432 |
#define PSTATE_SS (1U << 21) |
433 |
#define PSTATE_V (1U << 28) |
434 |
#define PSTATE_C (1U << 29) |
435 |
#define PSTATE_Z (1U << 30) |
436 |
#define PSTATE_N (1U << 31) |
437 |
#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
|
438 |
#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
|
439 |
#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
|
440 |
/* Mode values for AArch64 */
|
441 |
#define PSTATE_MODE_EL3h 13 |
442 |
#define PSTATE_MODE_EL3t 12 |
443 |
#define PSTATE_MODE_EL2h 9 |
444 |
#define PSTATE_MODE_EL2t 8 |
445 |
#define PSTATE_MODE_EL1h 5 |
446 |
#define PSTATE_MODE_EL1t 4 |
447 |
#define PSTATE_MODE_EL0t 0 |
448 |
|
449 |
/* Return the current PSTATE value. For the moment we don't support 32<->64 bit
|
450 |
* interprocessing, so we don't attempt to sync with the cpsr state used by
|
451 |
* the 32 bit decoder.
|
452 |
*/
|
453 |
static inline uint32_t pstate_read(CPUARMState *env) |
454 |
{ |
455 |
int ZF;
|
456 |
|
457 |
ZF = (env->ZF == 0);
|
458 |
return (env->NF & 0x80000000) | (ZF << 30) |
459 |
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3) |
460 |
| env->pstate | env->daif; |
461 |
} |
462 |
|
463 |
static inline void pstate_write(CPUARMState *env, uint32_t val) |
464 |
{ |
465 |
env->ZF = (~val) & PSTATE_Z; |
466 |
env->NF = val; |
467 |
env->CF = (val >> 29) & 1; |
468 |
env->VF = (val << 3) & 0x80000000; |
469 |
env->daif = val & PSTATE_DAIF; |
470 |
env->pstate = val & ~CACHED_PSTATE_BITS; |
471 |
} |
472 |
|
473 |
/* Return the current CPSR value. */
|
474 |
uint32_t cpsr_read(CPUARMState *env); |
475 |
/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
|
476 |
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
|
477 |
|
478 |
/* Return the current xPSR value. */
|
479 |
static inline uint32_t xpsr_read(CPUARMState *env) |
480 |
{ |
481 |
int ZF;
|
482 |
ZF = (env->ZF == 0);
|
483 |
return (env->NF & 0x80000000) | (ZF << 30) |
484 |
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
485 |
| (env->thumb << 24) | ((env->condexec_bits & 3) << 25) |
486 |
| ((env->condexec_bits & 0xfc) << 8) |
487 |
| env->v7m.exception; |
488 |
} |
489 |
|
490 |
/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
|
491 |
static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
492 |
{ |
493 |
if (mask & CPSR_NZCV) {
|
494 |
env->ZF = (~val) & CPSR_Z; |
495 |
env->NF = val; |
496 |
env->CF = (val >> 29) & 1; |
497 |
env->VF = (val << 3) & 0x80000000; |
498 |
} |
499 |
if (mask & CPSR_Q)
|
500 |
env->QF = ((val & CPSR_Q) != 0);
|
501 |
if (mask & (1 << 24)) |
502 |
env->thumb = ((val & (1 << 24)) != 0); |
503 |
if (mask & CPSR_IT_0_1) {
|
504 |
env->condexec_bits &= ~3;
|
505 |
env->condexec_bits |= (val >> 25) & 3; |
506 |
} |
507 |
if (mask & CPSR_IT_2_7) {
|
508 |
env->condexec_bits &= 3;
|
509 |
env->condexec_bits |= (val >> 8) & 0xfc; |
510 |
} |
511 |
if (mask & 0x1ff) { |
512 |
env->v7m.exception = val & 0x1ff;
|
513 |
} |
514 |
} |
515 |
|
516 |
/* Return the current FPSCR value. */
|
517 |
uint32_t vfp_get_fpscr(CPUARMState *env); |
518 |
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
|
519 |
|
520 |
/* For A64 the FPSCR is split into two logically distinct registers,
|
521 |
* FPCR and FPSR. However since they still use non-overlapping bits
|
522 |
* we store the underlying state in fpscr and just mask on read/write.
|
523 |
*/
|
524 |
#define FPSR_MASK 0xf800009f |
525 |
#define FPCR_MASK 0x07f79f00 |
526 |
static inline uint32_t vfp_get_fpsr(CPUARMState *env) |
527 |
{ |
528 |
return vfp_get_fpscr(env) & FPSR_MASK;
|
529 |
} |
530 |
|
531 |
static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) |
532 |
{ |
533 |
uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); |
534 |
vfp_set_fpscr(env, new_fpscr); |
535 |
} |
536 |
|
537 |
static inline uint32_t vfp_get_fpcr(CPUARMState *env) |
538 |
{ |
539 |
return vfp_get_fpscr(env) & FPCR_MASK;
|
540 |
} |
541 |
|
542 |
static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) |
543 |
{ |
544 |
uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); |
545 |
vfp_set_fpscr(env, new_fpscr); |
546 |
} |
547 |
|
548 |
enum arm_fprounding {
|
549 |
FPROUNDING_TIEEVEN, |
550 |
FPROUNDING_POSINF, |
551 |
FPROUNDING_NEGINF, |
552 |
FPROUNDING_ZERO, |
553 |
FPROUNDING_TIEAWAY, |
554 |
FPROUNDING_ODD |
555 |
}; |
556 |
|
557 |
int arm_rmode_to_sf(int rmode); |
558 |
|
559 |
enum arm_cpu_mode {
|
560 |
ARM_CPU_MODE_USR = 0x10,
|
561 |
ARM_CPU_MODE_FIQ = 0x11,
|
562 |
ARM_CPU_MODE_IRQ = 0x12,
|
563 |
ARM_CPU_MODE_SVC = 0x13,
|
564 |
ARM_CPU_MODE_ABT = 0x17,
|
565 |
ARM_CPU_MODE_UND = 0x1b,
|
566 |
ARM_CPU_MODE_SYS = 0x1f
|
567 |
}; |
568 |
|
569 |
/* VFP system registers. */
|
570 |
#define ARM_VFP_FPSID 0 |
571 |
#define ARM_VFP_FPSCR 1 |
572 |
#define ARM_VFP_MVFR1 6 |
573 |
#define ARM_VFP_MVFR0 7 |
574 |
#define ARM_VFP_FPEXC 8 |
575 |
#define ARM_VFP_FPINST 9 |
576 |
#define ARM_VFP_FPINST2 10 |
577 |
|
578 |
/* iwMMXt coprocessor control registers. */
|
579 |
#define ARM_IWMMXT_wCID 0 |
580 |
#define ARM_IWMMXT_wCon 1 |
581 |
#define ARM_IWMMXT_wCSSF 2 |
582 |
#define ARM_IWMMXT_wCASF 3 |
583 |
#define ARM_IWMMXT_wCGR0 8 |
584 |
#define ARM_IWMMXT_wCGR1 9 |
585 |
#define ARM_IWMMXT_wCGR2 10 |
586 |
#define ARM_IWMMXT_wCGR3 11 |
587 |
|
588 |
/* If adding a feature bit which corresponds to a Linux ELF
|
589 |
* HWCAP bit, remember to update the feature-bit-to-hwcap
|
590 |
* mapping in linux-user/elfload.c:get_elf_hwcap().
|
591 |
*/
|
592 |
enum arm_features {
|
593 |
ARM_FEATURE_VFP, |
594 |
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
|
595 |
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
|
596 |
ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
|
597 |
ARM_FEATURE_V6, |
598 |
ARM_FEATURE_V6K, |
599 |
ARM_FEATURE_V7, |
600 |
ARM_FEATURE_THUMB2, |
601 |
ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
|
602 |
ARM_FEATURE_VFP3, |
603 |
ARM_FEATURE_VFP_FP16, |
604 |
ARM_FEATURE_NEON, |
605 |
ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
|
606 |
ARM_FEATURE_M, /* Microcontroller profile. */
|
607 |
ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
|
608 |
ARM_FEATURE_THUMB2EE, |
609 |
ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
|
610 |
ARM_FEATURE_V4T, |
611 |
ARM_FEATURE_V5, |
612 |
ARM_FEATURE_STRONGARM, |
613 |
ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
|
614 |
ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
|
615 |
ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
|
616 |
ARM_FEATURE_GENERIC_TIMER, |
617 |
ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
|
618 |
ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
|
619 |
ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
|
620 |
ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
|
621 |
ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
|
622 |
ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
|
623 |
ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
|
624 |
ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
|
625 |
ARM_FEATURE_V8, |
626 |
ARM_FEATURE_AARCH64, /* supports 64 bit mode */
|
627 |
ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
|
628 |
ARM_FEATURE_CBAR, /* has cp15 CBAR */
|
629 |
}; |
630 |
|
631 |
static inline int arm_feature(CPUARMState *env, int feature) |
632 |
{ |
633 |
return (env->features & (1ULL << feature)) != 0; |
634 |
} |
635 |
|
636 |
/* Return true if the specified exception level is running in AArch64 state. */
|
637 |
static inline bool arm_el_is_aa64(CPUARMState *env, int el) |
638 |
{ |
639 |
/* We don't currently support EL2 or EL3, and this isn't valid for EL0
|
640 |
* (if we're in EL0, is_a64() is what you want, and if we're not in EL0
|
641 |
* then the state of EL0 isn't well defined.)
|
642 |
*/
|
643 |
assert(el == 1);
|
644 |
/* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
|
645 |
* is a QEMU-imposed simplification which we may wish to change later.
|
646 |
* If we in future support EL2 and/or EL3, then the state of lower
|
647 |
* exception levels is controlled by the HCR.RW and SCR.RW bits.
|
648 |
*/
|
649 |
return arm_feature(env, ARM_FEATURE_AARCH64);
|
650 |
} |
651 |
|
652 |
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
|
653 |
|
654 |
/* Interface between CPU and Interrupt controller. */
|
655 |
void armv7m_nvic_set_pending(void *opaque, int irq); |
656 |
int armv7m_nvic_acknowledge_irq(void *opaque); |
657 |
void armv7m_nvic_complete_irq(void *opaque, int irq); |
658 |
|
659 |
/* Interface for defining coprocessor registers.
|
660 |
* Registers are defined in tables of arm_cp_reginfo structs
|
661 |
* which are passed to define_arm_cp_regs().
|
662 |
*/
|
663 |
|
664 |
/* When looking up a coprocessor register we look for it
|
665 |
* via an integer which encodes all of:
|
666 |
* coprocessor number
|
667 |
* Crn, Crm, opc1, opc2 fields
|
668 |
* 32 or 64 bit register (ie is it accessed via MRC/MCR
|
669 |
* or via MRRC/MCRR?)
|
670 |
* We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
|
671 |
* (In this case crn and opc2 should be zero.)
|
672 |
* For AArch64, there is no 32/64 bit size distinction;
|
673 |
* instead all registers have a 2 bit op0, 3 bit op1 and op2,
|
674 |
* and 4 bit CRn and CRm. The encoding patterns are chosen
|
675 |
* to be easy to convert to and from the KVM encodings, and also
|
676 |
* so that the hashtable can contain both AArch32 and AArch64
|
677 |
* registers (to allow for interprocessing where we might run
|
678 |
* 32 bit code on a 64 bit core).
|
679 |
*/
|
680 |
/* This bit is private to our hashtable cpreg; in KVM register
|
681 |
* IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
|
682 |
* in the upper bits of the 64 bit ID.
|
683 |
*/
|
684 |
#define CP_REG_AA64_SHIFT 28 |
685 |
#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) |
686 |
|
687 |
#define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \
|
688 |
(((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ |
689 |
((crm) << 7) | ((opc1) << 3) | (opc2)) |
690 |
|
691 |
#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
|
692 |
(CP_REG_AA64_MASK | \ |
693 |
((cp) << CP_REG_ARM_COPROC_SHIFT) | \ |
694 |
((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ |
695 |
((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ |
696 |
((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ |
697 |
((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ |
698 |
((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) |
699 |
|
700 |
/* Convert a full 64 bit KVM register ID to the truncated 32 bit
|
701 |
* version used as a key for the coprocessor register hashtable
|
702 |
*/
|
703 |
static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) |
704 |
{ |
705 |
uint32_t cpregid = kvmid; |
706 |
if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
|
707 |
cpregid |= CP_REG_AA64_MASK; |
708 |
} else if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { |
709 |
cpregid |= (1 << 15); |
710 |
} |
711 |
return cpregid;
|
712 |
} |
713 |
|
714 |
/* Convert a truncated 32 bit hashtable key into the full
|
715 |
* 64 bit KVM register ID.
|
716 |
*/
|
717 |
static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) |
718 |
{ |
719 |
uint64_t kvmid; |
720 |
|
721 |
if (cpregid & CP_REG_AA64_MASK) {
|
722 |
kvmid = cpregid & ~CP_REG_AA64_MASK; |
723 |
kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; |
724 |
} else {
|
725 |
kvmid = cpregid & ~(1 << 15); |
726 |
if (cpregid & (1 << 15)) { |
727 |
kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; |
728 |
} else {
|
729 |
kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; |
730 |
} |
731 |
} |
732 |
return kvmid;
|
733 |
} |
734 |
|
735 |
/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
|
736 |
* special-behaviour cp reg and bits [15..8] indicate what behaviour
|
737 |
* it has. Otherwise it is a simple cp reg, where CONST indicates that
|
738 |
* TCG can assume the value to be constant (ie load at translate time)
|
739 |
* and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
|
740 |
* indicates that the TB should not be ended after a write to this register
|
741 |
* (the default is that the TB ends after cp writes). OVERRIDE permits
|
742 |
* a register definition to override a previous definition for the
|
743 |
* same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
|
744 |
* old must have the OVERRIDE bit set.
|
745 |
* NO_MIGRATE indicates that this register should be ignored for migration;
|
746 |
* (eg because any state is accessed via some other coprocessor register).
|
747 |
* IO indicates that this register does I/O and therefore its accesses
|
748 |
* need to be surrounded by gen_io_start()/gen_io_end(). In particular,
|
749 |
* registers which implement clocks or timers require this.
|
750 |
*/
|
751 |
#define ARM_CP_SPECIAL 1 |
752 |
#define ARM_CP_CONST 2 |
753 |
#define ARM_CP_64BIT 4 |
754 |
#define ARM_CP_SUPPRESS_TB_END 8 |
755 |
#define ARM_CP_OVERRIDE 16 |
756 |
#define ARM_CP_NO_MIGRATE 32 |
757 |
#define ARM_CP_IO 64 |
758 |
#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) |
759 |
#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) |
760 |
#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) |
761 |
#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) |
762 |
#define ARM_LAST_SPECIAL ARM_CP_CURRENTEL
|
763 |
/* Used only as a terminator for ARMCPRegInfo lists */
|
764 |
#define ARM_CP_SENTINEL 0xffff |
765 |
/* Mask of only the flag bits in a type field */
|
766 |
#define ARM_CP_FLAG_MASK 0x7f |
767 |
|
768 |
/* Valid values for ARMCPRegInfo state field, indicating which of
|
769 |
* the AArch32 and AArch64 execution states this register is visible in.
|
770 |
* If the reginfo doesn't explicitly specify then it is AArch32 only.
|
771 |
* If the reginfo is declared to be visible in both states then a second
|
772 |
* reginfo is synthesised for the AArch32 view of the AArch64 register,
|
773 |
* such that the AArch32 view is the lower 32 bits of the AArch64 one.
|
774 |
* Note that we rely on the values of these enums as we iterate through
|
775 |
* the various states in some places.
|
776 |
*/
|
777 |
enum {
|
778 |
ARM_CP_STATE_AA32 = 0,
|
779 |
ARM_CP_STATE_AA64 = 1,
|
780 |
ARM_CP_STATE_BOTH = 2,
|
781 |
}; |
782 |
|
783 |
/* Return true if cptype is a valid type field. This is used to try to
|
784 |
* catch errors where the sentinel has been accidentally left off the end
|
785 |
* of a list of registers.
|
786 |
*/
|
787 |
static inline bool cptype_valid(int cptype) |
788 |
{ |
789 |
return ((cptype & ~ARM_CP_FLAG_MASK) == 0) |
790 |
|| ((cptype & ARM_CP_SPECIAL) && |
791 |
((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); |
792 |
} |
793 |
|
794 |
/* Access rights:
|
795 |
* We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
|
796 |
* defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
|
797 |
* PL2 (hyp). The other level which has Read and Write bits is Secure PL1
|
798 |
* (ie any of the privileged modes in Secure state, or Monitor mode).
|
799 |
* If a register is accessible in one privilege level it's always accessible
|
800 |
* in higher privilege levels too. Since "Secure PL1" also follows this rule
|
801 |
* (ie anything visible in PL2 is visible in S-PL1, some things are only
|
802 |
* visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
|
803 |
* terminology a little and call this PL3.
|
804 |
* In AArch64 things are somewhat simpler as the PLx bits line up exactly
|
805 |
* with the ELx exception levels.
|
806 |
*
|
807 |
* If access permissions for a register are more complex than can be
|
808 |
* described with these bits, then use a laxer set of restrictions, and
|
809 |
* do the more restrictive/complex check inside a helper function.
|
810 |
*/
|
811 |
#define PL3_R 0x80 |
812 |
#define PL3_W 0x40 |
813 |
#define PL2_R (0x20 | PL3_R) |
814 |
#define PL2_W (0x10 | PL3_W) |
815 |
#define PL1_R (0x08 | PL2_R) |
816 |
#define PL1_W (0x04 | PL2_W) |
817 |
#define PL0_R (0x02 | PL1_R) |
818 |
#define PL0_W (0x01 | PL1_W) |
819 |
|
820 |
#define PL3_RW (PL3_R | PL3_W)
|
821 |
#define PL2_RW (PL2_R | PL2_W)
|
822 |
#define PL1_RW (PL1_R | PL1_W)
|
823 |
#define PL0_RW (PL0_R | PL0_W)
|
824 |
|
825 |
static inline int arm_current_pl(CPUARMState *env) |
826 |
{ |
827 |
if (env->aarch64) {
|
828 |
return extract32(env->pstate, 2, 2); |
829 |
} |
830 |
|
831 |
if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { |
832 |
return 0; |
833 |
} |
834 |
/* We don't currently implement the Virtualization or TrustZone
|
835 |
* extensions, so PL2 and PL3 don't exist for us.
|
836 |
*/
|
837 |
return 1; |
838 |
} |
839 |
|
840 |
typedef struct ARMCPRegInfo ARMCPRegInfo; |
841 |
|
842 |
typedef enum CPAccessResult { |
843 |
/* Access is permitted */
|
844 |
CP_ACCESS_OK = 0,
|
845 |
/* Access fails due to a configurable trap or enable which would
|
846 |
* result in a categorized exception syndrome giving information about
|
847 |
* the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
|
848 |
* 0xc or 0x18).
|
849 |
*/
|
850 |
CP_ACCESS_TRAP = 1,
|
851 |
/* Access fails and results in an exception syndrome 0x0 ("uncategorized").
|
852 |
* Note that this is not a catch-all case -- the set of cases which may
|
853 |
* result in this failure is specifically defined by the architecture.
|
854 |
*/
|
855 |
CP_ACCESS_TRAP_UNCATEGORIZED = 2,
|
856 |
} CPAccessResult; |
857 |
|
858 |
/* Access functions for coprocessor registers. These cannot fail and
|
859 |
* may not raise exceptions.
|
860 |
*/
|
861 |
typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); |
862 |
typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, |
863 |
uint64_t value); |
864 |
/* Access permission check functions for coprocessor registers. */
|
865 |
typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque); |
866 |
/* Hook function for register reset */
|
867 |
typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); |
868 |
|
869 |
#define CP_ANY 0xff |
870 |
|
871 |
/* Definition of an ARM coprocessor register */
|
872 |
struct ARMCPRegInfo {
|
873 |
/* Name of register (useful mainly for debugging, need not be unique) */
|
874 |
const char *name; |
875 |
/* Location of register: coprocessor number and (crn,crm,opc1,opc2)
|
876 |
* tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
|
877 |
* 'wildcard' field -- any value of that field in the MRC/MCR insn
|
878 |
* will be decoded to this register. The register read and write
|
879 |
* callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
|
880 |
* used by the program, so it is possible to register a wildcard and
|
881 |
* then behave differently on read/write if necessary.
|
882 |
* For 64 bit registers, only crm and opc1 are relevant; crn and opc2
|
883 |
* must both be zero.
|
884 |
* For AArch64-visible registers, opc0 is also used.
|
885 |
* Since there are no "coprocessors" in AArch64, cp is purely used as a
|
886 |
* way to distinguish (for KVM's benefit) guest-visible system registers
|
887 |
* from demuxed ones provided to preserve the "no side effects on
|
888 |
* KVM register read/write from QEMU" semantics. cp==0x13 is guest
|
889 |
* visible (to match KVM's encoding); cp==0 will be converted to
|
890 |
* cp==0x13 when the ARMCPRegInfo is registered, for convenience.
|
891 |
*/
|
892 |
uint8_t cp; |
893 |
uint8_t crn; |
894 |
uint8_t crm; |
895 |
uint8_t opc0; |
896 |
uint8_t opc1; |
897 |
uint8_t opc2; |
898 |
/* Execution state in which this register is visible: ARM_CP_STATE_* */
|
899 |
int state;
|
900 |
/* Register type: ARM_CP_* bits/values */
|
901 |
int type;
|
902 |
/* Access rights: PL*_[RW] */
|
903 |
int access;
|
904 |
/* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
|
905 |
* this register was defined: can be used to hand data through to the
|
906 |
* register read/write functions, since they are passed the ARMCPRegInfo*.
|
907 |
*/
|
908 |
void *opaque;
|
909 |
/* Value of this register, if it is ARM_CP_CONST. Otherwise, if
|
910 |
* fieldoffset is non-zero, the reset value of the register.
|
911 |
*/
|
912 |
uint64_t resetvalue; |
913 |
/* Offset of the field in CPUARMState for this register. This is not
|
914 |
* needed if either:
|
915 |
* 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
|
916 |
* 2. both readfn and writefn are specified
|
917 |
*/
|
918 |
ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
|
919 |
/* Function for making any access checks for this register in addition to
|
920 |
* those specified by the 'access' permissions bits. If NULL, no extra
|
921 |
* checks required. The access check is performed at runtime, not at
|
922 |
* translate time.
|
923 |
*/
|
924 |
CPAccessFn *accessfn; |
925 |
/* Function for handling reads of this register. If NULL, then reads
|
926 |
* will be done by loading from the offset into CPUARMState specified
|
927 |
* by fieldoffset.
|
928 |
*/
|
929 |
CPReadFn *readfn; |
930 |
/* Function for handling writes of this register. If NULL, then writes
|
931 |
* will be done by writing to the offset into CPUARMState specified
|
932 |
* by fieldoffset.
|
933 |
*/
|
934 |
CPWriteFn *writefn; |
935 |
/* Function for doing a "raw" read; used when we need to copy
|
936 |
* coprocessor state to the kernel for KVM or out for
|
937 |
* migration. This only needs to be provided if there is also a
|
938 |
* readfn and it has side effects (for instance clear-on-read bits).
|
939 |
*/
|
940 |
CPReadFn *raw_readfn; |
941 |
/* Function for doing a "raw" write; used when we need to copy KVM
|
942 |
* kernel coprocessor state into userspace, or for inbound
|
943 |
* migration. This only needs to be provided if there is also a
|
944 |
* writefn and it masks out "unwritable" bits or has write-one-to-clear
|
945 |
* or similar behaviour.
|
946 |
*/
|
947 |
CPWriteFn *raw_writefn; |
948 |
/* Function for resetting the register. If NULL, then reset will be done
|
949 |
* by writing resetvalue to the field specified in fieldoffset. If
|
950 |
* fieldoffset is 0 then no reset will be done.
|
951 |
*/
|
952 |
CPResetFn *resetfn; |
953 |
}; |
954 |
|
955 |
/* Macros which are lvalues for the field in CPUARMState for the
|
956 |
* ARMCPRegInfo *ri.
|
957 |
*/
|
958 |
#define CPREG_FIELD32(env, ri) \
|
959 |
(*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
|
960 |
#define CPREG_FIELD64(env, ri) \
|
961 |
(*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
|
962 |
|
963 |
#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
|
964 |
|
965 |
void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
|
966 |
const ARMCPRegInfo *regs, void *opaque); |
967 |
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
|
968 |
const ARMCPRegInfo *regs, void *opaque); |
969 |
static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) |
970 |
{ |
971 |
define_arm_cp_regs_with_opaque(cpu, regs, 0);
|
972 |
} |
973 |
static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) |
974 |
{ |
975 |
define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
|
976 |
} |
977 |
const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
|
978 |
|
979 |
/* CPWriteFn that can be used to implement writes-ignored behaviour */
|
980 |
void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
981 |
uint64_t value); |
982 |
/* CPReadFn that can be used for read-as-zero behaviour */
|
983 |
uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
|
984 |
|
985 |
/* CPResetFn that does nothing, for use if no reset is required even
|
986 |
* if fieldoffset is non zero.
|
987 |
*/
|
988 |
void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); |
989 |
|
990 |
/* Return true if this reginfo struct's field in the cpu state struct
|
991 |
* is 64 bits wide.
|
992 |
*/
|
993 |
static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) |
994 |
{ |
995 |
return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
|
996 |
} |
997 |
|
998 |
static inline bool cp_access_ok(int current_pl, |
999 |
const ARMCPRegInfo *ri, int isread) |
1000 |
{ |
1001 |
return (ri->access >> ((current_pl * 2) + isread)) & 1; |
1002 |
} |
1003 |
|
1004 |
/**
|
1005 |
* write_list_to_cpustate
|
1006 |
* @cpu: ARMCPU
|
1007 |
*
|
1008 |
* For each register listed in the ARMCPU cpreg_indexes list, write
|
1009 |
* its value from the cpreg_values list into the ARMCPUState structure.
|
1010 |
* This updates TCG's working data structures from KVM data or
|
1011 |
* from incoming migration state.
|
1012 |
*
|
1013 |
* Returns: true if all register values were updated correctly,
|
1014 |
* false if some register was unknown or could not be written.
|
1015 |
* Note that we do not stop early on failure -- we will attempt
|
1016 |
* writing all registers in the list.
|
1017 |
*/
|
1018 |
bool write_list_to_cpustate(ARMCPU *cpu);
|
1019 |
|
1020 |
/**
|
1021 |
* write_cpustate_to_list:
|
1022 |
* @cpu: ARMCPU
|
1023 |
*
|
1024 |
* For each register listed in the ARMCPU cpreg_indexes list, write
|
1025 |
* its value from the ARMCPUState structure into the cpreg_values list.
|
1026 |
* This is used to copy info from TCG's working data structures into
|
1027 |
* KVM or for outbound migration.
|
1028 |
*
|
1029 |
* Returns: true if all register values were read correctly,
|
1030 |
* false if some register was unknown or could not be read.
|
1031 |
* Note that we do not stop early on failure -- we will attempt
|
1032 |
* reading all registers in the list.
|
1033 |
*/
|
1034 |
bool write_cpustate_to_list(ARMCPU *cpu);
|
1035 |
|
1036 |
/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
|
1037 |
Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
|
1038 |
conventional cores (ie. Application or Realtime profile). */
|
1039 |
|
1040 |
#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
|
1041 |
|
1042 |
#define ARM_CPUID_TI915T 0x54029152 |
1043 |
#define ARM_CPUID_TI925T 0x54029252 |
1044 |
|
1045 |
#if defined(CONFIG_USER_ONLY)
|
1046 |
#define TARGET_PAGE_BITS 12 |
1047 |
#else
|
1048 |
/* The ARM MMU allows 1k pages. */
|
1049 |
/* ??? Linux doesn't actually use these, and they're deprecated in recent
|
1050 |
architecture revisions. Maybe a configure option to disable them. */
|
1051 |
#define TARGET_PAGE_BITS 10 |
1052 |
#endif
|
1053 |
|
1054 |
#if defined(TARGET_AARCH64)
|
1055 |
# define TARGET_PHYS_ADDR_SPACE_BITS 48 |
1056 |
# define TARGET_VIRT_ADDR_SPACE_BITS 64 |
1057 |
#else
|
1058 |
# define TARGET_PHYS_ADDR_SPACE_BITS 40 |
1059 |
# define TARGET_VIRT_ADDR_SPACE_BITS 32 |
1060 |
#endif
|
1061 |
|
1062 |
static inline CPUARMState *cpu_init(const char *cpu_model) |
1063 |
{ |
1064 |
ARMCPU *cpu = cpu_arm_init(cpu_model); |
1065 |
if (cpu) {
|
1066 |
return &cpu->env;
|
1067 |
} |
1068 |
return NULL; |
1069 |
} |
1070 |
|
1071 |
#define cpu_exec cpu_arm_exec
|
1072 |
#define cpu_gen_code cpu_arm_gen_code
|
1073 |
#define cpu_signal_handler cpu_arm_signal_handler
|
1074 |
#define cpu_list arm_cpu_list
|
1075 |
|
1076 |
/* MMU modes definitions */
|
1077 |
#define MMU_MODE0_SUFFIX _kernel
|
1078 |
#define MMU_MODE1_SUFFIX _user
|
1079 |
#define MMU_USER_IDX 1 |
1080 |
static inline int cpu_mmu_index (CPUARMState *env) |
1081 |
{ |
1082 |
return arm_current_pl(env) ? 0 : 1; |
1083 |
} |
1084 |
|
1085 |
#include "exec/cpu-all.h" |
1086 |
|
1087 |
/* Bit usage in the TB flags field: bit 31 indicates whether we are
|
1088 |
* in 32 or 64 bit mode. The meaning of the other bits depends on that.
|
1089 |
*/
|
1090 |
#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 |
1091 |
#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) |
1092 |
|
1093 |
/* Bit usage when in AArch32 state: */
|
1094 |
#define ARM_TBFLAG_THUMB_SHIFT 0 |
1095 |
#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) |
1096 |
#define ARM_TBFLAG_VECLEN_SHIFT 1 |
1097 |
#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) |
1098 |
#define ARM_TBFLAG_VECSTRIDE_SHIFT 4 |
1099 |
#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) |
1100 |
#define ARM_TBFLAG_PRIV_SHIFT 6 |
1101 |
#define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) |
1102 |
#define ARM_TBFLAG_VFPEN_SHIFT 7 |
1103 |
#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) |
1104 |
#define ARM_TBFLAG_CONDEXEC_SHIFT 8 |
1105 |
#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) |
1106 |
#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16 |
1107 |
#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) |
1108 |
|
1109 |
/* Bit usage when in AArch64 state */
|
1110 |
#define ARM_TBFLAG_AA64_EL_SHIFT 0 |
1111 |
#define ARM_TBFLAG_AA64_EL_MASK (0x3 << ARM_TBFLAG_AA64_EL_SHIFT) |
1112 |
|
1113 |
/* some convenience accessor macros */
|
1114 |
#define ARM_TBFLAG_AARCH64_STATE(F) \
|
1115 |
(((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) |
1116 |
#define ARM_TBFLAG_THUMB(F) \
|
1117 |
(((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) |
1118 |
#define ARM_TBFLAG_VECLEN(F) \
|
1119 |
(((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) |
1120 |
#define ARM_TBFLAG_VECSTRIDE(F) \
|
1121 |
(((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) |
1122 |
#define ARM_TBFLAG_PRIV(F) \
|
1123 |
(((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) |
1124 |
#define ARM_TBFLAG_VFPEN(F) \
|
1125 |
(((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) |
1126 |
#define ARM_TBFLAG_CONDEXEC(F) \
|
1127 |
(((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) |
1128 |
#define ARM_TBFLAG_BSWAP_CODE(F) \
|
1129 |
(((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT) |
1130 |
#define ARM_TBFLAG_AA64_EL(F) \
|
1131 |
(((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT) |
1132 |
|
1133 |
static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
1134 |
target_ulong *cs_base, int *flags)
|
1135 |
{ |
1136 |
if (is_a64(env)) {
|
1137 |
*pc = env->pc; |
1138 |
*flags = ARM_TBFLAG_AARCH64_STATE_MASK |
1139 |
| (arm_current_pl(env) << ARM_TBFLAG_AA64_EL_SHIFT); |
1140 |
} else {
|
1141 |
int privmode;
|
1142 |
*pc = env->regs[15];
|
1143 |
*flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) |
1144 |
| (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) |
1145 |
| (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) |
1146 |
| (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) |
1147 |
| (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT); |
1148 |
if (arm_feature(env, ARM_FEATURE_M)) {
|
1149 |
privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); |
1150 |
} else {
|
1151 |
privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; |
1152 |
} |
1153 |
if (privmode) {
|
1154 |
*flags |= ARM_TBFLAG_PRIV_MASK; |
1155 |
} |
1156 |
if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
1157 |
*flags |= ARM_TBFLAG_VFPEN_MASK; |
1158 |
} |
1159 |
} |
1160 |
|
1161 |
*cs_base = 0;
|
1162 |
} |
1163 |
|
1164 |
static inline bool cpu_has_work(CPUState *cpu) |
1165 |
{ |
1166 |
return cpu->interrupt_request &
|
1167 |
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); |
1168 |
} |
1169 |
|
1170 |
#include "exec/exec-all.h" |
1171 |
|
1172 |
static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb) |
1173 |
{ |
1174 |
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
|
1175 |
env->pc = tb->pc; |
1176 |
} else {
|
1177 |
env->regs[15] = tb->pc;
|
1178 |
} |
1179 |
} |
1180 |
|
1181 |
/* Load an instruction and return it in the standard little-endian order */
|
1182 |
static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, |
1183 |
bool do_swap)
|
1184 |
{ |
1185 |
uint32_t insn = cpu_ldl_code(env, addr); |
1186 |
if (do_swap) {
|
1187 |
return bswap32(insn);
|
1188 |
} |
1189 |
return insn;
|
1190 |
} |
1191 |
|
1192 |
/* Ditto, for a halfword (Thumb) instruction */
|
1193 |
static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, |
1194 |
bool do_swap)
|
1195 |
{ |
1196 |
uint16_t insn = cpu_lduw_code(env, addr); |
1197 |
if (do_swap) {
|
1198 |
return bswap16(insn);
|
1199 |
} |
1200 |
return insn;
|
1201 |
} |
1202 |
|
1203 |
#endif
|