root / hw / ppce500_pci.c @ 1fddfba1
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1 | 74c62ba8 | aurel32 | /*
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2 | 74c62ba8 | aurel32 | * QEMU PowerPC E500 embedded processors pci controller emulation
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3 | 74c62ba8 | aurel32 | *
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4 | 74c62ba8 | aurel32 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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5 | 74c62ba8 | aurel32 | *
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6 | 74c62ba8 | aurel32 | * Author: Yu Liu, <yu.liu@freescale.com>
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7 | 74c62ba8 | aurel32 | *
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8 | 74c62ba8 | aurel32 | * This file is derived from hw/ppc4xx_pci.c,
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9 | 74c62ba8 | aurel32 | * the copyright for that material belongs to the original owners.
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10 | 74c62ba8 | aurel32 | *
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11 | 74c62ba8 | aurel32 | * This is free software; you can redistribute it and/or modify
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12 | 74c62ba8 | aurel32 | * it under the terms of the GNU General Public License as published by
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13 | 74c62ba8 | aurel32 | * the Free Software Foundation; either version 2 of the License, or
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14 | 74c62ba8 | aurel32 | * (at your option) any later version.
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15 | 74c62ba8 | aurel32 | */
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16 | 74c62ba8 | aurel32 | |
17 | 74c62ba8 | aurel32 | #include "hw.h" |
18 | 74c62ba8 | aurel32 | #include "pci.h" |
19 | 74c62ba8 | aurel32 | #include "pci_host.h" |
20 | 74c62ba8 | aurel32 | #include "bswap.h" |
21 | 74c62ba8 | aurel32 | |
22 | 74c62ba8 | aurel32 | #ifdef DEBUG_PCI
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23 | 001faf32 | Blue Swirl | #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) |
24 | 74c62ba8 | aurel32 | #else
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25 | 001faf32 | Blue Swirl | #define pci_debug(fmt, ...)
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26 | 74c62ba8 | aurel32 | #endif
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27 | 74c62ba8 | aurel32 | |
28 | 74c62ba8 | aurel32 | #define PCIE500_CFGADDR 0x0 |
29 | 74c62ba8 | aurel32 | #define PCIE500_CFGDATA 0x4 |
30 | 74c62ba8 | aurel32 | #define PCIE500_REG_BASE 0xC00 |
31 | be13cc7a | Alexander Graf | #define PCIE500_ALL_SIZE 0x1000 |
32 | be13cc7a | Alexander Graf | #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
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33 | 74c62ba8 | aurel32 | |
34 | 74c62ba8 | aurel32 | #define PPCE500_PCI_CONFIG_ADDR 0x0 |
35 | 74c62ba8 | aurel32 | #define PPCE500_PCI_CONFIG_DATA 0x4 |
36 | 74c62ba8 | aurel32 | #define PPCE500_PCI_INTACK 0x8 |
37 | 74c62ba8 | aurel32 | |
38 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) |
39 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) |
40 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) |
41 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) |
42 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) |
43 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) |
44 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) |
45 | 74c62ba8 | aurel32 | |
46 | 74c62ba8 | aurel32 | #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) |
47 | 74c62ba8 | aurel32 | |
48 | 74c62ba8 | aurel32 | #define PCI_POTAR 0x0 |
49 | 74c62ba8 | aurel32 | #define PCI_POTEAR 0x4 |
50 | 74c62ba8 | aurel32 | #define PCI_POWBAR 0x8 |
51 | 74c62ba8 | aurel32 | #define PCI_POWAR 0x10 |
52 | 74c62ba8 | aurel32 | |
53 | 74c62ba8 | aurel32 | #define PCI_PITAR 0x0 |
54 | 74c62ba8 | aurel32 | #define PCI_PIWBAR 0x8 |
55 | 74c62ba8 | aurel32 | #define PCI_PIWBEAR 0xC |
56 | 74c62ba8 | aurel32 | #define PCI_PIWAR 0x10 |
57 | 74c62ba8 | aurel32 | |
58 | 74c62ba8 | aurel32 | #define PPCE500_PCI_NR_POBS 5 |
59 | 74c62ba8 | aurel32 | #define PPCE500_PCI_NR_PIBS 3 |
60 | 74c62ba8 | aurel32 | |
61 | 74c62ba8 | aurel32 | struct pci_outbound {
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62 | 74c62ba8 | aurel32 | uint32_t potar; |
63 | 74c62ba8 | aurel32 | uint32_t potear; |
64 | 74c62ba8 | aurel32 | uint32_t powbar; |
65 | 74c62ba8 | aurel32 | uint32_t powar; |
66 | 74c62ba8 | aurel32 | }; |
67 | 74c62ba8 | aurel32 | |
68 | 74c62ba8 | aurel32 | struct pci_inbound {
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69 | 74c62ba8 | aurel32 | uint32_t pitar; |
70 | 74c62ba8 | aurel32 | uint32_t piwbar; |
71 | 74c62ba8 | aurel32 | uint32_t piwbear; |
72 | 74c62ba8 | aurel32 | uint32_t piwar; |
73 | 74c62ba8 | aurel32 | }; |
74 | 74c62ba8 | aurel32 | |
75 | 74c62ba8 | aurel32 | struct PPCE500PCIState {
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76 | be13cc7a | Alexander Graf | PCIHostState pci_state; |
77 | 74c62ba8 | aurel32 | struct pci_outbound pob[PPCE500_PCI_NR_POBS];
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78 | 74c62ba8 | aurel32 | struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
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79 | 74c62ba8 | aurel32 | uint32_t gasket_time; |
80 | be13cc7a | Alexander Graf | qemu_irq irq[4];
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81 | be13cc7a | Alexander Graf | /* mmio maps */
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82 | be13cc7a | Alexander Graf | int cfgaddr;
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83 | be13cc7a | Alexander Graf | int cfgdata;
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84 | be13cc7a | Alexander Graf | int reg;
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85 | 74c62ba8 | aurel32 | }; |
86 | 74c62ba8 | aurel32 | |
87 | 74c62ba8 | aurel32 | typedef struct PPCE500PCIState PPCE500PCIState; |
88 | 74c62ba8 | aurel32 | |
89 | c227f099 | Anthony Liguori | static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr) |
90 | 74c62ba8 | aurel32 | { |
91 | 74c62ba8 | aurel32 | PPCE500PCIState *pci = opaque; |
92 | 74c62ba8 | aurel32 | unsigned long win; |
93 | 74c62ba8 | aurel32 | uint32_t value = 0;
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94 | 74c62ba8 | aurel32 | |
95 | 74c62ba8 | aurel32 | win = addr & 0xfe0;
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96 | 74c62ba8 | aurel32 | |
97 | 74c62ba8 | aurel32 | switch (win) {
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98 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW1:
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99 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW2:
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100 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW3:
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101 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW4:
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102 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
103 | 74c62ba8 | aurel32 | case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break; |
104 | 74c62ba8 | aurel32 | case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break; |
105 | 74c62ba8 | aurel32 | case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break; |
106 | 74c62ba8 | aurel32 | case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break; |
107 | 74c62ba8 | aurel32 | default: break; |
108 | 74c62ba8 | aurel32 | } |
109 | 74c62ba8 | aurel32 | break;
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110 | 74c62ba8 | aurel32 | |
111 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW3:
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112 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW2:
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113 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW1:
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114 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
115 | 74c62ba8 | aurel32 | case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break; |
116 | 74c62ba8 | aurel32 | case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break; |
117 | 74c62ba8 | aurel32 | case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break; |
118 | 74c62ba8 | aurel32 | case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break; |
119 | 74c62ba8 | aurel32 | default: break; |
120 | 74c62ba8 | aurel32 | }; |
121 | 74c62ba8 | aurel32 | break;
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122 | 74c62ba8 | aurel32 | |
123 | 74c62ba8 | aurel32 | case PPCE500_PCI_GASKET_TIMR:
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124 | 74c62ba8 | aurel32 | value = pci->gasket_time; |
125 | 74c62ba8 | aurel32 | break;
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126 | 74c62ba8 | aurel32 | |
127 | 74c62ba8 | aurel32 | default:
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128 | 74c62ba8 | aurel32 | break;
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129 | 74c62ba8 | aurel32 | } |
130 | 74c62ba8 | aurel32 | |
131 | c0a2a096 | Blue Swirl | pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, |
132 | c0a2a096 | Blue Swirl | win, addr, value); |
133 | 74c62ba8 | aurel32 | return value;
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134 | 74c62ba8 | aurel32 | } |
135 | 74c62ba8 | aurel32 | |
136 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const e500_pci_reg_read[] = { |
137 | 74c62ba8 | aurel32 | &pci_reg_read4, |
138 | 74c62ba8 | aurel32 | &pci_reg_read4, |
139 | 74c62ba8 | aurel32 | &pci_reg_read4, |
140 | 74c62ba8 | aurel32 | }; |
141 | 74c62ba8 | aurel32 | |
142 | c227f099 | Anthony Liguori | static void pci_reg_write4(void *opaque, target_phys_addr_t addr, |
143 | 74c62ba8 | aurel32 | uint32_t value) |
144 | 74c62ba8 | aurel32 | { |
145 | 74c62ba8 | aurel32 | PPCE500PCIState *pci = opaque; |
146 | 74c62ba8 | aurel32 | unsigned long win; |
147 | 74c62ba8 | aurel32 | |
148 | 74c62ba8 | aurel32 | win = addr & 0xfe0;
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149 | 74c62ba8 | aurel32 | |
150 | c0a2a096 | Blue Swirl | pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", |
151 | c0a2a096 | Blue Swirl | __func__, value, win, addr); |
152 | 74c62ba8 | aurel32 | |
153 | 74c62ba8 | aurel32 | switch (win) {
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154 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW1:
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155 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW2:
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156 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW3:
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157 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW4:
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158 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
159 | 74c62ba8 | aurel32 | case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break; |
160 | 74c62ba8 | aurel32 | case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break; |
161 | 74c62ba8 | aurel32 | case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break; |
162 | 74c62ba8 | aurel32 | case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break; |
163 | 74c62ba8 | aurel32 | default: break; |
164 | 74c62ba8 | aurel32 | }; |
165 | 74c62ba8 | aurel32 | break;
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166 | 74c62ba8 | aurel32 | |
167 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW3:
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168 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW2:
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169 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW1:
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170 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
171 | 74c62ba8 | aurel32 | case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break; |
172 | 74c62ba8 | aurel32 | case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break; |
173 | 74c62ba8 | aurel32 | case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break; |
174 | 74c62ba8 | aurel32 | case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break; |
175 | 74c62ba8 | aurel32 | default: break; |
176 | 74c62ba8 | aurel32 | }; |
177 | 74c62ba8 | aurel32 | break;
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178 | 74c62ba8 | aurel32 | |
179 | 74c62ba8 | aurel32 | case PPCE500_PCI_GASKET_TIMR:
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180 | 74c62ba8 | aurel32 | pci->gasket_time = value; |
181 | 74c62ba8 | aurel32 | break;
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182 | 74c62ba8 | aurel32 | |
183 | 74c62ba8 | aurel32 | default:
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184 | 74c62ba8 | aurel32 | break;
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185 | 74c62ba8 | aurel32 | }; |
186 | 74c62ba8 | aurel32 | } |
187 | 74c62ba8 | aurel32 | |
188 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const e500_pci_reg_write[] = { |
189 | 74c62ba8 | aurel32 | &pci_reg_write4, |
190 | 74c62ba8 | aurel32 | &pci_reg_write4, |
191 | 74c62ba8 | aurel32 | &pci_reg_write4, |
192 | 74c62ba8 | aurel32 | }; |
193 | 74c62ba8 | aurel32 | |
194 | 74c62ba8 | aurel32 | static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
195 | 74c62ba8 | aurel32 | { |
196 | 74c62ba8 | aurel32 | int devno = pci_dev->devfn >> 3, ret = 0; |
197 | 74c62ba8 | aurel32 | |
198 | 74c62ba8 | aurel32 | switch (devno) {
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199 | 74c62ba8 | aurel32 | /* Two PCI slot */
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200 | 74c62ba8 | aurel32 | case 0x11: |
201 | 74c62ba8 | aurel32 | case 0x12: |
202 | 74c62ba8 | aurel32 | ret = (irq_num + devno - 0x10) % 4; |
203 | 74c62ba8 | aurel32 | break;
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204 | 74c62ba8 | aurel32 | default:
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205 | 72b310e9 | Scott Wood | printf("Error:%s:unknown dev number\n", __func__);
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206 | 74c62ba8 | aurel32 | } |
207 | 74c62ba8 | aurel32 | |
208 | 74c62ba8 | aurel32 | pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
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209 | 74c62ba8 | aurel32 | pci_dev->devfn, irq_num, ret, devno); |
210 | 74c62ba8 | aurel32 | |
211 | 74c62ba8 | aurel32 | return ret;
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212 | 74c62ba8 | aurel32 | } |
213 | 74c62ba8 | aurel32 | |
214 | 5d4e84c8 | Juan Quintela | static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level) |
215 | 74c62ba8 | aurel32 | { |
216 | 5d4e84c8 | Juan Quintela | qemu_irq *pic = opaque; |
217 | 5d4e84c8 | Juan Quintela | |
218 | 74c62ba8 | aurel32 | pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
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219 | 74c62ba8 | aurel32 | |
220 | 74c62ba8 | aurel32 | qemu_set_irq(pic[irq_num], level); |
221 | 74c62ba8 | aurel32 | } |
222 | 74c62ba8 | aurel32 | |
223 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_pci_outbound = { |
224 | e0433ecc | Juan Quintela | .name = "pci_outbound",
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225 | e0433ecc | Juan Quintela | .version_id = 0,
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226 | e0433ecc | Juan Quintela | .minimum_version_id = 0,
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227 | e0433ecc | Juan Quintela | .minimum_version_id_old = 0,
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228 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
229 | e0433ecc | Juan Quintela | VMSTATE_UINT32(potar, struct pci_outbound),
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230 | e0433ecc | Juan Quintela | VMSTATE_UINT32(potear, struct pci_outbound),
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231 | e0433ecc | Juan Quintela | VMSTATE_UINT32(powbar, struct pci_outbound),
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232 | e0433ecc | Juan Quintela | VMSTATE_UINT32(powar, struct pci_outbound),
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233 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
234 | 74c62ba8 | aurel32 | } |
235 | e0433ecc | Juan Quintela | }; |
236 | 74c62ba8 | aurel32 | |
237 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_pci_inbound = { |
238 | e0433ecc | Juan Quintela | .name = "pci_inbound",
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239 | e0433ecc | Juan Quintela | .version_id = 0,
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240 | e0433ecc | Juan Quintela | .minimum_version_id = 0,
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241 | e0433ecc | Juan Quintela | .minimum_version_id_old = 0,
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242 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
243 | e0433ecc | Juan Quintela | VMSTATE_UINT32(pitar, struct pci_inbound),
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244 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwbar, struct pci_inbound),
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245 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwbear, struct pci_inbound),
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246 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwar, struct pci_inbound),
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247 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
248 | 74c62ba8 | aurel32 | } |
249 | e0433ecc | Juan Quintela | }; |
250 | 74c62ba8 | aurel32 | |
251 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_ppce500_pci = { |
252 | e0433ecc | Juan Quintela | .name = "ppce500_pci",
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253 | e0433ecc | Juan Quintela | .version_id = 1,
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254 | e0433ecc | Juan Quintela | .minimum_version_id = 1,
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255 | e0433ecc | Juan Quintela | .minimum_version_id_old = 1,
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256 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
257 | e0433ecc | Juan Quintela | VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
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258 | e0433ecc | Juan Quintela | vmstate_pci_outbound, struct pci_outbound),
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259 | e0433ecc | Juan Quintela | VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
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260 | e0433ecc | Juan Quintela | vmstate_pci_outbound, struct pci_inbound),
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261 | e0433ecc | Juan Quintela | VMSTATE_UINT32(gasket_time, PPCE500PCIState), |
262 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
263 | 74c62ba8 | aurel32 | } |
264 | e0433ecc | Juan Quintela | }; |
265 | 74c62ba8 | aurel32 | |
266 | be13cc7a | Alexander Graf | static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base) |
267 | be13cc7a | Alexander Graf | { |
268 | be13cc7a | Alexander Graf | PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); |
269 | be13cc7a | Alexander Graf | PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h); |
270 | be13cc7a | Alexander Graf | |
271 | be13cc7a | Alexander Graf | cpu_register_physical_memory(base + PCIE500_CFGADDR, 4, s->cfgaddr);
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272 | be13cc7a | Alexander Graf | cpu_register_physical_memory(base + PCIE500_CFGDATA, 4, s->cfgdata);
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273 | be13cc7a | Alexander Graf | cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE, |
274 | be13cc7a | Alexander Graf | s->reg); |
275 | be13cc7a | Alexander Graf | } |
276 | be13cc7a | Alexander Graf | |
277 | be13cc7a | Alexander Graf | static int e500_pcihost_initfn(SysBusDevice *dev) |
278 | be13cc7a | Alexander Graf | { |
279 | be13cc7a | Alexander Graf | PCIHostState *h; |
280 | be13cc7a | Alexander Graf | PPCE500PCIState *s; |
281 | be13cc7a | Alexander Graf | PCIBus *b; |
282 | be13cc7a | Alexander Graf | int i;
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283 | be13cc7a | Alexander Graf | |
284 | be13cc7a | Alexander Graf | h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); |
285 | be13cc7a | Alexander Graf | s = DO_UPCAST(PPCE500PCIState, pci_state, h); |
286 | be13cc7a | Alexander Graf | |
287 | be13cc7a | Alexander Graf | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { |
288 | be13cc7a | Alexander Graf | sysbus_init_irq(dev, &s->irq[i]); |
289 | be13cc7a | Alexander Graf | } |
290 | be13cc7a | Alexander Graf | |
291 | be13cc7a | Alexander Graf | b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
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292 | be13cc7a | Alexander Graf | mpc85xx_pci_map_irq, s->irq, PCI_DEVFN(0x11, 0), 4); |
293 | be13cc7a | Alexander Graf | s->pci_state.bus = b; |
294 | be13cc7a | Alexander Graf | |
295 | be13cc7a | Alexander Graf | pci_create_simple(b, 0, "e500-host-bridge"); |
296 | be13cc7a | Alexander Graf | |
297 | be13cc7a | Alexander Graf | s->cfgaddr = pci_host_conf_register_mmio(&s->pci_state, DEVICE_BIG_ENDIAN); |
298 | be13cc7a | Alexander Graf | s->cfgdata = pci_host_data_register_mmio(&s->pci_state, |
299 | be13cc7a | Alexander Graf | DEVICE_LITTLE_ENDIAN); |
300 | be13cc7a | Alexander Graf | s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s, |
301 | be13cc7a | Alexander Graf | DEVICE_BIG_ENDIAN); |
302 | be13cc7a | Alexander Graf | sysbus_init_mmio_cb(dev, PCIE500_ALL_SIZE, e500_pci_map); |
303 | be13cc7a | Alexander Graf | |
304 | be13cc7a | Alexander Graf | return 0; |
305 | be13cc7a | Alexander Graf | } |
306 | be13cc7a | Alexander Graf | |
307 | be13cc7a | Alexander Graf | static int e500_host_bridge_initfn(PCIDevice *dev) |
308 | be13cc7a | Alexander Graf | { |
309 | be13cc7a | Alexander Graf | pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_FREESCALE); |
310 | be13cc7a | Alexander Graf | pci_config_set_device_id(dev->config, PCI_DEVICE_ID_MPC8533E); |
311 | be13cc7a | Alexander Graf | pci_config_set_class(dev->config, PCI_CLASS_PROCESSOR_POWERPC); |
312 | be13cc7a | Alexander Graf | |
313 | be13cc7a | Alexander Graf | return 0; |
314 | be13cc7a | Alexander Graf | } |
315 | be13cc7a | Alexander Graf | |
316 | be13cc7a | Alexander Graf | static PCIDeviceInfo e500_host_bridge_info = {
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317 | be13cc7a | Alexander Graf | .qdev.name = "e500-host-bridge",
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318 | be13cc7a | Alexander Graf | .qdev.desc = "Host bridge",
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319 | be13cc7a | Alexander Graf | .qdev.size = sizeof(PCIDevice),
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320 | be13cc7a | Alexander Graf | .init = e500_host_bridge_initfn, |
321 | be13cc7a | Alexander Graf | }; |
322 | be13cc7a | Alexander Graf | |
323 | be13cc7a | Alexander Graf | static SysBusDeviceInfo e500_pcihost_info = {
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324 | be13cc7a | Alexander Graf | .init = e500_pcihost_initfn, |
325 | be13cc7a | Alexander Graf | .qdev.name = "e500-pcihost",
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326 | be13cc7a | Alexander Graf | .qdev.size = sizeof(PPCE500PCIState),
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327 | be13cc7a | Alexander Graf | .qdev.vmsd = &vmstate_ppce500_pci, |
328 | be13cc7a | Alexander Graf | }; |
329 | be13cc7a | Alexander Graf | |
330 | be13cc7a | Alexander Graf | static void e500_pci_register(void) |
331 | 74c62ba8 | aurel32 | { |
332 | be13cc7a | Alexander Graf | sysbus_register_withprop(&e500_pcihost_info); |
333 | be13cc7a | Alexander Graf | pci_qdev_register(&e500_host_bridge_info); |
334 | 74c62ba8 | aurel32 | } |
335 | be13cc7a | Alexander Graf | device_init(e500_pci_register); |