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1 | 6f7e9aec | bellard | /*
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2 | 67e999be | bellard | * QEMU ESP/NCR53C9x emulation
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3 | 5fafdf24 | ths | *
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4 | 4e9aec74 | pbrook | * Copyright (c) 2005-2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 6f7e9aec | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 6f7e9aec | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 6f7e9aec | bellard | * in the Software without restriction, including without limitation the rights
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9 | 6f7e9aec | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 6f7e9aec | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 6f7e9aec | bellard | * furnished to do so, subject to the following conditions:
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12 | 6f7e9aec | bellard | *
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13 | 6f7e9aec | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 6f7e9aec | bellard | * all copies or substantial portions of the Software.
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15 | 6f7e9aec | bellard | *
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16 | 6f7e9aec | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 6f7e9aec | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 6f7e9aec | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 6f7e9aec | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 6f7e9aec | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 6f7e9aec | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 6f7e9aec | bellard | * THE SOFTWARE.
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23 | 6f7e9aec | bellard | */
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24 | 5d20fa6b | blueswir1 | |
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "scsi-disk.h" |
27 | 8b17de88 | blueswir1 | #include "scsi.h" |
28 | 6f7e9aec | bellard | |
29 | 6f7e9aec | bellard | /* debug ESP card */
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30 | 2f275b8f | bellard | //#define DEBUG_ESP
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31 | 6f7e9aec | bellard | |
32 | 67e999be | bellard | /*
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33 | 5ad6bb97 | blueswir1 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
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34 | 5ad6bb97 | blueswir1 | * also produced as NCR89C100. See
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35 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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36 | 67e999be | bellard | * and
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37 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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38 | 67e999be | bellard | */
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39 | 67e999be | bellard | |
40 | 6f7e9aec | bellard | #ifdef DEBUG_ESP
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41 | 6f7e9aec | bellard | #define DPRINTF(fmt, args...) \
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42 | 6f7e9aec | bellard | do { printf("ESP: " fmt , ##args); } while (0) |
43 | 6f7e9aec | bellard | #else
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44 | 6f7e9aec | bellard | #define DPRINTF(fmt, args...)
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45 | 6f7e9aec | bellard | #endif
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46 | 6f7e9aec | bellard | |
47 | 5aca8c3b | blueswir1 | #define ESP_REGS 16 |
48 | 2e5d83bb | pbrook | #define TI_BUFSZ 32 |
49 | 67e999be | bellard | |
50 | 4e9aec74 | pbrook | typedef struct ESPState ESPState; |
51 | 6f7e9aec | bellard | |
52 | 4e9aec74 | pbrook | struct ESPState {
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53 | 5d20fa6b | blueswir1 | uint32_t it_shift; |
54 | 70c0de96 | blueswir1 | qemu_irq irq; |
55 | 5aca8c3b | blueswir1 | uint8_t rregs[ESP_REGS]; |
56 | 5aca8c3b | blueswir1 | uint8_t wregs[ESP_REGS]; |
57 | 67e999be | bellard | int32_t ti_size; |
58 | 4f6200f0 | bellard | uint32_t ti_rptr, ti_wptr; |
59 | 4f6200f0 | bellard | uint8_t ti_buf[TI_BUFSZ]; |
60 | 0fc5c15a | pbrook | int sense;
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61 | 4f6200f0 | bellard | int dma;
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62 | e4bcb14c | ths | SCSIDevice *scsi_dev[ESP_MAX_DEVS]; |
63 | 2e5d83bb | pbrook | SCSIDevice *current_dev; |
64 | 9f149aa9 | pbrook | uint8_t cmdbuf[TI_BUFSZ]; |
65 | 9f149aa9 | pbrook | int cmdlen;
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66 | 9f149aa9 | pbrook | int do_cmd;
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67 | 4d611c9a | pbrook | |
68 | 6787f5fa | pbrook | /* The amount of data left in the current DMA transfer. */
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69 | 4d611c9a | pbrook | uint32_t dma_left; |
70 | 6787f5fa | pbrook | /* The size of the current DMA transfer. Zero if no transfer is in
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71 | 6787f5fa | pbrook | progress. */
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72 | 6787f5fa | pbrook | uint32_t dma_counter; |
73 | a917d384 | pbrook | uint8_t *async_buf; |
74 | 4d611c9a | pbrook | uint32_t async_len; |
75 | 8b17de88 | blueswir1 | |
76 | 8b17de88 | blueswir1 | espdma_memory_read_write dma_memory_read; |
77 | 8b17de88 | blueswir1 | espdma_memory_read_write dma_memory_write; |
78 | 67e999be | bellard | void *dma_opaque;
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79 | 4e9aec74 | pbrook | }; |
80 | 6f7e9aec | bellard | |
81 | 5ad6bb97 | blueswir1 | #define ESP_TCLO 0x0 |
82 | 5ad6bb97 | blueswir1 | #define ESP_TCMID 0x1 |
83 | 5ad6bb97 | blueswir1 | #define ESP_FIFO 0x2 |
84 | 5ad6bb97 | blueswir1 | #define ESP_CMD 0x3 |
85 | 5ad6bb97 | blueswir1 | #define ESP_RSTAT 0x4 |
86 | 5ad6bb97 | blueswir1 | #define ESP_WBUSID 0x4 |
87 | 5ad6bb97 | blueswir1 | #define ESP_RINTR 0x5 |
88 | 5ad6bb97 | blueswir1 | #define ESP_WSEL 0x5 |
89 | 5ad6bb97 | blueswir1 | #define ESP_RSEQ 0x6 |
90 | 5ad6bb97 | blueswir1 | #define ESP_WSYNTP 0x6 |
91 | 5ad6bb97 | blueswir1 | #define ESP_RFLAGS 0x7 |
92 | 5ad6bb97 | blueswir1 | #define ESP_WSYNO 0x7 |
93 | 5ad6bb97 | blueswir1 | #define ESP_CFG1 0x8 |
94 | 5ad6bb97 | blueswir1 | #define ESP_RRES1 0x9 |
95 | 5ad6bb97 | blueswir1 | #define ESP_WCCF 0x9 |
96 | 5ad6bb97 | blueswir1 | #define ESP_RRES2 0xa |
97 | 5ad6bb97 | blueswir1 | #define ESP_WTEST 0xa |
98 | 5ad6bb97 | blueswir1 | #define ESP_CFG2 0xb |
99 | 5ad6bb97 | blueswir1 | #define ESP_CFG3 0xc |
100 | 5ad6bb97 | blueswir1 | #define ESP_RES3 0xd |
101 | 5ad6bb97 | blueswir1 | #define ESP_TCHI 0xe |
102 | 5ad6bb97 | blueswir1 | #define ESP_RES4 0xf |
103 | 5ad6bb97 | blueswir1 | |
104 | 5ad6bb97 | blueswir1 | #define CMD_DMA 0x80 |
105 | 5ad6bb97 | blueswir1 | #define CMD_CMD 0x7f |
106 | 5ad6bb97 | blueswir1 | |
107 | 5ad6bb97 | blueswir1 | #define CMD_NOP 0x00 |
108 | 5ad6bb97 | blueswir1 | #define CMD_FLUSH 0x01 |
109 | 5ad6bb97 | blueswir1 | #define CMD_RESET 0x02 |
110 | 5ad6bb97 | blueswir1 | #define CMD_BUSRESET 0x03 |
111 | 5ad6bb97 | blueswir1 | #define CMD_TI 0x10 |
112 | 5ad6bb97 | blueswir1 | #define CMD_ICCS 0x11 |
113 | 5ad6bb97 | blueswir1 | #define CMD_MSGACC 0x12 |
114 | 5ad6bb97 | blueswir1 | #define CMD_SATN 0x1a |
115 | 5ad6bb97 | blueswir1 | #define CMD_SELATN 0x42 |
116 | 5ad6bb97 | blueswir1 | #define CMD_SELATNS 0x43 |
117 | 5ad6bb97 | blueswir1 | #define CMD_ENSEL 0x44 |
118 | 5ad6bb97 | blueswir1 | |
119 | 2f275b8f | bellard | #define STAT_DO 0x00 |
120 | 2f275b8f | bellard | #define STAT_DI 0x01 |
121 | 2f275b8f | bellard | #define STAT_CD 0x02 |
122 | 2f275b8f | bellard | #define STAT_ST 0x03 |
123 | 2f275b8f | bellard | #define STAT_MI 0x06 |
124 | 2f275b8f | bellard | #define STAT_MO 0x07 |
125 | 5ad6bb97 | blueswir1 | #define STAT_PIO_MASK 0x06 |
126 | 2f275b8f | bellard | |
127 | 2f275b8f | bellard | #define STAT_TC 0x10 |
128 | 4d611c9a | pbrook | #define STAT_PE 0x20 |
129 | 4d611c9a | pbrook | #define STAT_GE 0x40 |
130 | c73f96fd | blueswir1 | #define STAT_INT 0x80 |
131 | 2f275b8f | bellard | |
132 | 2f275b8f | bellard | #define INTR_FC 0x08 |
133 | 2f275b8f | bellard | #define INTR_BS 0x10 |
134 | 2f275b8f | bellard | #define INTR_DC 0x20 |
135 | 9e61bde5 | bellard | #define INTR_RST 0x80 |
136 | 2f275b8f | bellard | |
137 | 2f275b8f | bellard | #define SEQ_0 0x0 |
138 | 2f275b8f | bellard | #define SEQ_CD 0x4 |
139 | 2f275b8f | bellard | |
140 | 5ad6bb97 | blueswir1 | #define CFG1_RESREPT 0x40 |
141 | 5ad6bb97 | blueswir1 | |
142 | 5ad6bb97 | blueswir1 | #define CFG2_MASK 0x15 |
143 | 5ad6bb97 | blueswir1 | |
144 | 5ad6bb97 | blueswir1 | #define TCHI_FAS100A 0x4 |
145 | 5ad6bb97 | blueswir1 | |
146 | c73f96fd | blueswir1 | static void esp_raise_irq(ESPState *s) |
147 | c73f96fd | blueswir1 | { |
148 | c73f96fd | blueswir1 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
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149 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_INT; |
150 | c73f96fd | blueswir1 | qemu_irq_raise(s->irq); |
151 | c73f96fd | blueswir1 | } |
152 | c73f96fd | blueswir1 | } |
153 | c73f96fd | blueswir1 | |
154 | c73f96fd | blueswir1 | static void esp_lower_irq(ESPState *s) |
155 | c73f96fd | blueswir1 | { |
156 | c73f96fd | blueswir1 | if (s->rregs[ESP_RSTAT] & STAT_INT) {
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157 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_INT; |
158 | c73f96fd | blueswir1 | qemu_irq_lower(s->irq); |
159 | c73f96fd | blueswir1 | } |
160 | c73f96fd | blueswir1 | } |
161 | c73f96fd | blueswir1 | |
162 | 9f149aa9 | pbrook | static int get_cmd(ESPState *s, uint8_t *buf) |
163 | 2f275b8f | bellard | { |
164 | a917d384 | pbrook | uint32_t dmalen; |
165 | 2f275b8f | bellard | int target;
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166 | 2f275b8f | bellard | |
167 | 5ad6bb97 | blueswir1 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
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168 | 5ad6bb97 | blueswir1 | target = s->wregs[ESP_WBUSID] & 7;
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169 | 9f149aa9 | pbrook | DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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170 | 4f6200f0 | bellard | if (s->dma) {
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171 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
172 | 4f6200f0 | bellard | } else {
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173 | f930d07e | blueswir1 | buf[0] = 0; |
174 | f930d07e | blueswir1 | memcpy(&buf[1], s->ti_buf, dmalen);
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175 | f930d07e | blueswir1 | dmalen++; |
176 | 4f6200f0 | bellard | } |
177 | 2e5d83bb | pbrook | |
178 | 2f275b8f | bellard | s->ti_size = 0;
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179 | 4f6200f0 | bellard | s->ti_rptr = 0;
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180 | 4f6200f0 | bellard | s->ti_wptr = 0;
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181 | 2f275b8f | bellard | |
182 | a917d384 | pbrook | if (s->current_dev) {
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183 | a917d384 | pbrook | /* Started a new command before the old one finished. Cancel it. */
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184 | 8ccc2ace | ths | s->current_dev->cancel_io(s->current_dev, 0);
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185 | a917d384 | pbrook | s->async_len = 0;
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186 | a917d384 | pbrook | } |
187 | a917d384 | pbrook | |
188 | e4bcb14c | ths | if (target >= ESP_MAX_DEVS || !s->scsi_dev[target]) {
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189 | 2e5d83bb | pbrook | // No such drive
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190 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = 0;
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191 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_DC; |
192 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_0; |
193 | c73f96fd | blueswir1 | esp_raise_irq(s); |
194 | f930d07e | blueswir1 | return 0; |
195 | 2f275b8f | bellard | } |
196 | 2e5d83bb | pbrook | s->current_dev = s->scsi_dev[target]; |
197 | 9f149aa9 | pbrook | return dmalen;
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198 | 9f149aa9 | pbrook | } |
199 | 9f149aa9 | pbrook | |
200 | 9f149aa9 | pbrook | static void do_cmd(ESPState *s, uint8_t *buf) |
201 | 9f149aa9 | pbrook | { |
202 | 9f149aa9 | pbrook | int32_t datalen; |
203 | 9f149aa9 | pbrook | int lun;
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204 | 9f149aa9 | pbrook | |
205 | 9f149aa9 | pbrook | DPRINTF("do_cmd: busid 0x%x\n", buf[0]); |
206 | 9f149aa9 | pbrook | lun = buf[0] & 7; |
207 | 8ccc2ace | ths | datalen = s->current_dev->send_command(s->current_dev, 0, &buf[1], lun); |
208 | 67e999be | bellard | s->ti_size = datalen; |
209 | 67e999be | bellard | if (datalen != 0) { |
210 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC; |
211 | a917d384 | pbrook | s->dma_left = 0;
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212 | 6787f5fa | pbrook | s->dma_counter = 0;
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213 | 2e5d83bb | pbrook | if (datalen > 0) { |
214 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_DI; |
215 | 8ccc2ace | ths | s->current_dev->read_data(s->current_dev, 0);
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216 | 2e5d83bb | pbrook | } else {
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217 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_DO; |
218 | 8ccc2ace | ths | s->current_dev->write_data(s->current_dev, 0);
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219 | b9788fc4 | bellard | } |
220 | 2f275b8f | bellard | } |
221 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
222 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
223 | c73f96fd | blueswir1 | esp_raise_irq(s); |
224 | 2f275b8f | bellard | } |
225 | 2f275b8f | bellard | |
226 | 9f149aa9 | pbrook | static void handle_satn(ESPState *s) |
227 | 9f149aa9 | pbrook | { |
228 | 9f149aa9 | pbrook | uint8_t buf[32];
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229 | 9f149aa9 | pbrook | int len;
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230 | 9f149aa9 | pbrook | |
231 | 9f149aa9 | pbrook | len = get_cmd(s, buf); |
232 | 9f149aa9 | pbrook | if (len)
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233 | 9f149aa9 | pbrook | do_cmd(s, buf); |
234 | 9f149aa9 | pbrook | } |
235 | 9f149aa9 | pbrook | |
236 | 9f149aa9 | pbrook | static void handle_satn_stop(ESPState *s) |
237 | 9f149aa9 | pbrook | { |
238 | 9f149aa9 | pbrook | s->cmdlen = get_cmd(s, s->cmdbuf); |
239 | 9f149aa9 | pbrook | if (s->cmdlen) {
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240 | 9f149aa9 | pbrook | DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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241 | 9f149aa9 | pbrook | s->do_cmd = 1;
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242 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
243 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
244 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
245 | c73f96fd | blueswir1 | esp_raise_irq(s); |
246 | 9f149aa9 | pbrook | } |
247 | 9f149aa9 | pbrook | } |
248 | 9f149aa9 | pbrook | |
249 | 0fc5c15a | pbrook | static void write_response(ESPState *s) |
250 | 2f275b8f | bellard | { |
251 | 0fc5c15a | pbrook | DPRINTF("Transfer status (sense=%d)\n", s->sense);
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252 | 0fc5c15a | pbrook | s->ti_buf[0] = s->sense;
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253 | 0fc5c15a | pbrook | s->ti_buf[1] = 0; |
254 | 4f6200f0 | bellard | if (s->dma) {
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255 | 8b17de88 | blueswir1 | s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
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256 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
257 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
258 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
259 | 4f6200f0 | bellard | } else {
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260 | f930d07e | blueswir1 | s->ti_size = 2;
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261 | f930d07e | blueswir1 | s->ti_rptr = 0;
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262 | f930d07e | blueswir1 | s->ti_wptr = 0;
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263 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RFLAGS] = 2;
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264 | 4f6200f0 | bellard | } |
265 | c73f96fd | blueswir1 | esp_raise_irq(s); |
266 | 2f275b8f | bellard | } |
267 | 4f6200f0 | bellard | |
268 | a917d384 | pbrook | static void esp_dma_done(ESPState *s) |
269 | a917d384 | pbrook | { |
270 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_TC; |
271 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS; |
272 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
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273 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RFLAGS] = 0;
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274 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCLO] = 0;
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275 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCMID] = 0;
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276 | c73f96fd | blueswir1 | esp_raise_irq(s); |
277 | a917d384 | pbrook | } |
278 | a917d384 | pbrook | |
279 | 4d611c9a | pbrook | static void esp_do_dma(ESPState *s) |
280 | 4d611c9a | pbrook | { |
281 | 67e999be | bellard | uint32_t len; |
282 | 4d611c9a | pbrook | int to_device;
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283 | a917d384 | pbrook | |
284 | 67e999be | bellard | to_device = (s->ti_size < 0);
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285 | a917d384 | pbrook | len = s->dma_left; |
286 | 4d611c9a | pbrook | if (s->do_cmd) {
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287 | 4d611c9a | pbrook | DPRINTF("command len %d + %d\n", s->cmdlen, len);
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288 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
289 | 4d611c9a | pbrook | s->ti_size = 0;
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290 | 4d611c9a | pbrook | s->cmdlen = 0;
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291 | 4d611c9a | pbrook | s->do_cmd = 0;
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292 | 4d611c9a | pbrook | do_cmd(s, s->cmdbuf); |
293 | 4d611c9a | pbrook | return;
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294 | a917d384 | pbrook | } |
295 | a917d384 | pbrook | if (s->async_len == 0) { |
296 | a917d384 | pbrook | /* Defer until data is available. */
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297 | a917d384 | pbrook | return;
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298 | a917d384 | pbrook | } |
299 | a917d384 | pbrook | if (len > s->async_len) {
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300 | a917d384 | pbrook | len = s->async_len; |
301 | a917d384 | pbrook | } |
302 | a917d384 | pbrook | if (to_device) {
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303 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
304 | 4d611c9a | pbrook | } else {
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305 | 8b17de88 | blueswir1 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
306 | a917d384 | pbrook | } |
307 | a917d384 | pbrook | s->dma_left -= len; |
308 | a917d384 | pbrook | s->async_buf += len; |
309 | a917d384 | pbrook | s->async_len -= len; |
310 | 6787f5fa | pbrook | if (to_device)
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311 | 6787f5fa | pbrook | s->ti_size += len; |
312 | 6787f5fa | pbrook | else
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313 | 6787f5fa | pbrook | s->ti_size -= len; |
314 | a917d384 | pbrook | if (s->async_len == 0) { |
315 | 4d611c9a | pbrook | if (to_device) {
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316 | 67e999be | bellard | // ti_size is negative
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317 | 8ccc2ace | ths | s->current_dev->write_data(s->current_dev, 0);
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318 | 4d611c9a | pbrook | } else {
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319 | 8ccc2ace | ths | s->current_dev->read_data(s->current_dev, 0);
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320 | 6787f5fa | pbrook | /* If there is still data to be read from the device then
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321 | 6787f5fa | pbrook | complete the DMA operation immeriately. Otherwise defer
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322 | 6787f5fa | pbrook | until the scsi layer has completed. */
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323 | 6787f5fa | pbrook | if (s->dma_left == 0 && s->ti_size > 0) { |
324 | 6787f5fa | pbrook | esp_dma_done(s); |
325 | 6787f5fa | pbrook | } |
326 | 4d611c9a | pbrook | } |
327 | 6787f5fa | pbrook | } else {
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328 | 6787f5fa | pbrook | /* Partially filled a scsi buffer. Complete immediately. */
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329 | a917d384 | pbrook | esp_dma_done(s); |
330 | a917d384 | pbrook | } |
331 | 4d611c9a | pbrook | } |
332 | 4d611c9a | pbrook | |
333 | a917d384 | pbrook | static void esp_command_complete(void *opaque, int reason, uint32_t tag, |
334 | a917d384 | pbrook | uint32_t arg) |
335 | 2e5d83bb | pbrook | { |
336 | 2e5d83bb | pbrook | ESPState *s = (ESPState *)opaque; |
337 | 2e5d83bb | pbrook | |
338 | 4d611c9a | pbrook | if (reason == SCSI_REASON_DONE) {
|
339 | 4d611c9a | pbrook | DPRINTF("SCSI Command complete\n");
|
340 | 4d611c9a | pbrook | if (s->ti_size != 0) |
341 | 4d611c9a | pbrook | DPRINTF("SCSI command completed unexpectedly\n");
|
342 | 4d611c9a | pbrook | s->ti_size = 0;
|
343 | a917d384 | pbrook | s->dma_left = 0;
|
344 | a917d384 | pbrook | s->async_len = 0;
|
345 | a917d384 | pbrook | if (arg)
|
346 | 4d611c9a | pbrook | DPRINTF("Command failed\n");
|
347 | a917d384 | pbrook | s->sense = arg; |
348 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] = STAT_ST; |
349 | a917d384 | pbrook | esp_dma_done(s); |
350 | a917d384 | pbrook | s->current_dev = NULL;
|
351 | 4d611c9a | pbrook | } else {
|
352 | 4d611c9a | pbrook | DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
|
353 | a917d384 | pbrook | s->async_len = arg; |
354 | 8ccc2ace | ths | s->async_buf = s->current_dev->get_buf(s->current_dev, 0);
|
355 | 6787f5fa | pbrook | if (s->dma_left) {
|
356 | a917d384 | pbrook | esp_do_dma(s); |
357 | 6787f5fa | pbrook | } else if (s->dma_counter != 0 && s->ti_size <= 0) { |
358 | 6787f5fa | pbrook | /* If this was the last part of a DMA transfer then the
|
359 | 6787f5fa | pbrook | completion interrupt is deferred to here. */
|
360 | 6787f5fa | pbrook | esp_dma_done(s); |
361 | 6787f5fa | pbrook | } |
362 | 4d611c9a | pbrook | } |
363 | 2e5d83bb | pbrook | } |
364 | 2e5d83bb | pbrook | |
365 | 2f275b8f | bellard | static void handle_ti(ESPState *s) |
366 | 2f275b8f | bellard | { |
367 | 4d611c9a | pbrook | uint32_t dmalen, minlen; |
368 | 2f275b8f | bellard | |
369 | 5ad6bb97 | blueswir1 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
|
370 | db59203d | pbrook | if (dmalen==0) { |
371 | db59203d | pbrook | dmalen=0x10000;
|
372 | db59203d | pbrook | } |
373 | 6787f5fa | pbrook | s->dma_counter = dmalen; |
374 | db59203d | pbrook | |
375 | 9f149aa9 | pbrook | if (s->do_cmd)
|
376 | 9f149aa9 | pbrook | minlen = (dmalen < 32) ? dmalen : 32; |
377 | 67e999be | bellard | else if (s->ti_size < 0) |
378 | 67e999be | bellard | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; |
379 | 9f149aa9 | pbrook | else
|
380 | 9f149aa9 | pbrook | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; |
381 | db59203d | pbrook | DPRINTF("Transfer Information len %d\n", minlen);
|
382 | 4f6200f0 | bellard | if (s->dma) {
|
383 | 4d611c9a | pbrook | s->dma_left = minlen; |
384 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
385 | 4d611c9a | pbrook | esp_do_dma(s); |
386 | 9f149aa9 | pbrook | } else if (s->do_cmd) { |
387 | 9f149aa9 | pbrook | DPRINTF("command len %d\n", s->cmdlen);
|
388 | 9f149aa9 | pbrook | s->ti_size = 0;
|
389 | 9f149aa9 | pbrook | s->cmdlen = 0;
|
390 | 9f149aa9 | pbrook | s->do_cmd = 0;
|
391 | 9f149aa9 | pbrook | do_cmd(s, s->cmdbuf); |
392 | 9f149aa9 | pbrook | return;
|
393 | 9f149aa9 | pbrook | } |
394 | 2f275b8f | bellard | } |
395 | 2f275b8f | bellard | |
396 | 5aca8c3b | blueswir1 | static void esp_reset(void *opaque) |
397 | 6f7e9aec | bellard | { |
398 | 6f7e9aec | bellard | ESPState *s = opaque; |
399 | 67e999be | bellard | |
400 | c73f96fd | blueswir1 | esp_lower_irq(s); |
401 | c73f96fd | blueswir1 | |
402 | 5aca8c3b | blueswir1 | memset(s->rregs, 0, ESP_REGS);
|
403 | 5aca8c3b | blueswir1 | memset(s->wregs, 0, ESP_REGS);
|
404 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
|
405 | 4e9aec74 | pbrook | s->ti_size = 0;
|
406 | 4e9aec74 | pbrook | s->ti_rptr = 0;
|
407 | 4e9aec74 | pbrook | s->ti_wptr = 0;
|
408 | 4e9aec74 | pbrook | s->dma = 0;
|
409 | 9f149aa9 | pbrook | s->do_cmd = 0;
|
410 | 6f7e9aec | bellard | } |
411 | 6f7e9aec | bellard | |
412 | 2d069bab | blueswir1 | static void parent_esp_reset(void *opaque, int irq, int level) |
413 | 2d069bab | blueswir1 | { |
414 | 2d069bab | blueswir1 | if (level)
|
415 | 2d069bab | blueswir1 | esp_reset(opaque); |
416 | 2d069bab | blueswir1 | } |
417 | 2d069bab | blueswir1 | |
418 | 6f7e9aec | bellard | static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
419 | 6f7e9aec | bellard | { |
420 | 6f7e9aec | bellard | ESPState *s = opaque; |
421 | 6f7e9aec | bellard | uint32_t saddr; |
422 | 6f7e9aec | bellard | |
423 | 5d20fa6b | blueswir1 | saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
|
424 | 9e61bde5 | bellard | DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
|
425 | 6f7e9aec | bellard | switch (saddr) {
|
426 | 5ad6bb97 | blueswir1 | case ESP_FIFO:
|
427 | f930d07e | blueswir1 | if (s->ti_size > 0) { |
428 | f930d07e | blueswir1 | s->ti_size--; |
429 | 5ad6bb97 | blueswir1 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
430 | 2e5d83bb | pbrook | /* Data in/out. */
|
431 | a917d384 | pbrook | fprintf(stderr, "esp: PIO data read not implemented\n");
|
432 | 5ad6bb97 | blueswir1 | s->rregs[ESP_FIFO] = 0;
|
433 | 2e5d83bb | pbrook | } else {
|
434 | 5ad6bb97 | blueswir1 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
435 | 2e5d83bb | pbrook | } |
436 | c73f96fd | blueswir1 | esp_raise_irq(s); |
437 | f930d07e | blueswir1 | } |
438 | f930d07e | blueswir1 | if (s->ti_size == 0) { |
439 | 4f6200f0 | bellard | s->ti_rptr = 0;
|
440 | 4f6200f0 | bellard | s->ti_wptr = 0;
|
441 | 4f6200f0 | bellard | } |
442 | f930d07e | blueswir1 | break;
|
443 | 5ad6bb97 | blueswir1 | case ESP_RINTR:
|
444 | 4d611c9a | pbrook | // Clear interrupt/error status bits
|
445 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] &= ~(STAT_GE | STAT_PE); |
446 | c73f96fd | blueswir1 | esp_lower_irq(s); |
447 | 9e61bde5 | bellard | break;
|
448 | 6f7e9aec | bellard | default:
|
449 | f930d07e | blueswir1 | break;
|
450 | 6f7e9aec | bellard | } |
451 | 2f275b8f | bellard | return s->rregs[saddr];
|
452 | 6f7e9aec | bellard | } |
453 | 6f7e9aec | bellard | |
454 | 6f7e9aec | bellard | static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
455 | 6f7e9aec | bellard | { |
456 | 6f7e9aec | bellard | ESPState *s = opaque; |
457 | 6f7e9aec | bellard | uint32_t saddr; |
458 | 6f7e9aec | bellard | |
459 | 5d20fa6b | blueswir1 | saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
|
460 | 5ad6bb97 | blueswir1 | DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
|
461 | 5ad6bb97 | blueswir1 | val); |
462 | 6f7e9aec | bellard | switch (saddr) {
|
463 | 5ad6bb97 | blueswir1 | case ESP_TCLO:
|
464 | 5ad6bb97 | blueswir1 | case ESP_TCMID:
|
465 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
466 | 4f6200f0 | bellard | break;
|
467 | 5ad6bb97 | blueswir1 | case ESP_FIFO:
|
468 | 9f149aa9 | pbrook | if (s->do_cmd) {
|
469 | 9f149aa9 | pbrook | s->cmdbuf[s->cmdlen++] = val & 0xff;
|
470 | 5ad6bb97 | blueswir1 | } else if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
471 | 2e5d83bb | pbrook | uint8_t buf; |
472 | 2e5d83bb | pbrook | buf = val & 0xff;
|
473 | 2e5d83bb | pbrook | s->ti_size--; |
474 | a917d384 | pbrook | fprintf(stderr, "esp: PIO data write not implemented\n");
|
475 | 2e5d83bb | pbrook | } else {
|
476 | 2e5d83bb | pbrook | s->ti_size++; |
477 | 2e5d83bb | pbrook | s->ti_buf[s->ti_wptr++] = val & 0xff;
|
478 | 2e5d83bb | pbrook | } |
479 | f930d07e | blueswir1 | break;
|
480 | 5ad6bb97 | blueswir1 | case ESP_CMD:
|
481 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
482 | 5ad6bb97 | blueswir1 | if (val & CMD_DMA) {
|
483 | f930d07e | blueswir1 | s->dma = 1;
|
484 | 6787f5fa | pbrook | /* Reload DMA counter. */
|
485 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
486 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; |
487 | f930d07e | blueswir1 | } else {
|
488 | f930d07e | blueswir1 | s->dma = 0;
|
489 | f930d07e | blueswir1 | } |
490 | 5ad6bb97 | blueswir1 | switch(val & CMD_CMD) {
|
491 | 5ad6bb97 | blueswir1 | case CMD_NOP:
|
492 | f930d07e | blueswir1 | DPRINTF("NOP (%2.2x)\n", val);
|
493 | f930d07e | blueswir1 | break;
|
494 | 5ad6bb97 | blueswir1 | case CMD_FLUSH:
|
495 | f930d07e | blueswir1 | DPRINTF("Flush FIFO (%2.2x)\n", val);
|
496 | 9e61bde5 | bellard | //s->ti_size = 0;
|
497 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_FC; |
498 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
|
499 | f930d07e | blueswir1 | break;
|
500 | 5ad6bb97 | blueswir1 | case CMD_RESET:
|
501 | f930d07e | blueswir1 | DPRINTF("Chip reset (%2.2x)\n", val);
|
502 | f930d07e | blueswir1 | esp_reset(s); |
503 | f930d07e | blueswir1 | break;
|
504 | 5ad6bb97 | blueswir1 | case CMD_BUSRESET:
|
505 | f930d07e | blueswir1 | DPRINTF("Bus reset (%2.2x)\n", val);
|
506 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_RST; |
507 | 5ad6bb97 | blueswir1 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
|
508 | c73f96fd | blueswir1 | esp_raise_irq(s); |
509 | 9e61bde5 | bellard | } |
510 | f930d07e | blueswir1 | break;
|
511 | 5ad6bb97 | blueswir1 | case CMD_TI:
|
512 | f930d07e | blueswir1 | handle_ti(s); |
513 | f930d07e | blueswir1 | break;
|
514 | 5ad6bb97 | blueswir1 | case CMD_ICCS:
|
515 | f930d07e | blueswir1 | DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
516 | f930d07e | blueswir1 | write_response(s); |
517 | f930d07e | blueswir1 | break;
|
518 | 5ad6bb97 | blueswir1 | case CMD_MSGACC:
|
519 | f930d07e | blueswir1 | DPRINTF("Message Accepted (%2.2x)\n", val);
|
520 | f930d07e | blueswir1 | write_response(s); |
521 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_DC; |
522 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
|
523 | f930d07e | blueswir1 | break;
|
524 | 5ad6bb97 | blueswir1 | case CMD_SATN:
|
525 | f930d07e | blueswir1 | DPRINTF("Set ATN (%2.2x)\n", val);
|
526 | f930d07e | blueswir1 | break;
|
527 | 5ad6bb97 | blueswir1 | case CMD_SELATN:
|
528 | f930d07e | blueswir1 | DPRINTF("Set ATN (%2.2x)\n", val);
|
529 | f930d07e | blueswir1 | handle_satn(s); |
530 | f930d07e | blueswir1 | break;
|
531 | 5ad6bb97 | blueswir1 | case CMD_SELATNS:
|
532 | f930d07e | blueswir1 | DPRINTF("Set ATN & stop (%2.2x)\n", val);
|
533 | f930d07e | blueswir1 | handle_satn_stop(s); |
534 | f930d07e | blueswir1 | break;
|
535 | 5ad6bb97 | blueswir1 | case CMD_ENSEL:
|
536 | 74ec6048 | blueswir1 | DPRINTF("Enable selection (%2.2x)\n", val);
|
537 | 74ec6048 | blueswir1 | break;
|
538 | f930d07e | blueswir1 | default:
|
539 | f930d07e | blueswir1 | DPRINTF("Unhandled ESP command (%2.2x)\n", val);
|
540 | f930d07e | blueswir1 | break;
|
541 | f930d07e | blueswir1 | } |
542 | f930d07e | blueswir1 | break;
|
543 | 5ad6bb97 | blueswir1 | case ESP_WBUSID ... ESP_WSYNO:
|
544 | f930d07e | blueswir1 | break;
|
545 | 5ad6bb97 | blueswir1 | case ESP_CFG1:
|
546 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
547 | 4f6200f0 | bellard | break;
|
548 | 5ad6bb97 | blueswir1 | case ESP_WCCF ... ESP_WTEST:
|
549 | 4f6200f0 | bellard | break;
|
550 | 5ad6bb97 | blueswir1 | case ESP_CFG2:
|
551 | 5ad6bb97 | blueswir1 | s->rregs[saddr] = val & CFG2_MASK; |
552 | 9e61bde5 | bellard | break;
|
553 | 5ad6bb97 | blueswir1 | case ESP_CFG3 ... ESP_RES4:
|
554 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
555 | 4f6200f0 | bellard | break;
|
556 | 6f7e9aec | bellard | default:
|
557 | f930d07e | blueswir1 | break;
|
558 | 6f7e9aec | bellard | } |
559 | 2f275b8f | bellard | s->wregs[saddr] = val; |
560 | 6f7e9aec | bellard | } |
561 | 6f7e9aec | bellard | |
562 | 6f7e9aec | bellard | static CPUReadMemoryFunc *esp_mem_read[3] = { |
563 | 6f7e9aec | bellard | esp_mem_readb, |
564 | 7c560456 | blueswir1 | NULL,
|
565 | 7c560456 | blueswir1 | NULL,
|
566 | 6f7e9aec | bellard | }; |
567 | 6f7e9aec | bellard | |
568 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *esp_mem_write[3] = { |
569 | 6f7e9aec | bellard | esp_mem_writeb, |
570 | 7c560456 | blueswir1 | NULL,
|
571 | 7c560456 | blueswir1 | NULL,
|
572 | 6f7e9aec | bellard | }; |
573 | 6f7e9aec | bellard | |
574 | 6f7e9aec | bellard | static void esp_save(QEMUFile *f, void *opaque) |
575 | 6f7e9aec | bellard | { |
576 | 6f7e9aec | bellard | ESPState *s = opaque; |
577 | 2f275b8f | bellard | |
578 | 5aca8c3b | blueswir1 | qemu_put_buffer(f, s->rregs, ESP_REGS); |
579 | 5aca8c3b | blueswir1 | qemu_put_buffer(f, s->wregs, ESP_REGS); |
580 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->ti_size); |
581 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->ti_rptr); |
582 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->ti_wptr); |
583 | 4f6200f0 | bellard | qemu_put_buffer(f, s->ti_buf, TI_BUFSZ); |
584 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->sense); |
585 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->dma); |
586 | 5425a216 | blueswir1 | qemu_put_buffer(f, s->cmdbuf, TI_BUFSZ); |
587 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->cmdlen); |
588 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->do_cmd); |
589 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->dma_left); |
590 | 5425a216 | blueswir1 | // There should be no transfers in progress, so dma_counter is not saved
|
591 | 6f7e9aec | bellard | } |
592 | 6f7e9aec | bellard | |
593 | 6f7e9aec | bellard | static int esp_load(QEMUFile *f, void *opaque, int version_id) |
594 | 6f7e9aec | bellard | { |
595 | 6f7e9aec | bellard | ESPState *s = opaque; |
596 | 3b46e624 | ths | |
597 | 5425a216 | blueswir1 | if (version_id != 3) |
598 | 5425a216 | blueswir1 | return -EINVAL; // Cannot emulate 2 |
599 | 6f7e9aec | bellard | |
600 | 5aca8c3b | blueswir1 | qemu_get_buffer(f, s->rregs, ESP_REGS); |
601 | 5aca8c3b | blueswir1 | qemu_get_buffer(f, s->wregs, ESP_REGS); |
602 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->ti_size); |
603 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->ti_rptr); |
604 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->ti_wptr); |
605 | 4f6200f0 | bellard | qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); |
606 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->sense); |
607 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->dma); |
608 | 5425a216 | blueswir1 | qemu_get_buffer(f, s->cmdbuf, TI_BUFSZ); |
609 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->cmdlen); |
610 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->do_cmd); |
611 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->dma_left); |
612 | 2f275b8f | bellard | |
613 | 6f7e9aec | bellard | return 0; |
614 | 6f7e9aec | bellard | } |
615 | 6f7e9aec | bellard | |
616 | fa1fb14c | ths | void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id) |
617 | fa1fb14c | ths | { |
618 | fa1fb14c | ths | ESPState *s = (ESPState *)opaque; |
619 | fa1fb14c | ths | |
620 | fa1fb14c | ths | if (id < 0) { |
621 | fa1fb14c | ths | for (id = 0; id < ESP_MAX_DEVS; id++) { |
622 | fa1fb14c | ths | if (s->scsi_dev[id] == NULL) |
623 | fa1fb14c | ths | break;
|
624 | fa1fb14c | ths | } |
625 | fa1fb14c | ths | } |
626 | fa1fb14c | ths | if (id >= ESP_MAX_DEVS) {
|
627 | fa1fb14c | ths | DPRINTF("Bad Device ID %d\n", id);
|
628 | fa1fb14c | ths | return;
|
629 | fa1fb14c | ths | } |
630 | fa1fb14c | ths | if (s->scsi_dev[id]) {
|
631 | fa1fb14c | ths | DPRINTF("Destroying device %d\n", id);
|
632 | 8ccc2ace | ths | s->scsi_dev[id]->destroy(s->scsi_dev[id]); |
633 | fa1fb14c | ths | } |
634 | fa1fb14c | ths | DPRINTF("Attaching block device %d\n", id);
|
635 | fa1fb14c | ths | /* Command queueing is not implemented. */
|
636 | 985a03b0 | ths | s->scsi_dev[id] = scsi_generic_init(bd, 0, esp_command_complete, s);
|
637 | 985a03b0 | ths | if (s->scsi_dev[id] == NULL) |
638 | 985a03b0 | ths | s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
|
639 | fa1fb14c | ths | } |
640 | fa1fb14c | ths | |
641 | 5d20fa6b | blueswir1 | void *esp_init(target_phys_addr_t espaddr, int it_shift, |
642 | 8b17de88 | blueswir1 | espdma_memory_read_write dma_memory_read, |
643 | 8b17de88 | blueswir1 | espdma_memory_read_write dma_memory_write, |
644 | 2d069bab | blueswir1 | void *dma_opaque, qemu_irq irq, qemu_irq *reset)
|
645 | 6f7e9aec | bellard | { |
646 | 6f7e9aec | bellard | ESPState *s; |
647 | 67e999be | bellard | int esp_io_memory;
|
648 | 6f7e9aec | bellard | |
649 | 6f7e9aec | bellard | s = qemu_mallocz(sizeof(ESPState));
|
650 | 6f7e9aec | bellard | if (!s)
|
651 | 67e999be | bellard | return NULL; |
652 | 6f7e9aec | bellard | |
653 | 70c0de96 | blueswir1 | s->irq = irq; |
654 | 5d20fa6b | blueswir1 | s->it_shift = it_shift; |
655 | 8b17de88 | blueswir1 | s->dma_memory_read = dma_memory_read; |
656 | 8b17de88 | blueswir1 | s->dma_memory_write = dma_memory_write; |
657 | 67e999be | bellard | s->dma_opaque = dma_opaque; |
658 | 6f7e9aec | bellard | |
659 | 6f7e9aec | bellard | esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
|
660 | 5d20fa6b | blueswir1 | cpu_register_physical_memory(espaddr, ESP_REGS << it_shift, esp_io_memory); |
661 | 6f7e9aec | bellard | |
662 | 6f7e9aec | bellard | esp_reset(s); |
663 | 6f7e9aec | bellard | |
664 | 5425a216 | blueswir1 | register_savevm("esp", espaddr, 3, esp_save, esp_load, s); |
665 | 6f7e9aec | bellard | qemu_register_reset(esp_reset, s); |
666 | 6f7e9aec | bellard | |
667 | 2d069bab | blueswir1 | *reset = *qemu_allocate_irqs(parent_esp_reset, s, 1);
|
668 | 2d069bab | blueswir1 | |
669 | 67e999be | bellard | return s;
|
670 | 67e999be | bellard | } |